Modem chip, electronic device including the modem chip, and method of operating the modem chip

Abstract

A modem chip that allocates a maximum number of decoding iterations per code block, an electronic device including the modem chip, and a method of operating the modem chip are provided. The method of operating the modem chip can include measuring a quality of a plurality of resource elements allocated for receiving a codeword, allocating a maximum number of decoding iterations per code block based on a result of the quality measurement and a resource element-to-code block (RE-CB) mapping pattern corresponding to a target slot, and decoding a plurality of first code blocks of the target slot based on the allocated maximum number of decoding iterations per code block.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0192964, filed on December 20, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments of this disclosure relate to a modem chip for processing codewords comprising multiple code blocks and an electronic device including the modem chip. Background Technology

[0003] In a communication system, the transmitting device can send codewords containing code blocks to the receiving device.

[0004] Such a receiving device can decode code blocks on a block-by-block basis for error correction. For example, the receiving device can perform low-density parity-check (LDPC) based decoding on code blocks to detect and correct errors in the code blocks.

[0005] The receiving device can decode a code block by assigning the same or similar maximum number of decoding iterations to each code block. In other words, the receiving device can perform decoding relatively quickly and easily by collectively assigning the same or similar maximum number of decoding iterations to the code block. However, efficient decoding can be difficult in certain channel environments. Summary of the Invention

[0006] One or more embodiments provide a modem chip and an electronic device including the modem chip, the modem chip being configured to allocate a maximum number of decoding iterations per code block, such that decoding of code blocks is performed efficiently on a block-by-block basis for error correction.

[0007] In addition, one or more embodiments provide a modem chip and an electronic device including the modem chip, the modem chip being configured to measure the quality of resource elements based on a resource element-to-code block (RE-CB) mapping mode and to allocate a maximum number of decoding iterations per code block.

[0008] According to an aspect of this disclosure, a method for operating a modem chip is provided, the method comprising: measuring the quality of a plurality of resource elements allocated for receiving codewords; allocating a maximum number of decoding iterations per codeword based on the quality measurement results and a resource element-to-code-block (RE-CB) mapping pattern corresponding to a target time slot; and decoding a plurality of first codewords of the target time slot based on the allocated maximum number of decoding iterations per codeword. According to another aspect of this disclosure, a modem chip is provided, the modem chip comprising: a memory; and processing circuitry configured to: access the internal memory to: allocate a maximum number of decoding iterations per code block based on the quality of the plurality of resource elements allocated for receiving codewords and a resource element-to-code-block (RE-CB) mapping mode corresponding to a target time slot; and decode a plurality of first code blocks of the target time slot based on the allocated maximum number of decoding iterations per code block.

[0009] According to another aspect of this disclosure, a method for operating a modem chip is provided, the method comprising: decoding a plurality of first code blocks in a plurality of time slots; measuring the quality of a plurality of resource elements based on the result of decoding the plurality of first code blocks and a resource element-to-code block (RE-CB) mapping pattern corresponding to each of the plurality of time slots; allocating a maximum number of decoding iterations per code block based on the measurement results of the plurality of resource elements; and decoding the plurality of first code blocks in a target time slot based on the allocated maximum number of decoding iterations per code block. Attached Figure Description

[0010] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 This is a block diagram schematically illustrating an electronic device according to one or more embodiments.

[0012] Figure 2A This is a diagram showing the basic structure of the time-frequency domain as a radio resource area. Figure 2B It is a diagram showing the time slot structure, and Figure 2C This is a diagram illustrating resource elements of a time slot according to one or more embodiments.

[0013] Figure 3 This is a diagram illustrating codewords according to one or more embodiments.

[0014] Figure 4 This is a block diagram showing in detail a decoding circuit according to one or more embodiments.

[0015] Figure 5 This is a flowchart illustrating a method of operating a decoding circuit according to one or more embodiments.

[0016] Figure 6 It is a diagram showing the monitoring range according to one or more embodiments, and Figure 7 It is shown in Figure 6 The flowchart shows the method for operating the decoding circuit and the quality measurement circuit within the monitoring range.

[0017] Figure 8AThis is a diagram illustrating an example of the decoding results of a monitoring interval according to one or more embodiments, and Figure 8B It shows the basis Figure 8A A diagram illustrating the quality measurement method for resource elements resulting from decoding.

[0018] Figure 9 It is shown Figure 5 A flowchart of a specific embodiment of operation S110.

[0019] Figure 10A This is a diagram illustrating a target time slot according to one or more embodiments, and Figure 10B This shows the generation representation and Figure 10A A diagram illustrating the method for measuring the quality of each code block in the code block corresponding to the target time slot.

[0020] Figure 11 It is shown Figure 9 The flowchart shows a specific embodiment of operation S112.

[0021] Figure 12 This is a diagram illustrating a method for allocating the maximum number of decoding iterations per code block based on a weight set per code block according to one or more embodiments.

[0022] Figure 13 It is shown in Figure 6 The flowchart shows the method for operating the decoding circuit and the quality measurement circuit within the monitoring range.

[0023] Figure 14 This is a flowchart illustrating a method of operating a decoding circuit according to one or more embodiments.

[0024] Figure 15A , Figure 15B , Figure 15C and Figure 15D A method for indirectly measuring the quality of resource elements is shown according to one or more embodiments.

[0025] Figure 16 This is a flowchart illustrating a method of operating a decoding circuit according to one or more embodiments.

[0026] Figure 17 This is a block diagram schematically illustrating a system-on-a-chip according to one or more embodiments.

[0027] Figure 18 This is a block diagram illustrating an electronic device according to one or more embodiments.

[0028] Figure 19 This is a diagram illustrating a communication device configured to perform a decoding operation according to one or more embodiments. Detailed Implementation

[0029] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0030] Figure 1 This is a block diagram schematically illustrating an electronic device 100 according to one or more embodiments.

[0031] Reference Figure 1 The electronic device 100 may include a baseband processor 110, a transceiver 120, an interface circuit 130, a memory 140, and multiple antennas 150_1, 150_2, ..., and 150_k. In some embodiments, the electronic device 100 may be implemented as or referred to as a user equipment, terminal, mobile station (MS), mobile terminal (MT), user terminal (UT), wireless communication device, handheld device, or wearable device.

[0032] For example, electronic device 100 may communicate with other electronic devices or base stations based on a New Radio (NR) network. However, this is merely an example, and the embodiments are not limited to NR networks. The embodiments can be applied to other wireless networks with similar technical backgrounds or channel settings (e.g., communication networks such as Long Term Evolution (LTE), LTE-A Advanced (LTE-A), WiBro, Global System for Mobile Communications (GSM) and 6G), or short-range communication networks such as Bluetooth and Near Field Communication (NFC)).

[0033] Furthermore, the various other functions described below may be implemented or supported by artificial intelligence (AI) technology or one or more computer programs, each of which may include computer-readable program code and be executed on a computer-readable medium. The terms “application” and “program” mean one or more computer programs, software components, instruction sets, processes, functions, objects, classes, instances, associated data, or any portion thereof suitable for implementing appropriate computer-readable program code. The term “computer-readable program code” includes any type of computer code containing source code, object code, and executable code. The term “computer-readable medium” includes any type of medium accessible by a computer (such as read-only memory (ROM), random access memory (RAM), hard disk drive, compact disc (CD), digital video disc (DVD), and any other type of memory). “Non-transitory” computer-readable media does not include wired links, wireless links, optical links, or other communication links that transmit transient electrical or other signals. Non-transitory computer-readable media includes media on which data can be permanently stored, and media on which data is stored and subsequently rewritten (such as rewritable optical discs and erasable memory devices).

[0034] In the embodiments described below, hardware methods are shown as examples. However, the embodiments include techniques using both hardware and software, and therefore, the embodiments do not exclude software-based methods.

[0035] Return to reference Figure 1 The interface circuit 130 may include multiple switches for connecting the transceiver 120 to multiple antennas 150_1, 150_2, ..., and 150_k according to the operation of the transceiver 120, multiple low-noise amplifiers for amplifying the received signal, and multiple power amplifiers for amplifying the signal to be transmitted.

[0036] Transceiver 120 can receive radio frequency (RF) signals via multiple antennas 150_1, 150_2, ..., and 150_k. Transceiver 120 can perform frequency-down conversion on the received RF signals to generate intermediate frequency (IF) signals or baseband signals. Transceiver 120 can generate data by filtering or digitizing the IF signals or baseband signals. Furthermore, this data may include multiple code blocks as codewords. See below for reference. Figure 3 This will be described in detail.

[0037] In addition, transceiver 120 can receive data from baseband processor 110. Transceiver 120 can multiplex or perform analog conversion on the received data to generate IF signals or baseband signals. Transceiver 120 can perform frequency-up conversion on the IF signals or baseband signals and transmit the converted signals as RF signals to a base station or other electronic devices via multiple antennas 150_1, 150_2, ..., and 150_k.

[0038] The baseband processor 110 can perform operations for controlling all data in the electronic device 100 or processing data for communicating with a base station or other electronic device. Furthermore, the baseband processor 110 can perform operations in conjunction with the processor of the electronic device 100 (e.g., a central processing unit (CPU)).

[0039] In one or more embodiments, the baseband processor 110 may include a decoding circuit 112 that performs decoding on a block-by-block basis for error correction of codewords received from the transceiver 120. For example, the decoding circuit 112 may perform decoding on a block-by-block basis based on low-density parity-check (LDPC) or turbo coding techniques. However, this is merely an example and is not a limitation. The decoding circuit 112 may perform decoding on a block-by-block basis based on other techniques. As used herein, decoding for error correction of a block may be referred to as decoding of a block.

[0040] In one or more embodiments, the decoding circuit 112 may perform parallel or sequential decoding of multiple code blocks in a single codeword based on a resource element-to-code block (RE-CB) mapping pattern. As used herein, an RE-CB mapping pattern may be defined as a mapping pattern between code blocks constituting a codeword in a time-frequency grid associated with the codeword and resource elements forming the time slots corresponding to the codeword. The RE-CB mapping pattern may also be referred to as a RE-CB mapping or RE-CB mapping information. Decoding operations based on a RE-CB mapping pattern may include at least one of measuring the quality of resource elements based on the RE-CB mapping pattern described below and allocating a maximum number of decoding iterations per code block based on the RE-CB mapping pattern described below.

[0041] In one or more embodiments, prior to decoding a target timeslot, the decoding circuit 112 may measure the quality of a plurality of resource elements, which will be described below, "serving as the basis for allocating the maximum number of decoding iterations per code block." For example, the decoding circuit 112 may measure the quality of a plurality of resource elements allocated for receiving codewords. The plurality of resource elements may include radio resources allocated for communications of the electronic device 100 and may form a channel for transmitting codewords comprising a plurality of code blocks. As used herein, a target timeslot may be defined as the timeslot corresponding to the target codeword currently being decoded.

[0042] In one or more embodiments, the decoding circuit 112 can measure the quality of multiple resource elements based on the results of decoding multiple code blocks corresponding to a monitoring interval preceding a target time slot. As used herein, a monitoring interval can be defined as a configurable time interval (such as a set of consecutive or non-consecutive time slots) for measuring the quality of multiple resource elements. For example, a monitoring interval may include multiple time slots, and the number of time slots included in the monitoring interval may be static or dynamically adjustable based on system configuration or channel conditions. Multiple codewords corresponding to multiple time slots in the monitoring interval may include multiple code blocks and may have the same or different RE-CB mapping patterns. The decoding circuit 112 can decode multiple code blocks of codewords in the monitoring interval and can measure the quality of multiple resource elements based on the decoding results and RE-CB mapping patterns (e.g., based on the results of decoding multiple code blocks in multiple time slots in the monitoring interval and the RE-CB mapping pattern corresponding to each of the multiple time slots in the monitoring interval). For example, the decoding results may include, but are not limited to: results regarding whether decoding for multiple code blocks failed, and results regarding whether decoding for multiple code blocks terminated prematurely (e.g., whether the decoding of multiple code blocks was completed before reaching their respective maximum number of decoding iterations). That is, the decoding circuit 112 may quantize the result value of decoding each code block into the quality of each resource element based on the RE-CB mapping mode, thereby measuring the quality of each resource element.

[0043] As described above, in addition to the embodiment that measures the quality of multiple resource elements, there may be another embodiment that measures the quality of multiple resource elements indirectly, which will be described below.

[0044] In one or more embodiments, before decoding a target time slot, decoding circuit 112 may indirectly measure the quality of a plurality of resource elements “used as the basis for allocating the maximum number of decoding iterations per code block,” as described below. As used herein, indirect measurement operations can be understood as prediction operations. In one or more embodiments, decoding circuit 112 may collect information about the quality of the plurality of resource elements and indirectly measure the quality of the plurality of resource elements based on the collected information. For example, this information may include at least one of the following: first information about the center frequency (center carrier) (e.g., the center frequency at which the bandwidth is allocated, which may affect channel conditions due to frequency-dependent fading); second information about time slots that change from uplink to downlink (e.g., information specifying whether a given time slot transitions between uplink and downlink, which may affect interference levels and signal reliability); third information about resource elements located at the edges of the frequency axis (e.g., information identifying resource elements located near spectral edges where signal degradation may occur); and fourth information about the arrangement of the demodulation reference signal (DMRS) (e.g., the configuration or placement of the DMRS, which may affect the accuracy of channel estimation on the frequency-time grid). However, this is merely an example, and the embodiments are not limited thereto. The quality of multiple resource elements can be measured indirectly by using more information about factors that may affect the quality of at least one particular resource element.

[0045] In one or more embodiments, the decoding circuit 112 may allocate a maximum number of decoding iterations per code block to decode multiple code blocks in a codeword corresponding to a target time slot. That is, the decoding circuit 112 may individually allocate a maximum number of decoding iterations applicable to each of the multiple code blocks. As used herein, the maximum number of decoding iterations represents the maximum number of iterations that can be performed until the code block is successfully decoded (e.g., an upper limit on the number of attempts allowed to successfully decode a given code block). For example, when a code block is allocated a maximum of 10 decoding iterations, decoding may be repeated up to 10 times until decoding of the code block is successfully performed. However, if decoding fails after all 10 iterations, it can be determined that decoding for the code block has failed. Furthermore, if decoding for the code block is successfully completed before 10 iterations, the iteration may be terminated, and it can be determined that decoding of the code block has been successfully completed.

[0046] In one or more embodiments, the decoding circuit 112 may allocate a maximum number of decoding iterations for each of a plurality of code blocks corresponding to a codeword in a target time slot based on the quality of a plurality of resource elements and the RE-CB mapping pattern corresponding to the target time slot. For example, the decoding circuit 112 may identify resource elements corresponding to each of a plurality of code blocks corresponding to a codeword in a target time slot based on the RE-CB mapping pattern corresponding to the target time slot. In a specific example, the decoding circuit 112 may check the quality of code blocks in a target time slot based on the quality of a plurality of resource elements and the RE-CB mapping pattern corresponding to the target time slot, and may allocate the maximum number of decoding iterations per code block in a specific manner according to the quality of the checked code blocks. For example, the decoding circuit 112 may allocate a smaller maximum number of decoding iterations to code blocks identified as having good quality, and may allocate a larger maximum number of decoding iterations to code blocks identified as having poor quality. For example, the decoding circuit 112 may set an upper limit and a lower limit for the maximum number of decoding iterations, and allocate the maximum number of decoding iterations per code block within the range defined by the upper and lower limits. For example, when the quality of a code block is determined to be very poor, the decoding circuit 112 can allocate a very small maximum number of decoding iterations, thus minimizing the number of decoding iterations for code blocks that are clearly expected to fail. Furthermore, for example, the decoding circuit 112 can be configured to ensure that the difference between the maximum number of decoding iterations allocated to a code block identified as having the worst quality and the maximum number of decoding iterations allocated to a code block identified as having the best quality does not exceed a threshold. In other words, the decoding circuit 112 can be configured to limit the difference in the maximum number of decoding iterations allocated between the highest quality code block and the lowest quality code block to a predefined threshold.

[0047] In some embodiments, the decoding circuit 112 may also allocate the maximum number of decoding iterations for each of a plurality of code blocks applicable to the codeword corresponding to the target time slot based on factors other than the quality of the plurality of resource elements. For example, the decoding circuit 112 may adaptively allocate the maximum number of decoding iterations per code block according to channel variations or characteristics by using a constructed and trained neural network model.

[0048] In one or more embodiments, the decoding circuit 112 may use the memory 140 when decoding code blocks.

[0049] In one or more embodiments, the baseband processor 110 and memory 140 may be integrated into the modem chip. In some embodiments, the transceiver 120 and interface circuitry 130 may be integrated into the RF chip, and the modem chip and RF chip may be integrated into a system-on-a-chip.

[0050] As used herein, the decoding circuit 112 may be implemented as hardware specifically for performing the operations according to the embodiments, as software as a collection of multiple codes or commands executed by the baseband processor 110, or as a combination of hardware and software. Therefore, the operation of the decoding circuit 112 can be understood as the operation of the baseband processor 110, the modem chip, or the electronic device 100.

[0051] According to one or more embodiments, the decoding circuit 112 can allocate the maximum number of decoding iterations per code block based on the quality of multiple resource elements, thereby performing the decoding operation efficiently. As a result, the decoding performance of the decoding circuit 112 can be improved, and the resources of the decoding circuit 112 can be used efficiently.

[0052] Figure 2A This is a diagram showing the basic structure of the time-frequency domain as a radio resource area. Figure 2B It is a diagram showing the time slot structure, and Figure 2C This is a diagram showing the resource elements of a time slot.

[0053] Reference Figure 2A The horizontal axis represents the time domain (or symbol domain), and the vertical axis represents the frequency domain (or subcarrier domain). The smallest transmission unit in the time domain is an orthogonal frequency division multiplexing (OFDM) symbol, and N SYMB OFDM symbols 202 can be grouped to form a single time slot 206. Two time slots can be grouped to form a single subframe 205. For example, the length of time slot 206 can be 0.5 ms, and the length of subframe 205 can be 1.0 ms. However, this is just an example. The length of time slot 206 can vary depending on the configuration of time slot 206, and the number of time slots 206 in subframe 205 can vary depending on the length of time slot 206. Furthermore, in an NR network, the time-frequency domain can be defined based on time slot 206. Additionally, radio frame 214 can be a time-domain unit comprising ten subframes 205.

[0054] The smallest transmission unit in the frequency domain is a subcarrier, and the width of the entire system's transmission bandwidth can include a total of N. BW - Subcarrier 204. In the time-frequency domain, the basic unit of a resource is resource element 212, which can be represented by OFDM symbol index and subcarrier index. Resource block 208 can be defined as a continuous N in the time domain. SYMB -OFDM symbol 202 and continuous N in the frequency domain RB - Subcarrier 210. Therefore, a resource block 208 may include (N SYMB ×N RB ) resource elements 212. A pair of resource blocks is a unit of two resource blocks connected to each other on the timeline, and may include (N) SYMB ×2NRB 212 resource elements.

[0055] Furthermore, the electronic device 100 can be accessed via (e.g., as in...) Figure 2A Radio resources in the time-frequency domain (like those in the example) communicate with base stations or other electronic devices. For example, electronic device 100 can allocate the maximum number of decoding iterations per code block based on the quality of resource element 212.

[0056] Further reference Figure 2B A radio frame 300 may have a duration of 10 ms, a subframe 301 may have a duration of 1 ms, and a radio frame 300 may include a total of 10 subframes 301. Each of time slots 302 and 303 may include 14 OFDM symbols (i.e., the number of symbols per time slot (...)). =14). A subframe 301 may include one or more time slots 302 and 303, and the number of time slots 302 and 303 in each subframe 301 may be determined according to a setting value regarding the subcarrier spacing (or subcarrier spacing setting value or setting value for subcarrier spacing). The number of symbols included in time slots 302 and 303 varies, as do the number of symbols in slots 304 and 305. Figure 2B The subcarrier spacing setting value is shown. (304) and (305) Case. When the subcarrier spacing setting value (304) In this case, a subframe 301 may include a time slot 302. Furthermore, when the subcarrier spacing is set to a certain value... (305) When a subframe 301 may include two time slots 303.

[0057] As mentioned above, the number of time slots per subframe can be determined based on the setting value for the subcarrier spacing (( The number of time slots per radio frame can vary, and therefore, the number of time slots per radio frame can also vary. The settings for each subcarrier interval can be defined in [Table 1]. The number of time slots in each subframe () ) and the number of time slots per frame ( ).

[0058] [Table 1]

[0059] Furthermore, in some embodiments, the number of time slots per subframe can vary depending on the number of symbols included in a single time slot. For example, setting a value ( It can have any of the values ​​“0, 1, 2, 3 and 4”, and these values ​​can represent “15kHz, 30kHz, 60kHz, 120kHz and 240kHz” respectively.

[0060] Time slots 302 and 303 can be configured according to the settings for each subcarrier interval ( They have different lengths, and the embodiments can be applied to time slots 302 and 303.

[0061] Reference Figure 2C The horizontal axis can represent the symbol domain (or time domain), and the vertical axis can represent the subcarrier domain (or frequency domain). A time slot SLOT has a configuration comprising seven symbols, and resource elements #0 through #69 (1st to 70th) can be mapped to the time slot SLOT. Codewords corresponding to a specific primary carrier and a specific Hybrid Automatic Repeat Request (HARQ) identifier (ID) can be arranged in the time slot SLOT. The code blocks of the corresponding codewords are mapped to resource elements #0 through #69 (1st to 70th), and the corresponding codewords can be transmitted via resource elements #0 through #69 (1st to 70th). That is, the corresponding codewords can be transmitted via radio resources comprising seven consecutive symbols in the symbol domain and ten consecutive subcarriers in the subcarrier domain.

[0062] Figure 3 This is a diagram illustrating the codeword CW according to one or more embodiments.

[0063] Reference Figure 3 The codeword CW may include a transport block TB and a transport block cyclic redundancy check (TBCRC) bit appended to the end of the transport block TB to determine whether the transport block TB has been successfully decoded by the receiving side (or receiving device). Furthermore, the codeword CW may include first code blocks CB#0 to the m-th code block CB#(m-1). Each of the first code blocks CB#0 to the m-th code block CB#(m-1) may include a CRC bit appended to the end of the code block to determine whether the code block has been successfully decoded by the receiving side (or receiving device).

[0064] In one or more embodiments, Figure 1 The decoding circuit 112 can allocate a maximum number of decoding iterations individually for each of the first code block CB#0 to the m-th code block CB#(m-1) based on the quality of the resource element where the codeword CW is located.

[0065] Figure 4 This is a block diagram showing in detail a decoding circuit 200 according to one or more embodiments.

[0066] Reference Figure 4 The decoding circuit 200 may include a quality measurement circuit 210, a decoding iteration control circuit 220, and a RE-CB mapping table 230.

[0067] In one or more embodiments, the quality measurement circuit 210 can measure quality on a resource element basis. For example, the quality measurement circuit 210 can measure the quality of a resource element (e.g., directly) based on the result of decoding multiple code blocks corresponding to a monitoring interval. In one specific example, the decoding result may include at least one of the following: a result regarding whether decoding for multiple code blocks has failed, and a result regarding whether decoding for multiple code blocks has been prematurely terminated. The quality measurement circuit 210 may refer to the RE-CB mapping table 230 to convert the decoding result on a code block basis to a result on a resource element basis, and then quantize the converted result numerically to measure the quality of each resource element. Furthermore, for example, the quality measurement circuit 210 can indirectly measure the quality of multiple resource elements based on information associated with the quality of multiple resource elements. In one specific example, the quality measurement circuit 210 can indirectly measure the quality of multiple resource elements based on at least one of the following: first information regarding the center frequency, second information regarding the time slot changing from uplink to downlink, third information regarding resource elements located at the edge of the frequency axis, and fourth information regarding the arrangement of the DMRS. In some embodiments, the quality measurement circuit 210 can measure the quality of multiple resource elements by using both the direct measurement method and the indirect measurement method described above.

[0068] In one or more embodiments, the decoding iteration control circuit 220 may allocate the maximum number of decoding iterations per code block based on the quality of multiple resource elements measured by the quality measurement circuit 210. For example, the decoding iteration control circuit 220 may reference the RE-CB mapping pattern of multiple code blocks (e.g., multiple code blocks of a target codeword corresponding to a target time slot) from the RE-CB mapping table 230, and may check the quality of the multiple code blocks corresponding to the target time slot based on the referenced RE-CB mapping pattern and the quality of the multiple resource elements. The decoding iteration control circuit 220 may allocate the maximum number of decoding iterations per code block based on the checked quality of the multiple code blocks. For example, the decoding iteration control circuit 220 may set a weight for each code block defined by a specific equation, and allocate the maximum number of decoding iterations per code block based on the result of the setting. For example, the specific equation may be designed to ensure stable decoding execution by setting an upper or lower limit on the maximum number of decoding iterations or by limiting the difference in the maximum number of decoding iterations between code blocks to less than a threshold.

[0069] also, Figure 4 The configuration of the decoding circuit 200 shown is merely an example illustrating an embodiment. Therefore, the embodiment is not limited thereto, and the decoding circuit 200 can be formed in other configurations. Furthermore, the operation of the quality measurement circuit 210 and the decoding iteration control circuit 220 can be understood as the operation of the decoding circuit 200.

[0070] Figure 5 This is a flowchart illustrating a method of operating a decoding circuit according to one or more embodiments. Furthermore, Figure 5 The operation of the decoding circuit in the text can be understood as the operation of the baseband processor, modem chip, or electronic device that includes the decoding circuit.

[0071] Reference Figure 5 In operation S100, the decoding circuit can measure the quality of each resource element based on the result of decoding the code blocks in the monitoring interval. For example, the decoding circuit can convert the decoding result of each code block into the decoding result of each resource element based on the RE-CB mapping mode of the code blocks in the monitoring interval, and then perform numerical quantization on the converted result to measure the quality of each resource element.

[0072] In operation S110, the decoding circuit may allocate the maximum number of decoding iterations per code block based on the measurement results from operation S100. For example, the decoding circuit may check the quality of each code block in the code block corresponding to the target time slot from the quality of each resource element included in the measurement results, based on the RE-CB mapping pattern corresponding to the target time slot (or the RE-CB mapping pattern corresponding to the codeword located in the target time slot). The decoding circuit may allocate the maximum number of decoding iterations per code block based on the quality of each identified code block.

[0073] Furthermore, in operation S120, the decoding circuit can decode the codeword located in the target time slot based on the allocation result in operation S110. For example, the decoding circuit can decode per code block based on the maximum number of decoding iterations allocated for each of the multiple code blocks of the codeword located in the target time slot. When decoding is successfully performed on a code block basis, the decoding circuit can... Figure 3 The TBCRC bit in the codeword is used to determine whether the transport block of the codeword has been successfully decoded.

[0074] Figure 6 This is a diagram illustrating the monitoring interval MP#0 according to one or more embodiments, and Figure 7 It is shown in Figure 6 The flowchart shows the method of operating the decoding circuit 200 and the quality measurement circuit 210 in the monitoring interval MP#0. Figure 7 Show Figure 5 A specific embodiment of operation S100.

[0075] Reference Figure 6 The monitoring interval MP#0 may include the first time slot to the third time slot SLOT#0, SLOT#1 and SLOT#2. The monitoring interval MP#0 may be preset to include three time slots, and the length of the monitoring interval MP#0 may vary.

[0076] The first codeword located in the first time slot SLOT#0 may include code blocks CB#0 to CB#13 (code blocks 1 to 14); the second codeword located in the second time slot SLOT#1 may include code blocks CB#0 to CB#7 (code blocks 1 to 8); and the third codeword located in the third time slot SLOT#2 may include code blocks CB#0 to CB#10 (code blocks 1 to 11). The first codeword may have a first RE-CB mapping pattern corresponding to a first HARQ ID, the second codeword may have a second RE-CB mapping pattern corresponding to a second HARQ ID, and the third codeword may have a third RE-CB mapping pattern corresponding to a third HARQ ID. Furthermore, it is assumed that the first to third codewords correspond to the same primary carrier.

[0077] In the first codeword of the first time slot SLOT#0, according to the first RE-CB mapping pattern, the first code block CB#0 can be mapped to resource elements #0 to #4, the second code block CB#1 can be mapped to resource elements #5 to #9, the third code block CB#2 can be mapped to resource elements #10 to #14, the fourth code block CB#3 can be mapped to resource elements #15 to #19, the fifth code block CB#4 can be mapped to resource elements #20 to #24, the sixth code block CB#5 can be mapped to resource elements #25 to #29, and the seventh code block CB#6 can be mapped to resource elements #30 to #35. Resource element #34, code block 8 CB#7 can be mapped to resource elements #36 #35 to #40 #39, code block 9 CB#8 can be mapped to resource elements #41 #40 to #45 #44, code block 10 CB#9 can be mapped to resource elements #46 #45 to #50 #49, code block 11 CB#10 can be mapped to resource elements #51 #50 to #55 #54, code block 12 CB#11 can be mapped to resource elements #56 #55 to #60 #59, code block 13 CB#12 can be mapped to resource elements #61 #60 to #65 #64, and code block 14 CB#13 can be mapped to resource elements #66 #65 to #70 #69.

[0078] In the second codeword of the second time slot SLOT#1, according to the second RE-CB mapping mode, the first code block CB#0 can be mapped to the first resource element #0 to the eighth resource element #7, the second code block CB#1 can be mapped to the ninth resource element #8 to the sixteenth resource element #15, the third code block CB#2 can be mapped to the seventeenth resource element #16 to the twenty-fourth resource element #23, the fourth code block CB#3 can be mapped to the twenty-fifth resource element #24 to the thirty-second resource element #31, the fifth code block CB#4 can be mapped to the thirty-third resource element #32 to the fortyth resource element #39, the sixth code block CB#5 can be mapped to the forty-first resource element #40 to the forty-eighth resource element #47, the seventh code block CB#6 can be mapped to the forty-ninth resource element #48 to the fifty-sixth resource element #55, and the eighth code block CB#7 can be mapped to the fifty-seventh resource element #56 to the sixty-fourth resource element #63.

[0079] Furthermore, in the third codeword of the third time slot SLOT#2, according to the third RE-CB mapping mode, the first code block CB#0 can be mapped to resource elements #0 to #5, the second code block CB#1 can be mapped to resource elements #6 to #11, the third code block CB#2 can be mapped to resource elements #12 to #17, the fourth code block CB#3 can be mapped to resource elements #18 to #23, the fifth code block CB#4 can be mapped to resource elements #24 to #29, and the sixth code block C... B#5 can be mapped to resource elements #30 to #35 of resource elements #31, CB#6 of code block #7 can be mapped to resource elements #36 to #41 of resource elements #42, CB#7 of code block #8 can be mapped to resource elements #42 to #47 of resource elements #43, CB#8 of code block #9 can be mapped to resource elements #48 to #53 of resource elements #54, CB#9 of code block #10 can be mapped to resource elements #54 to #59 of resource elements #60, and CB#10 of code block #11 can be mapped to resource elements #60 to #65 of resource elements #61.

[0080] Further reference Figure 7 In operation S10, the decoding circuit 200 can decode the first code block CB#0 to the 14th code block CB#13 in the first time slot SLOT#0. For example, the decoding circuit 200 can sequentially perform decoding operations for error correction on each code block from the first code block CB#0 to the 14th code block CB#13.

[0081] In operation S101, the quality measurement circuit 210 can generate a measurement result by numerically quantizing the quality of each resource element based on whether decoding failures have occurred for the first code block CB#0 to the 14th code block CB#13 (or based on whether decoding failures have occurred for the first code block CB#0 to the 14th code block CB#13 and the first RE-CB mapping pattern corresponding to the first time slot SLOT#0). In a specific example, the quality measurement circuit 210 can identify the resource elements of the code blocks mapped to the first code block CB#0 to the 14th code block CB#13 that have failed to be decoded based on the first RE-CB mapping pattern, and can generate a measurement result by using the numerically quantized value for each of the identified resource elements based on the decoding failure.

[0082] Furthermore, if a code block fails to be decoded in the first time slot SLOT#0, the decoding circuit 200 may request a retransmission of the code block from the base station or another electronic device.

[0083] In operation S20, the decoding circuit 200 can decode the first code block CB#0 to the eighth code block CB#7 of the second time slot SLOT#1. For example, the decoding circuit 200 can sequentially perform decoding operations for error correction on each code block from the first code block CB#0 to the eighth code block CB#7.

[0084] In operation S102, the quality measurement circuit 210 can numerically quantize the quality of each resource element based on whether decoding failures have occurred for the first code block CB#0 to the eighth code block CB#7 as identified in operation S20 (or based on whether decoding failures have occurred for the first code block CB#0 to the eighth code block CB#7 and the second RE-CB mapping mode corresponding to the second time slot SLOT#1), and can accumulate the numerically quantized quality in the measurement results. In a specific example, the quality measurement circuit 210 can identify the resource elements of the code blocks mapped to the first code blocks CB#0 to the eighth code blocks CB#7 that have failed to decode based on the second RE-CB mapping mode, and can accumulate (or update) the measurement results by using the numerically quantized value for each of the identified resource elements based on the decoding failure. Furthermore, when a code block has failed to decode in the second time slot SLOT#1, the decoding circuit 200 can request a retransmission of the code block from the base station or another electronic device.

[0085] In operation S30, the decoding circuit 200 can decode the first code block CB#0 to the eleventh code block CB#10 of the third time slot SLOT#2. For example, the decoding circuit 200 can sequentially perform decoding operations for error correction on each code block from the first code block CB#0 to the eleventh code block CB#10.

[0086] In operation S103, the quality measurement circuit 210 can numerically quantize the quality of each resource element based on whether decoding failure occurred for the first code block CB#0 to the eleventh code block CB#10 as identified in operation S30 (or based on whether decoding failure occurred for the first code block CB#0 to the eleventh code block CB#10 and the third RE-CB mapping mode corresponding to the third time slot SLOT#2), and can accumulate the numerically quantized quality in the measurement results. In a specific example, the quality measurement circuit 210 can identify the resource elements of the code blocks mapped to the first code block CB#0 to the eleventh code block CB#10 that have failed to decode based on the third RE-CB mapping mode, and can accumulate (or update) the measurement results by using the numerically quantized value for each of the identified resource elements based on the decoding failure. Furthermore, when a code block has failed to decode in the third time slot SLOT#2, the decoding circuit 200 can request a retransmission of the code block from the base station or another electronic device.

[0087] Figure 8A This is a diagram illustrating an example of the decoding results of the monitoring interval MP#0 according to one or more embodiments, and Figure 8B It shows the basis Figure 8A A diagram illustrating the quality measurement method for resource elements resulting from decoding. Furthermore, it is assumed that... Figure 8B The measurement results MRa, MRb, MRc and Figure 6 The first resource element #0 to the 69th resource element #68 correspond to this.

[0088] Reference Figure 8A In the first time slot SLOT#0, code blocks CB#0 (1st block), CB#2 (3rd block), CB#4 (5th block), CB#6 (7th block), CB#8 (9th block), CB#10 (11th block), and CB#12 (13th block) can be determined as having failed to decode. Furthermore, the remaining code blocks (CB#1, CB#3, CB#5, CB#7, CB#9, CB#11, and CB#13) can be determined as having been successfully decoded.

[0089] In the second time slot SLOT#1, code blocks CB#0, CB#1, CB#2, CB#5, CB#6, and CB#7 can be determined as having failed to decode. Furthermore, the remaining code blocks (CB#3 and CB#4) can be determined as having been successfully decoded.

[0090] Furthermore, in the third time slot SLOT#2, code blocks CB#0 (1st block), CB#3 (4th block), CB#6 (7th block), CB#8 (9th block), and CB#10 (11th block) can be determined as having failed to decode. Additionally, the remaining code blocks (CB#1, CB#2, CB#4, CB#5, CB#7, and CB#9) can be determined as having been successfully decoded.

[0091] Further reference Figure 8B In the first operation STEP#00, based on the decoding result of the first time slot SLOT#0 and the first RE-CB mapping mode, the quality measurement circuit 210 ( Figure 7 The value “1”, which is quantized to indicate decoding failure, can be applied to the resource elements (#0 to #4, #10 to #14, #20 to #24, #30 to #34, #40 to #44, #50 to #54, and #60 to #64) mapped to the code blocks (CB#0, CB#2, CB#4, CB#6, CB#8, CB#10, and CB#12) that have failed to decode, thereby generating the measurement result MRa.

[0092] In the second operation STEP#10, based on the decoding result of the second time slot SLOT#1 and the second RE-CB mapping mode, the quality measurement circuit 210 ( Figure 7 The value quantized to represent the decoding failure value "1" can be accumulated in the resource elements (#0 to #7, #8 to #15, #16 to #23, #40 to #47, #48 to #55, and #56 to #63) mapped to the code blocks (CB#0, CB#1, CB#2, CB#5, CB#6, and CB#7) to update the measurement result MRb.

[0093] Furthermore, in the third operation STEP#20, based on the decoding result of the third time slot SLOT#2 and the third RE-CB mapping mode, the quality measurement circuit 210 ( Figure 7 The value “1” representing the decoding failure can be accumulated in the resource elements (#0 to #5, #18 to #23, #36 to #41, #40 to #47, #48 to #53 and #60 to #65) mapped to the code blocks (CB#0, CB#3, CB#6, CB#8 and CB#10) to update the measurement result MRc by quantizing the values ​​to represent the decoding failure.

[0094] Quality measurement circuit 210 ( Figure 7 The quality of resource elements #0 to #69 (1st to 70th) can be measured based on the decoding results of multiple code blocks (CB#0 to CB#13, CB#0 to CB#7, and CB#0 to CB#10) in the monitoring interval MP#0. The generated measurement result MRc is then provided to the decoding iteration control circuit 220. Figure 7 ).

[0095] Figure 9 It is shown Figure 5 A flowchart of a specific embodiment of operation S110.

[0096] Reference Figure 9 In operation S111, the decoding circuit can identify the RE-CB mapping pattern corresponding to the target time slot. For example, the decoding circuit can identify the RE-CB mapping pattern from RE-CB mapping table 230 ( Figure 4 Obtain the RE-CB mapping pattern that matches the HARQID of the code block (or codeword) located in the target time slot.

[0097] In operation S112, the decoding circuit can be based on Figure 5 The measurement results in operation S100 are used to allocate the maximum number of decoding iterations for each code block in the code block corresponding to the target time slot. For example, the decoding circuit can check the quality of each code block based on the RE-CB mapping mode of the code block located in the target time slot and the measurement results, and can allocate the maximum number of decoding iterations for each code block based on the quality of each code block.

[0098] Figure 10A This is a diagram illustrating target time slot SLOT#3 according to one or more embodiments, and Figure 10B This shows the generation representation and Figure 10A A diagram illustrating the method for measuring the quality (MRd) of each code block in code blocks CB#0 to CB#13 (corresponding to target time slot SLOT#3). Assume... Figure 10A and Figure 10B The target slot SLOT#3 is Figure 6 The time slot following the monitoring interval MP#0.

[0099] Reference Figure 10A The fourth codeword located in target time slot SLOT#3 may include code blocks CB#0 to CB#16 (code blocks 1 through 17), and the fourth codeword may correspond to the fourth HARQ ID, thus having a fourth RE-CB mapping mode. Furthermore, it is assumed that the fourth codeword corresponds to... Figure 6 The primary carrier corresponding to the first to third codewords in the code.

[0100] In the fourth codeword of target time slot SLOT#3, according to the fourth RE-CB mapping mode, the first code block CB#0 can be mapped to resource elements #0 to #3, the second code block CB#1 can be mapped to resource elements #4 to #7, the third code block CB#2 can be mapped to resource elements #8 to #11, and the fourth code block CB#3 can be mapped to resource elements #12 to #16. #15, the 5th code block CB#4 can be mapped to resource elements #17 through #19, the 6th code block CB#5 can be mapped to resource elements #20 through #24, the 7th code block CB#6 can be mapped to resource elements #24 through #27, the 8th code block CB#7 can be mapped to resource elements #28 through #31, and the 9th code block CB#8 can be mapped to the resource elements #15 through #24, the 25th code block CB#4 can be mapped to resource elements #16 through #27, the 28th code block CB#7 can be mapped to resource elements #28 through #31, and the 9th code block CB#8 can be mapped to the resource elements #19 through #24, the 25th code block CB#4 can be mapped to resource elements #19, the 20th code block CB#5 can be mapped to resource elements #21 through #23, the 24th code block CB#4 can be mapped to resource elements #24 through #27, the 25th code block CB#6 can be mapped to resource elements #24 through #27, the 28th code block CB#7 can be mapped to resource elements #28 through #22, the 23rd code block CB#4 can be mapped to resource elements #19, the 20th ... Resource elements 33#32 to 36#35, and code block CB#9 can be mapped to resource elements 37#36 to 40#39; code block CB#10 can be mapped to resource elements 41#40 to 44#43; code block CB#11 can be mapped to resource elements 45#44 to 48#47; and code block CB#12 can be mapped to resource elements 49#48 to 49# ... Resource element #51 (52), code block CB#13 (14) can be mapped to resource elements #52 (53) to #55 (56), code block CB#14 (15) can be mapped to resource elements #56 (57) to #59 (60), code block CB#15 (16) can be mapped to resource elements #60 (61) to #63 (64), and code block CB#16 (17) can be mapped to resource elements #64 (65) to #67 (68).

[0101] Further reference Figure 10B Decoding Iteration Control Circuit 220 ( Figure 4 ) can be based on Figure 8B The measurement result MRc and the fourth RE-CB mapping mode are used to generate a measurement result MRd representing the quality of the first code block CB#0 to the 17th code block CB#16 corresponding to the target time slot. Specifically, the quality of the first code block CB#0 can be defined as "12", where "12" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #0 to #3 in the first resource element () and the quality of the second code block CB#1 can be defined as "7", where "7" is the ... Figure 8B The sum of the values ​​corresponding to resource elements #4 to #7 of resource element #5 in the code block CB#2, the quality of code block CB#2 can be defined as "6", where "6" is the measurement result MRc ( Figure 8BThe sum of the values ​​corresponding to resource elements #8 to #11 of resource elements #12 in the 4th code block CB#3, the quality of the 4th code block CB#3 can be defined as "7", where "7" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #12 to #15 of resource element #13 in the 5th code block CB#4 can be defined as "6", where "6" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #16 to #19 of resource element #17 in the code block CB#5, the quality of code block 6 can be defined as "12", where "12" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #20 to #23 of resource element #21 in the ) indicates that the quality of code block CB#6 of code 7 can be defined as "1", where "1" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #24 to #27 of resource elements #25 in the ) indicates that the quality of code block CB#7 can be defined as "4", where "4" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #28 to #31 of resource element #29 in the ) indicates that the quality of code block CB#8 can be defined as "7", where "7" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #32 to #35 of resource element #33 in the 10th code block CB#9 can be defined as "0", where "0" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #37 to #40 in the ) is used to define the quality of code block CB#10 as "8", where "8" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #40 to #43 of resource element #41 in the ) indicates that the quality of code block CB#11 can be defined as "5", where "5" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #44 to #47 of resource elements #45 in the ) indicates that the quality of code block CB#12 of code 13 can be defined as "10", where "10" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #48 to #51 (49th resource element) in the code block CB#13, the quality of code block CB#13 can be defined as "9", where "9" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #52 to #55 of resource element #53 in the ), the quality of code block CB#14 can be defined as "4", where "4" is the measurement result MRc ( Figure 8BThe sum of the values ​​corresponding to resource elements #57 to #60 in the ) is used to define the quality of code block CB#15 as "12", where "12" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #60 to #63 of resource element #61 in the ) indicates that the quality of code block CB#16 of code 17 can be defined as "3", where "3" is the measurement result MRc ( Figure 8B The sum of the values ​​corresponding to resource elements #64 to #67 of resource element #65 in the resource element 65.

[0102] Based on the above method, the measurement result MRc (representing the quality of resource elements) can be obtained from the above method. Figure 8B Derive the measurement result MRd, which represents the quality of the code block in the target time slot.

[0103] In one or more embodiments, the decoding iteration control circuit 220 ( Figure 4 The maximum number of decoding iterations can be allocated for each of the 1st to 17th code blocks CB#16 based on the quality of the first code block CB#0 to the 17th code block CB#16. For example, based on the fact that the quality of the first code block CB#0 is "12" worse than the quality of the second code block CB#1 (which is "7"), the decoding iteration control circuit 220 ( Figure 4 A larger maximum number of decoding iterations can be assigned to the first code block CB#0.

[0104] Figure 11 It is shown Figure 9 The flowchart shows a specific embodiment of operation S112.

[0105] Reference Figure 11 In operation S112_1, the decoding circuit can be based on Figure 5 The measurement results of operation S100 are used to set the weight of each code block in the code block corresponding to the target time slot.

[0106] In operation S112_2, the decoding circuit can allocate the maximum number of decoding iterations for each code block in the code block corresponding to the target time slot based on the weight set for each code block.

[0107] The following reference Figure 12 This will be described in detail.

[0108] Figure 12 This is a diagram illustrating a method for allocating the maximum number of decoding iterations per code block based on a weight set per code block according to one or more embodiments.

[0109] Reference Figure 12 In the first operation STEP#01, the decoding iteration control circuit 220 ( Figure 4 ) can be based on Figure 10B The measurement result MRd and a specific equation generate the measurement result MRe, which sets the weight for each code block. The specific equation can correspond to the following equation 1. [Equation 1]

[0110] p can represent the index of the code block, Wp can represent the weight of the code block with index p, Q can represent the maximum cumulative value in the measurement result MRd due to decoding failure (e.g., "12"), and Qp can represent the value in the measurement result MRd corresponding to the code block with index p (e.g., "7" corresponding to the second code block CB#1). Equation 1 can represent an equation defined as performing an assignment such that the maximum number of decoding iterations for the code block with the best quality (e.g., CB#9) is 2:3 or close to 2:3, and the maximum number of decoding iterations for the code block with the worst quality (e.g., CB#0, CB#5, or CB#15) is 2:3. However, it should be understood that the method of setting weights according to Equation 1 is merely an example, and the embodiments are not limited thereto.

[0111] In the measurement result MRe, the weight corresponding to the first code block CB#0 can be set to "36", the weight corresponding to the second code block CB#1 can be set to "31", the weight corresponding to the third code block CB#2 can be set to "30", the weight corresponding to the fourth code block CB#3 can be set to "31", the weight corresponding to the fifth code block CB#4 can be set to "30", the weight corresponding to the sixth code block CB#5 can be set to "36", the weight corresponding to the seventh code block CB#6 can be set to "25", the weight corresponding to the eighth code block CB#7 can be set to "28", and the weight corresponding to the ninth code block CB#8 can be set to "36". The weight can be set to "31", the weight corresponding to CB#9 of code block 10 can be set to "24", the weight corresponding to CB#10 of code block 11 can be set to "32", the weight corresponding to CB#11 of code block 12 can be set to "29", the weight corresponding to CB#12 of code block 13 can be set to "34", the weight corresponding to CB#13 of code block 14 can be set to "33", the weight corresponding to CB#14 of code block 15 can be set to "28", the weight corresponding to CB#15 of code block 16 can be set to "36", and the weight corresponding to CB#16 of code block 17 can be set to "17".

[0112] In the second operation STEP#11, the decoding iteration control circuit 220 ( Figure 4 The maximum number of decoding iterations per code block can be allocated based on the measurement result MRe and a specific equation. The specific equation can correspond to the following equation 2. [Equation 2]

[0113] p can represent the index of the code block, Wp can represent the weight of the code block with index p, Z can represent the total number of decoding iterations that can be assigned to a single codeword (e.g., "200"), and Zp can represent the maximum number of decoding iterations assigned to the code block with index p. Furthermore, the decoding iteration control circuit 220 ( Figure 4 The maximum number of decoding iterations per code block can be increased by an increment of "1" in a specific order until all remaining iterations have been consumed after the allocation based on Equation 2. For example, decoding iteration control circuit 220 ( Figure 4 The remaining number of iterations can be allocated by sequentially assigning "1" additional iterations to code blocks ordered from the code block with the smallest maximum number of decoding iterations allocated to the code block with the largest maximum number of decoding iterations allocated. For example, decoding iteration control circuit 220 ( Figure 4 The remaining number of iterations can be consumed by sequentially assigning "1" additional iterations to the code blocks listed from the code block with the lowest (or highest) index to the code block with the highest (or lowest) index.

[0114] Based on Equations 1 and 2, as shown in the result of the allocation AR in the second operation STEP#11, the decoding iteration control circuit 220 ( Figure 4 The maximum number of decoding iterations that can be allocated per code block. In other words, code block CB#0 can be allocated "20" iterations, code block CB#1 can be allocated "18" iterations, code block CB#2 can be allocated "18" iterations, code block CB#3 can be allocated "18" iterations, code block CB#4 can be allocated "17" iterations, code block CB#5 can be allocated "20" iterations, code block CB#6 can be allocated "15" iterations, code block CB#7 can be allocated "17" iterations, and code block CB#8 can be allocated "17" iterations. In the next iteration, block 10 (CB#9) can be assigned "14" iterations, block 11 (CB#10) can be assigned "18" iterations, block 12 (CB#11) can be assigned "17" iterations, block 13 (CB#12) can be assigned "19" iterations, block 14 (CB#13) can be assigned "19" iterations, block 15 (CB#14) can be assigned "17" iterations, block 16 (CB#15) can be assigned "20" iterations, and block 17 (CB#16) can be assigned "16" iterations.

[0115] Furthermore, using Equations 1 and 2, the upper limit of the maximum number of decoding iterations can be set to "20", and the lower limit can be set to "14". Therefore, the difference between the maximum and minimum number of maximum decoding iterations can be controlled to not exceed "6". As a result, stable and reliable decoding operations can be guaranteed.

[0116] To perform stable and reliable decoding operations, a decoding iteration control circuit 220 according to one or more embodiments ( Figure 4 The measurement result MRd can be corrected based on a specific equation, and then the maximum number of decoding iterations per code block can be allocated based on the corrected measurement result MRe.

[0117] In some embodiments, the maximum number of decoding iterations per code block can be determined based on the weights according to Equation 3. [Equation 3]

[0118] p can represent the index of the code block, and Qp' can represent the value corresponding to the code block with index p. Mp This can represent the maximum cumulative value caused by decoding failures. Y This can represent the total number of time slots in the monitoring interval. i It can represent the index of a time slot, and Mi This can be expressed as due to time slots i The cumulative value resulting from decoding failures corresponding to the p-code block is Qp'. As Qp' increases, the quality of the p-code block deteriorates, which can represent a high probability of decoding failure. Qp' can be used as a weight (which will be used as the basis for allocating the maximum number of decoding iterations per code block), or it can be used as a flag to increase the maximum number of decoding iterations for a code block when Qp' is greater than a certain threshold.

[0119] However, this is merely an example, and the embodiments may be implemented in other embodiments.

[0120] Figure 13 It is shown in Figure 6 The flowchart shows the method of operating the decoding circuit 200 and the quality measurement circuit 210 in the monitoring interval MP#0. Figure 13 Show Figure 5 A specific embodiment of operation S100.

[0121] Reference Figure 13 In operation S10, the decoding circuit 200 can decode the first code block CB#0 to the 14th code block CB#13 in the first time slot SLOT#0. For example, the decoding circuit 200 can sequentially perform decoding operations for error correction on each code block from the first code block CB#0 to the 14th code block CB#13.

[0122] In operation S101', the quality measurement circuit 210 can generate a measurement result by numerically quantizing the quality of each resource element based on whether the decoding of the first code block CB#0 to the 14th code block CB#13 has been prematurely terminated (or based on whether the decoding of the first code block CB#0 to the 14th code block CB#13 has been prematurely terminated and the first RE-CB mapping mode). In a specific example, the quality measurement circuit 210 can identify the resource elements of the code blocks mapped to the first code blocks CB#0 to the 14th code blocks CB#13 whose decoding has been prematurely terminated based on the first RE-CB mapping mode, and can generate a measurement result by using the numerically quantized value for each of the identified resource elements according to the premature termination of decoding.

[0123] In operation S20, the decoding circuit 200 can decode the first code block CB#0 to the eighth code block CB#7 of the second time slot SLOT#1. For example, the decoding circuit 200 can sequentially perform decoding operations for error correction on each code block from the first code block CB#0 to the eighth code block CB#7.

[0124] In operation S102', the quality measurement circuit 210 can numerically quantize the quality of each resource element based on whether the decoding of the first code block CB#0 to the eighth code block CB#7 has been prematurely terminated (or based on whether the decoding of the first code block CB#0 to the eighth code block CB#7 has been prematurely terminated and the second RE-CB mapping mode) identified in operation S20, and can accumulate the numerically quantized quality in the measurement results. In a specific example, the quality measurement circuit 210 can identify the resource elements of the code blocks mapped to the first code block CB#0 to the eighth code block CB#7 whose decoding has been prematurely terminated based on the second RE-CB mapping mode, and can accumulate (or update) the measurement results by using the numerically quantized value for each of the identified resource elements according to the premature termination of decoding.

[0125] In operation S30, the decoding circuit 200 can decode the first code block CB#0 to the eleventh code block CB#10 of the third time slot SLOT#2. For example, the decoding circuit 200 can sequentially perform decoding operations for error correction on each code block from the first code block CB#0 to the eleventh code block CB#10.

[0126] In operation S103', the quality measurement circuit 210 can numerically quantize the quality of each resource element based on whether the decoding of the first code block CB#0 to the eleventh code block CB#10 has been prematurely terminated (or based on whether the decoding of the first code block CB#0 to the eleventh code block CB#10 has been prematurely terminated and the third RE-CB mapping mode corresponding to the third time slot SLOT#2), and can accumulate the numerically quantized quality in the measurement results. In a specific example, the quality measurement circuit 210 can identify the resource elements of the code blocks mapped to the first code block CB#0 to the eleventh code block CB#10 whose decoding has been prematurely terminated based on the third RE-CB mapping mode, and can accumulate (or update) the measurement results by using the numerically quantized value for each of the identified resource elements according to the premature termination of decoding.

[0127] In some embodiments, the quality measurement circuit 210 can measure the quality of a resource element by considering whether the decoding of a code block has been prematurely terminated and failed, or by applying weights to the code block.

[0128] Figure 14 This is a flowchart illustrating a method of operating a decoding circuit according to one or more embodiments. Furthermore, Figure 14 The operation of the decoding circuit in the text can be understood as the operation of the baseband processor, modem chip, or electronic device that includes the decoding circuit.

[0129] Reference Figure 14 In operation S300, the decoding circuit can collect information related to the various qualities of the resource elements. For example, the decoding circuit can collect at least one of the following: first information about the center frequency, second information about the time slot that changes from uplink to downlink, third information about the resource element located at the edge based on the frequency axis, and fourth information about the arrangement of the DMRS.

[0130] In operation S310, the decoding circuit can indirectly measure the quality of each resource element based on the information collected in operation S300. For example, the decoding circuit can predict the quality difference of resource elements within a specific range around the center frequency based on first information. Based on second information, the decoding circuit can identify that the target time slot corresponds to the transition between uplink and downlink, and can predict the quality difference of resource elements located at the front end of the target time slot. The decoding circuit can predict the quality difference of resource elements located at the frequency edge based on third information. Furthermore, the decoding circuit can predict, based on fourth information, that resource elements located further from the DMRS than the critical distance have poor quality.

[0131] In operation S320, the decoding circuit can allocate the maximum number of decoding iterations per code block based on the measurement results in operation S310. For example, based on the RE-CB mapping pattern corresponding to the target time slot, the decoding circuit can identify code blocks to which resource elements measured to have poor quality have been mapped. Compared to the remaining code blocks, the decoding circuit can allocate a smaller maximum number of decoding iterations to the identified code blocks.

[0132] In operation S330, the decoding circuit can decode the codeword located in the target time slot based on the allocation result in operation S320. For example, the decoding circuit can perform per-block decoding based on the maximum number of decoding iterations allocated for each of the multiple code blocks of the codeword located in the target time slot.

[0133] Figures 15A to 15D A method for indirectly measuring the quality of resource elements #0 to #69 according to one or more embodiments is shown.

[0134] Reference Figure 15A Resource elements #4, #5, #14, #15, #24, #25, #34, #35, #44, #45, #54, #55, #64, and #65 in a predetermined range RG_CF adjacent to the center frequency of the component carrier corresponding to the codeword located in the time slot SLOT may have poor quality. Therefore, compared with other code blocks, the code block to which resource elements #4, #5, #14, #15, #24, #25, #34, #35, #44, #45, #54, #55, #64, and #65 are mapped can be assigned a larger maximum number of decoding iterations. Furthermore, a larger maximum number of decoding iterations can be allocated to code blocks to which fewer resource elements among the corresponding resource elements #4, #5, #14, #15, #24, #25, #34, #35, #44, #45, #54, #55, #64, and #65 are mapped, compared to code blocks to which fewer resource elements are mapped.

[0135] Reference Figure 15B When a time slot SLOT corresponds to a time slot transitioning from uplink to downlink, resource elements #0 to #19 in the predetermined range RG_UL2DL at the beginning of the time slot SLOT may have poor quality. Therefore, a larger maximum number of decoding iterations can be allocated to the code block to which resource elements #0 to #19 are mapped, compared to other code blocks. Furthermore, a larger maximum number of decoding iterations can be allocated to code blocks to which many resource elements #0 to #19 are mapped, compared to code blocks to which fewer resource elements are mapped.

[0136] Further reference Figure 15C Resource elements #0, #10, #20, #30, #40, #50, #60, #9, #19, #29, #39, #49, #59, and #69 within a predetermined range RG_EDGE based on the frequency axis located at the edge of the time slot SLOT may have poor quality. Therefore, compared to other code blocks, the code blocks to which resource elements #0, #10, #20, #30, #40, #50, #60, #9, #19, #29, #39, #49, #59, and #69 are mapped can be assigned a larger maximum number of decoding iterations. Furthermore, a larger maximum number of decoding iterations can be allocated to code blocks to which fewer resource elements among the corresponding resource elements #0, #10, #20, #30, #40, #50, #60, #9, #19, #29, #39, #49, #59, and #69 are mapped, compared to code blocks to which fewer resource elements among the corresponding resource elements #0, #10, #20, #30, #40, #50, #60, #9, #19, #29, #39, #49, #59, and #69 are mapped.

[0137] Further reference Figure 15D The DMRS can be located in some resource elements #10, #12, #14, #16, and #18 within the time slot SLOT. Resource elements located further from some resource elements #10, #12, #14, #16, and #18 than the critical distance may have poor quality. Therefore, a larger maximum number of decoding iterations can be allocated to the code block to which the corresponding resource element is mapped compared to other code blocks. Furthermore, a larger maximum number of decoding iterations can be allocated to the code block to which many resource elements are mapped compared to code blocks to which fewer resource elements are mapped.

[0138] Figure 16 This is a flowchart illustrating a method of operating a decoding circuit according to one or more embodiments. Furthermore, Figure 16 The operation of the decoding circuit in the text can be understood as the operation of the baseband processor, modem chip, or electronic device that includes the decoding circuit.

[0139] Reference Figure 16 In operation of the S400, the decoding circuit can measure the channel environment.

[0140] In operation S410, the decoding circuit may determine the length of the monitoring interval based on the measurement results of operation S400. For example, the length of the monitoring interval may vary depending on the channel environment. For instance, the decoding circuit may determine to extend the monitoring interval when the channel environment is measured to be changing rapidly, and to shorten the monitoring interval when the channel environment is measured to be relatively stable or changing slowly. However, this is merely an example, and the embodiments are not limited thereto. The decoding circuit may determine the length of the monitoring interval based on other methods.

[0141] Figure 17 This is a block diagram schematically illustrating a system-on-chip 900 according to one or more embodiments.

[0142] Reference Figure 17 The system-on-a-chip 900 may include a modem chip 910, a host device 920, an external memory 930, and a bus interface 940.

[0143] In one or more embodiments, external memory 930 may include memory accessible to modem chip 910 and host device 920 via bus interface 940, and may be shared by modem chip 910 and host device 920. As used herein, external memory 930 and internal memory 916 are defined relative to modem chip 910. External memory 930 may be memory physically separate from modem chip 910, and internal memory 916 may be memory located within modem chip 910.

[0144] In one or more embodiments, the host device 920 may access the external memory 930 via a bus interface 940. For example, the host device 920 may include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or other types of devices for processing data.

[0145] In one or more embodiments, the modem chip 910 may include HARQ processing circuitry 911 and internal memory 916. HARQ functionality is defined in various mobile communication standards, such as LTE and NR, and the HARQ processing circuitry 911 may support HARQ functionality according to the mobile communication standard. The HARQ processing circuitry 911 may be implemented as hardware for performing the embodiments described above, or it may be implemented as software executed by a processor within the modem chip 910. In some embodiments, the HARQ processing circuitry 911 may be implemented as a combination of software and hardware. For example, the internal memory 916 may be implemented as a volatile memory dedicated to the modem chip 910.

[0146] In one or more embodiments, the HARQ processing circuit 911 may include a code block processing circuit 912 and a codeword processing circuit 913. The code block processing circuit 912 may perform processing operations on received codewords on a code block basis, and the codeword processing circuit 913 may perform processing operations on a codeword basis based on the result of the code block-based processing performed by the code block processing circuit 912.

[0147] In one or more embodiments, the code block processing circuit 912 may include a quality measurement circuit 914 and a decoding iteration control circuit 915. As described above, the quality measurement circuit 914 may measure the quality of multiple resource elements based on the RE-CB mapping pattern. Furthermore, as described above, the decoding iteration control circuit 915 may allocate a maximum number of decoding iterations per code block based on the RE-CB mapping pattern and the quality of the multiple resource elements.

[0148] Figure 18 This is a block diagram illustrating an electronic device 1000 according to one or more embodiments.

[0149] Reference Figure 18 The electronic device 1000 may include a memory 1010, a processor 1020, an input / output controller 1040, a display 1050, an input device 1060, and a communication processor 1090. Here, the memory 1010 may be configured as multiple units. Each of the components is described below.

[0150] The memory 1010 may include a program storage device 1011 for storing programs for controlling the operation of the electronic device 1000 and a data storage device 1012 for storing data generated during the execution of the program. The data storage device 1012 may store data required for the operation of the application program 1013 and the decoding iterative control program 1014.

[0151] The program storage device 1011 may include an application program 1013 and a decoding iteration control program 1014. Here, the program in the program storage device 1011 may be represented as a set of instructions. The application program 1013 may include multiple program codes for executing various applications running on the electronic device 1000. In other words, the application program 1013 may include multiple codes (or commands) for various applications driven by the processor 1022. The decoding iteration control program 1014 may include multiple control codes for measuring the quality of resource elements according to embodiments and allocating a maximum number of decoding iterations per code block based on the measurement results.

[0152] In one or more embodiments, the processor 1022 may measure the quality of resource elements by executing a decoding iteration control program 1014, and may allocate a maximum number of decoding iterations per code block based on the measurement results. Furthermore, the RE-CB mapping mode may be referenced in the above operations.

[0153] In addition, the electronic device 1000 may include a communication processor 1090 that performs communication functions for voice and data communication. A peripheral interface 1023 controls the connections between the input / output controller 1040, the communication processor 1090, the processor 1022, and the memory interface 1021.

[0154] Input / output controller 1040 provides an interface between input / output devices (such as display 1050 and input device 1060) and peripheral device interface 1023. Display 1050 displays status information, text being typed, moving images, and still images. For example, display 1050 may display information about an application driven by processor 1022.

[0155] Input device 1060 can provide input data generated by selecting electronic device 1000 to processor 1020 via input / output controller 1040. Here, input device 1060 may include a keypad with at least one hardware button and a touchpad for sensing touch information. For example, input device 1060 can provide touch information (such as touch, touch movement, and touch release) sensed by touchpad to processor 1022 via input / output controller 1040.

[0156] Figure 19 This is a diagram illustrating a communication device configured to perform a decoding operation according to one or more embodiments.

[0157] Reference Figure 19 According to an embodiment, the modem chip included in the home gadget 2100, home appliance 2120, entertainment device 2140, and access point (AP) 2200 can perform decoding operations on a block-by-block basis after allocating a maximum number of decoding iterations per block.

[0158] In some embodiments, household gadgets 2100, home appliances 2120, entertainment devices 2140, and AP 2200 can form an Internet of Things (IoT) network system. Figure 19 The communication device shown is merely an example, and it will be understood that... Figure 19 Other communication devices not shown may also include wireless communication devices according to the embodiments.

[0159] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for operating a modem chip, the method comprising: Measure the quality of multiple resource elements allocated for receiving codewords; The maximum number of decoding iterations per code block is allocated based on the quality measurement results and the resource element-to-code block mapping pattern corresponding to the target time slot. as well as The first blocks of the target time slot are decoded based on the maximum number of decoding iterations allocated per block.

2. The method according to claim 1, wherein, The steps for measuring the quality of the plurality of resource elements include: The quality of the multiple resource elements is measured based on the results of decoding multiple code blocks corresponding to the monitoring interval prior to the target time slot.

3. The method according to claim 2, wherein, The decoding result includes one or both of the following: whether the decoding of the plurality of code blocks corresponding to the monitoring interval has failed, and whether the decoding of the plurality of code blocks corresponding to the monitoring interval has been completed before reaching the maximum number of decoding iterations for each of the plurality of code blocks.

4. The method according to claim 2, wherein, The monitoring interval includes multiple time slots.

5. The method according to claim 2, wherein, The length of the monitoring interval varies depending on the channel environment.

6. The method according to claim 2, wherein, The monitoring interval includes the first time slot and the second time slot, and The step of measuring the quality of the plurality of resource elements includes: A first measurement result is generated by numerically quantizing the quality of each resource element based on whether decoding of multiple second code blocks in the first time slot has failed and the resource element-to-code block mapping pattern corresponding to the first time slot; and The second measurement result is generated by numerically quantizing the quality of each resource element based on whether the decoding of multiple third code blocks in the second time slot has failed and the resource element-to-code block mapping mode corresponding to the second time slot, and accumulating the quantized quality for the second time slot in the first measurement result.

7. The method according to claim 2, wherein, The monitoring interval includes the first time slot and the second time slot, and The step of measuring the quality of the plurality of resource elements includes: A first measurement result is generated by numerically quantizing the quality of each resource element based on whether the decoding of multiple second code blocks in the first time slot has been completed before reaching the maximum number of decoding iterations for each of the multiple second code blocks, and the resource element-to-code block mapping pattern corresponding to the first time slot; and The second measurement result is generated by numerically quantifying the quality of each resource element based on whether the decoding of multiple third code blocks in the second time slot has been completed before reaching the maximum number of decoding iterations for each of the multiple third code blocks and the resource element-to-code block mapping pattern corresponding to the second time slot.

8. The method according to claim 1, wherein, The steps for measuring the quality of the plurality of resource elements include: Collect information related to the quality of the plurality of resource elements; and The quality of the plurality of resource elements is measured based on the information provided.

9. The method according to claim 8, wherein, The quality-related information includes at least one of the following: first information indicating the center frequency, second information indicating the time slot transition between the uplink and downlink, third information indicating resource elements located at the edge along the frequency axis, and fourth information indicating the arrangement of the demodulation reference signal.

10. The method according to claim 1, wherein, The steps for allocating the maximum number of decoding iterations per code block include: Based on the resource element-to-code block mapping pattern corresponding to the target time slot, identify the resource element among the plurality of resource elements that corresponds to each of the plurality of first code blocks; and The maximum number of decoding iterations for each of the plurality of first code blocks is allocated based on the quality of the plurality of resource elements identified in the measurement results.

11. The method according to claim 1, wherein, The steps for allocating the maximum number of decoding iterations per code block include: Based on the measurement results, a weight is set for each of the plurality of first code blocks corresponding to the target time slot; and The maximum number of decoding iterations per code block is allocated based on the result of setting the weight of each code block in the plurality of first code blocks.

12. The method according to claim 11, wherein, The maximum number of decoding iterations per code block is within a range defined by a predetermined upper and lower limit.

13. The method according to any one of claims 1 to 12, wherein, The resource element-to-code block mapping pattern corresponding to the target time slot conforms to the hybrid automatic repeat request identifier corresponding to the first codeword including the plurality of first code blocks.

14. The method according to any one of claims 1 to 12, wherein, The steps for decoding the plurality of first code blocks include: Repeated attempts are made to decode the first code block included in the plurality of first code blocks until the first code block is successfully decoded or until the maximum number of decoding iterations corresponding to the first code block is reached.

15. A modem chip, comprising: Memory; as well as The processing circuitry is configured to access memory to: The maximum number of decoding iterations per code block is allocated based on the quality of the multiple resource elements assigned for receiving codewords and the resource element-to-code-block mapping pattern corresponding to the target time slot. as well as The first blocks of the target time slot are decoded based on the maximum number of decoding iterations allocated per block.

16. The modem chip according to claim 15, wherein, The processing circuit is also configured to measure the quality of the plurality of resource elements based on the results of decoding the plurality of code blocks corresponding to the monitoring interval prior to the target time slot.

17. The modem chip according to claim 16, wherein, The decoding result includes at least one of the following: whether the decoding for the plurality of code blocks has failed, and whether the decoding for the plurality of code blocks has been completed before reaching the respective maximum number of decoding iterations for the plurality of code blocks.

18. The modem chip according to claim 15, wherein, The processing circuit is a hybrid automatic repeat request processing circuit, and is also configured to predict the quality of the plurality of resource elements based on information related to the quality of the plurality of resource elements.

19. The modem chip according to any one of claims 15 to 18, wherein, The resource element-to-code block mapping pattern corresponding to the target time slot conforms to the hybrid automatic repeat request identifier corresponding to the first codeword including the plurality of first code blocks.

20. A method of operating a modem chip, the method comprising: Decode multiple code blocks across multiple time slots; The quality of multiple resource elements is measured based on the results of decoding the multiple code blocks and the resource element-to-code block mapping pattern corresponding to each of the multiple time slots; Based on the measurement results of the multiple resource elements, allocate the maximum number of decoding iterations per code block; as well as The first blocks of the target time slot are decoded based on the maximum number of decoding iterations allocated per block.

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