Polar code encoding and decoding method and device

Abstract

This application provides a Polar encoding method, comprising: performing CRC encoding on an information block to obtain a CRC-encoded block of length B, wherein the CRC length is Lcrc, the information block length is K, and B = K + Lcrc; interleaving the CRC-encoded block, wherein Lpc CRC bits in the interleaved block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, wherein Lpc is an integer greater than 0 and less than Lcrc; mapping the interleaved block to information bits, setting frozen bits to a predetermined fixed value, and performing Polar encoding on the information bits and the frozen bits to obtain a Polar encoded codeword; wherein the position of the information bits corresponds to the position of the B polarization channels with optimal reliability; the position of the frozen bits corresponds to the position of the remaining N-B polarization channels, where N is the length of the Polar code mother code. This encoding method can further improve the performance of CA-Polar codes.

Description

[0001] This application is a divisional application. The original application has the application number 201710121488.7 and the original application date is March 2, 2017. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] The embodiments of the present invention relate to the field of wireless communication, and more specifically, to a Polar code encoding and decoding method and apparatus. Background Technology

[0003] Communication systems typically employ channel coding to improve data transmission reliability and ensure communication quality. Polar codes, proposed by Turkish professor Arikan, were the first theoretically proven good codes to achieve Shannon capacity while maintaining low encoding and decoding complexity. Polar codes are linear block codes with an encoding matrix of G. N The encoding process is as follows in It is a binary row vector with a length of N (i.e., the length of the mother code); G N It is an N×N matrix, and It is defined as the Kronecker product of log2N matrices F2.

[0004] The above matrix

[0005] In the encoding process of traditional Polar codes, A portion of the bits are used to carry information and are called information bits; the set of indices of these bits is denoted as A. The other portion of the bits are set to fixed values ​​agreed upon by the transmitting and receiving ends; these are called fixed bits or frozen bits, and the set of their indices is the complement of A, A' ... c This indicates that the encoding process of Polar codes is equivalent to: Here, G N. (A) is G N The submatrix G is obtained by considering the rows corresponding to the indices in set A. N (A C ) is G N In the set A C The submatrix obtained by referring to the rows corresponding to the indices in u. A for The set of information bits in the array, where the number of information bits is K; u A C for The set of frozen bits in the code, with a number of frozen bits (NK), are known bits. These frozen bits are usually set to 0, but their values ​​can be arbitrarily set as long as the transmitting and receiving ends agree beforehand. When the frozen bits are set to 0, the Polar code's encoded output can be simplified to: It is a K×N matrix.

[0006] The construction process of Polar codes, i.e., the selection process of set A, determines the performance of Polar codes. The construction process typically involves determining N polarization channels based on the mother code length N, each corresponding to one of the N rows of the coding matrix. The reliability of each polarization channel is calculated, and the indices of the top K polarization channels with the highest reliability are used as elements of set A. The indices corresponding to the remaining (NK) polarization channels are used as a fixed-bit index set A. c The elements. Set A determines the position of the information bits, set A. c It determines the position of the fixed bits.

[0007] At the decoding end, Polar codes can be decoded sequentially starting from the first bit using the Successive Cancellation (SC) decoding algorithm. The Successive Cancellation List (SCL) decoding algorithm is an improvement on the SC algorithm, retaining multiple candidate decoding results during the decoding process. SCL treats the decoding process as a path search process, expanding the path with the first bit as the root node and evaluating the path using a metric that is dynamically updated according to predetermined rules as the path expands. Each time the path is expanded (decoding the next bit), L candidate paths with the best path metric in the current layer are retained, until the last layer is reached (decoding the last bit). Finally, the path with the best metric among the L candidate paths is output as the decoded output. The SCL decoding algorithm can achieve maximum likelihood decoding performance.

[0008] To improve the performance of Polar codes, existing technologies have proposed CA-Polar codes. CA-Polar codes are concatenated CRC (Cyclic Redundancy Check) Polar codes, abbreviated as CA-Polar codes. This involves CRC encoding of the information block and then mapping the CRC-encoded bits back to the information bits. Correspondingly, the CA-SCL (CRC-Aided Successive Cancellation List) decoding algorithm is used, selecting the candidate path that passes the CRC check from the L candidate paths output by SCL decoding as the decoded output. If, at an intermediate node of CA-SCL decoding, a correct path is deleted due to a poor metric value, subsequent CRC checks cannot improve the performance of SCL decoding. Summary of the Invention

[0009] This application provides a Polar code encoding method and encoding device, a decoding method and decoding device, which can further improve the performance of CA-Polar codes.

[0010] Firstly, a Polar encoding method is provided, including:

[0011] The information block is CRC encoded to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc.

[0012] The CRC-encoded blocks are interleaved. The Lpc CRC bits in the interleaved blocks are located between the bits of the information blocks, and each of the Lpc CRC bits is located after all the bits it checks. Here, Lpc is an integer greater than 0 and less than Lcrc.

[0013] The interleaved coded blocks are mapped to information bits, and the frozen bits are set to agreed fixed values. Polar coding is performed on the information bits and the frozen bits to obtain Polar codewords. The positions of the information bits are the positions corresponding to the B polarization channels with the best reliability. The positions of the frozen bits are the positions corresponding to the remaining NB polarization channels, and N is the length of the Polar code mother code.

[0014] Secondly, an encoding device is provided, comprising:

[0015] The CRC encoding unit is used to perform CRC encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc.

[0016] The interleaving unit interleaves the CRC-encoded blocks. The Lpc CRC bits in the interleaved blocks are located between the bits of the information blocks, and each of the Lpc CRC bits is located after all the bits it checks. Here, Lpc is an integer greater than 0 and less than Lcrc.

[0017] A Polar coding unit is used to map the interleaved coding block to information bits, with frozen bits set to a predetermined fixed value. Polar coding is performed on the information bits and the frozen bits to obtain Polar codewords. The positions of the information bits are the positions corresponding to the B polarization channels with the best reliability, and the positions of the frozen bits are the positions corresponding to the remaining NB polarization channels, where N is the length of the Polar code mother code.

[0018] Thirdly, an encoding device is provided, comprising:

[0019] Memory, used to store programs;

[0020] A processor is configured to execute the program stored in the memory. When the program is executed, the processor performs CRC encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc. The CRC-encoded block is interleaved, with Lpc CRC bits in the interleaved block located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, where Lpc is an integer greater than 0 and less than Lcrc. The interleaved block is mapped to information bits, and frozen bits are set to agreed-upon fixed values. Polar encoding is performed on the information bits and the frozen bits to obtain Polar codewords. The positions of the information bits correspond to the B polarization channels with optimal reliability, and the positions of the frozen bits correspond to the remaining NB polarization channels, where N is the length of the Polar code mother code.

[0021] Fourthly, an encoding device is provided, comprising:

[0022] At least one input terminal is provided for receiving information blocks;

[0023] A signal processor is configured to perform CRC encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc; interleave the CRC-encoded block, where Lpc CRC bits in the interleaved block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, where Lpc is an integer greater than 0 and less than Lcrc; map the interleaved block to information bits, set the frozen bits to a predetermined fixed value, and perform Polar encoding on the information bits and the frozen bits to obtain Polar codewords; wherein the positions of the information bits correspond to the positions of the B polarization channels with optimal reliability; the positions of the frozen bits correspond to the positions of the remaining NB polarization channels, and N is the length of the Polar code mother code;

[0024] At least one output terminal is used to output the Polar-encoded codeword obtained by the signal processor.

[0025] Fifthly, a Polar decoding method is provided, including:

[0026] Obtain the positions of information bits and frozen bits in the bits to be decoded. The information bits include K bits of the information block and Lcrc bits of CRC. Among them, Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it checks. Here, Lpc is an integer greater than 0 and less than Lcrc.

[0027] The Serial Cancellation List (SCL) decoding algorithm is used to decode the bits to be decoded sequentially, and outputs L candidate paths with the best metric values. During the decoding process, the value of the frozen bit in each candidate path is set to a fixed value. The value of each CRC bit in Lpc CRC bits is determined according to the value of the bit of the information block it is checking before that CRC bit. The remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits.

[0028] Deinterleave the T candidate paths with the best metric values ​​out of L candidate paths, where T is an integer greater than 0 and less than or equal to L;

[0029] Perform CRC checks on the T candidate paths, and use the information block in the candidate path that passes the CRC check and has the best path metric as the decoded output.

[0030] Sixthly, a decoding apparatus is provided, comprising:

[0031] The acquisition unit is used to acquire the positions of information bits and frozen bits in the bits to be decoded. The information bits include K bits of the information block and Lcrc bits of CRC, wherein Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it verifies, wherein Lpc is an integer greater than 0 and less than Lcrc.

[0032] The decoding unit uses the Serial Cancellation List (SCL) decoding algorithm to decode the bits to be decoded sequentially and outputs L candidate paths with the best metric values. During the decoding process, the value of the frozen bit in each candidate path is set to a fixed value. The value of each CRC bit in the Lpc CRC bits is determined according to the value of the bit in the information block it is checking before that CRC bit. The remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits.

[0033] The interleaving unit deinterleaves the T candidate paths with the best metric values ​​out of L candidate paths, where T is an integer greater than 0 and less than or equal to L;

[0034] The CRC check unit is used to perform CRC check on the T candidate paths and output the information block in the candidate path that passes the CRC check and has the best path metric as the decoded output.

[0035] Seventhly, a decoding apparatus is provided, comprising:

[0036] Memory, used to store programs;

[0037] A processor is configured to execute the program stored in the memory. When the program is executed, the processor is configured to obtain the positions of information bits and frozen bits in the bits to be decoded. The information bits include K bits of an information block and Lcrc bits of CRC, wherein Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it checks, where Lpc is an integer greater than 0 and less than Lcrc. The Serial Cancellation List (SCL) decoding algorithm is used to decode the bits to be decoded sequentially, and L candidate paths with the best metric values ​​are output. In the decoding process, the value of the frozen bit in each candidate path is set to a fixed value according to an agreement. The value of each CRC bit in Lpc CRC bits is determined according to the value of the bit of the information block it is checking before that CRC bit. The remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits. The T candidate paths with the best metric value among the L candidate paths are deinterleaved, where T is an integer greater than 0 and less than or equal to L. The T candidate paths are CRC checked, and the information block in the candidate path that passes the CRC check and has the best path metric is used as the decoded output.

[0038] Eighth aspect, a decoding apparatus is provided, comprising:

[0039] At least one input terminal is used to receive the bit information to be decoded;

[0040] A signal processor is used to obtain the positions of information bits and frozen bits in the bits to be decoded. The information bits include K bits of an information block and Lcrc bits of CRC, wherein Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it checks. Here, Lpc is an integer greater than 0 and less than Lcrc. The Serial Cancellation List (SCL) decoding algorithm is used to decode the bits to be decoded sequentially, outputting L candidate paths with the best metric values. During the decoding process, the value of the frozen bits in each candidate path is set to a fixed value according to an agreement. The value of each of the Lpc bits of CRC is determined according to the value of the bits of the information block it checks before that CRC bit. The remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits. The T candidate paths with the best metric values ​​among the L candidate paths are deinterleaved, where T is an integer greater than 0 and less than or equal to L. CRC checks are performed on the T candidate paths.

[0041] At least one output is used to output the information block in the candidate path that has passed CRC check and has the best path metric as the decoded output.

[0042] In light of all the above, in the first possible implementation, the interleaving of the CRC-encoded block includes: interleaving the CRC-encoded block using an interleaving sequence π = [π1, π2, ..., πn], transforming the CRC-encoded bit sequence [b1, b2, ..., bn] into bπ1, bπ2, ..., bπn; where n is an integer greater than 0 and less than or equal to B, and the value of πn represents the bit position index of the nth bit in the interleaved block in the previous CRC block.

[0043] Combining all the above aspects and the first possible implementation, in the second possible implementation, Lpc, Lcrc, T, and the upper limit of false alarm probability FAR specified by the communication system satisfy the following relationship:

[0044] L pc ≤L crc -log2T+log2FAR.

[0045] Combining all the above aspects and all possible implementations, in the third possible implementation, Lcrc is 27 and Lpc is 8; or Lcrc is 24 and Lpc is 6; or Lcrc is 22, 23, 14 or 15 and Lpc is 4; or...

[0046] In a fourth possible implementation, combining any of the fifth to eighth aspects, the metric is the path value PM.

[0047] Combining any aspect from the fifth to the eighth aspects or the fourth possible implementation, in the fifth possible implementation, if the CRC check of all T candidate paths fails, the information block of the path with the best metric value among the T candidate paths is used as the decoding output or determined as a decoding failure.

[0048] In conjunction with the first to fourth aspects, in the sixth possible implementation, the CRC encoding is: a single CRC encoding. Only one CRC encoding is needed according to the length of Lcrc to obtain the CRC-encoded block.

[0049] Combining all the above aspects and all possible implementations, in the sixth possible implementation, Lcrc and Lpc satisfy the following relationship: Lcrc-Lpc = 10; or Lcrc-Lpc = 18.

[0050] Combining all the above aspects and all possible implementation methods, in the seventh possible implementation method, Lpc=1, Lcrc=11; or Lpc=2, Lcrc=12; or Lpc=4, Lcrc=14; or Lpc=6, Lcrc=16; or Lpc=8, Lcrc=18.

[0051] Combining all the above aspects and all possible implementation methods, in the eighth possible implementation method, Lpc=1,Lcrc=19; or Lpc=2,Lcrc=20; or Lpc=4,Lcrc=22; or Lpc=6,Lcrc=24; or Lpc=8,Lcrc=26.

[0052] The ninth aspect of this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the encoding or decoding methods described in the foregoing aspects or various possible implementations.

[0053] Another aspect of this application provides a computer program product containing instructions that, when run on a computer, causes the computer to perform the encoding or decoding methods described in the above aspects or various possible implementations.

[0054] Another aspect of this application provides a computer program that, when run on a computer, causes the computer to perform the encoding or decoding methods described in the above aspects or various possible implementations.

[0055] In this embodiment, after CRC encoding, the CRC-encoded block is interleaved, so that some CRC bits in the interleaved block are distributed among the bits of the information block, and each CRC bit in this part is located after all the bits it checks. That is, this part of the CRC bits only checks the bits of the information block preceding it. During the decoding process, this part of the CRC bits is used as parity check bits for decoding. If the decoding of the preceding information bits is incorrect, the value of the CRC bit calculated based on the preceding information bits is more likely to not match the received LLR, making the metric value of that path worse. Therefore, it is more likely to delete the erroneous path when sorting the metric values ​​of candidate paths, thus improving the performance of CA-SCL decoding. Attached Figure Description

[0056] Figure 1 This is a basic flowchart of the wireless communication transmitter and receiver.

[0057] Figure 2(a) is a schematic diagram of path extension and metric calculation when the LLR of the current bit is greater than 0 in an embodiment of this application;

[0058] Figure 2(b) is a schematic diagram of path extension and metric calculation when the LLR of the current bit is less than 0 in an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of path extension and PM value update in SCL decoding;

[0060] Figure 4 This is a schematic diagram of the CA-Polar encoding process;

[0061] Figure 5 This is a schematic diagram of the CA-Polar structure;

[0062] Figure 6 This is a schematic diagram of the encoding process provided in the embodiments of this application;

[0063] Figure 7 This is a schematic diagram of the structure of an encoding device provided in this application;

[0064] Figure 8 This is a flowchart illustrating an encoding method provided in this application.

[0065] Figure 9 This is a schematic diagram illustrating the verification relationship between each special CRC bit and its preceding information bits in an embodiment of this application;

[0066] Figure 10 This is a schematic diagram of a CA-Polar structure provided in an embodiment of this application;

[0067] Figure 11 This is a flowchart of another encoding method provided in the embodiments of this application;

[0068] Figure 12 This is a schematic diagram of the structure of another encoding device provided in this application;

[0069] Figure 13 This is a schematic diagram of the structure of another encoding device provided in this application;

[0070] Figure 14 This is a schematic diagram of the structure of a decoding device provided in this application;

[0071] Figure 15 This is a flowchart illustrating a decoding method provided in this application;

[0072] Figure 16 This is a schematic diagram of path expansion and path value update for SCL decoding provided in an embodiment of this application;

[0073] Figure 17(a) shows the performance comparison between the proposed scheme and the traditional CA-Polar in the AWGN channel when List=8 and K=32.

[0074] Figure 17(b) shows the performance comparison between the proposed scheme and the traditional CA-Polar in the AWGN channel when K=48; Figure 18 This is a schematic diagram of the structure of another decoding device provided in this application;

[0075] Figure 19 This is a schematic diagram of the structure of another decoding device provided in this application; Detailed Implementation

[0076] The technical solutions of this application embodiment can be applied to 5G communication systems or future communication systems, as well as various other wireless communication systems, such as: Global System of Mobile Communication (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), General Packet Radio Service (GPRS), Long Term Evolution (LTE), LTE Frequency Division Duplex (FDD), LTE Time Division Duplex (TDD), Universal Mobile Telecommunication System (UMTS), etc.

[0077] Figure 1 This is the basic process of wireless communication. At the transmitting end, the signal source is transmitted after undergoing source coding, channel coding, and digital modulation. At the receiving end, it is transmitted after digital demodulation, channel decoding, and source decoding. Channel coding and decoding can use Polar codes, while channel decoding can employ SC decoding and SCL decoding. The SCL decoding algorithm is an improvement on the SC decoding algorithm. During the decoding process, multiple candidate paths are retained, and finally, a path is selected as the decoding result based on the metric value of each candidate path.

[0078] The metric value PMl(i) of the l-th path, i.e., the path metric (PM) at the i-th bit, is shown in formula (1) (where the value corresponding to LLR>0 is 0 and the value corresponding to LLR<0 is 1):

[0079]

[0080] Where LLR(i) is the log-likelihood ratio (LLR) of the current bit. The value of LLR can be either 0 or 1. For example, when LLR < 0, the value is 1, and when LLR > 0, the value is 0. Of course, other methods can be used in practical applications, such as setting the value corresponding to LLR < 0 to 0 and setting the value corresponding to LLR > 0 to 1. When LLR = 0, its value can be considered as either 0 or 1, and can be set as needed in practical applications. If the value of the LLR corresponding to the current bit is consistent with the decision result, PM remains unchanged; if the value of the LLR corresponding to the current bit (0 or 1) is inconsistent with the decision result, PM is increased by the penalty value |LLR(i)|, that is, the penalty value is the absolute value of the LLR of the current bit. From the calculation formula of PM, it can be seen that the smaller the PM, the closer the codeword corresponding to the path is to the received signal, which means that the metric value of the path is better. Therefore, the path with the smallest PM can be output as the decoding result. If the value (0 or 1) corresponding to the LLR of the current bit is inconsistent with the decision result in formula (1), PM can also be changed to subtract the penalty value |LLR(i)|, that is, PMl(i)=PMl(i-1)-|LLR(i)|. Accordingly, selecting the path with the optimal metric value means selecting the path with the largest PM. This application uses formula (1) as an example for description.

[0081] In the SCL decoding process, if the current bit is an information bit, each path will be expanded into 2 paths, for a total of 2L paths, where L is the number of candidate paths to be retained. The decision result of each node is 0 or 1, and the PM of each path is calculated according to the above formula. Then, the expanded paths are sorted according to the PM, and the L paths with the smallest PM are retained, while the remaining L paths are deleted, which is also called pruning. If the current bit is a frozen bit, the corresponding nodes in each path are not expanded, but are directly decided as the corresponding known fixed values, and the PM of each path is calculated according to formula (1).

[0082] For ease of description, the following examples will use the case where LLR < 0 corresponds to a value of 1 and LLR > 0 corresponds to a value of 0. As shown in Figure 2(a), if the LLR(i) of the current decoded bit is greater than 0 (corresponding to a value of 0), during the path extension process, if the current bit is an information bit, two paths need to be extended. If the decision result is also 0, then the decision result is consistent with the value corresponding to LLR (represented by "√" in Figure 2). In this case, PM(i) = PM(i-1); if the decision result is 1, then the decision result is inconsistent with the value corresponding to LLR (represented by "x" in Figure 2). In this case, PM(i) = PM(i-1) + |LLR(i)|. If the current bit is a frozen bit, the path is not extended. PM is calculated according to the known fixed value. If the known fixed value is 0, the corresponding value of LLR is also 0. In this case, the known fixed value is consistent with the corresponding value of LLR, and PM(i) = PM(i-1). If the known fixed value is 1, the known fixed value is inconsistent with the corresponding value of LLR, and PM(i) = PM(i-1) + |LLR(i)|. As shown in Figure 2(b), if the LLR(i) of the current decoded bit is less than 0 (the corresponding value is 1), during the path extension process, if the current bit is an information bit, two paths need to be extended. If the decision result is 0, the decision result is inconsistent with the corresponding value of LLR, and PM(i) = PM(i-1) + |LLR(i)|. If the decision result is 1, the decision result is consistent with the corresponding value of LLR, and PM(i) = PM(i-1). If the current bit is a frozen bit, no expansion is performed. PM is calculated according to the known fixed value. If the known fixed value is 0 and the corresponding value of LLR is also 1, then the known fixed value is inconsistent with the corresponding value of LLR, and PM(i) = PM(i-1) + |LLR(i)|. If the known fixed value is 1, then the known fixed value is consistent with the corresponding value of LLR, and PM(i) = PM(i-1).

[0083] Figure 3This is an example of the SCL decoding algorithm List=2, which retains two candidate paths during the decoding process. Typically, the first few bits are frozen bits, set to fixed values ​​such as 0. Therefore, decoding actually starts from the first information bit. In Figure 2, by retaining the path with the smallest PM value at each expansion, two candidate paths L1 and L2 are finally obtained, as shown by the arrows. The final PM value of path L1 is 0.0, while the PM value of the other path L2 is 0.2. Therefore, the path L1 with the smaller PM value of 0.0 is selected as the decoding output, and the decoded information bit value is 0011. Concatenating CRC (Cyclic Redundancy Check) with Polar codes, abbreviated as CA-Polar, and selecting the path that passes CRC check from the candidate paths in the SCL decoding output as the decoding output, the CA-SCL (CRC-Aided Successive Cancellation List) decoding algorithm can significantly improve the performance of Polar codes.

[0084] CA-Polar code construction process: Assuming the information block size is Kinfo, the CRC length is Kcrc, and the Polar code length is N, then Kinfo + Kcrc bits with the highest reliability are selected from N polarization channels as information bits, and the rest are frozen bits. The CA-Polar encoding process is as follows: Figure 4 As shown, the information block is first CRC encoded, then the CRC-encoded bits are mapped to the positions of the information bits. Fixed values ​​agreed upon by the sender and receiver are placed at the positions of the frozen bits. Then, Polar encoding is performed to obtain the CA-Polar encoded block. During SCL decoding, both the information block and the CRC bits are unknown, and decoding proceeds according to the normal SCL decoding process. After SCL decoding, L candidate decoding results are obtained, each including the information block and CRC bits. Starting from the path with the smallest PM, each candidate result undergoes CRC verification. If the verification passes, the information block of that path is output as the decoded block; if all CRC verifications fail, the information block of the path with the smallest PM is output as the decoded block, or decoding failure can be directly indicated.

[0085] like Figure 5 As shown, during the CA-Polar encoding and decoding process, CRC bits are treated as information bits. At the end of SCL decoding, CRC bits are used to assist in path selection. However, at intermediate nodes of SCL, the correct path may be deleted due to a large PM value.

[0086] In this embodiment of CA-Polar, interleaving moves some CRC bits to the middle of the information block's bits. The value of these CRC bits is determined by the values ​​of the bits preceding them in the information block. In other words, these CRC bits are used to perform parity checking on the preceding information bits, assisting CA-Polar's SCL decoding, increasing the probability of removing erroneous paths at intermediate nodes, and improving CA-Polar's performance. These CRC bits can also be called parity check (PC) bits or special CRC bits. Regardless of the name, these special CRC bits satisfy the following condition: they are located in the middle of the information block's bits according to the encoding order (interleaved order), and only check the bits of the information block preceding them. The check equation for the special CRC bits is determined through CRC encoding; that is, they are used to check which bits were determined during the CRC encoding process. Interleaving does not change the bits checked by a particular special CRC bit; it only changes the position of the checked bits, ensuring that all bits checked by a particular special CRC bit are located before that special CRC bit. Thus, during decoding, when the special CRC bit is decoded, its value is directly determined based on the bits checked before it. The position of special CRC bits changes each time the block length, CRC length, and CRC generator polynomial are different; they are not always fixed in a certain position. The number of special CRC bits can also be set differently according to actual needs. For ease of description, they will be referred to as special CRC bits below.

[0087] like Figure 6 As shown, the encoding process includes:

[0088] (1) CRC encoding: The information block is CRC encoded to obtain the CRC encoded block.

[0089] (2) Interleaving: The CRC-encoded block is interleaved. Since a serial SCL decoding algorithm is used, if some CRC bits are used as PC check bits, these CRC bits are only related to the previous decoded bits. Interleaving ensures that some CRC check bits distributed in the middle of the information block are before the CRC bits.

[0090] (3) Polar coding: The interleaved coded blocks are mapped to the positions of the information bits (the polarization channel can be a bit position with a higher polarization channel). The remaining polarization channels correspond to the positions of the frozen bits and are set to a fixed value, such as all 0 or all 1. Polar coding is performed on the information bits and the frozen bits to obtain the Polar coded codewords.

[0091] During decoding at the receiving end, the SCL decoding algorithm is used to perform path expansion on the information bits. Decisions are made based on the path values. However, for special CRC bits distributed in the middle of the information block where the check bits precede them, path expansion is not required; the value of these special CRC bits is determined by the information bits decoded before them. Frozen bits are not path expanded and are directly decoded to their agreed-upon fixed values. After SCL decoding, L candidate paths are obtained. Partial or complete deinterleaving of these L candidate paths yields the information block and CRC bits. A CRC check is performed on each path, and the optimal path that passes the CRC check is selected as the decoded output. During decoding, the CRC bits can be used to select decoding results from candidate paths and also for error detection, i.e., to determine the correctness of the decoding result. Special CRC bits can be used as PC bits to assist SCL decoding, increasing the probability of deleting erroneous paths. Error detection can also be performed during decoding; if all expanded paths fail the CRC check, subsequent decoding is stopped, i.e., decoding is terminated, and the decoding is considered a failure.

[0092] Since the value of the special CRC bit is determined by the value of the information bit obtained from the previous decoding, if the information bit in the previous decoding is incorrect, the possibility of the value of the special CRC bit calculated from the information bit and the value corresponding to the received LLR will increase when decoding the special CRC bit. Accordingly, when calculating the PM value of the path, according to the calculation of the aforementioned formula (1), the PM value will be added to the absolute value of the special CRC bit LLR, thereby increasing the PM value of the path, and the possibility of the path being deleted in the subsequent decoding process will increase.

[0093] like Figure 7 The encoding device 700 shown can perform, for example Figure 7 The encoding method shown includes an encoding device 700 comprising a CRC encoding unit 701, an interleaving unit 702, and a Polar encoding unit 703. For example... Figure 7 As shown, the encoding method in this application embodiment may include the following process:

[0094] 801. Perform Cyclic Redundancy Check (CRC) encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc.

[0095] CRC encoding unit 701 performs CRC encoding on the information block to be transmitted, obtaining K+Lcrc CRC encoded bits. The CRC generator polynomial is [C0, C1, ..., C...]. n-K ], where K is the block length, n = K + Lcrc, and one of the original generator matrices for CRC encoding is a K*n matrix:

[0096]

[0097] Using Gaussian elimination, the generator matrix is ​​simplified to: G = [IP], where I is a K*K identity matrix and P is a K*Lcrc matrix. Matrix G is a K*n matrix. The row number of each row can be understood as the sequence number of a bit in the corresponding information block, and the column number of each column can be understood as the sequence number of the bit output after CRC encoding. The value of each bit after CRC encoding is the sum of the bit values ​​corresponding to all rows with a value of 1 in that column. Therefore, each column of matrix P corresponds to a CRC bit, and the bit corresponding to the row number of the 1 in each column is used as the bit of the information block verified by that CRC bit. Taking Lcrc = 4 and K = 12 as an example, according to the generator polynomial of CRC-4 [1 0 0 1 1], the generator matrix G = [IP] is calculated as shown in Table 1. Here, only one CRC encoding is needed for the information block.

[0098]

[0099]

[0100] Table 1. CRC generation matrix with K=12 and CRC length of 4

[0101] The sequence [a1,a2,...,a12] represents an information block, and [b1,b2,...b16] represents a CRC-encoded block, where b13,b14,b15, andb16 are CRC bits. As can be seen from the table, the bits of the information block corresponding to a value of 1 in the column containing b13 are a2,a3,a4,a5,a7,a9,a10, and the corresponding CRC-encoded bits are b2,b3,b4,b5,b7,b9,b10. Therefore, b13 = b2 + b3 + b4 + b5 + b7 + b9 + b10, and the check equation is: b2 + b3 + b4 + b5 + b7 + b9 + b1 + b13 = 0. This check equation can be represented by the sequence [2,3,4,5,7,9,10,13]. Similarly, for b14, b15, and b16, according to Table 1, the verification equations are expressed as: [3,4,5,7,9,10,11,14], [4,5,6,7,9,11,12], and [1,2,3,4,6,8,9,12].

[0102] Different CRC lengths have different CRC generator polynomials; the same CRC length can also have multiple different polynomials. The following lists several CRC lengths and their corresponding generator polynomials.

[0103] Assuming the Lcrc length is 14, the corresponding CRC generator polynomials include: [100111110011111] [101000101010011] [110111111011111] [100000000101011] [111010101110111] [110100100101111] [100111011010011] [101010010011111] [100011001000101] [100011000111101] [110011101010111] [1000000000000111] [1101111111111111] [100100000000101] [110111001010111] [101111111110111] [100001111010001] [101000111011101] [101010110011101] [1111101111011111] [100001001011011] [100011011100011] [1011101111111011]

[0127] Assuming the Lcrc length is 15, the corresponding CRC generator polynomials include: [1001111001000111] [10111111111111111] [1001111010100011] [1011011010101111] [1001011111110011] [1001101001111001] [1010100110101101] [10000000000000011] [1011010010001111] [1000011000001101] [1010111111001111] [1110111101111111] [1100111101001011] [1100011000010111] [1000000000101001] [1011100110111101] [1001001011101101] [1001101011001011] [1011011110101011] [1101010100011011] [1010111001110101] [1100010110011001] [1001000010111001] [1110100000010101]

[0152] Assuming the Lcrc length is 18, the corresponding CRC generator polynomials include: [1000111001011110011] [1000000000000100111] [1000111000101111101] [1011010000100111111] [1000011011101010111] [1010111110110101101] [1011101110010010011] [1001101010001111011] [1010000111101110011] [10000000000000110001] [1001011111010100111] [1011100111110111101] [1001111011101111001] [1100101100011010011] [1110010101010100111] [1001011111011010101]

[0169] Assuming the Lcrc length is 19, the corresponding CRC generator polynomials include: [11011111011010101111] [10010000000100111111] [10000001001101110101] [11011010001001100111] [10001011111000111001] [11101010111001111111] [10011110110101000101] [10000000000000100111] [10010111010110011001] [11101111011000011111] [100000000000000101001] [10100011101011110011] [10001001111011101011] [10101101000010110101] [10100001011010010011] [11101111001110001111]

[0186] Assuming the Lcrc length is 22, the corresponding CRC generator polynomials include: [11000010001111110100111] [11011011100100000000001] [10100101001101010101001] [11100100010101111010011] [10011100101001101101011] [11101111000011000101101] [11111011111000101100011] [10010111101111011111011] [11011011100000100110001] [11100010110000110100101] [100000000000000000000011] [10101011101101110100111] [11011011110110001001111] [10010010000111100101001] [100000000000000010001111] [11100101011011010100111] [10101010010101001010101] [10110111001110100100011] [101000100111001111111101] [10010001111011110001001] [10001011101111101101111]

[0208] Assuming the Lcrc length is 23, the corresponding CRC generator polynomials include: [101010000001101111100001] [100101101011000010110001] [101101100111100101001001] [110011100110001011100011] [100011010110001101010111] [100001010010111101100001] [100001001001111001110111] [101111001111011001000111] [1000000000000000000100001] [1000000000000001010101001] [1000000000000000000110111] [100100110101101010100101] [101001111011111011011101] [100101101111001110100011] [110101111000000111101011] [101111000100100000110011] [100011010011101011111001] [100011000111011011101111]

[0227] Assuming the Lcrc length is 26, the corresponding CRC generator polynomials include: [110011110000011001111011111] [111010011001101110010011111] [100111111010110111101100111] [1010010000101000101111110101] [110110010010101010110010111] [111011011000010100011001111] [111110100110010001001010111] [101001010011110111100111101] [101110100000001111101001111] [101101100000111011100111111] [111010010010111110010011111] [1000000000000000000001000111] [110000011011111110011101011] [100111100010110100100101011] [1000000000000000000000010011] [100011101110110110000100101] [110001000111101001101011011] [100101000111110110011010111] [100001100001101100001100001] [101100010001010100010001101] [101011110110001001001110111] [100100100011010011101111101] [101011111110111101100011111] [110010110111101111011010011]

[0252] Assuming the Lcrc length is 27, the corresponding CRC generator polynomials include: [1011110000001000110001101011] [1000100001010010110100001101] [10000000000000000000000100111] [110100110000110001100011000100111] [1110100010111101000101111111] [10000000000000000000000100011] [1101010011000010001101111111] [1010001101011111111100110101] [1100101101111010101000100111] [1011000011010010101111000111] [1101100001111111111000011011] [1001100101101100101100011111] [1010010000111110110010010111] [1000010010110001100000011111] [1000111010011111101010001111]

[0268] 802. Interleave the CRC-encoded blocks. The Lpc CRC bits in the interleaved blocks are located between the bits of the information blocks, and each of the Lpc CRC bits is located after all the bits it checks.

[0269] Interleaving unit 702 interleaves the CRC-encoded block, resulting in Lpc CRC bits located between bits in the information block, with each of the Lpc CRC bits following all the bits it checks. Lpc is an integer greater than 0 and less than Lcrc. Interleaving unit 702 may perform the following steps on the CRC-encoded block: using an interleaving sequence π = [π1, π2, ..., π...]. n Interleave the CRC-encoded blocks to transform the CRC-encoded bit sequence [b1,b2,...,bn] into bπ1,bπ2,...,bπ n Where n is an integer greater than 0 and less than or equal to B, π n The value represents the bit position index of the nth bit in the interleaved coded block within the coded block before interleaving. For example... Figure 9 As shown, after interleaving, some CRC bits are distributed between the bits of the information block, and each CRC bit in the partial CRC bits checks the bits of the preceding information block, such as... Figure 9 As shown by the arrow in the image.

[0270] The setting of the number of special CRC bits, Lpc, can be any integer greater than 0 and less than Lcrc. For example, if Lcrc = 27, then Lpc can be any value from 1 to 26, such as 8. For example, if Lcrc is 22, 23, 14, or 15, Lpc is 4. Alternatively, it can be specified that if Lcrc is within a certain range, the value of Lpc is fixed; for example, if Lcrc is less than or equal to 23, Lpc is uniformly set to 4.

[0271] If the false alarm rate (FAR) is considered, the value of Lpc is related to the CRC length Lcrc, the number of paths T after SCL decoding through CRC-assisted decoding, and the requirement for the false alarm rate (FAR). The false alarm rate refers to the probability of an event where the decoding result is incorrect but the CRC check passes. For example, the value of Lpc can be selected with reference to the following formula (2):

[0272] L pc ≤L crc -log2T+log2FAR (2)

[0273] In formula (2), Lpc is the partial CRC length, Lcrc is the total CRC length, and T is the number of candidate paths selected by CRC check during decoding. If there are L candidate paths, then T is an integer greater than 0 and less than or equal to L.

[0274] Communication systems may specify an upper limit for the false alarm probability. For example, suppose the downlink control channel in 5G NR requires a false alarm probability of less than or equal to 2. -16 (Ignoring blind detection), the number of paths T for auxiliary decoding via CRC after SCL decoding of the Polar code is 4, and the CRC length Lcrc is 24. Therefore, the number of CRC bits available for parity checking is Lpc ≤ (24 - 2 - 16) = 6. The false alarm probability required by the uplink control channel is less than or equal to 2. -8 If the number of paths T for auxiliary decoding via CRC after SCL decoding of Polar code is 8, and the CRC length is Lcrc24, then the number of CRC bits that can be used for parity checking is Lpc≤24-3-8=13.

[0275] In one implementation, Lcrc and Lpc can be connected via L pc =L crc -log2T+log2FAR calculates a fixed value, that is, Lcrc-Lpc=log2T-log2FAR. For example, if FAR=2 -16 If T = 4, then Lcrc - Lpc = 18; if FAR = 2 -8 , T=4, then Lcrc-Lpc=10; FAR=2 -16 If T = 8, then Lcrc - Lpc = 19; if FAR = 2 -8 If T = 8, then Lcrc - Lpc = 11. Of course, different values ​​for T and FAR will result in different values ​​for (Lcrc - Lpc). Different combinations can also be set based on the value of (Lcrc - Lpc) and stored in the compiler / decoder. For example, when Lcrc - Lpc = 10, Lpc and Lcrc can be: Lpc = 1, Lcrc = 11; or Lpc = 2, Lcrc = 12; or Lpc = 4, Lcrc = 14; or Lpc = 6, Lcrc = 16; or Lpc = 8, Lcrc = 18. When Lcrc - Lpc = 18, Lpc and Lcrc can be: Lpc = 1, Lcrc = 19; or Lpc = 2, Lcrc = 20; or Lpc = 4, Lcrc = 22; or Lpc = 6, Lcrc = 24; or Lpc = 8, Lcrc = 26.

[0276] The CRC bits after CRC encoding are usually located at the end of the encoded block, as shown in Table 1. Bits b13, b14, b15, and b16 are located after bits b1, b2, ..., b12. CRC verification is performed at the decoding end after all information blocks and CRC bits have been decoded. To allow some CRC bits to be verified before the end of decoding, the positions of bits and CRC bits in the information block can be changed through interleaving, so that some CRC bits are located between information bits, and the bits of the information block being verified are before these CRC bits.

[0277] Interleaving can be achieved using an interleaving sequence π = [π1, π2, ..., π]. n The CRC-encoded blocks [b1, b2, ..., bn] are interleaved, where each element in π is the sequence number of the CRC-encoded block, representing the interleaved block C = [C1, C2, ..., Cn]. n ] = [bπ1, bπ2, ..., bπ n Taking the example shown in Table 1, the interleaved sequence can be: π = [2,3,4,5,7,9,10,13,8,6,11,14,12,1,15,16], representing the interleaved sequence C = [C1,C2,...,C]. 12 ]=[b2,b3,b4,b5,b7,b9,b10, b13 ,b8,b6,b11, b14 ,b12,b1, b15 , b16 The underlined bits are CRC bits, and the bit correspondence before and after interleaving is shown in Table 2. It can be seen that CRC bit b13 is interleaved to position C8. Bits b2, b3, b4, b5, b7, b9, and b10 before C8 are all the bits checked by b13, corresponding to C1, C2, C3, C4, C5, C6, and C7 respectively. Bit b14 is interleaved to position C12. Bits b3, b4, b5, b7, b9, b10, and b11 are all the bits checked by b14, corresponding to the interleaved C2, C3, C4, C5, C6, C7, C9, and C11 respectively. 10 C 11 All of these are located before b14. The positions of b15 and b16 remain unchanged, but the positions of the bits they check have changed. The bits b4, b5, b6, b7, b9, b11, and b12 checked by b15 now correspond to the interleaved C3, C4, and C5. 10 C5, C6, C 11 C 13 The bits b1, b2, b3, b4, b6, b8, b9, and b12 of the b16 checksum correspond to the interleaved C. 14 ,C1,C2,C3,C10 C9, C6, C 13 For the sequence number of the interleaved coded block, the check equations are updated as follows:

[0278] C1+C2+C3+C4+C5+C6+C7+C8=0;

[0279] C2+C3+C4+C5+C6+C7+C9+C 10 +C 11 +C 12 =0;

[0280] C3+C4+C 10 +C5+C6+C 11 +C 13 +C 15 =0;

[0281] C 14 +C1+C2+C3+C 10 +C9+C6+C 13 +C 16 =0;

[0282] The check equations, represented by sequences, are as follows:

[0283] [1,2,3,4,5,6,7,8];[2,3,4,5,6,7,9,10,11,12];[3,4,10,5,6,11,13,15];[14,1,2,3,10,9,6,13,16].

[0284] b2 b3 b4 b5 b7 b9 b10 <![CDATA[ b13 ]]> b8 b6 b11 <![CDATA[ b14 ]]> b12 b1 <![CDATA[ b15 ]]> <![CDATA[ b16 ]]> <![CDATA[C1]]> <![CDATA[C2]]> <![CDATA[C3]]> <![CDATA[C4]]> <![CDATA[C5]]> <![CDATA[C6]]> <![CDATA[C7]]> <![CDATA[ C 8]]> <![CDATA[C9]]> <![CDATA[C 10 ]]> <![CDATA[C 11 ]]> <![CDATA[ C 12 ]]> <![CDATA[C 13 ]]> <![CDATA[C 14 ]]> <![CDATA[ C 15 ]]> <![CDATA[ C 16 ]]>

[0285] Table 2

[0286] In the example in Table 2, b13 is moved to the earliest position after all the bits it checks, but this is not a limitation. For example, b13 can also be moved to a later position, such as after b8. The same applies to b14, which can also be moved after b12. b13 and b14 are called special CRC bits. After interleaving, they are distributed among the bits of the information block, and the bits of the information block they check all precede these special CRC bits. The remaining CRC bits b15 and b16 can be used as normal CRC bits for CRC check. Since CRC check is used to select candidate paths after decoding, these two CRC bits are located at the end during interleaving, but they can also be moved to any other position. For example, an interleaving sequence π = [2,3,15,4,5,16,7,9,10,8,13,6,11,14,12,1] can be used. Compared to the interleaving method shown in Table 3, b13 is moved after b8, and b15 and b16 are also distributed among the bits of the information block.

[0287] b2 b3 <![CDATA[ b15 ]]> b4 b5 <![CDATA[ b16 ]]> b7 b9 b10 b8 <![CDATA[ b13 ]]> b6 b11 <![CDATA[ b14 ]]> b12 b1 <![CDATA[C1]]> <![CDATA[C2]]> <![CDATA[ C 3]]> <![CDATA[C4]]> <![CDATA[C5]]> <![CDATA[ C 6]]> <![CDATA[C7]]> <![CDATA[C8]]> <![CDATA[C9]]> <![CDATA[C 10 ]]> <![CDATA[ C 11 ]]> <![CDATA[C 12 ]]> <![CDATA[C 13 ]]> <![CDATA[ C 14 ]]> <![CDATA[C 15 ]]> <![CDATA[C 16 ]]>

[0288] Table 3

[0289] 803. Map the interleaved coded blocks to information bits, set the frozen bits to a fixed value as agreed, and perform Polar encoding on the information bits and the frozen bits to obtain Polar encoded codewords.

[0290] Polar coding unit 703 maps the interleaved coded blocks to information bits, sets the frozen bits to agreed-upon fixed values, and performs Arikan Polar coding on the information bits and frozen bits to obtain the Polar codeword. The encoded codeword can also be called a coded block, coded sequence, etc. The positions of the information bits correspond to the first B polarization channels in the Polar code, sorted by reliability from highest to lowest. The bits corresponding to the remaining (NB) polarization channels are used as frozen bits and set to agreed-upon fixed values, where N is the length of the Polar code's mother code.

[0291] like Figure 10As shown, in the Polar code constructed in this embodiment, the information block and CRC bits are distributed together on the most reliable polarization channel, while the frozen bits are distributed on polarization channels with lower reliability than the information bits. After interleaving, the encoded block is mapped to the information bit positions corresponding to the polarization channels, and the CRC bits are distributed between the bits of the information block. Using some CRC bits as parity check bits during decoding can increase the probability of removing erroneous paths during CA-SCL decoding. Furthermore, the remaining CRC bits can still be used for CRC verification. Since the check equation for the special CRC bits is determined through the CRC verification process, it is not necessary to set a separate check equation.

[0292] In step 802, the interleaving sequence can be pre-set after calculation, or it can be calculated in real time during the encoding process. There are several ways to determine the interleaving sequence; some examples are given below.

[0293] The interleaving sequence π is calculated based on the CRC generator matrix, CRC length Lcrc, information bit length K, and special CRC bit count Lpc. The process may include the following:

[0294] (1) Perform elementary row swaps on the CRC generator matrix G = [IP] to obtain G = [I' P'].

[0295] a) By swapping rows, the first p1 rows of column 1 of P' are 1s, and all subsequent elements are 0s; the (p1+1)th to (p1+p2)th rows of column 2 are 1s, and all subsequent elements are 0s; and so on, the (p1+p2...+p)th rows of column n-1 are 1s, and all subsequent elements are 0s. n-1 +1) results in a value of 1, after which all other elements are 0.

[0296] b) Based on the column index of element 1 in each row of I', the initial interleaving sequence π0 is obtained.

[0297] (2) Insert the Lpc row into P' to obtain P'. Select the special CRC bits corresponding to the Lpc column in P', and then process P' column by column for all CRC bits in the following manner:

[0298] a) If the i-th column corresponds to a special CRC bit, insert a row after the row containing the last element 1 in the i-th column and record the row number; the i-th element of the inserted row is 1, and the rest are 0.

[0299] b) If the i-th column corresponds to a normal CRC bit, insert a row after any row, record the row number, and the i-th element of the inserted row is 1, and the rest are 0.

[0300] (3) Read P". For the Lpc column of P” containing the special CRC bits, read the set of row numbers containing element 1 column by column. For the i-th column, the set read represents the check equation PCF.i .

[0301] (4) Based on the row number of the insertion row recorded in step (2), sequence π p =[K+1,K+2,...,K+Lcrc], and sequentially insert the initial interleaving sequence π0 to obtain the final interleaving sequence π = [π1,π2,...,π]. n ], and obtain the final verification equation.

[0302] Note that the operation process of matrix P in steps (1)-(2) is not unique. It is only necessary to ensure that the last element 1 of each column of the Lpc column corresponding to the special CRC bit is located in the row inserted in step (2).

[0303] The following example, using CRC-4, illustrates one process for generating interleaved sequences.

[0304] (1) Based on the CRC-4 generator polynomial [1 0 0 1 1], for K=12, calculate the generator matrix G=[IP], as shown in Table 1. Perform row swapping on the generator matrix G. Based on the row number of element 1 in column 13, swap rows 2, 3, 4, 5, 7, 9, 10 to rows 1, 2, 3, 4, 5, 6, 7; based on the row number of 1 in column 14, swap row 11 to row 10; based on the row number of 1 in column 15, swap row 12 to row 11, finally obtaining G=[I'P'], as shown in Table 4. Based on the left square matrix I' of G', read the column number of element 1 row by row to obtain the initial interleaving sequence π0=[2,3,4,5,7,9,10,8,6,11,12,1], where π0 represents the initial interleaving of the information block.

[0305]

[0306]

[0307] Table 4

[0308] (2) Insert rows into P' to obtain P'". The element 1 of the inserted row can be adjacent to the last element 1 of the same column in P', or it can be separated from the last element 1 of the same column in P' by several rows. The inserted row represents the position of the CRC bits after interleaving. For example, insert rows into the matrix P' in the 8th, 12th, 14th and 16th rows in sequence. The row number sequence is [8,12,14,16], as shown in Table 5.

[0309] (3) Insert the CRC bits [13,14,15,16] into the initial interleaving sequence at positions [8,12,14,16] to obtain the final interleaving sequence π = [2,3,4,5,7,9,10, 13 ,8,6,11,14 ,12, 15 ,1, 16 The check equations for the four CRC bits can be expressed as follows: [1,2,3,4,5,6,7,8], [2,3,4,7,9,10,11,12], [3,4,5,6,10,11,13,14], [1,2,3,6,9,10,13,15,16].

[0310] The insertion position of the rows is not limited; it can be placed as far forward as possible, before the special CRC bits in the information block that satisfies the verification. For ordinary CRC bits, the insertion position is arbitrary. For example, rows can be inserted sequentially into matrix P' at rows 9, 13, 14, and 16, resulting in the row number sequence [9, 13, 14, 16], as shown in Table 6. Inserting the CRC bits [13, 14, 15, 16] into the initial interleaving sequence at positions [9, 13, 14, 16] yields the final interleaving sequence π = [2, 3, 4, 5, 7, 9, 10, 8, ...]. 13 ,6,11,12, 14 , 15 ,1, 16 The check equations for the four CRC bits can be expressed as follows: [1,2,3,4,5,6,7,9], [2,3,4,7,8,10,11,13], [3,4,5,6,10,11,13,14], [1,2,3,6,9,10,13,15,16].

[0311]

[0312] Table 5

[0313]

[0314]

[0315] Table 6

[0316] Figure 11 This is a flowchart illustrating another encoding method provided in an embodiment of this application. This method can be... Figure 7 , Figure 12 or Figure 13 The encoding device shown is executed. The method includes:

[0317] 1101: Obtain the CRC length Lcrc and CRC polynomial. This step can be performed by... Figure 7 Acquisition unit 701, Figure 12 Processor 1202 or Figure 13 The signal processor 1302 executes the operation. The CRC length Lcrc can usually be pre-configured in the transceiver of the communication system.

[0318] 1102: Perform CRC encoding on the information block. This step can be performed by... Figure 7 CRC encoding unit 701, Figure 12 Processor 1202 or Figure 13 The signal processor 1302 executes.

[0319] Assuming A = K, B = K + Lcrc, the input to the CRC encoding is the sequence a0, a1, a2, ..., a A-1 The check bits generated after CRC encoding are p0, p1, ..., p Lcrc-1 The output sequence after CRC encoding is b1, b2, ..., b B-1 The sequence obtained by CRC encoding satisfies formula (3).

[0320]

[0321] 1103: Obtain the interleaved sequence π = [π1, π2, ..., π] B The interleaving sequence can be pre-set or calculated based on the CRC generation matrix, the information block length, and the CRC length Lcrc. Through interleaving, Lpc CRC bits are positioned between the bits of the information block, with the check bits preceding the CRC bits. Lpc can be selected as a number less than Lcrc, or it can be selected according to the range determined by formula (2). Lpc, selected according to predetermined rules, can be configured in the transceiver end of the communication system.

[0322] 1104: The output sequence after CRC encoding based on the interleaved sequence is b1, b2, ..., b B-1 Interweaving is performed to obtain the interleaved sequence C0, C1, ..., C C-1 C = B. C0, C1, C2, ..., C C-1 The values ​​of the sequence correspond to bπ1, bπ2, ..., bπ B .

[0323] 1105: Set the values ​​of the information bits and freeze bits to obtain d0, d1, d2, d D-1 D = N, where N is the length of the Polar code mother code. This step can be performed by... Figure 7 Polar coding unit 703, Figure 12 Processor 1202 or Figure 13 The signal processor 1302 executes the settings. The values ​​of the information bit and the freeze bit are obtained according to formula (4).

[0324]

[0325] 1106: Arikan Polar encoding, the output encoded sequence is e0, e1, e2, ..., e E-1 Where E = N. The calculation process of Polar encoding can be represented by the following formula (5). This step can be performed by... Figure 7 The Polar encoding unit 703 is executed.

[0326] Where n = log₂N, formula (5)

[0327] Optionally, the method may further include step 1105: performing rate matching on the encoded sequence and outputting the rate-matched encoded sequence F0, F1, F2, ..., F F-1 F = M, where M is the target code length. If the target code length M is not the same as the mother code length N, rate matching is performed on the encoded sequence obtained in step 2105, for example, by repetition, shortening, or puncturing. When the mother code length N is less than the target code length M, the encoded sequence can be repeated (MN) bits to obtain the encoded sequence of the target code length M. If the mother code length N is greater than the target code length M, the encoded sequence of the target code length M can be obtained by puncturing or shortening (NM) bits. The puncturing or shortening scheme can be preset. Step 2105 can be... Figure 7 Rate matching unit (not shown in the figure) in the encoding device Figure 11 Processor 1102 or Figure 12 The signal processor 1202 executes.

[0328] like Figure 12 As shown, this application provides another encoding apparatus 1200 that can implement the encoding method of this application. The encoding apparatus 1200 includes:

[0329] Memory 1201 is used to store programs;

[0330] Processor 1202 is configured to execute the program stored in the memory, and when the program is executed, to perform... Figure 8The encoding method is illustrated. For example, the method includes: performing CRC encoding on an information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc; interleaving the CRC-encoded block, where Lpc CRC bits in the interleaved block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, where Lpc is an integer greater than 0 and less than Lcrc; mapping the interleaved block to information bits, setting frozen bits to a predetermined fixed value, and performing Polar encoding on the information bits and the frozen bits to obtain Polar codewords; wherein the positions of the information bits correspond to the positions of the B polarization channels with optimal reliability; the positions of the frozen bits correspond to the positions of the remaining NB polarization channels, and N is the length of the Polar code mother code.

[0331] The number of special CRC bits (Lpc), the interleaving sequence, and the generation method can be found in the aforementioned encoding method. The memory 1201 can be a physically independent unit or integrated with the processor 1202. For other details regarding the encoding method, please refer to... Figure 8 as well as Figure 8 The relevant parts of the corresponding embodiments will not be described again here.

[0332] Figure 12 The encoding device may further include a transmitter (not shown in the figure) for transmitting the encoded block obtained by the processor 1102 after Polar encoding of the information bits and frozen bits.

[0333] like Figure 13 As shown, this application provides another encoding apparatus 1300 that can implement the encoding method of this application. The encoding apparatus 1300 includes:

[0334] At least one input terminal (inPut) 1301 is used to receive information blocks;

[0335] The signal processor 1302 is used to perform CRC encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc; interleave the CRC-encoded block, where Lpc CRC bits in the interleaved block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks, where Lpc is an integer greater than 0 and less than Lcrc; map the interleaved block to the information bits, set the frozen bits to a predetermined fixed value, and perform Polar encoding on the information bits and the frozen bits to obtain Polar codewords; wherein the positions of the information bits are the positions corresponding to the B polarization channels with optimal reliability; the positions of the frozen bits are the positions corresponding to the remaining NB polarization channels, and N is the length of the Polar code mother code;

[0336] At least one output port (outPut) 1303 is used to output the encoded block obtained by the signal processor 1302.

[0337] The number of special CRC bits (Lpc), the interleaving sequence and its generation method, etc., can be found in the aforementioned encoding method. Optionally, the signal processor 1302 described above can be implemented in hardware, such as a baseband processor, processing circuit, encoder, or encoding circuit. For other details regarding the encoding method, please refer to... Figure 8 as well as Figure 8 The relevant parts of the corresponding embodiments will not be described again here.

[0338] Figure 12 The encoding device may further include a transmitter (not shown) for transmitting the encoded block output by the output port 1303.

[0339] The encoding device in this application can be any device with wireless communication capabilities, such as an access point, site, user equipment, base station, etc.

[0340] Figure 14 The decoding device 1400 shown can be used to execute the decoding method of this application. For example... Figure 15 As shown, the decoding process includes the following steps:

[0341] 1501. Obtain the positions of information bits and frozen bits in the bits to be decoded.

[0342] The acquisition unit 1401 acquires the positions of information bits and frozen bits in the bits to be decoded. The information bits include K bits of the information block and Lcrc bits of CRC, wherein Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it verifies. The acquisition unit 1401 can acquire the positions of information bits and frozen bits according to the reliability of the polarization channel, wherein the reliability of the polarization channel corresponding to the information bit is higher than the reliability of the polarization channel corresponding to the frozen bit. Specifically, the acquisition unit 1401 selects K+Lcrc most reliable bits as information bits according to the reliability of the polarization channels, and uses the remaining polarization channels as frozen bits. K is the size of the information block, and Lcrc is the number of CRC bits.

[0343] 1502. The Serial Cancellation List (SCL) decoding algorithm is used to decode the bits to be decoded in sequence and output the L candidate paths with the best metric values.

[0344] The decoding unit 1402 uses the Serial Cancellation List (SCL) decoding algorithm to decode the bits to be decoded sequentially and outputs L candidate paths with the best metric values. During the decoding process, the value of the frozen bit in each candidate path is set to a fixed value. The value of each CRC bit in the Lpc CRC bits is determined according to the value of the bit in the information block it is checking before that CRC bit. The remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits.

[0345] In SCL decoding, CRC bits are decoded as information bits, which are unknown bits and require path extension during decoding. Since interleaving at the encoding end ensures that the value of some CRC bits is determined solely by the preceding information bits, if these CRC bits are used as parity check bits, decoding is performed similarly to frozen bits, treating them as known bits. No path extension is performed during decoding; the decoding result of these CRC bits is simply determined using the previously decoded information bits and the parity check equation. Frozen bits do not require path extension; they are directly set to a pre-defined fixed value during decoding. Refer to Figure 2 for the specific decoding process. Figure 3 And its corresponding description.

[0346] 1503. Deinterleave the T candidate paths with the best metric values ​​among the L candidate paths, where T is an integer greater than 0 and less than or equal to L.

[0347] The deinterleaving unit 1403 deinterleaves the T candidate paths with the optimal metric values among the L candidate paths, where T is an integer greater than 0 and less than or equal to L. That is to say, the deinterleaving unit 1403 can deinterleave all L candidate paths (T = L), or can select some paths for deinterleaving (T < L). Under the given upper limits of Lrc, Lpc and false alarm probability, the value of T can be determined by referring to formula (2).

[0348] 1504. Perform CRC check on the T candidate paths.

[0349] The CRC check unit 1404 can start from the candidate path with the optimal metric value and perform CRC check on the T candidate paths in sequence. The CRC check unit 1404 can perform CRC check on all T candidate paths respectively to obtain the results of passing or failing the check. It can also stop checking the remaining candidate paths after obtaining the first candidate path that passes the CRC check.

[0350] 1505. Take the information block in the candidate path that passes the CRC check and has the optimal path metric as the decoding output.

[0351] The output unit 1405 selects the candidate path that passes the CRC check and has the optimal path metric, and takes the information block corresponding to the information bits therein as the output of this decoding. If the CRC check unit 1404 starts the CRC check from the candidate path with the optimal metric value, the first candidate path that passes the CRC check can be directly used as the decoding result, and the information block therein is output.

[0352] Step 1501 may further include obtaining a check equation. The check equation can be determined by the CRC polynomial and the interleaving sequence. The generation matrix determined by the CRC polynomial determines the information bits of each CRC check, and the interleaving sequence can determine the positions of the information bits of each CRC check after interleaving, so as to obtain the check equation after interleaving.

[0353] Figure 16 This is an example of the SCL decoding algorithm List = 2, and 2 candidate paths are retained during the decoding process. Usually, the first few bits are frozen bits and are set to fixed values, such as 0 or 1. Therefore, the decoding actually starts from the first information bit. Figure 16In the decoding process, the PM value is calculated using formula (1). By retaining the path with the smallest PM value during each expansion, two candidate paths, L1 and L2, are obtained as shown by the arrows. The final PM value of path L1 is 0.3, and the final PM value of the other path L2 is 0.2. The path L2 with the smallest PM (optimal metric value) is first subjected to CRC check. If the check passes, L2 is selected as the decoding output. If the L2 path check fails, the L1 path is checked again. If the check passes, L1 is selected as the decoding output. If both L1 and L2 fail the check, the L2 path with the smaller PM (optimal metric value) can be selected as the decoding result output. If both L1 and L2 fail the check, the decoding is considered to have failed. During the decoding process, the value of List can be different, such as List = 8, 16, 32, or 64, etc.

[0354] Figure 16 The i-th bit marked in the diagram is the partial CRC bit (special CRC bit) mentioned in this application. The two arrows 1601 indicate that the value of this special CRC bit is determined by the (i-3)-th bit (information bit). It can be seen that when decoding the i-th bit, path extension is not required; the value of the i-th bit is determined by the value of the (i-3)-th bit in the path. Therefore, the value of the special CRC bit in path L1 is 0, and the value of the special CRC bit in path L2 is 1. Figure 16 and Figure 3 The difference is that the i-th bit is in Figure 3 The part in the middle corresponds to the frozen bit, while in the middle... Figure 15 The corresponding bit is a special CRC bit. Figure 16 In the decoding process, the PM value is compared with the special CRC bits. Figure 3 Things have changed compared to before. Specifically, Figure 16 In this example, we assume that the LLR(i) of the special CRC bits in paths L1 and L2 is less than 0. We assume that the value corresponding to LLR(i) being less than 0 is 1. The decoding result of bit i in path L1 is 0, which is inconsistent with the result of LLR(i). According to formula (1), the PM value is increased by |LLR(i)|, which is assumed to be 0.3. In path L2, the decoding result of bit i is 1, which is consistent with the value corresponding to LLR(i). According to formula (1), PM(i) = PM(i-1) = 0.2. If the decoding of L1 is incorrect, the special CRC bit i, which is determined based on the result of the previous decoding, may also be incorrect. This will increase the probability that the decoding result of bit i is inconsistent with the value corresponding to LLR(i). PM(i) will be increased by adding the penalty value |LLR(i)|, which will increase the PM value of the path. The probability of the erroneous path being deleted during the decoding process will also increase. In this example, the smaller the PM value, the better the path is, and the larger the PM value, the worse the path is.

[0355] Figure 17(a) compares the performance of the proposed scheme with that of the traditional CA-Polar under an AWGN channel when List=8 and K=32. Figure 17(b) compares the performance of the proposed scheme with that of the traditional CA-Polar under an AWGN channel when K=48. In the traditional CA-Polar, all CRC bits are used for CRC checksum verification for error correction or detection. The proposed scheme interleaves some CRC bits into the bits between information blocks, and the bits of the information block being checked are all before the CRC bits, which are used as the PC bit for decoding. In Figures 17(a) and 17(b), the performance curve represented by the solid line corresponds to a CRC length of 27, where 8 bits are interleaved and used as PC bits to assist SCL decoding, and the remaining CRC bits are used to select the path after SCL decoding; the dashed line represents a CRC length of 27, all of which are used to select the path after SCL decoding. As can be seen, compared with CA-Polar, the proposed solution has a performance gain of more than 0.4 dB for K=32 and a gain of more than 0.1 dB for K=48.

[0356] like Figure 18 The decoding apparatus 1800 shown can also be used to perform a decoding method. The decoding apparatus 1800 includes:

[0357] Memory 1801 is used to store programs;

[0358] Processor 1802 is configured to execute the program stored in the memory, and when the program is executed, to perform... Figure 15 The decoding method shown includes: obtaining the positions of information bits and frozen bits in the bits to be decoded, wherein the information bits include K bits of the information block and Lcrc bits of CRC, wherein Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it checks, wherein Lpc is an integer greater than 0 and less than Lcrc; decoding the bits to be decoded sequentially using the Serial Cancellation List (SCL) decoding algorithm, and outputting L candidate paths with the best metric value, wherein the value of the frozen bit in each candidate path is set to a fixed value agreed upon during the decoding process, and the value of each of the Lpc bits of CRC is determined according to the value of the bits of the information block it checks before that CRC bit, and the remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits; deinterleaving the T candidate paths with the best metric value among the L candidate paths, where T is an integer greater than 0 and less than or equal to L; performing CRC check on the T candidate paths, and using the information block in the candidate path that passes the CRC check and has the best path metric as the decoded output.

[0359] If the CRC check of all T candidate paths fails, the path with the best metric value can be selected as the decoding output, or the decoding can be considered a failure.

[0360] The details regarding the number of special CRC bits (Lpc), the interleaving sequence and its generation method, and the number of CRC checks can be found in the embodiments of the aforementioned encoding and decoding methods. The memory 1801 can be a physically independent unit or integrated with the processor 1802.

[0361] Figure 18 The decoding device may further include a receiver (not shown) for receiving the bit information to be decoded.

[0362] like Figure 19 As shown, this application provides another decoding apparatus 1900 that can implement the encoding method of this application. The decoding apparatus 1900 includes:

[0363] At least one input terminal 1901 is used to receive the bit information to be decoded;

[0364] Signal processor 1902 is used to obtain the positions of information bits and frozen bits in the bits to be decoded. The information bits include K bits of the information block and Lcrc bits of CRC, wherein Lpc bits of CRC are located between the bits of the information block, and each of the Lpc bits of CRC is located after all the bits it checks, where Lpc is an integer greater than 0 and less than Lcrc. The serial cancellation list (SCL) decoding algorithm is used to decode the bits to be decoded sequentially, and L candidate paths with the best metric values ​​are output. During the decoding process, the value of the frozen bits in each candidate path is set to a fixed value according to an agreement. The value of each of the Lpc bits of CRC is determined according to the value of the bits of the information block it checks before that CRC bit. The remaining (Lcrc-Lpc) CRC bits are decoded according to the information bits. The T candidate paths with the best metric values ​​among the L candidate paths are deinterleaved, where T is an integer greater than 0 and less than or equal to L. CRC checks are performed on the T candidate paths.

[0365] At least one output terminal 1903 is used to output the information block in the first candidate path that passes the CRC check as the decoded output.

[0366] For details regarding the number of special CRC bits (Lpc), the interleaving sequence and its generation method, and the number of CRC checks, please refer to the aforementioned examples of the encoding and decoding methods.

[0367] Optionally, the signal processor 1902 described above can be implemented in hardware, such as a baseband processor, processing circuit, decoder, or decoding circuit.

[0368] Figure 19 The decoding device may further include a receiver (not shown) for receiving the bit information to be decoded.

[0369] The decoding device in this application embodiment can be any device with wireless communication function, such as an access point, site, user equipment, base station, etc.

[0370] The information block mentioned in this application refers to information bits to be transmitted, which can also be called an information bit sequence, a bit sequence to be encoded, a data block, data bits, an information bit set, an information bit vector, etc. Correspondingly, the length of the information block can be called the information block size, which refers to the number of bits in the information bit sequence, the number of bits to be encoded in the bit sequence to be encoded, the number of bits in the data block, the number of data bits, or the number of elements in the information bit set. The coded block mentioned in this application can also be called coded bits, a coded bit sequence, etc.

[0371] The Serial Cancellation List (SCL) decoding algorithm described in the embodiments of this application includes other sequential decoding algorithms, SCL-like decoding algorithms that provide multiple candidate paths, or improved SCL decoding algorithms.

[0372] The encoding or decoding device described in the embodiments of this application may be a separate and independent device in actual use; or it may be an integrated device used to encode the information to be sent and then send it, or to decode the received information.

[0373] The units and methods described in the embodiments of this application can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application.

[0374] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and other division methods may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system. Some steps in the method may be omitted or not performed. Furthermore, the coupling or direct coupling or communication connection between the various units may be implemented through some interfaces, which may be electrical, mechanical, or other forms.

[0375] The units described as separate components may or may not be physically separate; they may be located in one place or distributed across multiple network units. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0376] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes, USB flash drives, ROM, RAM, etc.), optical media (e.g., CDs, DVDs, etc.), or semiconductor media (e.g., solid state disks (SSDs)).

[0377] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Polar encoding method, characterized in that, include: The information block is encoded using Cyclic Redundancy Check (CRC) to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc. The CRC-encoded blocks are interleaved, and the Lpc CRC bits in the interleaved blocks are located between the bits of the information blocks, with each of the Lpc CRC bits following the bit it checks. Where Lpc is an integer greater than 0 and less than Lcrc, and satisfies the following condition: Where T is the number of candidate paths for the decoding result that need to be selected through CRC check during decoding, and FAR is the upper limit of the false alarm probability of the communication system. The interleaved coded blocks are mapped to information bits, and the information bits are then polar encoded to obtain polar encoded codewords; wherein the position of the information bits is determined based on the reliability of the polarization channel.

2. The method according to claim 1, characterized in that, The CRC-encoded block satisfies the following formula: in This represents the bits in the CRC-encoded block. This represents the bits in the information block. A represents the CRC bits obtained after CRC encoding, where A equals K.

3. The method according to claim 1 or 2, characterized in that, The interleaving of the CRC-encoded blocks includes: using an interleaving sequence π=[π1, π2, ..., π...]. n The CRC-encoded block is interleaved, transforming the CRC-encoded bit sequence [b1, b2, ..., bn] into bπ1, bπ2, ..., bπ. n Where n is an integer greater than 0 and less than or equal to B, π n The value represents the bit position number of the nth bit in the interleaved coded block within the coded block before interleaving.

4. The method according to claim 1 or 2, characterized in that, T=4, or T=8.

5. The method according to claim 1 or 2, characterized in that, Lcrc=24.

6. The method according to claim 1 or 2, characterized in that, Lcrc and Lpc satisfy the following relationship: Lcrc-Lpc=10; or Lcrc-Lpc=18.

7. A Polar encoding method, characterized in that, include: The information block is encoded using Cyclic Redundancy Check (CRC) to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc. The CRC-encoded blocks are interleaved, and the Lpc CRC bits in the interleaved blocks are located between the bits of the information blocks, with each of the Lpc CRC bits following the bit it checks; where Lcrc equals 24 and Lpc is an integer greater than 0 and less than or equal to 13. The interleaved coded blocks are mapped to information bits, and the information bits are then polar encoded to obtain polar encoded codewords; wherein the position of the information bits is determined based on the reliability of the polarization channel.

8. The method according to claim 7, characterized in that, The CRC-encoded block satisfies the following formula: in This represents the bits in the CRC-encoded block. This represents the bits in the information block. A represents the CRC bits obtained after CRC encoding, where A equals K.

9. The method according to claim 7 or 8, characterized in that, Lpc=6.

10. The method according to claim 7 or 8, characterized in that, Lcrc-Lpc=11, or Lcrc-Lpc=19.

11. The method according to claim 7 or 8, characterized in that, The interleaving of the CRC-encoded blocks includes: using an interleaving sequence π=[π1, π2, ..., π...]. n The CRC-encoded block is interleaved, transforming the CRC-encoded bit sequence [b1, b2, ..., bn] into bπ1, bπ2, ..., bπ. n Where n is an integer greater than 0 and less than or equal to B, π n The value represents the bit position number of the nth bit in the interleaved coded block within the coded block before interleaving.

12. An encoding device, characterized in that, include: The Cyclic Redundancy Check (CRC) encoding unit is used to perform CRC encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc. The interleaving unit interleaves the CRC-encoded blocks. The Lpc CRC bits in the interleaved block are located between the bits of the information block, and each of the Lpc CRC bits follows all the bits it checks. Lpc is an integer greater than 0 and less than Lcrc, and satisfies the following condition: Where T is the number of candidate paths for the decoding result that need to be selected through CRC check during decoding, and FAR is the upper limit of the false alarm probability of the communication system. A Polar coding unit is used to map the coded block interleaved by the interleaving unit to information bits, and to perform Polar coding on the information bits to obtain Polar coded codewords; wherein the position of the information bits is determined according to the reliability of the polarization channel.

13. The apparatus according to claim 12, characterized in that, The CRC-encoded block satisfies the following formula: in This represents the bits in the CRC-encoded block. This represents the bits in the information block. A represents the CRC bits obtained after CRC encoding, where A equals K.

14. The apparatus according to claim 12 or 13, characterized in that, The interleaving unit is specifically used to employ an interleaving sequence π = [π1, π2, ..., π]. n The CRC-encoded block is interleaved, transforming the CRC-encoded bit sequence [b1, b2, ..., bn] into bπ1, bπ2, ..., bπ. n Where n is an integer greater than 0 and less than or equal to B, π n The value represents the bit position number of the nth bit in the interleaved coded block within the coded block before interleaving.

15. The apparatus according to claim 12 or 13, characterized in that, T=4, or T=8.

16. The apparatus according to claim 12 or 13, characterized in that, Lcrc=24.

17. The apparatus according to claim 12 or 13, characterized in that, Lcrc and Lpc satisfy the following relationship: Lcrc-Lpc=10; or Lcrc-Lpc=18.

18. An encoding device, characterized in that, include: The Cyclic Redundancy Check (CRC) encoding unit is used to perform CRC encoding on the information block to obtain a CRC-encoded block of length B, where the CRC length is Lcrc, the information block length is K, and B = K + Lcrc. The interleaving unit interleaves the CRC-encoded block. The Lpc CRC bits in the interleaved block are located between the bits of the information block, and each of the Lpc CRC bits is located after all the bits it checks. Here, Lcrc is equal to 24, and Lpc is an integer greater than 0 and less than or equal to 13. A Polar coding unit is used to map the coded block interleaved by the interleaving unit to information bits, and to perform Polar coding on the information bits to obtain Polar coded codewords; wherein the position of the information bits is determined according to the reliability of the polarization channel.

19. The apparatus according to claim 18, characterized in that, The CRC-encoded block satisfies the following formula: in This represents the bits in the CRC-encoded block. This represents the bits in the information block. A represents the CRC bits obtained after CRC encoding, where A equals K.

20. The apparatus according to claim 18 or 19, characterized in that, Lpc=6.

21. The apparatus according to claim 18 or 19, characterized in that, Lcrc-Lpc=11, or Lcrc-Lpc=19.

22. The apparatus according to claim 18 or 19, characterized in that, The interleaving unit is specifically used to employ an interleaving sequence π = [π1, π2, ..., π]. n The CRC-encoded block is interleaved, transforming the CRC-encoded bit sequence [b1, b2, ..., bn] into bπ1, bπ2, ..., bπ. n Where n is an integer greater than 0 and less than or equal to B, π n The value represents the bit position number of the nth bit in the interleaved coded block within the coded block before interleaving.

23. A Polar decoding method, characterized in that, include: Obtain the information of the bits to be decoded; The position of the information bit is obtained based on the reliability of the polarization channel. The information bit includes Lcrc cyclic redundancy check (CRC) bits and K bits of the information block. The Lpc CRC bits are located between the K bits of the information block, and each of the Lpc CRC bits is located after the position of the bit it checks. Where Lpc is an integer greater than 0 and less than Lcrc, and satisfies the following condition: Where T is the number of candidate paths for the decoding result that need to be selected through CRC check during decoding, and FAR is the upper limit of the false alarm probability of the communication system. The bits to be decoded are decoded according to the position of the information bits.

24. The method according to claim 23, characterized in that, T=4, or T=8.

25. The method according to claim 23 or 24, characterized in that, Lcrc=24.

26. The method according to claim 23 or 24, characterized in that, Lcrc and Lpc satisfy the following relationship: Lcrc-Lpc=10; or Lcrc-Lpc=18.

27. A Polar decoding method, characterized in that, include: Obtain the information of the bits to be decoded; The position of the information bit is obtained based on the reliability of the polarization channel. The information bit includes Lcrc cyclic redundancy check (CRC) bits and K bits of the information block. The Lpc CRC bits are located between the K bits of the information block, and each of the Lpc CRC bits is located after the bit it checks. Lcrc is equal to 24, and Lpc is an integer greater than 0 and less than or equal to 13. The information bits to be decoded are decoded according to their positions.

28. The method according to claim 27, characterized in that, The value of Lpc is 6.

29. The method according to claim 27, characterized in that, Lcrc-Lpc=11, or Lcrc-Lpc=19.

30. A decoding device, characterized in that, include: The acquisition unit is used to acquire the bit information to be decoded and to acquire the position of the information bits according to the reliability of the polarization channel. The information bits include K bits of the information block and Lcrc bits of cyclic redundancy check (CRC) bits, wherein Lpc bits are located between the bits of the information block, and each of the Lpc bits of CRC bits is located after all the bits it checks. Lpc is an integer greater than 0 and less than Lcrc, and satisfies the following condition: Where T is the number of candidate paths for the decoding result that need to be selected through CRC check during decoding, and FAR is the upper limit of the false alarm probability of the communication system. A decoding unit is used to decode the bit information to be decoded according to the position of the information bit to obtain a decoded information block; The output unit is used to output the decoded information block.

31. The apparatus according to claim 30, characterized in that, T=4, or T=8.

32. The apparatus according to claim 30 or 31, characterized in that, Lcrc=24.

33. The apparatus according to claim 30 or 31, characterized in that, Lcrc and Lpc satisfy the following relationship: Lcrc-Lpc=10; or Lcrc-Lpc=18.

34. A decoding device, characterized in that, include: The acquisition unit is used to acquire the bit information to be decoded and to acquire the position of the information bit according to the reliability of the polarization channel. The information bit includes K bits of the information block and Lcrc cyclic redundancy check (CRC) bits, wherein Lpc CRC bits are located between the bits of the information block, and each CRC bit in Lpc CRC bits is located after all the bits it checks. Wherein, Lcrc is equal to 24 and Lpc is an integer greater than 0 and less than or equal to 13. A decoding unit is used to decode the bit information to be decoded according to the position of the information bit to obtain a decoded information block; The output unit is used to output the decoded information block.

35. The apparatus according to claim 34, characterized in that, Lpc=6.

36. The apparatus according to claim 34, characterized in that, Lcrc-Lpc=11, or Lcrc-Lpc=19.

37. An encoding device, characterized in that, include: At least one input terminal is provided for receiving information blocks; A signal processor is configured to perform Polar encoding on the information block according to any one of claims 1-11 to obtain Polar encoded codewords; At least one output terminal is used to output the Polar encoded codeword.

38. A decoding device, characterized in that, include: At least one input terminal is provided for receiving the bit information to be decoded; A signal processor, configured to decode the bit information to be decoded using the method according to any one of claims 23-29, to obtain a decoded information block; At least one output terminal is used to output the decoded information block.

39. A communication device, characterized in that, Includes a processor for executing a program stored in a memory, causing the communication device to perform the method according to any one of claims 1-11, or to perform the method according to any one of claims 23-29.

40. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a computer, cause the method of any one of claims 1-11 to be performed; or cause the method of any one of claims 23-29 to be performed.

41. A computer program product containing instructions, characterized in that, When it is run on a computer, it causes the method of any one of claims 1-11 to be performed; or causes the method of any one of claims 23-29 to be performed.

Images