A processing method and device of a QC-LDPC decoder

Abstract

The present application relates to the technical field of communication, especially to a processing method of QC-LDPC decoder, the method comprising: obtaining soft information of QC-LDPC decoder; performing field splicing on the soft information to obtain spliced code block set; performing decoding on the spliced code block set to obtain decoding information field; deleting zero-puncturing bits in the decoding information field to obtain standard information field. The method improves the working efficiency of QC-LDPC decoder, makes QC-LDPC decoder compatible with different code length and code rate of QC-LDPC code, and further makes QC-LDPC decoder work flexibly and in real time according to different protocols.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a processing method and apparatus for a QC-LDPC decoder. Background Technology

[0002] Currently, QC-LDPC (Quasi-Cyslice Low Density Parity Check Code) codes are widely used in wireless communication protocols, such as IEEE 802.11n / ac / ax, due to their excellent error correction performance. Typically, QC-LDPC decoders directly perform complex decoding of the received user data and must also consider the requirements of various protocols, leading to reduced efficiency. Summary of the Invention

[0003] This application provides a processing method and apparatus for a QC-LDPC decoder, which solves the technical problem of reduced working efficiency of QC-LDPC decoders in the prior art. It achieves the technical effects of improving the working efficiency of QC-LDPC decoders, enabling QC-LDPC decoders to be compatible with different code lengths and code rates of QC-LDPC codes, and enabling QC-LDPC decoders to work flexibly and in real time according to different protocols.

[0004] In a first aspect, embodiments of the present invention provide a processing method for a QC-LDPC decoder, comprising:

[0005] Obtain the soft information of the QC-LDPC decoder;

[0006] The soft information is concatenated to obtain a set of concatenated code blocks;

[0007] The concatenated code block set is decoded to obtain the decoding information field;

[0008] Remove the zero bits from the decoded information field to obtain the standard information field.

[0009] Preferably, the acquisition of the soft information of the QC-LDPC decoder includes:

[0010] After acquiring the soft information, the soft information is cached, wherein the cache includes a first-in-first-out cache.

[0011] Preferably, caching the soft information includes:

[0012] The soft information is buffered according to the modulation scheme and number of antennas of the QC-LDPC decoder.

[0013] Preferably, the step of concatenating fields in the soft information includes:

[0014] During the process of reading the soft information in the cache, when reading a codeword from the soft information, a zero-shortening bit is added between the information bit and the check bit of the codeword. The zero-shortening bit is determined based on the total number of codewords corresponding to the soft information and the total number of zero-shortening bits corresponding to the soft information.

[0015] Preferably, if a copy bit of the codeword exists after the check bit of the codeword, the method further includes:

[0016] Delete the copied bit;

[0017] If no pruned bits of the codeword exist after the check bit of the codeword, the method further includes:

[0018] The plucking bit is added after the check bit.

[0019] Preferably, obtaining the spliced ​​code block set includes:

[0020] When reading a codeword from the soft information, the concatenated code block of the codeword is obtained according to the codeword length; if the bit width of the concatenated code block of the codeword does not reach the bit width threshold, the bit width of the concatenated code block of the codeword is filled to the bit width threshold.

[0021] Based on the same inventive concept, in a second aspect, the present invention also provides a processing apparatus for a QC-LDPC decoder, comprising:

[0022] The acquisition module is used to acquire the soft information of the QC-LDPC decoder;

[0023] The preprocessing module is used to concatenate fields of the soft information to obtain a set of concatenated code blocks;

[0024] The decoding module is used to decode the concatenated code block set to obtain the decoding information field;

[0025] The post-processing module is used to remove the zero bits from the decoded information field to obtain the standard information field.

[0026] Preferably, the acquisition module is specifically used for:

[0027] After acquiring the soft information, the soft information is cached, and then the soft information is read from the cache, wherein the cache includes a first-in-first-out cache.

[0028] Based on the same inventive concept, in a third aspect, the present invention provides a QC-LDPC decoder, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of a processing method for the QC-LDPC decoder.

[0029] Based on the same inventive concept, in a fourth aspect, the present invention provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps of a processing method for a QC-LDPC decoder.

[0030] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0031] In this embodiment of the invention, after acquiring the soft information of the QC-LDPC decoder, the soft information is concatenated to obtain a concatenated code block set. Here, the soft information is preprocessed by concatenating its fields, and the soft information being concatenated is simultaneously segmented into blocks to obtain the concatenated code block set. This facilitates decoding of the concatenated code block set, improves the working efficiency of the QC-LDPC decoder, and enables the QC-LDPC decoder to be compatible with different code lengths and rates of QC-LDPC codes. This allows the QC-LDPC decoder to work flexibly and in real-time according to different protocols. After decoding the concatenated code block set, a decoding information field is obtained. This decoding information field is then post-processed by removing the zero-shortening bits to obtain a standard information field, which can be directly used by subsequent higher-level devices, further improving the working efficiency of the QC-LDPC decoder. Attached Figure Description

[0032] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0033] Figure 1 A flowchart illustrating the steps of the processing method of the QC-LDPC decoder in an embodiment of the present invention is shown.

[0034] Figure 2 A schematic diagram of the format of soft information in an embodiment of the present invention is shown;

[0035] Figure 3 This diagram illustrates the structure of a codeword read in an embodiment of the present invention.

[0036] Figure 4 This diagram illustrates the structure of the codeword after field concatenation in an embodiment of the present invention.

[0037] Figure 5 A schematic diagram of the processing device of the QC-LDPC decoder in an embodiment of the present invention is shown. Detailed Implementation

[0038] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0039] Example 1

[0040] The first embodiment of the present invention provides a processing method for a QC-LDPC decoder, such as... Figure 1 As shown, it includes:

[0041] S101, obtain the soft information of the QC-LDPC decoder;

[0042] S102, perform field concatenation on the soft information to obtain a concatenated code block set;

[0043] S103, decode the spliced ​​code block set to obtain the decoding information field;

[0044] S104, remove the zero bits from the decoded information field to obtain the standard information field.

[0045] The processing method in this embodiment is applied to a quasi-cyclic low-density parity check (QC-LDPC) decoder, which is abbreviated as QC-LDPC decoder. The QC-LDPC decoder is a WLAN (Wireless Local Area Network) device that uses QC-LDPC encoding.

[0046] Below, in conjunction with Figure 1 The following details the specific implementation steps of the processing method of the QC-LDPC decoder provided in this embodiment:

[0047] First, execute step S101 to obtain the soft information of the QC-LDPC decoder.

[0048] Specifically, after acquiring the soft information, it is buffered according to the modulation scheme and number of antennas of the QC-LDPC decoder. The buffering includes First In, First Out (FIFO) buffering.

[0049] For example, suppose the QC-LDPC decoder has two antennas, n_nss = 0 and n_nss = 1 respectively.

[0050] The modulation schemes of the QC-LDPC decoder with the first antenna n_nss=0 include: 1 (BPSK), 2 (QPSK), 4 (16QAM), 6 (64QAM), 8 (256QAM), 10 (1024QAM), and 12 (4096QAM).

[0051] The modulation schemes of the QC-LDPC decoder with the second antenna n_nss=1 include: 2 (BPSK), 4 (QPSK), 8 (16QAM), 12 (64QAM), 16 (256QAM), 10 (1024QAM), and 12 (4096QAM).

[0052] In this diagram, the number before the parentheses for each antenna represents the number of bits for each symbol, and the letter inside the parentheses indicates the modulation scheme. Modulation schemes include: BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 16QAM (16-Quadrature Amplitude Modulation), 64QAM (64-Quadrature Amplitude Modulation), 256QAM (256-Quadrature Amplitude Modulation), 1024QAM (1024-Quadrature Amplitude Modulation), and 4096QAM (4096-Quadrature Amplitude Modulation).

[0053] Taking the two antennas mentioned above, and using the QPSK debugging method as an example, as follows... Figure 2 As shown, the format of the soft information is determined by the modulation scheme and number of antennas of the QC-LDPC decoder. Assuming the bit width of the soft information is 8 bits, in... Figure 2 In the diagram, looking from right to left, dins0_0 represents the first bit of the first antenna, dins0_1 represents the second bit of the first antenna, dins1_0 represents the first bit of the second antenna, dins1_1 represents the second bit of the second antenna, and zeros represents the padding zeros. Since there are remaining bits in this soft information, zeros are used for padding.

[0054] In this embodiment, the use of FIFO buffering improves the processing efficiency and working efficiency of the QC-LDPC decoder.

[0055] After obtaining the soft information, step S102 is executed to concatenate the fields of the soft information to obtain a concatenated code block set.

[0056] Specifically, step S102 is to preprocess the soft information. The preprocessing process is to concatenate the fields of the soft information to obtain a concatenated code block set.

[0057] The specific process of concatenating fields in soft information is as follows: during the reading of soft information from the cache, when reading a codeword from the soft information, a zero-shortening bit is added between the information bits and the check bits of the codeword. The zero-shortening bit is determined based on the total number of codewords corresponding to the soft information and the total number of zero-shortening bits corresponding to the soft information.

[0058] It also needs to be explained that information bits represent valid information data, parity bits represent data used to verify valid information data, and null bits represent supplementary data when the width of the information bits read from the buffer is insufficient. If there is residual data in the previous codeword, the residual data is written into the information bits of the next codeword, with the residual data immediately following the end of the previous codeword. Then, the corresponding input width and length are retrieved from the FIFO buffer to form the information bits of the next codeword. Null bits are represented by padding with 0s of the corresponding length, and their corresponding soft information is +127 (the probability of being 0). The sign bit is filled with 0, and the other bits are filled with 1. For example, reading a codeword from the soft information will give you the codeword length and structure. The codeword length is 648 bits. Theoretically, this 648-bit codeword includes 324 bits of information bits and 324 bits of parity bits. In reality, 320 bits of information bits and 324 bits of parity bits of this 648-bit codeword are read from the buffer. Obviously, the actual 320 bits of information read are 4 bits short. These 4 bits are then formed into zero bits, which are filled with 0s of the corresponding length to make the read codeword more complete, which facilitates subsequent decoding and improves the working efficiency of the QC-LDPC decoder.

[0059] Specifically, when acquiring soft information, the total number of codewords and the total number of null bits corresponding to that soft information are obtained. Dividing the total number of codewords by the total number of null bits yields the null bits of the corresponding codeword. Therefore, when reading a codeword, the null bits of that codeword are obtained and added between the information bits and the check bits of that codeword.

[0060] For example, when acquiring soft information, if the total number of codewords corresponding to that soft information is 5, and the total number of zero-shortening bits corresponding to that soft information is 8, then dividing 8 by 5 yields a quotient of 1 and a remainder of 3. This means the first codeword is allocated 2 zero-shortening bits, the second codeword is allocated 2 zero-shortening bits, the third codeword is allocated 2 zero-shortening bits, the fourth codeword is allocated 1 zero-shortening bit, and the fifth codeword is allocated 1 zero-shortening bit. It's important to note that the quotient represents the number of zero-shortening bits allocated to each codeword corresponding to that soft information, and the remainder represents the number of zero-shortening bits added starting from the first codeword in that soft information, until all remaining zero-shortening bits are allocated.

[0061] When reading the first codeword, we know that it has been allocated 2 zero-shortening bits. These 2 zero-shortening bits are added between the information bits and the parity bits of the first codeword. When reading the second codeword, we know that it has been allocated 2 zero-shortening bits. These 2 zero-shortening bits are added between the information bits and the parity bits of the second codeword, and so on.

[0062] If a copy bit exists after the parity bit of the read codeword, the copy bit is deleted. If no pruning bit exists after the parity bit of the read codeword, a pruning bit is added after the parity bit. The copy bit indicates that during encoding, the actual codeword length of the read codeword did not reach its theoretical codeword length; therefore, a portion of the codeword's data was copied to the parity bit, forming the copy bit. Essentially, the copy bit represents the excess data in the read codeword. The pruning bit indicates that during encoding, the actual codeword length of the read codeword exceeded its theoretical codeword length; therefore, the excess data was deleted, and the remaining data was padded to complete the codeword for easier subsequent decoding. The pruning bit is represented by padding with zeros of the corresponding length, with the corresponding soft information being 0 (an indeterminate number), the sign bit being filled with 0, and the other bits being filled with 0.

[0063] Specifically, when acquiring soft information, the total number of codewords with copy bits, the total number of copy bits corresponding to the soft information, the total number of codewords without pruned bits, and the total number of pruned bits corresponding to the soft information are obtained. Dividing the total number of codewords with copy bits by the total number of copy bits yields the copy bits of the corresponding codeword. Dividing the total number of codewords without pruned bits by the total number of pruned bits yields the pruned bits of the corresponding codeword. The principles behind obtaining the copy bits and pruned bits of a codeword are the same as those for obtaining the zero-shortened bits of a codeword, and will not be elaborated further here. Therefore, when reading a codeword, either the copy bits or the pruned bits of that codeword can be obtained.

[0064] For example, during the process of reading soft information from the cache, a codeword is read, such as... Figure 3 As shown, this codeword includes data bits, parity bits, and repeat bits. Concatenating these fields results in the following codeword: Figure 4 As shown. Shortened bits are added between the data bits and parity bits of the codeword. Since repeat bits exist after the parity bits, these repeat bits are deleted.

[0065] It should also be noted that, Figure 4 The content within the dashed box represents the parity bits. This means that if the read codeword includes data bits and parity bits, then shortened bits are added between the data bits and parity bits of the codeword, and parity bits are added after the parity bits.

[0066] During the reading of soft information from the cache, not only is the codeword concatenated with fields each time it is read from the soft information, but the codeword being concatenated is also segmented into blocks. The specific process of segmentation is as follows: each time a codeword is read from the soft information, the concatenated code block of the codeword is obtained according to the codeword length; if the bit width of the concatenated code block of the codeword does not reach the bit width threshold, then the bit width of the concatenated code block of the codeword is padded to the bit width threshold.

[0067] Specifically, when acquiring soft information, the code length of the corresponding codeword is obtained. Since the QC-LDPC decoder, after dividing a codeword of arbitrary length into blocks, always results in a set of 24 concatenated code blocks, the size of each concatenated code block differs depending on the codeword length, meaning the bit width of each concatenated code block is different. For example, when the QC-LDPC decoder divides a codeword with a code length of 648 bits into blocks, it obtains 24 concatenated code blocks, and any one of these 24 blocks is 27 bits in size. When the QC-LDPC decoder divides a codeword with a code length of 1296 bits into blocks, it obtains 24 concatenated code blocks, and any one of these 24 blocks is 54 bits in size. The QC-LDPC decoder divides a codeword with a code length of 1944 bits into blocks, resulting in 24 concatenated code blocks. The size of any one of these 24 concatenated code blocks is 81 bits.

[0068] Therefore, when reading a codeword from the soft information, the codeword length is obtained. Based on this codeword length, the concatenated code block and its bit width are then determined. If the bit width of the concatenated code block does not reach the bit width threshold, it is padded to the threshold using a ping-pong operation. The bit width threshold is set based on the longest codeword length. Since the longest codeword is 1944 bits, setting the bit width threshold based on a 1944-bit codeword results in a bit width threshold of 81 bits for each concatenated code block.

[0069] For example, a codeword with a length of 648 bits is read from soft information. Based on the codeword length, the codeword is divided into 24 concatenated code blocks, and the bit width of any one of these 24 concatenated code blocks is 27 bits. Since the bit width of each concatenated code block is less than 81 bits (27 < 81), the high-order bits of each concatenated code block are filled with 0s, so that the bit width of each concatenated code block is 81 bits.

[0070] The following example illustrates the specific process of step S102:

[0071] A number is read from the cache to form a 648-bit codeword. This codeword is then concatenated and segmented. Specifically, 320 bits of information bits and 324 bits of parity bits are read from the cache. When the 27th number is read, the first concatenated codeword block is obtained; when the 54th number is read, the second concatenated codeword block is obtained, and so on. When the 320th number is read, the information bits of the codeword have been read. Four bits of zeroing are added after the information bits, and a concatenated codeword block is generated from the 297th to the 320th numbers read, along with the added 4 bits of zeroing. The parity bits continue to be read from the cache, and while concatenating the parity bits, segmentation is performed on the parity bits being concatenated.

[0072] In practical implementation, state machine 1 of the QC-LDPC decoder only performs field concatenation on soft information, while state machine 2 only performs block processing on the codeword being concatenated. This hierarchical control mechanism preprocesses the soft information, improving the efficiency of the QC-LDPC decoder and enabling it to be compatible with codewords of different code lengths and rates. It avoids the problems of numerous control situations, poor code readability, and poor robustness that result from mixing field concatenation and block processing together.

[0073] After the bit width of each concatenated code block in the concatenated code block set reaches the bit width threshold, step S103 is executed to decode the concatenated code block set to obtain the decoding information field. The method for decoding the concatenated code block set can be set according to actual needs, such as using the normalized minimum sum decoding method. After obtaining the decoding information field, post-processing is performed on the decoding information field, i.e., step S104 is executed to delete the zero-shortening bits in the decoding information field to obtain the standard information field, which can be directly used by subsequent devices.

[0074] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0075] In this embodiment, after acquiring the soft information of the QC-LDPC decoder, the soft information is concatenated to obtain a concatenated code block set. Here, the soft information is preprocessed by concatenating its fields, and the soft information being concatenated is simultaneously segmented into blocks to obtain the concatenated code block set. This facilitates decoding of the concatenated code block set, improves the efficiency of the QC-LDPC decoder, and enables the QC-LDPC decoder to be compatible with different code lengths and rates of QC-LDPC codes. This allows the QC-LDPC decoder to work flexibly and in real-time according to different protocols. After decoding the concatenated code block set, the decoding information field is obtained. This decoding information field is then post-processed by removing the zero-shortening bits to obtain the standard information field, which can be directly used by subsequent higher-level devices, further improving the efficiency of the QC-LDPC decoder.

[0076] Example 2

[0077] Based on the same inventive concept, the second embodiment of the present invention also provides a processing device for a QC-LDPC decoder, such as... Figure 5 As shown, it includes:

[0078] Acquisition module 201 is used to acquire the soft information of the QC-LDPC decoder;

[0079] Preprocessing module 202 is used to concatenate fields of the soft information to obtain a concatenated code block set;

[0080] Decoding module 203 is used to decode the spliced ​​code block set to obtain a decoding information field;

[0081] The post-processing module 204 is used to remove the zero bits in the decoded information field to obtain the standard information field.

[0082] As an optional embodiment, the acquisition module 201 is used to acquire the soft information of the QC-LDPC decoder, including:

[0083] After acquiring the soft information, the soft information is cached, wherein the cache includes a first-in-first-out cache.

[0084] As an optional embodiment, caching the soft information includes:

[0085] The soft information is buffered according to the modulation scheme and number of antennas of the QC-LDPC decoder.

[0086] As an optional embodiment, the preprocessing module 202 is used for field concatenation of the soft information, including:

[0087] During the process of reading the soft information in the cache, when reading a codeword from the soft information, a zero-shortening bit is added between the information bit and the check bit of the codeword. The zero-shortening bit is determined based on the total number of codewords corresponding to the soft information and the total number of zero-shortening bits corresponding to the soft information.

[0088] As an optional embodiment, if a copy bit of the codeword exists after the check bit of the codeword, the method further includes:

[0089] Delete the copied bit;

[0090] If no pruned bits of the codeword exist after the check bit of the codeword, the method further includes:

[0091] The plucking bit is added after the check bit.

[0092] As an optional embodiment, the preprocessing module 202, used to obtain the spliced ​​code block set, includes:

[0093] When reading a codeword from the soft information, the concatenated code block of the codeword is obtained according to the codeword length; if the bit width of the concatenated code block of the codeword does not reach the bit width threshold, the bit width of the concatenated code block of the codeword is filled to the bit width threshold.

[0094] Since the processing apparatus of the QC-LDPC decoder described in this embodiment is the apparatus used to implement the processing method of the QC-LDPC decoder in Embodiment 1 of this application, those skilled in the art can understand the specific implementation and various variations of the processing apparatus of the QC-LDPC decoder in this embodiment based on the processing method of the QC-LDPC decoder described in Embodiment 1 of this application. Therefore, how the processing apparatus of the QC-LDPC decoder implements the method in Embodiment 1 of this application will not be described in detail here. Any apparatus used by those skilled in the art to implement the processing method of the QC-LDPC decoder in Embodiment 1 of this application falls within the scope of protection of this application.

[0095] Example 3

[0096] Based on the same inventive concept, the third embodiment of the present invention also provides a QC-LDPC decoder, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of any of the above-described processing methods for the QC-LDPC decoder.

[0097] Example 4

[0098] Based on the same inventive concept, the fourth embodiment of the present invention also provides a readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of any of the processing methods of the QC-LDPC decoder described in the first embodiment above.

[0099] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0100] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0101] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0102] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0103] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0104] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A processing method for a QC-LDPC decoder, characterized in that, include: Obtain the soft information of the QC-LDPC decoder; The soft information is concatenated to obtain a set of concatenated code blocks; The process of concatenating fields in the soft information includes: during the reading of the soft information in the cache, when reading a codeword from the soft information, adding a zero-shortening bit between the information bit and the check bit of the codeword through the state machine 1 of the QC-LDPC decoder; The zero-shortening bit is determined as follows: the copy bit is determined based on the total number of codewords with copy bits and the total number of copy bits in the soft information; the pruned bit is determined based on the total number of codewords without pruned bits and the total number of pruned bits in the soft information; the zero-shortening bit includes the copy bit and the pruned bit. The process of obtaining the concatenated code block set includes: when reading a codeword from the soft information, obtaining the concatenated code block of the codeword through the state machine 2 of the QC-LDPC decoder according to the code length of the codeword; if the bit width of the concatenated code block of the codeword does not reach the bit width threshold, then filling the bit width of the concatenated code block of the codeword to the bit width threshold. The concatenated code block set is decoded to obtain the decoding information field; Remove the zero bits from the decoded information field to obtain the standard information field.

2. The method as described in claim 1, characterized in that, The acquisition of soft information of the QC-LDPC decoder includes: After acquiring the soft information, the soft information is cached, wherein the cache includes a first-in-first-out cache.

3. The method as described in claim 2, characterized in that, The step of caching the soft information includes: The soft information is buffered according to the modulation scheme and number of antennas of the QC-LDPC decoder.

4. The method as described in claim 3, characterized in that, If a copy bit of the codeword exists after the check bit of the codeword, the method further includes: Delete the copied bit; If no pruned bits of the codeword exist after the check bit of the codeword, the method further includes: The plucking bit is added after the check bit.

5. A processing device for a QC-LDPC decoder, characterized in that, include: The acquisition module is used to acquire the soft information of the QC-LDPC decoder; The preprocessing module is used to concatenate fields of the soft information to obtain a set of concatenated code blocks; The process of concatenating fields in the soft information includes: during the reading of the soft information in the cache, when reading a codeword from the soft information, adding a zero-shortening bit between the information bit and the check bit of the codeword through the state machine 1 of the QC-LDPC decoder; The zero-shortening bit is determined as follows: the copy bit is determined based on the total number of codewords with copy bits and the total number of copy bits in the soft information; the pruned bit is determined based on the total number of codewords without pruned bits and the total number of pruned bits in the soft information; the zero-shortening bit includes the copy bit and the pruned bit. The process of obtaining the concatenated code block set includes: when reading a codeword from the soft information, obtaining the concatenated code block of the codeword through the state machine 2 of the QC-LDPC decoder according to the code length of the codeword; if the bit width of the concatenated code block of the codeword does not reach the bit width threshold, then filling the bit width of the concatenated code block of the codeword to the bit width threshold. The decoding module is used to decode the concatenated code block set to obtain the decoding information field; The post-processing module is used to remove the zero bits from the decoded information field to obtain the standard information field.

6. The apparatus as claimed in claim 5, characterized in that, The acquisition module is specifically used for: After acquiring the soft information, the soft information is cached, and then the soft information is read from the cache, wherein the cache includes a first-in-first-out cache.

7. A QC-LDPC decoder, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1-4.

8. A readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1-4.

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