Chip power consumption optimization method and system based on multi-level optimization strategy

Abstract

The application provides a chip power consumption optimization method and system based on a multi-level optimization strategy, relates to the technical field of electronic engineering, and comprises the following steps: collecting real-time running state data of a chip, and obtaining a predicted load through Kalman filtering; based on the predicted load and real-time congestion degree in the real-time running state data, a plurality of candidate paths in the chip NoC are generated, and the path comprehensive cost of each candidate path is calculated to form a cost list; based on the real-time running state data, the predicted load and the cost list, a joint control instruction is output through a deep neural network model; the joint control instruction is subjected to performance constraint verification, if yes, it is determined that the verification is passed, and the chip is subjected to multi-level power consumption optimization based on the joint control instruction that passes the verification; otherwise, it is determined that the verification is not passed, and the joint control instruction is output; and the chip is subjected to multi-level power consumption optimization based on the joint control instruction that passes the verification.

Description

Technical Field

[0001] This invention relates to the field of electronic engineering technology, and in particular to a chip power consumption optimization method and system based on a multi-level optimization strategy. Background Technology

[0002] With continuous advancements in integrated circuit technology, chip integration density and operating frequencies have steadily increased, significantly enhancing chip performance. However, power consumption has also become a major bottleneck restricting chip design and applications. On one hand, excessive power consumption leads to increased chip temperature, affecting device reliability and lifespan; on the other hand, applications such as mobile terminals and IoT devices have a particularly urgent need for low power consumption. Therefore, how to effectively reduce chip power consumption while ensuring performance has become an important research direction in the field of chip design.

[0003] Currently, common power consumption optimization methods in the industry mainly include the following categories: First, at the process level, power consumption is reduced by improving semiconductor process materials, optimizing device structure, and adopting advanced process technology; Second, at the circuit level, common methods include clock gating, power gating, multi-voltage domain design (Multi-Vdd), dynamic voltage frequency regulation (DVFS), etc., which dynamically manage the power consumption of different functional modules.

[0004] However, existing chip power optimization methods typically rely on passive adjustments to real-time operating conditions, lacking effective prediction of future loads. This makes it difficult to respond promptly to sudden load changes, leading to performance fluctuations. Furthermore, most existing chip power optimization methods are limited to a single level or local module, lacking comprehensive consideration of chip interconnect network congestion and multi-level power control. This can easily result in fragmented optimization, making it difficult to balance overall power consumption and performance. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a chip power consumption optimization method based on a multi-level optimization strategy. This method addresses the problem that existing chip power consumption optimization methods typically rely on passive adjustments to the real-time operating state, lacking effective prediction of future loads. This leads to difficulty in responding promptly to sudden load changes, resulting in performance fluctuations. Furthermore, most existing chip power consumption optimization methods are limited to a single level or local module, lacking comprehensive consideration of chip interconnect network congestion and multi-level power consumption control. This easily leads to fragmented optimization and makes it difficult to balance overall power consumption and performance.

[0006] A first aspect of this invention proposes a chip power consumption optimization method based on a multi-level optimization strategy, comprising:

[0007] S1: Collects real-time operating status data of the chip;

[0008] S2: Based on the real-time operating status data, the workload of the chip is predicted by Kalman filtering to obtain the predicted load;

[0009] S3: Based on the predicted load and the real-time congestion in the real-time operating status data, generate multiple candidate paths in the chip NoC, and calculate the comprehensive path cost of each candidate path to form a cost list;

[0010] S4: Based on the real-time operating status data, the predicted load, and the cost list, output joint control commands through a deep neural network model;

[0011] S5: Perform performance constraint verification on the joint control instruction to determine whether the corresponding chip performance loss is within a preset threshold; if yes, determine that the joint control instruction verification has passed and proceed to S6; otherwise, determine that the joint control instruction verification has failed and return to S4.

[0012] S6: Based on the verified joint control instructions, perform multi-level power consumption optimization on the chip;

[0013] S7: Evaluate the multi-level power consumption optimization effect and determine whether the actual power consumption optimization effect of the chip has reached the expected target; if so, consolidate the optimization strategy through the feedback mechanism and return to S1; otherwise, adjust the optimization strategy based on the reason for not reaching the expected target and return to S1.

[0014] A second aspect of this invention provides a chip power consumption optimization system based on a multi-level optimization strategy, comprising: a processor and a memory;

[0015] The memory stores programs or instructions that can run on the processor, and when the programs or instructions are executed by the processor, they implement the steps of the chip power consumption optimization method based on a multi-level optimization strategy as described in the first aspect.

[0016] A third aspect of the present invention provides a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, the steps of the chip power consumption optimization method based on a multi-level optimization strategy as described in the first aspect are implemented.

[0017] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0018] In this embodiment of the invention, by collecting the real-time operating status of the chip and using Kalman filtering for load prediction, combined with joint decision-making and performance constraint verification of deep neural networks, a forward-looking response to load fluctuations is achieved, avoiding performance fluctuations caused by the lack of prediction in existing technologies. At the same time, by comprehensively calculating the NoC candidate paths and their costs, combined with unified control of multi-level power consumption and feedback iteration mechanism, the overall integrity and coordination of power consumption optimization are improved, cross-level collaborative capabilities are enhanced, and the dynamic scheduling of congestion factors is taken into account, thereby reducing power consumption while ensuring the stability and balance of overall performance. Attached Figure Description

[0019] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0020] Figure 1 This is a flowchart illustrating a chip power consumption optimization method based on a multi-level optimization strategy provided in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of a chip power consumption optimization system based on a multi-level optimization strategy provided in an embodiment of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] The chip power consumption optimization method based on a multi-level optimization strategy provided by the present invention will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0024] Reference manual attached Figure 1 The diagram shows a schematic flowchart of a chip power consumption optimization method based on a multi-level optimization strategy provided by an embodiment of the present invention.

[0025] This invention provides a chip power consumption optimization method based on a multi-level optimization strategy, which may include the following steps:

[0026] S1: Collects real-time operating status data of the chip.

[0027] In one possible implementation, the real-time operational status data specifically includes: core layer data and NoC layer data.

[0028] The core layer data includes the number of historical completed instructions, the number of instructions per cycle, the actual operating frequency, and the actual operating voltage.

[0029] NoC layer data includes real-time link occupancy, real-time virtual channel utilization, real-time router congestion, and path hop count.

[0030] It's worth noting that the advantage of combining core layer and NoC layer data is that it comprehensively reflects the chip's real-time operating status at both the computing and communication levels, providing more accurate input for subsequent load prediction. Simultaneously, this data serves as a crucial basis for modeling costs such as latency, power consumption, and performance degradation, leading to more reasonable control command generation.

[0031] S2: Based on real-time operating status data, the workload of the chip is predicted by Kalman filtering to obtain the predicted workload.

[0032] Kalman filtering is a recursive optimal estimation algorithm used to estimate the true state of a system from a series of observation data of a dynamic system in the presence of noise and uncertainty.

[0033] In one possible implementation, S2 specifically includes:

[0034] S201: Establish the state model and observation model of the chip workload, wherein the observation model includes the observation matrix and the measurement noise covariance.

[0035] Optionally, the state equation of the state model and the observation equation of the observation model are specifically as follows:

[0036]

[0037]

[0038] in, Let A represent the workload state vector of the nth control cycle, and let A represent the state transition matrix. B represents the workload state vector of the (n-1)th control cycle, and B represents the control input matrix. This represents the control quantity in the (n-1)th control cycle. This represents the process noise in the (n-1)th control cycle. H represents the observations in the nth control cycle, and H represents the observation matrix. This represents the noise measured in the nth control cycle.

[0039] S202: Using the posterior state estimate and error covariance of the previous control cycle as initial inputs, calculate the prior state estimate and prior error covariance based on the state model and the control commands issued to the chip in the previous control cycle.

[0040]

[0041]

[0042] in, This represents the prior state estimate for the nth control cycle. This represents the posterior state estimate for the (n-1)th control period. This represents the prior error covariance of the nth control cycle. T Let represent the transpose of the matrix, and Q represent the process noise covariance matrix.

[0043] S203: Obtain observations from real-time operating status data.

[0044] S204: Calculate the Kalman gain based on the prior error covariance, observation matrix, and measurement noise covariance.

[0045]

[0046] in, R represents the Kalman gain, and R represents the measurement noise covariance. This represents the inverse operation of a matrix.

[0047] S205: Based on the observations, the prior state estimate is corrected using Kalman gain to obtain the posterior state estimate for the current control cycle.

[0048]

[0049] in, This represents the posterior state estimate for the nth control cycle.

[0050] S206: Update the prior error covariance using Kalman gain to obtain the posterior error covariance, and use the posterior error covariance as the input for the next cycle.

[0051]

[0052] in, Let I represent the posterior error covariance of the nth control cycle, and let I represent the identity matrix.

[0053] S207: Output the predicted index from the posterior state estimate as the predicted load.

[0054] In this embodiment of the invention, Kalman filtering is used to predict the chip workload. In the presence of noise and uncertainty, a more accurate and stable load estimate can be obtained through a recursive prediction and correction mechanism, thereby improving prediction accuracy and real-time performance, reducing observation noise interference, avoiding control lag, and providing reliable data support for subsequent path selection and power consumption optimization.

[0055] S3: Based on the predicted load and real-time congestion in the real-time operating status data, generate multiple candidate paths in the chip NoC, and calculate the comprehensive path cost of each candidate path to form a cost list.

[0056] Real-time congestion refers to the data transmission pressure currently experienced by routers and links during the operation of a Network on Chip (NoC). It reflects the usage of network resources (link bandwidth, router buffers, and virtual channels, etc.) and the potential degree of queuing or congestion.

[0057] In one possible implementation, S3 specifically includes:

[0058] S301: Obtain chip task scheduling information, which includes core allocation instructions for processes and threads.

[0059] Specifically, for example, "process P1 is assigned to core C5" and "thread T2 is assigned to core C8".

[0060] It's important to note that determining which processes or threads run on which cores ensures that path generation is based on actual task requirements, not theoretical connections, thus avoiding redundant calculations on irrelevant cores. This allows for dynamic matching of task allocation and data transmission needs, improving the coordination efficiency of scheduling and routing.

[0061] S302: Based on chip task scheduling information, extract the source core position and target core position in the NoC topology of the source core used for data transmission and the target core used for data reception.

[0062] The source core is a processing core in the on-chip network that needs to send data. It is usually the one responsible for generating the computation results after task scheduling, and needs to pass the results or instructions to other cores.

[0063] The target core is the processing core in the on-chip network that receives data transmitted from the source core. It is the computing collaboration node designated by the task scheduler and needs to use the data transmitted from the source core to continue processing or execute related tasks.

[0064] In this context, NoC topology refers to the interconnection method between various processing elements (PEs), routers, and links in a network-on-a-chip (NOC). It determines the path, latency, and power consumption characteristics of data transmission within the chip.

[0065] It should be noted that the NoC topology is specifically a 2D mesh NoC topology.

[0066] S303: Based on the NoC topology, source core location, target core location, and real-time congestion level, generate multiple candidate paths from the source core to the target core.

[0067] Specifically, movement is limited to the horizontal (X-axis) or vertical (Y-axis) direction (e.g., the path from source (0,0) to target (3,3): right → right → up → up). Diagonal paths allow diagonal movement (e.g., the path from source (0,0) to target (3,3): top right → top right → top right), reducing the number of hops. Congestion avoidance paths: Based on real-time congestion data, bypass currently highly congested links or routers (e.g., avoid paths with link occupancy > 70%). When all links are congested, the top few links with lower congestion are selected as candidate paths.

[0068] In this embodiment of the invention, the provided alternative paths not only consider the shortest path but also the flexibility to reduce latency and avoid hotspot links. The optimal path can be dynamically selected under different traffic scenarios, improving system throughput and reliability.

[0069] S304: Calculate the latency cost of each candidate path based on real-time operational status data:

[0070]

[0071] in, This represents the delay cost, and k represents the number of hops in the candidate path. This represents the base delay of the i-th link in the candidate paths. , All of these represent adjustment coefficients for maintaining dimensional consistency. This represents the real-time occupancy rate of the i-th link among the candidate paths. This represents the proportion of the router queue length for the i-th link in the candidate path.

[0072] It should be noted that when calculating latency costs, we should avoid relying solely on "hop count" as a latency metric, and instead combine link occupancy and router queue length to more accurately reflect path latency.

[0073] S305: Calculate the power cost of each candidate path based on real-time operating status data and predicted load.

[0074]

[0075] in, Indicates power cost, This represents the base power of the i-th link in the candidate paths. This represents the prediction load factor, where m represents the number of virtual channels in the candidate path. This represents the base power consumption of the j-th virtual channel. This represents the trigger power consumption when the j-th virtual channel in the candidate path is activated. This indicates the activation state of the j-th virtual channel in the candidate path. This indicates that the channel is active. This indicates that the channel is not active, and n represents the number of routers in the candidate path. Indicates the first candidate path The static power consumption of a router Indicates the first candidate path Dynamic power consumption of a router Indicates the first candidate path The status of each router Indicates an idle state. This indicates a busy state.

[0076] Optionally, predict the load factor The predicted load output by S2 is divided by the historical maximum load.

[0077] It should be noted that evaluating the energy consumption of a path involves comprehensively considering link power consumption, load level, VC activation, and router status, which can dynamically reflect path energy consumption. This reduces overall power consumption while avoiding performance degradation caused by excessive resource shutdown, achieving a balance between energy efficiency and performance.

[0078] S306: Calculate the performance loss cost of each candidate path based on the latency cost and the predicted load:

[0079]

[0080] in, This indicates the performance loss cost. This represents the minimum delay cost among the candidate paths.

[0081] In this embodiment of the invention, by comparing with the path of least delay, the performance degradation is quantified and amplified in conjunction with the load, which effectively prevents the excessive pursuit of low power consumption from causing system performance degradation. This ensures that optimization strikes a balance between power consumption and performance.

[0082] S307: The combined path cost for each candidate path is obtained by weighted summation of delay cost, power cost, and performance loss cost.

[0083]

[0084] in, Indicates the total cost of the path. Indicates the delay cost weight. Indicates the delay reference base, Indicates the power cost weight. Indicates the power reference. Indicates the weight of performance loss cost. This represents the maximum allowable performance loss threshold. This indicates taking the maximum value.

[0085] Optionally, the delay reference base is set based on the theoretical maximum value and the worst-case path delay. The power reference base is set based on the historical maximum observed power consumption.

[0086] S308: Sort and combine the comprehensive path costs of each candidate path in ascending order to obtain a cost list.

[0087] Specifically, the cost list is a ranking result obtained after comprehensively evaluating multiple candidate paths from the source core to the target core. The "cost" of each path is calculated by weighting multiple indicators (latency, power consumption, performance loss, etc.), and finally, these paths are sorted in ascending order of cost to form a list. The lower the score, the better the path.

[0088] In this embodiment of the invention, the above steps enable the generation of multiple candidate paths based on clearly defined task requirements, combined with the topology and real-time congestion status. The latency, power consumption, and performance loss costs are then calculated for each path, resulting in a comprehensively ranked cost list. This improves the accuracy and flexibility of path selection and achieves a dynamic balance between power consumption and performance, providing a reliable basis for subsequent intelligent control decisions.

[0089] S4: Based on real-time operating status data, predicted load, and cost list, outputs joint control commands through a deep neural network model.

[0090] Deep neural network models are a type of artificial neural network composed of multiple layers of neurons. Through nonlinear mapping between the input layer, multiple hidden layers, and the output layer, they can automatically extract features from complex data and make predictions or decisions.

[0091] Optionally, the joint control instructions are multi-dimensional control commands output by the optimization model that act simultaneously on the core layer and the NoC layer. These instructions include voltage and frequency regulation, path selection, virtual channel management, and router state adjustment. The advantage is that they enable collaborative optimization at both the computation and communication levels, thereby balancing performance and power consumption and improving overall chip operating efficiency.

[0092] In one possible implementation, S4 specifically includes:

[0093] S401: Integrate the core layer data, NoC layer data, predicted load, and cost list from the real-time running status data to obtain the input feature vector.

[0094] Specifically, the chip's current operating status, future load trends, and path optimization information are unified into a feature space, thereby ensuring that the deep neural network model considers all aspects when making decisions. It does not rely on a single data dimension, but performs global optimization based on multi-dimensional information, making the output control commands more accurate and reliable.

[0095] S402: Normalize the input feature vector.

[0096] S403: Input the normalized input feature vector into the deep neural network model, and obtain the output layer result through forward propagation.

[0097] Specifically, the output layer results can be (the dimension of the joint control instruction corresponding to the output layer node, such as "core 1 V / F pair, core 2 V / F pair, NoC path selection, number of VC activations").

[0098] In this embodiment of the invention, the ability of deep neural networks to model complex nonlinear relationships is utilized to automatically extract features from multidimensional inputs and complete efficient reasoning, thereby realizing the intelligent generation of joint control commands and avoiding the limitations of traditional heuristic methods, thus achieving a better balance between performance and power consumption.

[0099] S404: Performs multi-level parsing on the output layer results to obtain joint control instructions that the chip can execute.

[0100] In one possible implementation, S404 specifically includes:

[0101] S4041: Executes core layer control level instruction parsing, converting the node values ​​of the calculated core voltage-frequency pair in the output layer results into actual voltage and frequency.

[0102] S4042: Execute NoC level control instruction parsing. Based on the probability values ​​of the corresponding paths in the output layer results, select the path with the highest probability value as the optimal path for data transmission. Calculate the number of virtual channels to be activated based on the node values ​​of the corresponding virtual channels in the output layer results.

[0103] For example, (such as "diagonal path probability 0.8 → select diagonal path"). If the output layer node value is 0.4 and the total number of VCs for this port is 5, then the number of VCs to be activated is 0.4 × 5 = 2 (that is, activate 2 virtual channels and close the remaining 3 idle channels).

[0104] S4043: Integrates the parsed core-level control instructions with the parsed NoC-level control instructions and converts them into joint control instructions that can be executed by the chip.

[0105] In this embodiment of the invention, by parsing the output of the deep neural network, the voltage and frequency adjustment instructions at the core level and the path selection and virtual channel management control instructions at the NoC level are transformed into specific executable joint control instructions. The advantage of doing so is that it can achieve collaborative optimization between the computing layer and the communication layer, which not only ensures the dynamic balance of performance and energy consumption of each core, but also flexibly selects the optimal transmission path and reasonably configures virtual channel resources according to the real-time congestion situation, thereby improving the chip's energy efficiency ratio and operating efficiency on a global scale.

[0106] S5: Perform performance constraint verification on the joint control instructions to determine whether the corresponding chip performance loss is within a preset threshold; if so, the joint control instruction verification is deemed successful, and proceed to S6. Otherwise, the joint control instruction verification is deemed unsuccessful, and return to S4.

[0107] Among them, performance constraint verification refers to verifying the generated joint control instructions during the chip power consumption optimization process to ensure that the chip's performance loss after executing these instructions does not exceed a preset threshold.

[0108] It should be noted that those skilled in the art can set the size of the preset threshold according to actual needs, and this invention does not limit it.

[0109] In one possible implementation, S5 specifically includes:

[0110] S501: Calculate the chip's performance loss rate when using joint control instructions:

[0111]

[0112] in, Q represents the performance loss rate, N represents the number of computing cores, and Q represents the performance loss rate. t This indicates the proportion of instructions in the t-th computing core within the current window. This indicates the chip's highest operating frequency. This represents the actual operating frequency set by the t-th computing core after executing the joint control instruction.

[0113] S502: Determine if the performance loss rate is within the preset threshold. If yes, determine that the joint control command verification has passed and proceed to S6. Otherwise, determine that the joint control command verification has failed and return to S4.

[0114] Optionally, the preset threshold is 10%.

[0115] It should be noted that those skilled in the art can set the size of the preset threshold according to actual needs, and this invention does not limit it.

[0116] In this embodiment of the invention, by calculating the performance loss rate and determining a threshold before executing joint control instructions, it is possible to ensure that chip performance does not drop to an unacceptable level while optimizing power consumption, thereby effectively avoiding performance crashes caused by excessive frequency reduction or unreasonable path selection. This mechanism achieves a dynamic balance between power consumption and performance, ensuring that the optimization scheme is both energy-efficient and reliable. Furthermore, by returning to regenerate instructions when constraints are not met, a closed-loop verification is formed, improving the stability and robustness of system operation.

[0117] S6: Based on the verified joint control instructions, perform multi-level power consumption optimization on the chip.

[0118] In one possible implementation, the verified joint control instructions include core-level control instructions and NoC-level control instructions. S6 specifically includes:

[0119] S601: Based on the core-level control instructions, perform dynamic voltage and frequency scaling operations on each computing core to set the operating voltage and frequency of the computing core to the optimal values ​​specified by the instructions.

[0120] S602: Based on the optimal path selection instruction in the NoC level control instructions, the path with the lowest overall path cost is set as the data transmission path from the source core to the target core.

[0121] S603: According to the virtual channel activation quantity instruction in the NoC level control instruction, close idle virtual channels and reserve virtual channels that meet the current data transmission requirements.

[0122] It should be noted that closing idle virtual channels and retaining virtual channels that meet the current data transmission needs should be based on traffic density. More virtual channels should be closed during low traffic, and redundant virtual channels should be retained during high traffic.

[0123] S604: According to the router status adjustment instruction in the NoC level control instruction, idle routers are not activated and highly congested routers are bypassed, thus completing the power consumption optimization of the chip.

[0124] Specifically, the core layer's dynamic voltage and frequency scaling can reduce voltage and frequency within the load's tolerance range, thus significantly reducing dynamic power consumption. The NoC layer effectively reduces latency and communication energy consumption by selecting the transmission path with the lowest overall cost. Furthermore, combining dynamic adjustment of the number of virtual channels with adaptive traffic control avoids power waste caused by idle channels while maintaining sufficient bandwidth in high-traffic scenarios. Finally, router state-based control can shut down unused routers and avoid highly congested nodes, further reducing energy consumption and performance loss caused by congestion.

[0125] In this embodiment of the invention, this step ensures that the chip can achieve fine-grained power consumption management at both the computing and communication levels, enabling the system to achieve an optimal balance between power reduction and performance maintenance.

[0126] S7: Evaluate the multi-level power consumption optimization effect to determine whether the actual power consumption optimization effect of the chip has achieved the expected goal. If so, reinforce the optimization strategy through the feedback mechanism and return to S1. Otherwise, adjust the optimization strategy based on the reasons for not achieving the expected goal and return to S1.

[0127] Optionally, the expected target is a power consumption reduction rate of greater than 10%.

[0128] In one possible implementation, S7 specifically includes:

[0129] S701: Calculate the actual total power consumption generated by executing the verified joint control command:

[0130]

[0131] in, This represents the actual total power consumption. Indicates the number of computing cores. Indicates the first The equivalent capacitance of a core, V a Indicates the first The operating voltage of each core, This represents the operating frequency of the a-th core. Indicates the number of routers. This represents the power consumption of the virtual channel portion in the b-th router. This represents the power consumption of the switching matrix section in the b-th router.

[0132] S702: Calculate the baseline total power consumption before optimization.

[0133] S703: Calculate the power reduction rate based on the actual total power consumption and the baseline total power consumption:

[0134]

[0135] in, Indicates the rate of reduction in power consumption. Indicates the reference total power consumption. This represents the actual total power consumption.

[0136] S704: If the power consumption reduction rate is greater than the preset power consumption reduction rate and the performance loss rate is less than the preset threshold, determine whether the actual power consumption optimization effect of the chip has achieved the expected goal. If yes, proceed to S705. Otherwise, proceed to S706.

[0137] It should be noted that those skilled in the art can set the preset power consumption reduction rate according to actual needs, and this invention does not limit it.

[0138] In this embodiment of the invention, by quantitatively evaluating the actual power consumption and performance of the chip after optimization, and comparing the results with the baseline value before optimization and the preset threshold, it is possible to objectively determine whether the joint control instructions have truly achieved power consumption reduction and performance maintenance, thereby avoiding the situation of "formal optimization but poor actual effect". When the power consumption reduction rate is greater than the preset value and the performance loss is controlled within an acceptable range, the optimization goal can be confirmed to have been achieved, and the effective strategy can be solidified and saved to improve the reference value and convergence speed of future optimizations. When the goal is not met, targeted adjustments can be made according to the specific reasons, forming a closed-loop mechanism of optimization-evaluation-feedback, enabling the system to have continuous adaptive improvement capabilities, thereby achieving stable and reliable high-efficiency optimization results in long-term operation.

[0139] S705: Saves the valid parameters of the current joint control command to the policy library. It uses the input feature vector of the current scene and the valid joint control command as training data to fine-tune the weights of the deep neural network model. Then, it transmits the optimized signal to S1 through the feedback channel to continue monitoring the chip's operating status.

[0140] S706: Collect the reasons why the expected target was not achieved. If the reason is that the power consumption reduction rate is less than the preset power consumption reduction rate, prioritize ensuring that the performance loss rate is less than a preset threshold, and increase the core frequency reduction, adjust the NoC path selection strategy, and increase the number of virtual channels disabled. If the reason is that the performance loss rate is greater than the preset threshold, increase the computing core frequency, bypass the high-congestion path, and return to S1.

[0141] Specifically, if the expected goal is achieved, the effective joint control commands and corresponding input features are saved to the policy library and used to fine-tune the weights of the deep neural network. This not only accumulates optimization experience but also improves the model's prediction and decision-making capabilities in subsequent scenarios, making the optimization process increasingly efficient and accurate. If the goal is not achieved, targeted adjustments are made based on the cause of the problem. For example, if the power consumption reduction is insufficient, the frequency reduction may be further strengthened or more redundant channels may be shut down. If the performance loss is too great, the frequency may be appropriately increased and a low-latency path may be selected. Returning to S1 is to re-collect the latest operating status after optimization and incorporate the corrective measures into a new complete optimization loop, realizing a closed-loop feedback of monitoring-adjustment-verification, allowing the chip power consumption optimization process to continuously iterate and adapt. This differentiated correction mechanism can avoid blind adjustments and ensure that the optimization process is both energy-saving and does not sacrifice performance.

[0142] Specifically, when a control command passes the verification and achieves the desired effect, the input features at that time and the valid command are saved together and fed into the neural network as a new training sample. The model weights are then updated in small increments so that the model can remember "how to do this in this scenario".

[0143] In this embodiment of the invention, a closed-loop feedback mechanism of differential correction (learning on success and correcting on failure) enables the chip optimization system to have continuous adaptive improvement capabilities and long-term stable high energy efficiency.

[0144] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0145] In this embodiment of the invention, by collecting the real-time operating status of the chip and using Kalman filtering for load prediction, combined with joint decision-making and performance constraint verification of deep neural networks, a forward-looking response to load fluctuations is achieved, avoiding performance fluctuations caused by the lack of prediction in existing technologies. At the same time, by comprehensively calculating the NoC candidate paths and their costs, combined with unified control of multi-level power consumption and feedback iteration mechanism, the overall integrity and coordination of power consumption optimization are improved, cross-level collaborative capabilities are enhanced, and the dynamic scheduling of congestion factors is taken into account, thereby reducing power consumption while ensuring the stability and balance of overall performance.

[0146] The chip power consumption optimization method based on a multi-level optimization strategy provided in this application can be executed by a chip power consumption optimization device based on a multi-level optimization strategy. This application uses an example of a chip power consumption optimization device executing the chip power consumption optimization method based on a multi-level optimization strategy to illustrate the chip power consumption optimization device based on a multi-level optimization strategy provided in this application.

[0147] Reference manual attached Figure 2The diagram shows a schematic of a chip power consumption optimization system based on a multi-level optimization strategy provided by an embodiment of the present invention.

[0148] This invention provides a chip power consumption optimization system 20 based on a multi-level optimization strategy, including: a processor 201 and a memory 202;

[0149] The memory 202 stores programs or instructions that can run on the processor 201. When the program or instructions are executed by the processor 201, they implement the steps of the chip power consumption optimization method based on the multi-level optimization strategy described above and can achieve the same technical effect. To avoid repetition, the present invention will not elaborate further.

[0150] It should be understood that the processor 201 in this embodiment of the invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0151] It should also be understood that the memory 202 in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DR RAM).

[0152] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0153] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0154] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0155] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0156] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0157] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0158] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0159] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0160] This invention provides a readable storage medium comprising: storing a program or instructions on the readable storage medium, wherein when the program or instructions are executed by a processor, the program or instructions implement the steps of the chip power consumption optimization method based on the multi-level optimization strategy described above, and can achieve the same technical effect. To avoid repetition, this invention will not elaborate further.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A chip power consumption optimization method based on a multi-level optimization strategy, characterized in that, include: S1: Collects real-time operating status data of the chip; S2: Based on the real-time operating status data, the workload of the chip is predicted by Kalman filtering to obtain the predicted load; S3: Based on the predicted load and the real-time congestion in the real-time operating status data, generate multiple candidate paths in the chip NoC, and calculate the comprehensive path cost of each candidate path to form a cost list; S4: Based on the real-time operating status data, the predicted load, and the cost list, output joint control commands through a deep neural network model; S5: Perform performance constraint verification on the joint control instruction to determine whether the corresponding chip performance loss is within a preset threshold; if yes, determine that the joint control instruction verification has passed and proceed to S6; otherwise, determine that the joint control instruction verification has failed and return to S4. S6: Based on the verified joint control instructions, perform multi-level power consumption optimization on the chip; S7: Evaluate the multi-level power consumption optimization effect and determine whether the actual power consumption optimization effect of the chip has reached the expected target; If so, reinforce the optimization strategy through the feedback mechanism and return to S1; Otherwise, based on the reason for not achieving the expected goal, adjust the optimization strategy and return to S1.

2. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 1, characterized in that, The real-time operating status data specifically includes: core layer data and NoC layer data; The core layer data includes the number of historical completed instructions, the number of cycle instructions, the actual operating frequency, and the actual operating voltage. The NoC layer data includes real-time link occupancy, real-time virtual channel utilization, real-time router congestion, and path hop count.

3. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 1, characterized in that, S2 specifically includes: S201: Establish a state model and an observation model for the chip workload, wherein the observation model includes an observation matrix and a measurement noise covariance; S202: Using the posterior state estimate and error covariance of the control cycle as initial inputs, calculate the prior state estimate and prior error covariance based on the state model and the control instructions issued to the chip in the previous control cycle. S203: Obtain the observations from the real-time operating status data; S204: Calculate the Kalman gain based on the prior error covariance, the observation matrix, and the measurement noise covariance; S205: Based on the observations, the prior state estimate is corrected using the Kalman gain to obtain the posterior state estimate for the current control cycle; S206: Update the prior error covariance using the Kalman gain to obtain the posterior error covariance, and use the posterior error covariance as the input for the next control cycle; S207: Output the prediction index in the posterior state estimation as the prediction load.

4. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 1, characterized in that, S3 specifically includes: S301: Obtain chip task scheduling information, wherein the chip task scheduling information includes core allocation instructions for processes and threads; S302: Based on the chip task scheduling information, extract the source core position and target core position of the source core used for data transmission and the target core used for data reception in the NoC topology; S303: Based on the NoC topology, the source core location, the target core location, and the real-time congestion level, generate multiple candidate paths from the source core to the target core; S304: Calculate the delay cost of each candidate path based on the real-time running status data; S305: Calculate the power cost of each candidate path based on the real-time operating status data and the predicted load; S306: Calculate the performance loss cost of each of the candidate paths based on the respective delay costs and the predicted load; S307: The delay cost, the power cost, and the performance loss cost are weighted and summed to obtain the comprehensive path cost of each candidate path; S308: Sort and combine the comprehensive path costs of each candidate path in ascending order to obtain the cost list.

5. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 1, characterized in that, S4 specifically includes: S401: Integrate the core layer data, NoC layer data, the predicted load, and the cost list in the real-time running status data to obtain the input feature vector; S402: Normalize the input feature vector; S403: Input the normalized input feature vector into the deep neural network model, and obtain the output layer result through forward propagation calculation; S404: Perform multi-level parsing on the output layer results to obtain the joint control instructions that the chip can execute.

6. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 5, characterized in that, Specifically, S404 includes: S4041: Execute core-level control instruction parsing to convert the node values ​​of the calculated core voltage-frequency pair in the output layer results into actual voltage and frequency; S4042: Execute NoC level control instruction parsing, select the path with the highest probability value as the optimal path for data transmission based on the probability value of the corresponding path in the output layer result; calculate the number of virtual channels to be activated based on the node value of the corresponding virtual channel in the output layer result; S4043: Integrate the parsed core-level control instructions with the parsed NoC-level control instructions, and convert them into joint control instructions executable by the chip.

7. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 1, characterized in that, S5 specifically includes: S501: Calculate the performance loss rate of the chip when using the joint control instructions; S502: Determine whether the performance loss rate is within the preset threshold; if yes, determine that the joint control command verification has passed and proceed to S6; otherwise, determine that the joint control command verification has failed and return to S4.

8. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 1, characterized in that, The verified joint control commands include core-level control commands and NoC-level control commands; S6 specifically includes: S601: According to the core-level control instruction, perform dynamic voltage-frequency scaling operation on each computing core to set the operating voltage and frequency of the computing core to the optimal value specified by the instruction. S602: According to the optimal path selection instruction in the NoC level control instruction, the path with the lowest overall cost is set as the data transmission path from the source core to the target core; S603: According to the virtual channel activation quantity instruction in the NoC level control instruction, close the idle virtual channels and reserve the virtual channels that meet the current data transmission requirements; S604: According to the router status adjustment instruction in the NoC level control instruction, idle routers are not activated, and highly congested routers are bypassed, thereby completing the power consumption optimization of the chip.

9. The chip power consumption optimization method based on a multi-level optimization strategy according to claim 7, characterized in that, Specifically, S7 includes: S701: Calculates the actual total power consumption generated by executing the verified joint control command; S702: Calculate the baseline total power consumption before optimization; S703: Calculate the power consumption reduction rate based on the actual total power consumption and the reference total power consumption; S704: If the power consumption reduction rate is greater than the preset power consumption reduction rate and the performance loss rate is less than the preset threshold, determine whether the actual power consumption optimization effect of the chip has reached the expected target; if yes, proceed to S705; otherwise, proceed to S706. S705: Save the effective parameters of the current joint control command to the strategy library; use the current input feature vector and the effective joint control command as training data to fine-tune the weights of the deep neural network model; and transmit the optimization target signal to S1 through the feedback channel to continue monitoring the chip's operating status. S706: Collect the reasons why the expected target was not achieved. If the reason is that the power consumption reduction rate is less than the preset power consumption reduction rate, prioritize ensuring that the performance loss rate is less than the preset threshold, increase the core frequency reduction, adjust the NoC path selection strategy, and increase the number of virtual channels to be shut down. If the reason is that the performance loss rate is greater than the preset threshold, increase the computing core frequency and bypass the high congestion path, and return to S1.

10. A chip power consumption optimization system based on a multi-level optimization strategy, characterized in that, include: Processor and memory; The memory stores programs or instructions that can run on the processor, and when the program or instructions are executed by the processor, they implement the steps of the chip power consumption optimization method based on a multi-level optimization strategy as described in any one of claims 1 to 9.

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