Data processing method and device based on CSI protocol and ATE test system

Abstract

The application is suitable for the technical field of data interface of chip testing, and provides a data processing method and device based on CSI protocol and an ATE testing system. The method comprises the following steps: receiving interface data from at least one physical channel of a physical layer; packetizing the interface data of each physical channel based on a CSI packet structure to obtain a packet header and a payload of each physical channel; merging the packet headers among the physical channels to obtain a data type identifier of a recombined packet header; performing cross-channel merging on the payloads of each channel by identifying the data type identifier, generating a pixel data stream, and generating metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream; and outputting the pixel data stream and the metadata for testing by a semiconductor testing device. The above scheme can realize stable acquisition and unified output across devices, significantly reduce the adaptation cost, and improve the positioning efficiency and yield.

Description

Technical Field

[0001] This application belongs to the field of data interface technology for chip testing, and in particular relates to a data processing method, apparatus and ATE test system based on the CSI protocol. Background Technology

[0002] Chip manufacturing typically involves wafer-level / chip-level testing (CP), package / finished product testing (FP), and system-level testing (SLT). Test data for different chips under test vary in firmware version, protocol configuration, and physical layer implementation, such as the number of channels, bit width settings, control message usage habits, and low-power management strategies. This significantly increases the adaptation and maintenance costs for the testing end.

[0003] Existing testing equipment often relies on fixed-function receiving and protocol processing modules. Faced with different vendors, firmware versions, and diverse protocol usage habits, parameters frequently need to be preset or repeatedly adjusted. Inconsistent timing characteristics in low-power / gap links can easily lead to acquisition anomalies and compatibility issues. Furthermore, the granularity of error detection and diagnostic information is insufficient, backtracking is difficult, and upper-layer interface forms are inconsistent, resulting in high adaptation and maintenance costs, low location efficiency, and poor script reusability. Summary of the Invention

[0004] In view of this, embodiments of this application provide a data processing method, apparatus and ATE test system based on the CSI protocol, which can achieve stable acquisition and unified output across devices, significantly reduce adaptation costs and improve positioning efficiency and yield.

[0005] A first aspect of this application provides a data processing method based on the CSI protocol, the method comprising:

[0006] Receive interface data from at least one physical channel of the physical layer;

[0007] Based on the CSI packet structure, the interface data of each physical channel is divided into packets to obtain the packet header and payload of each physical channel;

[0008] Merge the packet headers of the various physical channels to obtain the data type identifier of the recombined packet header;

[0009] By identifying the data type identifier, cross-channel merging is performed on the payload of each physical channel to generate a pixel data stream, and metadata synchronized with the pixel data stream is generated by restoring the timing boundary of the pixel data stream.

[0010] The pixel data stream and the metadata are output for testing by semiconductor testing equipment.

[0011] In this embodiment, a closed-loop process is implemented by "receiving interface data from at least one physical channel of the physical layer; packetizing the interface data of each physical channel based on the CSI packet structure to obtain the packet header and payload of each physical channel; merging the packet headers between physical channels to obtain the data type identifier of the recombined packet header; performing cross-channel merging on the payload of each channel by identifying the data type identifier to generate a pixel data stream, and generating metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream; and outputting the pixel data stream and the metadata for testing by semiconductor testing equipment." This process, at the protocol level, first... Packetization by channel and merging of packet headers across channels ensures data type identification is based on a standard packet structure, thereby mitigating the impact of differences in devices and firmware on the receiver and improving cross-device compatibility and adaptability. At the data level, the payload of each channel is merged across channels based on data type, ensuring consistency and continuity of multi-channel data reassembly and improving acquisition stability. At the interface level, by restoring timing boundaries and outputting metadata synchronously with the data stream, a unified interface form of "data stream plus metadata" is provided to the upper layer, simplifying alignment and judgment, enhancing anomaly location and backtracking capabilities, significantly reducing configuration and maintenance costs, and improving testing efficiency and yield.

[0012] In one possible implementation, the step of packetizing the interface data of each physical channel based on the CSI packet structure to obtain the packet header and payload of each physical channel includes:

[0013] Based on the high-speed reception validity status of each physical channel, initiate packet subpacketization operation for the corresponding physical channel;

[0014] The packet splitting operation includes: during the period when the high-speed reception valid state is a first target value, dividing the interface data into packet headers and payloads corresponding to the physical channels according to the synchronization identifier in the interface data, and writing them into the channel buffer; when the high-speed reception valid state changes from the first target value to a second target value, closing the current packet splitting operation and fixing the packet splitting boundary, and obtaining the packet headers and payloads corresponding to the physical channels from the channel buffer.

[0015] In one possible implementation, merging the packet headers between the physical channels to obtain the data type identifier of the recombined packet header includes:

[0016] Cyclic redundancy check is performed on the packet headers of each physical channel;

[0017] The reconstructed packet header is obtained by reassembling the verified packet header according to the channel position order;

[0018] The data type identifier is obtained by parsing the type field of the recombinant header.

[0019] In one possible implementation, the step of performing cross-channel merging on the payload of each physical channel by identifying the data type identifier to generate a pixel data stream, and generating metadata synchronized with the pixel data stream by restoring the timing boundaries of the pixel data stream, includes:

[0020] When the data type is identified as a long packet type, the number of effective payload bytes is obtained;

[0021] Based on the number of payload bytes, perform cross-channel merging of the payload of each physical channel to generate a pixel data stream;

[0022] When the data type identifier is identified as a short packet type, a temporal boundary identifier used to indicate the boundary of the image data is obtained;

[0023] The timing boundary of the pixel data stream is recovered based on the timing boundary identifier and the number of payload bytes to generate metadata synchronized with the pixel data stream.

[0024] In another possible implementation, the method further includes:

[0025] Perform cyclic redundancy check on the pixel data stream;

[0026] When the cyclic redundancy check result of the pixel data stream is normal, the timing boundary of the pixel data stream is restored based on the timing boundary identifier and the number of payload bytes to generate metadata synchronized with the pixel data stream.

[0027] In one possible implementation, the method further includes:

[0028] The state machine schedules the packet splitting, packet header merging, cross-channel merging of payload, and timing recovery. The control states of the control state machine include at least a low-power state, a transmission start state, a packet header processing state, a data processing state, a tailing processing state, and a transmission end state.

[0029] In one possible implementation, the operation flow of the control state machine includes:

[0030] In low-power mode, listen for the stop indication of the interface, and enter the transmission start state when the stop indication of any physical channel is negative;

[0031] In the transmission start state, when the channel buffers of each physical channel have received packet headers, the packet header processing state is entered.

[0032] In the packet header processing state, the packet header is read from the channel buffer and cyclic redundancy check is performed. The packet header is reassembled between the physical channels and the data type identifier is parsed to obtain the data type identifier. When the data type identifier is a long packet type, the data processing state is entered. When the data type identifier is a short packet type, the closing processing state is entered.

[0033] In the data processing state, the effective load is read from each physical channel and cross-channel merging is performed to generate a pixel data stream. Cyclic redundancy check is performed on the pixel data stream. When the length of the merged data reaches the number of bytes of the effective load, a data completion indication is generated and the process enters the finishing processing state.

[0034] In the closing processing state, the remaining data that does not require protocol layer processing is retrieved and discarded, and the type of the next data packet is determined. If it is determined to be a packet header, the packet header processing state is returned; if it is determined to be a packet tail, the transmission end state is entered. The remaining data includes placeholder bytes.

[0035] When the transmission is complete, it waits for the interface to indicate a stop and then returns to a low-power state.

[0036] A second aspect of this application provides a data processing apparatus based on the CSI protocol, configured in a semiconductor testing device, the apparatus comprising:

[0037] A receiving module is used to receive interface data from at least one physical channel of the physical layer;

[0038] The packet sub-module is used to sub-packetize the interface data of each physical channel based on the CSI packet structure, and obtain the packet header and payload of each physical channel.

[0039] The packet header merging module is used to merge the packet headers between the various physical channels to obtain the data type identifier of the recombined packet header;

[0040] The load merging module is used to perform cross-channel merging on the payload of each physical channel by identifying the data type identifier, generate a pixel data stream, and generate metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream.

[0041] The data output module is used to output the pixel data stream and the metadata for testing by semiconductor testing equipment.

[0042] A third aspect of this application provides an ATE testing system, the ATE testing system comprising: a physical layer, a data processing device based on the CSI protocol, and a processing unit;

[0043] The physical layer is used to receive high-speed serial signals from the camera under test, perform signal recovery and channel alignment, and output interface data of at least one physical channel to the data processing device based on the CSI protocol.

[0044] The data processing apparatus based on the CSI protocol is used to execute the data processing method based on the CSI protocol as described in the first aspect;

[0045] The processing unit, configured in a semiconductor testing device, is used to receive pixel data streams and metadata, perform pixel-level processing, display, and / or storage on the pixel data streams, and perform alignment and testing based on the metadata.

[0046] In one possible implementation, the physical layer is a receiving module of a three-phase coded physical layer;

[0047] The physical layer is also used to output a status indication of at least one physical channel to the data processing device of the CSI protocol, the status indication including at least a high-speed reception valid status and a stop indication;

[0048] The processing unit is further configured to receive the pixel data stream in a row-organized manner and perform frame and row alignment based on the temporal boundary identifier in the metadata.

[0049] A fourth aspect of this application provides a semiconductor testing apparatus, including a data processing device based on the CSI protocol, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described in the first aspect above.

[0050] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0051] A sixth aspect of this application provides a computer program product that, when run on a semiconductor testing device, causes the semiconductor testing device to perform the steps of the method described in the first aspect.

[0052] For the beneficial effects of the second to sixth aspects mentioned above, please refer to the first aspect mentioned above, which will not be repeated here. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the structure of an ATE testing system provided in an embodiment of this application;

[0055] Figure 2 This is a schematic diagram of another ATE testing system provided in an embodiment of this application;

[0056] Figure 3 This is a flowchart illustrating a data processing method based on the CSI protocol provided in an embodiment of this application;

[0057] Figure 4 This is a diagram illustrating the subcontracting rules of the subcontractor;

[0058] Figure 5 This is a flowchart illustrating the preprocessor module.

[0059] Figure 6 This is a flowchart of the post-processor module;

[0060] Figure 7 This is a schematic diagram of the operation flow of the control state machine;

[0061] Figure 8 This is a flowchart of the CSI data splitting and merging process under multi-channel conditions;

[0062] Figure 9 This is a diagram illustrating the subcontracting of short packages;

[0063] Figure 10 This is a diagram illustrating the subcontracting of a long package;

[0064] Figure 11 This is a diagram illustrating packet subpackaging under link energy-saving mode;

[0065] Figure 12 This is a schematic diagram of the structure of a data processing device based on the CSI protocol provided in an embodiment of this application;

[0066] Figure 13 This is a schematic diagram of the structure of a semiconductor testing device provided in an embodiment of this application. Detailed Implementation

[0067] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0068] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0069] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0070] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0071] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0072] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0073] Chip manufacturing typically involves wafer-level / chip-level testing (CP), package / finished product testing (FP), and system-level testing (SLT). Test data for different chips under test vary in firmware version, protocol configuration, and physical layer implementation, such as the number of channels, bit width settings, control message usage habits, and low-power management strategies. This significantly increases the adaptation and maintenance costs for the testing end.

[0074] Most existing test equipment relies on dedicated physical layer receiver chips or fixed function modules to receive high-speed signals and process basic protocols. When faced with differences in protocol details across different devices, this approach often requires pre-setting specific operating parameters or scripts. When the firmware version of the device under test (DUT) is updated, protocol characteristics change, or production lines switch to different vendors, incompatibility issues, complex reconfiguration, and difficulties in troubleshooting can easily arise in the test link. For example, the timing behavior of low-power related link management strategies varies across different devices. If the test equipment is not robust enough in its identification and processing of these strategies, it may lead to abnormal data gap processing, thereby affecting the continuity and stability of chip data acquisition.

[0075] Furthermore, traditional solutions offer limited information for error detection and diagnosis, lacking a unified presentation and backtracking capability for fine-grained information such as anomaly locations, boundary consistency, and link status changes. When test anomalies occur, such as screen flickering, black screens, or intermittent frame drops, repeated troubleshooting at the physical layer, protocol layer, and host computer software is often required, impacting production line efficiency and yield closed-loop speed. For upper-layer testing programs, the data interface formats vary between different projects, lacking a unified and stable interface, increasing the cost of algorithm verification and automation script modification.

[0076] In summary, existing technologies generally suffer from insufficient adaptability, high configuration and maintenance costs, weak error localization and diagnosis capabilities, and inconsistent upper-layer interfaces in testing environments with multiple vendors, firmware versions, and protocol characteristics. There is an urgent need for an image acquisition and data processing solution that is compatible with different device protocol characteristics, possesses flexible configuration and comprehensive testing and diagnostic capabilities, and can stably interface with the testing process.

[0077] To address the problems in the prior art, embodiments of this application provide a data processing method, apparatus, and ATE testing system based on the CSI protocol. The method involves: receiving interface data from at least one physical channel at the physical layer; packetizing the interface data of each physical channel based on the CSI packet structure to obtain the packet header and payload of each physical channel; merging the packet headers between physical channels to obtain a data type identifier for the recombined packet header; performing cross-channel merging on the payload of each channel by identifying the data type identifier to generate a pixel data stream; and generating metadata synchronized with the pixel data stream by restoring the timing boundaries of the pixel data stream; and outputting the pixel data stream and metadata for testing equipment. The closed-loop process of "conducting tests" first divides packets by channel at the protocol level and merges packet headers between channels, establishing data type identification based on the standard packet structure. This reduces the impact of differences in different devices and firmware on the receiver, improving cross-device compatibility and adaptability. At the data level, the payload of each channel is merged across channels according to data type, ensuring the consistency and continuity of multi-channel data reconstruction and improving acquisition stability. At the interface level, by restoring timing boundaries and outputting metadata synchronously with the data stream, a unified interface form of "data stream plus metadata" is provided to the upper layer, simplifying alignment and judgment, enhancing anomaly location and backtracking capabilities, significantly reducing configuration and maintenance costs, and improving testing efficiency and yield.

[0078] The data processing method, apparatus, ATE test system, semiconductor test equipment, storage medium, and computer program based on the CSI protocol provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0079] Figure 1 A schematic diagram of an ATE testing system according to an embodiment of this application is shown. The ATE testing system includes a physical layer, a data processing device based on the CSI protocol, and a processing unit. Their connection relationships are shown in the figure.

[0080] The physical layer is used to receive high-speed serial signals from the device under test (DUT), perform signal recovery and channel alignment, and output interface data and status indicators (including high-speed reception valid status and stop indication) of at least one physical channel to the data processing device. The DUT can be a camera sensor / module, or other DUTs with CSI output interfaces, such as a system-on-a-chip (SoC) with an integrated image signal processing unit (ISP) or a processor chip with a CSI peripheral controller; this application does not limit the specific implementation of the physical layer. The implementation form of the physical layer is not limited and can be a receiving module of a three-phase coded physical layer (C-PHY).

[0081] The data processing device based on the CSI protocol is used to process the interface data output from the physical layer at the protocol layer and provide the processing unit with unified data and information, namely pixel data streams and metadata.

[0082] This device can be specifically used for:

[0083] According to the CSI packet structure, during the period when the high-speed reception valid state changes from negative to positive, the interface data of each physical channel is divided into packet headers and payloads based on the synchronization flag and written into the channel buffer; when the high-speed reception valid state changes from positive to negative, the packet boundaries are fixed, and the packet headers and payloads of each channel are obtained.

[0084] Error detection (i.e., cyclic redundancy check) is performed on the headers of each channel, and the headers are reassembled according to the channel bit order. The data type identifier is obtained by parsing the type field of the reassembled header, and the timing boundary identifier used to indicate the data boundary is identified. When the chip under test is a camera sensor / module, the data boundary can refer to the image data boundary.

[0085] When the data type is identified as a long packet type, the number of payload bytes is obtained, and cross-channel merging is performed on the payload of each channel according to the number of bytes to generate a pixel data stream. Cyclic redundancy check can also be performed on the pixel data stream. Combined with the timing boundary identifier and / or the number of payload bytes, the frame and line boundaries of the pixel data stream are restored, and metadata synchronized with the pixel data stream is generated.

[0086] The pixel data stream, organized by line or frame, and its synchronized metadata are output to the processing unit.

[0087] The processing unit receives pixel data streams and metadata, performs pixel-level processing, displays, and / or stores the pixel data streams; and completes alignment and testing based on frame / line boundary information in the metadata. The specific processing algorithm and storage medium are not limited.

[0088] The working process of the system in the embodiments of this application is described in detail below:

[0089] First, the system is prepared based on parameters such as the number of channels and bit width of the data to be tested from the chip under test; the physical layer begins outputting interface data and status indicators. Second, the packet segmentation module of the data processing unit segments and buffers the data from each channel while maintaining high-speed reception. The packet header merging module reassembles the packet header and parses it to obtain the data type identifier; if it is a long packet type, it obtains the number of bytes of the payload; if it is a short packet type, it obtains the timing boundary identifier used to indicate the boundary. The payload merging module performs cross-channel merging of the payloads of each channel to generate a pixel data stream, performs cyclic redundancy check, and recovers the frame and line boundaries based on the timing boundary identifier and / or the number of bytes of the payload, forming metadata synchronized with the pixel data stream. The data output module outputs the pixel data stream and metadata to the processing unit; the processing unit completes display, storage, and test determination.

[0090] The above embodiments are used to illustrate the system configuration and typical data / control flow. The interface type, caching strategy and parallel mode do not constitute a limitation on this application.

[0091] For ease of description, this application divides the apparatus according to its functions corresponding to the method steps into: a receiving module, a packet sub-module, a packet header merging module, a load merging module, and a data output module. It should be understood that the above names are only used to indicate the functions they perform, and are a logical / virtual division, not limited to physically independent devices or boards. In specific implementations, the above functions can be implemented by the same processor / programmable logic through software, firmware, or hardware circuitry, or they can be implemented centrally or distributed by multiple devices; any module can be merged, split, or reused with another module's storage and control resources, and their connection order and internal coupling method do not constitute a limitation on the scope of protection of this application.

[0092] and Figure 2 The terms "packet splitter, preprocessor, postprocessor, and control state machine" used in the diagram represent different naming conventions: the packet splitting module can be implemented by the packet splitter; the packet header merging module corresponds to the packet header verification / merging unit in the preprocessor; the load merging module corresponds to the long packet merging / verification / timing recovery unit in the postprocessor; and the control state machine is used for the unified scheduling of the above functions. The two sets of names can correspond to each other, but do not constitute additional limitations.

[0093] In this application, the terms "module," "unit," and "component" are used interchangeably, and their specific carrier forms (independent chip, SoC internal logic, FPGA IP, firmware program, or a combination thereof) should all fall within the protection scope claimed in this application.

[0094] As one possible implementation scheme, Figure 2 A schematic diagram of another ATE testing system provided in this application embodiment is shown. The data processing device based on the CSI protocol in this ATE testing system includes: a packet splitter, a preprocessor, a postprocessor, and a controller. Their connection relationship is as follows: the physical layer outputs interface data and status indicators to the packet splitter; the packet splitter, preprocessor, and postprocessor are connected sequentially and scheduled by the control state machine; the postprocessor outputs pixel data streams and synchronized metadata to the processing unit.

[0095] In the embodiments of this application, the processing unit may refer to an image processor, which is used to process the received image data.

[0096] In this embodiment, the physical layer begins outputting interface data and status indicators; the control state machine listens for stop indicators in a low-power state, and enters the transmission start state when the conditions are met. During the transition from "no" to "yes" in the high-speed reception valid state, the packet segmenter segments the data of each channel according to the synchronization identifier, obtains and buffers the packet header and payload. The preprocessor reads the buffer, and the packet header is sent to the postprocessor after cyclic redundancy check; long packet data is sent to the postprocessor as the payload. The postprocessor merges and parses the packet header to obtain the data type identifier (long packet / short packet); if it is a long packet type, it obtains the payload byte count, performs cross-channel merging of the payload of each channel to generate a pixel data stream, and performs cyclic redundancy check; combined with the timing boundary identifier and / or the payload byte count, it restores the frame and line boundaries and generates metadata synchronized with the pixel data stream. The data is output to the processing unit; the control state machine switches between the end-of-processing state and the transmission end state according to the buffer and status indicators, and returns to the low-power state after completing a transmission segment, waiting for the next round of data.

[0097] It should be noted that the above-mentioned "packet sub-processor, preprocessor, postprocessor, and control state machine" are functional / logic units that can be implemented by the same chip or programmable logic in hardware, firmware, or software.

[0098] Compared to the previous embodiment, this embodiment introduces a control state machine to uniformly schedule packet splitting, header merging, cross-channel merging, and timing recovery, forming a deterministic process of "low power consumption, transmission start, header processing, data processing, tailing processing, and transmission end." It can combine stop indicators and placeholder / gap words to automatically identify link stages, reducing reliance on preset parameters and improving cross-device compatibility. It uses the number of effective payload bytes as the termination condition and cooperates with cyclic redundancy check to achieve anomaly self-recovery, reducing the probability of frame loss and jamming. The pixel data stream and metadata output under state-driven conditions have more stable timing, which is more conducive to upper-layer alignment and judgment. At the same time, key states and completion indicators are event-driven, enhancing diagnostic observability and traceability, and facilitating parameter expansion and portability such as channel number and bit width.

[0099] See Figure 3 This document illustrates a flowchart of a data processing method based on the CSI protocol provided in an embodiment of this application. This method can be applied to the CSI protocol-based data processing device shown in the above embodiment. Taking a camera sensor as an example, the method may include the following steps:

[0100] Step 301: Receive interface data from at least one physical channel of the physical layer.

[0101] The physical layer refers to the three-phase coded physical layer (C-PHY) receiver, which completes signal recovery and channel alignment on the link side and outputs parallel protocol interface data and status indications at the protocol boundary.

[0102] Among them, the physical channel refers to the parallel receiving channel of the physical layer (C-PHY is a three-phase channel with three wires as a group), which will be referred to as Lane0, Lane1, and Lane2 below.

[0103] Among them, interface data refers to the data bus word and its status indication output by the physical layer on the parallel interface, including but not limited to: high-speed receive active status (RxActiveHS): indicating that the current channel is in the high-speed receive window; stop indication (StopState): indicating that the channel is in the low-power / stop window; parallel data word (output according to the bit width set by the implementation, such as 16 bits or 32 bits).

[0104] It should be noted that this step only receives and caches the above data and status, and does not involve subsequent processing such as packet splitting and header parsing.

[0105] The specific execution process of step 301 is as follows: After the device is powered on, it first reads the physical layer configuration, sets the number of channels to 3 (three C-PHY channels) and the parallel bit width (e.g., 32 bits), and allocates a receive buffer for each physical channel. Then, the high-speed receive valid status and stop indication output by the physical layer are synchronously latched within the device's clock domain. When the high-speed receive valid status of any channel changes from negative to positive, the channel is marked as entering the receive segment, and buffer writing for that channel is initiated. During the entire period when the high-speed receive valid status is positive, data words and accompanying status are sampled cycle by cycle according to the parallel bit width, and information such as "channel number, data word, timestamp, and status bit" is written into the corresponding buffer. When the high-speed receive valid status changes from positive to negative, the current receive segment for that channel ends, and the boundary of the receive segment is fixed in the buffer. After completing the receive segment of one or more channels, the device submits the channel buffer data containing segment boundary information to subsequent packet processing as input.

[0106] For example, in a three-channel C-PHY scenario, the system sets the parallel bit width to 32 bits and synchronizes with the physical layer parallel clock. At a certain time t0, the high-speed reception valid status of Lane0, Lane1, and Lane2 simultaneously changes from negative to positive, and the three channels start receiving in parallel, continuously writing the sampled parallel data words and status into their respective buffers. Then, at time t1, the high-speed reception valid status of Lane2 changes from positive to negative, and Lane2's current reception segment is closed and its boundary is fixed. Then, at time t2, Lane0 and Lane1 successively end their respective reception segments. Thus, three channel buffers are formed, each with a clear start / end marker and time marker, which can be directly used as input for the next step (packet subdivision).

[0107] Step 302: Based on the CSI packet structure, the interface data of each physical channel is divided into packets to obtain the packet header and payload of each physical channel.

[0108] The header refers to the fixed-length header field defined by the CSI protocol (including data type identifier, length / short data and its check digits, etc.), which is used to describe the attributes of subsequent data segments.

[0109] The payload refers to the sequence of bytes carrying pixels, as indicated by the "Number of Bytes" field, when the packet type is a long packet.

[0110] After obtaining the channel buffers and receive segment boundaries of each physical channel output in step 301, the device performs a separation operation on each physical channel: within the same receive segment, according to the packet structure of the CSI protocol, one or more "header-payload" pairs are extracted from consecutive data in the buffer and written to the header buffer and payload buffer of that channel respectively; when the receive segment ends, the extracted header and payload boundaries within this segment are fixed and indexed. Through the above processing, each physical channel can obtain a header set and payload set corresponding to this segment, which serve as input for subsequent header merging and payload merging.

[0111] For example, in a three-channel configuration, step 301 outputs one receive segment each for Lane0, Lane1, and Lane2. After executing step 302:

[0112] This segment of Lane 0 is separated into a group of "header-payload";

[0113] This section of Lane 1 is divided into two groups of "header-payload";

[0114] This section of Lane 2 is separated into a group of "header-load".

[0115] All separation results are written to the header cache and payload cache of the corresponding channel, and the boundaries and indexes are fixed at the end of the segment for subsequent steps to perform inter-channel header merging and cross-channel payload merging.

[0116] In one possible implementation, the interface data of each physical channel is packetized based on the CSI packet structure to obtain the packet header and payload of each physical channel, including:

[0117] Based on the high-speed reception validity status of each physical channel, initiate packet sub-operation for the corresponding physical channel;

[0118] The packet splitting operation includes: during the period when the high-speed reception valid state is the first target value, dividing the interface data into the packet header and payload of the corresponding physical channel according to the synchronization identifier in the interface data, and writing them into the channel buffer; when the high-speed reception valid state changes from the first target value to the second target value, closing the current packet splitting operation and fixing the packet splitting boundary, and obtaining the packet header and payload of the corresponding physical channel from the channel buffer.

[0119] The high-speed reception valid state refers to the activity indication given by the physical layer on the parallel interface, which takes the value of a first target value or a second target value to indicate yes or no. It can be used to define a high-speed reception segment, wherein the first target value and the second target value can take the value of "1" or "0" or other values, which is not limited in this application.

[0120] In this embodiment of the application, after obtaining the receiving segment entry formed in step 301, the device initiates packet subpacketization by channel: when the high-speed reception validity status of a certain channel is "yes", the packet subpacketization process is entered; during this period, "synchronization identifier determination, extraction of packet header or payload according to the determination result, and writing to the corresponding buffer" are executed cyclically; when the high-speed reception validity status of the channel changes from "yes" to "no", an SOP control packet is output to prompt the control state machine to solidify the boundary, the current packet subpacketization is closed and the boundary is solidified, thus obtaining one or more sets of "packet header plus payload" in this receiving segment for the channel.

[0121] For example, see Figure 4 The diagram shows the sub-packaging rules of the sub-packetizer; as shown. Figure 4 As shown, the packet splitting process first determines whether high-speed reception is valid; that is, when the high-speed reception validity status of a certain channel is detected as "yes", the packet splitting loop for that channel is entered; then, the synchronization flag is determined.

[0122] If the determination is yes, then the subsequent fixed-length 48-bit data will be extracted as the packet header and written to the packet header cache;

[0123] If the determination is negative, the segment is treated as a long data segment, extracted continuously as a payload at 16 bits / words, and written to the payload cache.

[0124] The aforementioned process of "synchronous determination to extract packet headers or payloads" is continuously and repeatedly executed during the high-speed reception period. When the process detects the end of high-speed reception (the high-speed reception validity status changes to "No"), it transitions to the end process of that reception segment, that is, outputting a SOP control packet as a segment end marker and fixing the boundaries and indices of the "packet header plus payload" already formed within this reception segment. Afterward, the process returns to the starting point, waiting for the next high-speed reception validity status to be "Yes" before starting a new round of packet segmentation. For multi-channel scenarios, the above process is executed independently and in parallel on each channel, ultimately forming a packet header set and payload set corresponding to its reception segment for each physical channel, for subsequent packet header merging and parsing and cross-channel merging.

[0125] This implementation uses the high-speed reception valid state as the start and stop of packet segmentation, distinguishes and extracts the packet header and long data according to the criteria during the valid period, and performs convergence and boundary solidification at the end of the reception segment. It also uses the channel buffer to form pairs of "packet header-payload" and indexes. This enables the determination of the separation by channel in multi-channel scenarios, avoids confusion between packet header and payload and cross-packet adhesion, provides clear input for subsequent processing, and reduces the dependence on preset parameters.

[0126] In one possible implementation, after obtaining the packet headers of each physical channel, the packet header data is checked using CRC (Cyclic Redundancy Check), and then merged.

[0127] For example, see Figure 5 The flowchart of the preprocessor module shown shows that after processing by the preprocessor module, the packet headers and payloads of each physical channel can be output.

[0128] Specifically, the preprocessor module processes the "data packets / control packets" from upstream in the following order: First, it performs PPI interface packet splitting, dividing the C-PHY physical layer data into header data packets, long data packets, and EOP (End of Packet) control packets for process processing. These packets are used only for control, allowing the state machine to recognize the packet tail for process processing. Then, the data buffer module provides buffering. At the demultiplexer, data packets are retrieved from the data buffer according to the control state machine's instructions and distributed according to type: the header data is distributed to the internal data packet header verification and merging unit, and the long data is distributed to the subsequent processor module. The data packet header verification and merging unit performs CRC verification and merging on the header data and outputs the original bit information of the header. The preprocessor ultimately forms two outputs: header data and long data.

[0129] Step 303: Merge the packet headers between each physical channel to obtain the data type identifier of the recombined packet header.

[0130] Among them, header reassembly refers to reassembling header fragments belonging to the same data packet but scattered across multiple physical channels into a complete header according to a predetermined channel bit order and bit sequence.

[0131] Among them, the channel order refers to the fixed sequence used when reassembling physical channels (such as Lane0, Lane1, Lane2).

[0132] The data type identifier is obtained from the type field of the reassembled packet header and is used to indicate whether the data packet is a long packet or a short packet, as well as the specific data category.

[0133] In this embodiment, the merging of packet headers between physical channels is performed based on the packet header verification and merging unit described in the previous embodiment. First, according to the time and order relationship within the same receiving segment, packet header segments from different channels corresponding to the same data packet are grouped. Within each group, inter-channel packet header reassembly is performed according to the predetermined channel bit order and protocol bit order to obtain a reassembled packet header. Subsequently, the reassembled packet header is parsed, and information such as the data type identifier (DT) and (when it belongs to a long packet) payload byte count (WC) is read and registered to form a "packet header parsing record," which serves as a necessary input for subsequent long packet data merging and image timing recovery.

[0134] Specifically, in one possible implementation, the packet headers between physical channels are merged to obtain a data type identifier for the recombined packet header, including:

[0135] Perform cyclic redundancy check on the packet headers of each physical channel;

[0136] The verified packet header is reassembled according to the channel position order to obtain the reassembled packet header;

[0137] The data type identifier is obtained by parsing the type field of the recombinant header.

[0138] In this embodiment, the preprocessor retrieves packet header data from the channel buffers of each physical channel and sends it to the packet header verification and merging unit. It performs cyclic redundancy check (CRC) on the packet header of each channel and outputs the original bit information of the packet header. Subsequently, the postprocessor performs inter-lane packet header merging and parsing, reassembling the verified packet headers of each channel according to channel bit order into a reassembled packet header, and parsing the data type identifier from the type field in the reassembled packet header. For example, in a three-channel C-PHY configuration, the packet headers of Lane 0, Lane 1, and Lane 2 are concatenated according to Lane bit order after CRC to form the reassembled packet header of the data packet, and the data type identifier of the data packet is parsed from its type field.

[0139] Step 304: By identifying the data type identifier, perform cross-channel merging on the payload of each physical channel to generate a pixel data stream, and generate metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream.

[0140] In this embodiment of the application, the specific execution process of step 304 is as follows:

[0141] The post-processor processes the payload of each physical channel based on the data type identifier parsed in step 303: when the data type identifier indicates a long packet type, it performs long packet merging (merging data from multiple channels into a continuous byte stream according to bit order) between channels according to the byte count given in the reassembled packet header; when the data type identifier indicates a short packet type, it participates in timing recovery as timing boundary information, where frame timing is determined according to the "frame start, frame end" in the short packet type, and line timing is recovered according to the valid indication of the long packet data. Through the above merging and timing recovery, the post-processor outputs a pixel data stream organized by line or frame, and synchronously outputs metadata (including at least one or more of frame start, frame end, line start, and line end) to describe the boundaries for downstream processing units to align and test.

[0142] Specifically, in one possible implementation, cross-channel merging is performed on the payload of each channel by identifying data type identifiers to generate a pixel data stream, and metadata synchronized with the pixel data stream is generated by restoring the timing boundaries of the pixel data stream, including:

[0143] When the data type is identified as a long packet type, obtain the number of effective payload bytes;

[0144] Based on the number of bytes of payload, perform cross-channel merging of the payload of each physical channel to generate a pixel data stream;

[0145] When the identified data type is a short packet type, obtain the temporal boundary identifier used to indicate the boundary of the image data;

[0146] The temporal boundaries of the pixel data stream are recovered based on the temporal boundary identifier and the number of payload bytes to generate metadata synchronized with the pixel data stream.

[0147] The timing boundary identifier includes at least one of frame start, frame end, line start, and line end, and the metadata includes at least one or more of frame start, frame end, line start, and line end.

[0148] In another possible implementation, the method further includes:

[0149] Perform cyclic redundancy check on the pixel data stream;

[0150] When the cyclic redundancy check result of the pixel data stream is normal, the timing boundary of the pixel data stream is restored based on the timing boundary identifier and the number of payload bytes to generate metadata synchronized with the pixel data stream.

[0151] In this embodiment, after the post-processor completes the cross-channel merging of the payload of each physical channel, it first performs cyclic redundancy check on the merged pixel data stream. When the check result is normal, timing recovery is initiated: based on the timing boundary identifiers (frame start, frame end, line start, line end) obtained from the previous parsing and the number of payload bytes (when it belongs to a long packet), the frame and line start and end positions of the pixel data stream are determined, the boundary organized by line / frame is reconstructed, and metadata synchronized with the pixel data stream is generated under the same time base to mark the boundary. For example, in a three-channel C-PHY scenario, the payload length after merging a certain line is equal to the corresponding byte count. After the cyclic redundancy check passes, the line is terminated with the line start and line end identifiers, and the line boundary is written into the metadata, and then output together with the pixel data stream.

[0152] For example, see Figure 6 A flowchart of the post-processor module is shown; after processing by the post-processor module, pixel data streams and synchronous metadata can be output.

[0153] Specifically, the post-processor receives header data and long packet data from Lane 0 to Lane 2: First, in the "header merging and parsing" unit, the headers of each channel are reassembled and parsed between channels to obtain the data type identifier and (when it is a long packet) the number of payload bytes; when parsed as a long packet, the "long packet merging" unit splices the long packet data of each channel into a continuous data stream according to the predetermined channel bit order, and performs counting control based on the number of bytes, while sending the data stream to the "CRC check" for line-by-line integrity check; the checked data enters the "image frame timing recovery" unit, which restores the frame and line boundaries based on the short packet type (frame start, frame end, etc.) and long packet validity indication obtained from the header parsing, and outputs the image data; throughout the entire processing, the post-processor starts and stops and coordinates the rhythm according to the "control state machine state", and outputs the "processing completion indication" after completing the processing of one frame / one packet.

[0154] Step 305: Output pixel data stream and metadata for testing by semiconductor testing equipment.

[0155] The data processing device, after completing cross-channel merging and timing recovery, uses a pixel data stream organized by line / frame as the main output and simultaneously outputs metadata for use by semiconductor testing equipment.

[0156] In this embodiment, the pixel data stream is written to the output buffer (or directly to the downstream interface) in the form of a continuous byte stream or in blocks by frame / line, and its time base is consistent with the metadata. The metadata is used to identify and align the boundary information of the pixel data stream, including at least one or more of frame start, frame end, line start, and line end, and may carry fields such as the data type identifier related to the current frame / line, the number of effective payload bytes (when it is a long packet), and the cyclic redundancy check result (when configuration check is used). While outputting the pixel data stream, the device synchronously sends out the corresponding metadata in the form of events or flags, so that the semiconductor test equipment can complete frame / line level alignment, result statistics and judgment accordingly, and give a processing completion indication at the end of an output cycle so that the upper layer can schedule the next round of testing.

[0157] In one possible implementation, the data processing device based on the CSI protocol further includes a control state machine, and the method further includes: scheduling packet splitting, packet header merging, cross-channel merging of payload and timing recovery through the control state machine. The control states of the control state machine include at least a low-power state, a transmission start state, a packet header processing state, a data processing state, a tailing processing state and a transmission end state.

[0158] The operation flow of the control state machine includes:

[0159] In low-power mode, listen for the stop indication of the interface, and enter the transmission start state when the stop indication of any physical channel is negative;

[0160] In the initial transmission state, when the channel buffers of each physical channel have received the packet header, the packet header processing state is entered.

[0161] In the packet header processing state, the packet header is read from the channel buffer and cyclic redundancy check is performed. The packet header is reassembled between each physical channel and the data type identifier is parsed. When the data type identifier is a long packet type, the data processing state is entered. When the data type identifier is a short packet type, the closing processing state is entered.

[0162] In the data processing state, the effective load is read from each physical channel and cross-channel merging is performed to generate a pixel data stream. Cyclic redundancy check is performed on the pixel data stream. When the length of the merged data reaches the number of effective load bytes, a data completion indication is generated and the process enters the finishing processing state.

[0163] In the end-of-transmission processing state, the remaining data that does not require protocol layer processing is retrieved and discarded, and the type of the next data packet is determined. If it is determined to be a packet header, the packet header processing state is returned; if it is determined to be a packet tail, the transmission end state is entered. The remaining data includes placeholder bytes.

[0164] When the transmission is complete, it returns to a low-power state if the waiting interface indicates a stop.

[0165] For example, see Figure 7 The diagram shows the operation flow of the control state machine; as shown. Figure 7 As shown, the control state machine starts from a low-power state and enters the transmission start state when it detects a no-stop indication from any physical channel. In the transmission start state, after all the channel buffers of each physical channel have obtained the packet header, it enters the packet header processing state. In the packet header processing state, the packet header is read from the channel buffer and cyclic redundancy check is performed. The packet header is reassembled between channels and parsed to obtain the data type identifier: if it is determined to be a long packet type, it enters the data processing state; if it is determined to be a short packet type, it enters the end-of-processing state. In the data processing state, the payload is read from each physical channel and cross-channel merging is performed to generate a pixel data stream. Cyclic redundancy check is performed on the pixel data stream. When the cumulative length reaches the number of payload bytes, a data completion indication is generated and it enters the end-of-processing state. In the end-of-processing state, the remaining data (including placeholder bytes) that does not need to be processed by the protocol layer is retrieved and discarded, and the type of the next data packet is determined: if it is determined to be a packet header, it returns to the packet header processing state; if it is determined to be a packet tail, it enters the transmission end state. In the transmission end state, it waits for the interface's stop indication to be yes and then returns to the low-power state, thus completing the closed-loop scheduling of one transmission cycle.

[0166] Through the above method embodiments, this application achieves a closed-loop process by "receiving interface data from at least one physical channel of the physical layer; dividing the interface data of each physical channel into packets based on the CSI packet structure to obtain the packet header and payload of each physical channel; merging the packet headers between physical channels to obtain the data type identifier of the recombined packet header; performing cross-channel merging on the payload of each channel by identifying the data type identifier to generate a pixel data stream, and generating metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream; and outputting the pixel data stream and metadata for testing by the test equipment." This process, at the protocol level, first... Packetization by channel and merging of packet headers across channels ensures data type identification is based on a standard packet structure, thereby mitigating the impact of differences in devices and firmware on the receiver and improving cross-device compatibility and adaptability. At the data level, the payload of each channel is merged across channels based on data type, ensuring consistency and continuity of multi-channel data reassembly and improving acquisition stability. At the interface level, by restoring timing boundaries and outputting metadata synchronously with the data stream, a unified interface form of "data stream plus metadata" is provided to the upper layer, simplifying alignment and judgment, enhancing anomaly location and backtracking capabilities, significantly reducing configuration and maintenance costs, and improving testing efficiency and yield.

[0167] The above method is implemented using a camera sensor as an example of a chip under test, but this application is applicable to chips under test with CSI output interfaces, including but not limited to: camera sensors / modules, system-on-a-chip (SoC) with integrated image signal processing units (ISPs), etc. The method and apparatus can be used as stand-alone test equipment, or integrated and deployed as an image interface acquisition channel in a semiconductor automated test equipment (ATE) platform for production line testing, reliability verification, or laboratory evaluation.

[0168] See Figure 8 The flowchart of CSI data splitting and merging under multi-channel conditions is shown, which is a specific application scenario corresponding to the above method embodiment.

[0169] like Figure 8 As shown, in a 3-channel C-PHY configuration, the PPI interface data width is 32 bits (both lane preprocessing and external interfaces use 32 bits), and after lane (channel) merging processing, a 96-bit data width output is formed. The control state machine schedules the links: the right side is lane preprocessing, and the left side is lane merging processing. The two parts are connected through the "packet header merging and parsing" unit.

[0170] During the Lane preprocessing, each channel independently executes a pipeline of "packet processing, data buffering, demultiplexing, and header CRC check". The 32-bit data from the physical layer first enters the buffer. Under the instruction of the control state machine, the demultiplexing unit retrieves data from the buffer and splits it according to type. Data identified as header data is sent to "header CRC" for verification, and data identified as length data is output as long packet data. The output of this stage is the header data stream and the long packet data stream of each channel.

[0171] During the Lane merging process, the three packet header data enters "Packet Header Merging and Parsing". After being reassembled between channels, the DT (data type) and (when it is a long packet) WC (payload bytes) are parsed. If it is a long packet, "Long Packet Merging" concatenates the three 32-bit data into 96-bit continuous data according to the predetermined channel bit order and sends it to "CRC Check" for integrity checking. Then it enters "Image Timing Recovery", which combines the type / boundary information obtained from packet header parsing to recover the frame and line timing, and outputs the image data through the streaming video data interface. In this application, "streaming video data interface" is used to refer to a video data transmission channel implemented based on an advanced extensible interface streaming protocol, such as a streaming video data interface based on the AXIS-Stream protocol.

[0172] The following describes specific implementations of the packet processor in three scenarios:

[0173] See Figure 9When short packets are split, the physical layer data packets are split into two header data packets and one EOP control packet. After preprocessing by each lane, only the header path is formed. The header merging and parsing directly generates boundary events to participate in timing recovery.

[0174] Among them, SYNC is the synchronization identifier, used to indicate the start of the packet header; the preamble is used to indicate the start of the high-speed data transmission phase; and the postamble is used to indicate the end of the physical layer data packet.

[0175] See Figure 10 When long packets are split, the physical layer data packet is split into two header data packets, one long data packet, and one EOP control packet. After the packet headers are merged and parsed to obtain DT / WC, the "long packet merging" process completes the splicing between the three channels according to the WC count and performs CRC verification before entering the timing recovery output of the corresponding line / frame image data.

[0176] See Figure 11 In the link energy-saving mode, when packet splitting, taking n rows as an example, the packets are split into 2n header packets + n long packets + 1 EOP control packet according to the time relationship. The sequence of "packet header → long packet → gap word" of each row is output to the packet header and long packet channels respectively at the Lane preprocessing end. The merging end merges and verifies each row of long packets according to WC, and reconstructs the boundary line by line through timing recovery. Finally, multiple rows of image data are continuously output with a data width of 96 bits.

[0177] See Figure 12 The diagram shows a schematic of a data processing device based on the CSI protocol provided in an embodiment of this application; for ease of explanation, only the parts related to the embodiment of this application are shown.

[0178] A data processing device 1200 based on the CSI protocol is configured in a semiconductor testing equipment. The device may specifically include:

[0179] The receiving module 1201 is used to receive interface data from at least one physical channel of the physical layer;

[0180] The packet sub-module 1202 is used to sub-packet the interface data of each physical channel based on the CSI packet structure to obtain the packet header and payload of each physical channel.

[0181] The packet header merging module 1203 is used to merge the packet headers between physical channels to obtain the data type identifier of the recombined packet header;

[0182] The load merging module 1204 is used to perform cross-channel merging on the payload of each channel by identifying the data type identifier, generate a pixel data stream, and generate metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream.

[0183] The data output module 1205 is used to output pixel data streams and metadata for testing by semiconductor testing equipment.

[0184] In this embodiment of the application, the sub-packaging module 1202 may specifically include:

[0185] The packet initiation unit is used to initiate packet initiation operations for the corresponding physical channel based on the high-speed reception validity status of each physical channel.

[0186] The packet subdivision operation unit is used to divide the interface data into the header and payload of the corresponding physical channel according to the synchronization identifier in the interface data during the period when the high-speed reception valid state is the first target value, and write it into the channel buffer; when the high-speed reception valid state changes from the first target value to the second target value, the current packet subdivision operation is closed and the packet subdivision boundary is fixed, and the header and payload of the corresponding physical channel are obtained from the channel buffer.

[0187] In this embodiment of the application, the header merging module 1203 may specifically include:

[0188] The packet header verification unit is used to perform cyclic redundancy verification on the packet headers of each physical channel.

[0189] The reassembly unit is used to reassemble the verified packet header according to the channel bit order to obtain a reassembled packet header;

[0190] The parsing unit is used to parse the data type identifier from the type field of the recombined packet header.

[0191] In this embodiment of the application, the load merging module 1204 may specifically include:

[0192] The first acquisition unit is used to acquire the number of effective payload bytes when the identified data type is a long packet type;

[0193] The data stream generation unit is used to perform cross-channel merging of the payload of each physical channel to generate a pixel data stream based on the number of payload bytes.

[0194] The second acquisition unit is used to acquire a temporal boundary identifier that indicates the boundary of image data when the identified data type is a short packet type.

[0195] The first metadata generation unit is used to recover the temporal boundaries of the pixel data stream based on the temporal boundary identifier and the number of payload bytes, so as to generate metadata synchronized with the pixel data stream.

[0196] In this embodiment of the application, the load merging module 1204 may further include:

[0197] The pixel verification unit is used to perform cyclic redundancy check on the pixel data stream.

[0198] When the cyclic redundancy check result of the pixel data stream is normal, the second metadata generation unit restores the temporal boundary of the pixel data stream based on the temporal boundary identifier and the number of payload bytes, so as to generate metadata synchronized with the pixel data stream.

[0199] In this embodiment of the application, the data processing device 1200 based on the CSI protocol may further include:

[0200] The scheduling module is used to schedule packet splitting, packet header merging, cross-channel merging of payload, and timing recovery through a state machine. The control states of the state machine include at least a low-power state, a transmission start state, a packet header processing state, a data processing state, a tailing processing state, and a transmission end state.

[0201] In this embodiment of the application, the control state machine can specifically be used for:

[0202] In low-power mode, listen for the stop indication of the interface, and enter the transmission start state when the stop indication of any physical channel is negative;

[0203] In the initial transmission state, when the channel buffers of each physical channel have received the packet header, the packet header processing state is entered.

[0204] In the packet header processing state, the packet header is read from the channel buffer and cyclic redundancy check is performed. The packet header is reassembled between each physical channel and the data type identifier is parsed. When the data type identifier is a long packet type, the data processing state is entered. When the data type identifier is a short packet type, the closing processing state is entered.

[0205] In the data processing state, the effective load is read from each physical channel and cross-channel merging is performed to generate a pixel data stream. Cyclic redundancy check is performed on the pixel data stream. When the length of the merged data reaches the number of effective load bytes, a data completion indication is generated and the process enters the finishing processing state.

[0206] In the end-of-transmission processing state, the remaining data that does not require protocol layer processing is retrieved and discarded, and the type of the next data packet is determined. If it is determined to be a packet header, the packet header processing state is returned; if it is determined to be a packet tail, the transmission end state is entered. The remaining data includes placeholder bytes.

[0207] When the transmission is complete, it returns to a low-power state if the waiting interface indicates a stop.

[0208] The data processing device 1200 based on the CSI protocol provided in this application embodiment can be applied to the data processing device based on the CSI protocol provided in the foregoing embodiment. For details, please refer to the description of the data processing method based on the CSI protocol provided in the above embodiment, which will not be repeated here.

[0209] See Figure 13This diagram illustrates the structure of a semiconductor testing device provided in an embodiment of this application. Figure 13 As shown, the semiconductor testing equipment 1300 of this embodiment includes: at least one processor 1310 ( Figure 13 Only one is shown in the diagram), memory 1320, and computer program 1321 stored in the memory 1320 and executable on the at least one processor 1310, wherein the processor 1310 executes the computer program 1321 to implement the above-described data processing steps based on the CSI protocol.

[0210] The semiconductor testing equipment 1300 can be a server, physical server, or computing device, etc. This semiconductor testing equipment may include, but is not limited to, a processor 1310 and a memory 1320. Those skilled in the art will understand that... Figure 13 This is merely an example of semiconductor test equipment 1300 and does not constitute a limitation on semiconductor test equipment 1300. It may include more or fewer components than shown, or combine certain components, or use different components.

[0211] The processor 1310 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0212] In some embodiments, the memory 1320 may be an internal storage unit of the semiconductor testing equipment 1300, such as a hard disk or memory of the semiconductor testing equipment 1300. In other embodiments, the memory 1320 may be an external storage device of the semiconductor testing equipment 1300, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the semiconductor testing equipment 1300. Furthermore, the memory 1320 may include both internal storage units and external storage devices of the semiconductor testing equipment 1300. The memory 1320 is used to store operating systems, applications, boot loaders, data, and other programs, such as the program code of computer programs. The memory 1320 can also be used to temporarily store data that has been output or will be output.

[0213] In specific implementations, the processor 1310, memory 1320, and computer program 1321 described in the embodiments of this application can execute the embodiments of the data processing method based on the CSI protocol of this application, which will not be repeated here.

[0214] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0215] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0216] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0217] In the embodiments provided in this application, it should be understood that the disclosed apparatus / semiconductor testing equipment and methods can be implemented in other ways. For example, the apparatus / semiconductor testing equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0218] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0219] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0220] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0221] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the various method embodiments described above.

[0222] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data processing method based on the CSI protocol, characterized in that, The method includes: Receive interface data from at least one physical channel of the physical layer; Based on the CSI packet structure, the interface data of each physical channel is divided into packets to obtain the packet header and payload of each physical channel; Merge the packet headers of the various physical channels to obtain the data type identifier of the recombined packet header; By identifying the data type identifier, cross-channel merging is performed on the payload of each physical channel to generate a pixel data stream, and metadata synchronized with the pixel data stream is generated by restoring the timing boundary of the pixel data stream. The pixel data stream and the metadata are output for testing by semiconductor testing equipment.

2. The method as described in claim 1, characterized in that, The interface data of each physical channel is packetized based on the CSI packet structure to obtain the packet header and payload of each physical channel, including: Based on the high-speed reception validity status of each physical channel, initiate packet subpacketization operation for the corresponding physical channel; The packet splitting operation includes: during the period when the high-speed reception valid state is a first target value, dividing the interface data into packet headers and payloads corresponding to the physical channels according to the synchronization identifier in the interface data, and writing them into the channel buffer; when the high-speed reception valid state changes from the first target value to a second target value, closing the current packet splitting operation and fixing the packet splitting boundary, and obtaining the packet headers and payloads corresponding to the physical channels from the channel buffer.

3. The method as described in claim 1, characterized in that, The process of merging the packet headers between the various physical channels to obtain the data type identifier of the recombined packet header includes: Cyclic redundancy check is performed on the packet headers of each physical channel; The reconstructed packet header is obtained by reassembling the verified packet header according to the channel position order; The data type identifier is obtained by parsing the type field of the recombinant header.

4. The method as described in claim 1, characterized in that, The process of identifying the data type identifier, performing cross-channel merging on the payload of each physical channel to generate a pixel data stream, and generating metadata synchronized with the pixel data stream by restoring the timing boundaries of the pixel data stream includes: When the data type is identified as a long packet type, the number of effective payload bytes is obtained; Based on the number of payload bytes, perform cross-channel merging of the payload of each physical channel to generate a pixel data stream; When the data type identifier is identified as a short packet type, a temporal boundary identifier used to indicate the boundary of the image data is obtained; The timing boundary of the pixel data stream is recovered based on the timing boundary identifier and the number of payload bytes to generate metadata synchronized with the pixel data stream.

5. The method as described in claim 4, characterized in that, The method further includes: Perform cyclic redundancy check on the pixel data stream; When the cyclic redundancy check result of the pixel data stream is normal, the timing boundary of the pixel data stream is restored based on the timing boundary identifier and the number of payload bytes to generate metadata synchronized with the pixel data stream.

6. The method as described in claim 1, characterized in that, The method further includes: The packet splitting, header merging, cross-channel payload merging, and timing recovery are scheduled by a control state machine. The control states of the control state machine include at least a low-power state, a transmission start state, a header processing state, a data processing state, a tailing processing state, and a transmission end state.

7. The method as described in claim 6, characterized in that, The operation flow of the control state machine includes: In low-power mode, listen for the stop indication of the interface, and enter the transmission start state when the stop indication of any physical channel is negative; In the transmission start state, when the channel buffers of each physical channel have received packet headers, the packet header processing state is entered. In the packet header processing state, the packet header is read from the channel buffer and cyclic redundancy check is performed. The packet header is reassembled between the physical channels and the data type identifier is parsed to obtain the data type identifier. When the data type identifier is a long packet type, the data processing state is entered. When the data type identifier is a short packet type, the closing processing state is entered. In the data processing state, the effective load is read from each physical channel and cross-channel merging is performed to generate a pixel data stream. Cyclic redundancy check is performed on the pixel data stream. When the length of the merged data reaches the number of effective load bytes, a data completion indication is generated and the process enters the finishing processing state. In the closing processing state, the remaining data that does not require protocol layer processing is retrieved and discarded, and the type of the next data packet is determined. If it is determined to be a packet header, the packet header processing state is returned; if it is determined to be a packet tail, the transmission end state is entered. The remaining data includes placeholder bytes. When the transmission is complete, it waits for the interface to indicate a stop and then returns to a low-power state.

8. A data processing device based on the CSI protocol, characterized in that, Configured in a semiconductor testing device, the apparatus includes: A receiving module is used to receive interface data from at least one physical channel of the physical layer; The packet sub-module is used to sub-packetize the interface data of each physical channel based on the CSI packet structure, and obtain the packet header and payload of each physical channel. The packet header merging module is used to merge the packet headers between the various physical channels to obtain the data type identifier of the recombined packet header; The load merging module is used to perform cross-channel merging on the payload of each physical channel by identifying the data type identifier, generate a pixel data stream, and generate metadata synchronized with the pixel data stream by restoring the timing boundary of the pixel data stream. The data output module is used to output the pixel data stream and the metadata for testing by semiconductor testing equipment.

9. An ATE testing system, characterized in that, The ATE test system includes: a physical layer, a data processing device based on the CSI protocol, and a processing unit; The physical layer is used to receive high-speed serial signals from the chip under test, perform signal recovery and channel alignment, and output interface data of at least one physical channel to the data processing device based on the CSI protocol. The data processing device based on the CSI protocol is used to execute the data processing method based on the CSI protocol as described in any one of claims 1 to 7; The processing unit, configured in a semiconductor testing device, is used to receive pixel data streams and metadata, perform pixel-level processing, display, and / or storage on the pixel data streams, and perform alignment and test determination based on the metadata.

10. The system as described in claim 9, characterized in that, The physical layer is a receiving module for a three-phase coded physical layer; The physical layer is also used to output a status indication of at least one physical channel to the data processing device of the CSI protocol, the status indication including at least a high-speed reception valid status and a stop indication; The processing unit is further configured to receive the pixel data stream in a row-organized manner and perform frame and row alignment based on the temporal boundary identifier in the metadata.

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