Method for realizing PAL video superposition based on FPGA

Abstract

The invention provides a method for achieving PAL video superposition based on an FPGA, and the method comprises the following steps: carrying out the power-on configuration of a video decoder and a video encoder through a CPLD and based on a heartbeat handshake signal generated after the FPGA is started, and carrying out the power-on configuration of a register through an IIC time sequence, and enabling a line synchronization signal and a field synchronization signal to only jump in an EAV code; receiving and decoding the analog video signal to generate a digital video stream conforming to the ITU-R BT656 protocol; parsing the digital video stream to extract a frame start flag and a line start flag; caching the video data to a block memory of the FPGA to serve as background video data; operating a video superposition algorithm state machine, performing row and column pointer updating in subsequent coding by adopting an internal synchronization mode based on the frame start mark and the row start mark, and selecting background video data or superposition mark data for output in a specific row and specific column region to generate a superposed digital video stream; and encoding the superposed digital video stream to output an analog video signal.

Description

Technical Field

[0001] This application relates to the development technology of logic gate arrays in aerospace and other fields, and specifically to a method for PAL video overlay based on FPGA. Background Technology

[0002] In fields such as airborne pod display and control, in order to provide clear instructions to operators, it is necessary to overlay graphic information such as center cursors, direction markers, and field of view indicators onto the transmitted raw video footage. This process relies primarily on stable and reliable video overlay technology.

[0003] Currently, traditional video overlay control solutions mostly employ a dedicated chip (such as ARM) with a digital signal processor (DSP) architecture. However, this traditional solution has many inherent drawbacks: Poor flexibility: The ARM+DSP hardware architecture is fixed, and its processing flow and display mode are difficult to adapt and adjust flexibly and quickly according to changing application scenarios (such as different marking styles and different refresh rate requirements).

[0004] Complex configuration and long development cycle: The register configuration of dedicated chips is usually quite complex and depends on specific underlying drivers, which leads to a heavy workload in software development and prolongs the project development cycle.

[0005] High hardware costs: ARM and DSP chips are inherently expensive, and their peripheral circuits are complex, further increasing the overall hardware cost.

[0006] Maintenance and upgrades are difficult: the functional modules are highly coupled, and if defects need to be fixed or functions upgraded later, it often requires major modifications to the entire software and hardware system, resulting in high maintenance costs and inflexible upgrade paths.

[0007] Furthermore, at the technical implementation level, video processing based on the ITU-R BT.656 protocol presents specific technical challenges: the standard does not explicitly specify the exact positions where the field synchronization signal V and the parity field flag F transition from 0 to 1 (whether in SAV or EAV code). This uncertainty leads to unpredictable transition edges for the line synchronization H, field synchronization V, and parity flag F generated by the decoder, easily causing frame decoding errors in the original video and resulting in image corruption. Simultaneously, system power-on timing is also a critical issue. In practical applications, the power-on loading time of the FPGA is much longer than that of the CPLD. If the CPLD configures the encoder first, register write failures may occur due to the FPGA not being ready and the configuration clock LLC being unstable, affecting the reliability of system initialization. Summary of the Invention

[0008] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide a method for PAL video overlay based on FPGA, the method being executed by a hardware system including an FPGA and a CPLD, and comprising the following steps: The CPLD is used to power up and configure the video decoder and video encoder respectively, based on the heartbeat handshake signal generated after the FPGA is started. The configuration of the video decoder includes: configuring its registers through IIC timing so that the line synchronization signal and the field synchronization signal only change in the EAV code; Receives and decodes analog video signals to generate a digital video stream conforming to the ITU-R BT656 protocol; The digital video stream is parsed to extract the start-of-frame and start-of-line markers; The digital video stream is cached in the block memory of the FPGA as background video data; The video overlay algorithm state machine is run. Based on the frame start flag and the row start flag, the row and column pointers are updated in the subsequent encoding using an internal synchronization mode. In specific row and column regions, the background video data or overlay marker data is selected for output to generate the overlaid digital video stream. The superimposed digital video stream is encoded to output an analog video signal.

[0009] According to the technical solution provided in the embodiments of this application, configuring a video decoder includes the following steps: The IIC timing is generated by the CPLD, and its registers are configured to make it work in internal synchronization mode and conform to the BT656 protocol. By configuring the register, the line synchronization signal H and the parity field flag signal F are locked to change only in the EAV code.

[0010] According to the technical solution provided in the embodiments of this application, a video decoder is configured, and the specific registers and values ​​configured include: Configure register at address 0x03 to 09h; Configure registers at addresses 0x11 and 0x13 to 04h, and configure registers at addresses 0x12 and 0x14 to 00h; Configure registers at addresses 0xA0, 0x69, and 0x6D to 55h, 40h, and 90h respectively.

[0011] According to the technical solution provided in the embodiments of this application, configuring a video encoder includes the following steps: After the CPLD detects the square wave heartbeat signal from the FPGA, it generates IIC timing to configure its registers. Configure its working mode as PAL, BT656 standard, and internal synchronization mode; Configure the subcarrier frequency, color difference phase, U / V component gain, black level, and blanking level parameters.

[0012] According to the technical solution provided in the embodiments of this application, a video encoder is configured, and the specific registers and values ​​configured include at least one of the following: Configure address 0x3A to 13h to set internal synchronization mode; Configure address 0x61 as 06h to set PAL output; Configure registers at addresses 0x5A, 0x5B, 0x5C, 0x5D, and 0x5E as 00h, 6Dh, 9Fh, 0Eh, and 1Ch respectively to control the phase, gain, and level of the color difference. Configure registers at addresses 0x63, 0x64, 0x65, and 0x66 as CBh, 8Ah, 09h, and 2Ah respectively to configure the PAL subcarrier frequency.

[0013] According to the technical solution provided in the embodiments of this application, the extraction of the frame start flag and the line start flag includes the following steps: The frame start flag is triggered by the falling edge of the parity field flag F. After continuously detecting the three preambles 8'hFF, 8'h00, and 8'h00 in the BT656 data stream, the 6th bit of the 4th byte is read to determine the change of the F signal. The line start flag is triggered by the falling edge of the line synchronization signal H. After continuously detecting the three preambles 8'hFF, 8'h00, and 8'h00 in the BT656 data stream, the 4th bit of the 4th byte is read to determine the change of the H signal.

[0014] According to the technical solution provided in the embodiments of this application, the video overlay algorithm state machine includes the following states: IDLE state: Initialize pixel pointer Pixels=0, line pointer Lines=0, wait for encoder and decoder configuration completion signals GM7121_CFG_DONE and GM7150_CFG_DONE, and detect the frame start flag and line start flag; WORK state: Controls the pixel pointer Pixels to increment on the falling edge of the pixel clock pclk, and performs state transitions based on the values ​​of Pixels and Lines; EAV state: When Pixels<=4, output the end synchronization code, including 8'hFF, 8'h00, 8'h00 and the EAVx code representing the field information; VBLANKING state: When 4 < Pixels <= 284, according to the parity of Pixels, alternately output the line blanking area filling code 8'h10 or 8'h80; SAV state: When 284 < Pixels <= 288, output the start synchronization code, including 8'hFF, 8'h00, 8'h00 and the SAVx code representing field information; DATA state: When 288 < Pixels <= 1728, enter the EVEN, Y1, ODD, Y2 sub - states in sequence according to the YCbCr422 format, and complete the data source selection and output of the background video data and the superimposed marker data.

[0015] According to the technical solution provided by the embodiment of the present application, in the DATA state, the specific method of data source selection is: For the rows and columns belonging to the background area, the output pixel data is sourced from the original video data read from the BRAM 10 clock cycles in advance; For the rows and columns belonging to the superimposed marker area, the output pixel data is preset marker data.

[0016] According to the technical solution provided by the embodiment of the present application, the row - column pointer update and clearing rules in the internal synchronization mode are: The pixel pointer Pixels is incremented by 1 at the falling edge of each pixel clock pclk. When Pixels accumulates to 1728, it is automatically cleared, and the line pointer Lines is incremented by 1; When the line pointer Lines accumulates to 625 and the pixel pointer Pixels is 1728, the line pointer Lines is cleared.

[0017] According to the technical solution provided by the embodiment of the present application, in the hardware system, the FPGA uses the XILINX XC7A100T chip, the video decoder uses the GM7150A chip, the video encoder uses the GM7121 - D chip, and the CPLD uses the紫光PGC7KD series chip.

[0018] Compared with the prior art, the beneficial effects of the present application are: First, the hardware cost is significantly reduced: The present invention uses a general - purpose FPGA as the core processor, replacing the expensive "ARM + DSP" combination in the traditional solution. At the same time, domestic - made decoder (GM7150A), encoder (GM7121 - D) and CPLD chips are selected, greatly reducing the hardware cost of system components.

[0019] II. Excellent System Flexibility and Scalability: Based on the programmable nature of FPGA, its internal logic (such as overlay graphics, overlay positions, state machine processes, etc.) can be flexibly and quickly modified according to the needs of different display scenarios without changing the hardware circuit. Each functional module (such as decoding, overlay, encoding) is implemented internally by logic design within the FPGA, with low coupling, facilitating independent updates and expansions of functions.

[0020] Third, shorter development cycle and easier maintenance: Development using hardware description languages ​​(such as Verilog / VHDL) avoids the complex low-level driver writing and register configuration work of traditional solutions. The modular design makes later maintenance and upgrades easier, effectively saving project development and maintenance costs.

[0021] IV. Fundamental Improvement in Synchronization Reliability: By precisely configuring the decoder register through CPLD, the line synchronization signal H and the parity field flag F are forced to change only in the EAV code, which fundamentally eliminates the problem of accumulated frame de-framing phase error caused by protocol ambiguity, ensuring the stability and accuracy of video sequence synchronization, and laying a solid foundation for subsequent lossless video overlay.

[0022] V. Enhanced System Initialization Reliability: An innovative heartbeat handshake mechanism is introduced between the FPGA and CPLD. The CPLD only initiates the encoder configuration process after detecting a stable square wave heartbeat generated after the FPGA has started up. This design ensures the stability of the configuration clock LLC and the success rate of register configuration, effectively solving the system initialization failure problem caused by differences in chip power-on timing.

[0023] VI. Precise and Stable Overlay Effect: Utilizing a strategy of "initial synchronous capture, internal synchronization mode maintenance," synchronization is achieved only once upon state machine startup using the frame / line start flag from the external video source. Subsequent frames are encoded entirely using a stable clock generated internally by the FPGA. This mechanism effectively avoids output phase drift caused by non-ideal characteristics of the front-end video source (such as line cycle jitter), thus preventing distortions such as flickering and stripes in the overlay image and ensuring a high-quality overlay display effect. Attached Figure Description

[0024] Figure 1 A flowchart illustrating the steps of a method for PAL video overlay based on FPGA provided in this application embodiment; Figure 2 A hardware block diagram of a method for implementing PAL video overlay based on FPGA provided in an embodiment of this application; Figure 3 Key timing diagrams for GM7150A frame de-framing provided in this application embodiment; Figure 4Another key timing diagram for GM7150A frame de-framing provided in this application embodiment; Figure 5 The flowchart of the video overlay algorithm for the PAL video overlay method based on FPGA provided in this application embodiment is shown. Detailed Implementation

[0025] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Example 1 As mentioned in the background section, to address the problems in the prior art, this application proposes a method for PAL video overlay based on FPGA. This method is executed by a hardware system including an FPGA and a CPLD, such as... Figure 1 As shown, it includes the following steps: S1. Power on and configure the video decoder and video encoder respectively using the CPLD and based on the heartbeat handshake signal generated after the FPGA is started. S11. Configuring the video decoder includes: configuring its registers via IIC timing to ensure that the line synchronization signal and the field synchronization signal only change within the EAV code; S2. Receive and decode analog video signals to generate a digital video stream conforming to the ITU-R BT656 protocol; S3. Parse the digital video stream to extract the frame start marker and line start marker; S4. Cache the digital video stream into the block memory of the FPGA as background video data; S5. Run the video overlay algorithm state machine. Based on the frame start flag and the row start flag, update the row and column pointers in the subsequent encoding using the internal synchronization mode. In the region of a specific row and a specific column, select the background video data or overlay mark data for output to generate the overlaid digital video stream. S6. Encode the superimposed digital video stream to output an analog video signal.

[0028] In a preferred embodiment, configuring the video decoder includes the following steps: The IIC timing is generated by the CPLD, and its registers are configured to make it work in internal synchronization mode and conform to the BT656 protocol. By configuring the register, the line synchronization signal H and the parity field flag signal F are locked to change only in the EAV code.

[0029] In a preferred embodiment, the video decoder is configured, and the specific registers and values ​​configured include: Configure register at address 0x03 to 09h; Configure registers at addresses 0x11 and 0x13 to 04h, and configure registers at addresses 0x12 and 0x14 to 00h; Configure registers at addresses 0xA0, 0x69, and 0x6D to 55h, 40h, and 90h respectively.

[0030] According to the technical solution provided in the embodiments of this application, configuring a video encoder includes the following steps: After the CPLD detects the square wave heartbeat signal from the FPGA, it generates IIC timing to configure its registers. Configure its working mode as PAL, BT656 standard, and internal synchronization mode; Configure the subcarrier frequency, color difference phase, U / V component gain, black level, and blanking level parameters.

[0031] In a preferred embodiment, a video encoder is configured, and the specific registers and values ​​configured include at least one of the following: Configure address 0x3A to 13h to set internal synchronization mode; Configure address 0x61 as 06h to set PAL output; Configure registers at addresses 0x5A, 0x5B, 0x5C, 0x5D, and 0x5E as 00h, 6Dh, 9Fh, 0Eh, and 1Ch respectively to control the phase, gain, and level of the color difference. Configure registers at addresses 0x63, 0x64, 0x65, and 0x66 as CBh, 8Ah, 09h, and 2Ah respectively to configure the PAL subcarrier frequency.

[0032] In a preferred embodiment, the extraction of the frame start flag and the line start flag includes the following steps: The frame start flag is triggered by the falling edge of the parity field flag F. After continuously detecting the three preambles 8'hFF, 8'h00, and 8'h00 in the BT656 data stream, the 6th bit of the 4th byte is read to determine the change of the F signal. The line start flag is triggered by the falling edge of the line synchronization signal H. After continuously detecting the three preambles 8'hFF, 8'h00, and 8'h00 in the BT656 data stream, the 4th bit of the 4th byte is read to determine the change of the H signal.

[0033] In a preferred embodiment, the video overlay algorithm state machine includes the following states: IDLE state: Initialize the pixel pointer Pixels = 0 and the line pointer Lines = 0, wait for the encoder and decoder configuration completion signals GM7121_CFG_DONE and GM7150_CFG_DONE, and detect the frame start flag and line start flag; WORK state: Control the pixel pointer Pixels to increment on the falling edge of the pixel clock pclk, and perform state jumps according to the values of Pixels and Lines; EAV state: When Pixels <= 4, output the end sync code, including 8'hFF, 8'h00, 8'h00, and the EAVx code representing the field information; VBLANKING state: When 4 < Pixels <= 284, alternately output the line blanking area filling code 8'h10 or 8'h80 according to the parity of Pixels; SAV state: When 284 < Pixels <= 288, output the start sync code, including 8'hFF, 8'h00, 8'h00, and the SAVx code representing the field information; DATA state: When 288 < Pixels <= 1728, sequentially enter the EVEN, Y1, ODD, and Y2 sub-states in the YCbCr422 format, and complete the data source selection and output of the background video data and the overlay marker data.

[0034] In a preferred embodiment, in the DATA state, the specific method for data source selection is: For the rows and columns belonging to the background area, the output pixel data is sourced from the original video data read from the BRAM 10 clock cycles in advance; For the rows and columns belonging to the overlay marker area, the output pixel data is the preset marker data.

[0035] In a preferred embodiment, the row and column pointer update and clearing rules in the internal synchronization mode are: The pixel pointer Pixels increments by 1 on the falling edge of each pixel clock pclk. When Pixels accumulates to 1728, it is automatically cleared, and the line pointer Lines is incremented by 1; When the line pointer Lines accumulates to 625 and the pixel pointer Pixels is 1728, the line pointer Lines is cleared.

[0036] In a preferred embodiment, the hardware system uses a XILINX XC7A100T chip for the FPGA, a GM7150A chip for the video decoder, a GM7121-D chip for the video encoder, and a Ziguang PGC7KD series chip for the CPLD.

[0037] Specifically, the technical problems to be solved by this invention are: hardware configuration of CPLD for decoder GM7150A; hardware configuration of CPLD for decoder GM7121-D; and FPGA implementation of video overlay conforming to the ITU-R BT656 transmission protocol. The technical solution adopted to address these problems is as follows: Configuration of the GM7150A video decoder chip: The decoder configuration refers to the FPGA setting the working mode of the decoding chip by generating IIC timing (baud rate 400Kbps). The ITU-R BT656 standard embeds horizontal and vertical synchronization information into the video stream by inserting SAV and EAV codes. The advantage of using BT656 for video transmission is that no external horizontal and vertical synchronization signals need to be added to the cable, avoiding unpredictable interference during long-distance on-machine cabling, which could lead to loss of synchronization in video decoding and image corruption. However, the ITU-R BT656 standard does not specify whether the transition of the vertical blanking bit V from 0 to 1 is completed in the SAV code or the EAV code. Therefore, the transitions of the horizontal synchronization H, vertical synchronization V, and parity flag F generated by the decoding logic are also unpredictable, which can cause frame decoding errors in the original video. Therefore, it is necessary to configure relevant registers to ensure that the horizontal and vertical synchronization information only changes in the EAV code, avoiding the accumulation of phase errors in the decoded data.

[0038] Configuration of the GM7121-D image encoder chip: The encoder configuration refers to the FPGA setting the operating mode of the encoding chip by generating IIC timing (baud rate 400Kbps). The main configuration parameters of the GM7121-D encoder include: encoding standard (PAL / NTSC), standard met by the image transmission control data (BT601 / BT656), resolution of the encoded output image (standard definition / high definition / high definition), encoding color requirements (color / black and white), frame rate (25fps / 30fps / 60fps), synchronization method (internal synchronization / external synchronization), master-slave mode (receiving video control data, outputting video control data), etc.

[0039] Specifically, it should be noted that the clock LLC (27MHz) used for the encoder GM7121-D configuration is generated from the same source as the FPGA and the video data PIXOUT. The configuration register operation is performed by the CPLD, and the FPGA's power-on loading time is much longer than the CPLD's startup time. This will cause the register data to be invalid during the initial power-on phase of the GM7121-D (because the configuration clock LLC is not yet stable at this time). Therefore, in this invention, a heartbeat handshake signal between the FPGA and the CPLD is designed. Only when the CPLD detects the square wave heartbeat of the FPGA does it consider that the FPGA has started and generates a stable configuration clock LLC. Only then can the register configuration be successfully performed.

[0040] Video overlay algorithm based on BT656 transmission format: The video overlay mentioned refers to a technique that uses an externally input video source as a background layer and overlays the image to be displayed on top of it; it is not a simple scalar overlay of pixel values. The overlaid video data must still meet the BT656 protocol standard. Therefore, it involves parsing and storing the original video data. In the encoder state machine, the vector overlay of the video images is completed by selecting the data source of the original data and the newly added video data.

[0041] The BT656 protocol refers to the FPGA transmitting timing information consistent with the image encoding protocol, enabling the GM7121-D to reliably receive data and achieve the expected encoding effect. For standard definition PAL format encoding, with a resolution of 720*576, the generated data format must meet the YUV422 (i.e., Cb, Y1, Cr, Y2) timing. Since each effective pixel is determined by two luminance components (Y1, Y2), each line requires 1440 chrominance and luminance information. Including line blanking, encoding one line of image requires a total of 1728 pixel clock cycles.

[0042] This invention uses the variable Pixels to count the sequence number of the current in-row pixel clock PCLK, which serves as the column index for the current encoding. The PAL system refers to phase inversion by row: the number of scan rows is 625, and an interlaced scanning method is used. That is, the scan of one frame of image consists of: even field scan rows (288) + odd field scan rows (288) + field blanking rows (49). Therefore, in this paper, the variable Lines (maximum 625) is used as the row index for the current encoding.

[0043] The aforementioned overlay algorithm essentially uses an encoding algorithm state machine to drive the active pixel data to be overlaid in specific areas of the image (certain rows and columns), while in other areas, the data (original video data) is read out of the memory in advance and output through the encoding algorithm state machine. This allows for the selection of different data sources in different areas, thereby completing the vector overlay process.

[0044] This invention proposes a method for PAL video overlay based on FPGA, which offers more flexible control, lower hardware costs, and a shorter development cycle. (See reference...) Figure 1-4 The present invention provides a method for PAL video overlay based on FPGA as follows: In this example, the hardware circuit uses the GM7150A (video decoding circuit) from Chengdu Zhenxin Company as the onboard video source receiving and preprocessing component to convert the analog composite video CVBS signal input on the aircraft via coaxial cable into a digital signal conforming to the CCIRBT656 format. The XC7A100T from Xilinx is used as the core of video processing. It receives and synchronizes the 8-bit image data PIX_IN signal from the upstream decoder chip (meeting the BT656 protocol's line synchronization HSYNC, field synchronization VSYNC, parity field flag FID, and pixel sampling clock PCLK_IN). The parsed input data is cached in real time into the FPGA's BRAM (one frame's worth of data) as the display background area. In specific areas (certain lines and certain pixel positions within each line), driving and marking data is applied and superimposed on the background data layer. Finally, a data stream conforming to the BT656 internal synchronization format and a clock drive are provided to the video physical layer encoding circuit GM7121-D. After DA conversion by the physical layer encoder, the signal is converted into a CVBS signal output and transmitted back to the pod display and control components via a 75-ohm coaxial cable to complete the onboard video overlay processing.

[0045] In this example, the CPLD is used to complete the power-on initialization configuration of the physical layer encoder chip GM7121-D and the decoder chip GM7150A. After configuration, it sends the FPGA indicator signals GM7121_CFG_DONE and GM7150_CFG_DONE, indicating that the encoder and decoder circuits are ready to execute the FPGA's video processing algorithm logic. Specifically, the key register configurations involved in the GM7150A decoder chip include: Configure the frame decoding format to meet the internal synchronization mode and comply with the BT656 protocol: 0x03 is configured as 09h; Configure the line synchronization H and parity field flag F transitions within the embedded EAV data field: 0x11 is configured as 04h, 0x12 as 00h, 0x13 as 04h, 0x14 as 00h, 0xA0 as 55h, 0xA1 as AAh, 0x69 as 40h, and 0x6D as 90h. The key register configurations involved in the GM7121-D encoder chip include: Configure encoder real-time control, Burst start position: 0x28 is configured as 21h; Configure encoder real-time control, Burst end position: 0x29 is configured as 1Dh; Configure the encoder to operate in internal synchronization mode, without providing line and field signals through external interfaces RCV2 and RCV1: 0x3A is configured as 13h; Encoder color difference phase initial phase control: 0x5A is configured as 00h; Encoder U-component gain control: 0x5B is configured as 6Dh; Encoder V-component gain control: 0x5C is configured as 9Fh; Encoder black level configuration: 0x5D is configured as 0Eh; Encoder blanking level configuration: 0x5E is configured as 1Ch; Configure the encoder to output PAL analog signals: 0x61 is configured as 06h; Encoder RTC disabled: 0x62 is configured as 3Bh; Configure PAL subcarrier frequency, minimum byte value: 0x63 is configured as CBh; Configure the PAL subcarrier frequency, second lowest byte value: 0x64 is configured as 8Ah; Configure the PAL subcarrier frequency, second-highest byte value: 0x65 is configured as 09h; Configure PAL subcarrier frequency, maximum byte value: 0x66 is configured as 2Ah; RCV port control, does not receive or output RCV port control signals: 0x6B is configured as 00h; Configure the encoder's line trigger position: 0x6C is configured as 11h; Configure the encoder's field trigger position: 0x6D is configured as 13h, and 0x75 is configured as 90h; like Figure 2 The diagram shows a hardware block diagram of a method for PAL video overlay based on FPGA. In this example, the GM7150A is used as the parsing and preprocessing circuit for an external analog video source. The CVBS analog signal is converted into a digital signal conforming to the CCIR BT656 protocol by the ADC. After preprocessing, the pixel clock and pixel data are generated and output to the video core processor FPGA. The FPGA is used to store the background data source in real time and overlay recognition tags. The data source is selected through the implemented encoding algorithm state machine. Finally, the pixel data and pixel clock are output through the BT656 algorithm to drive the physical layer encoder GM7121-D to complete the digital-to-analog conversion. The output CVBS analog video is then transmitted back to the airborne pod via a coaxial cable. like Figure 3-4 The diagram shown is a key timing diagram of GM7150A frame decoding for a method of PAL video overlay based on FPGA according to the present invention.

[0046] In this example, in order to achieve recognition mark overlay on the externally input video background, it is necessary to ensure that the timing difference between the overlaid image data and the timing difference between the externally input video source data is fixed. The fixed phase difference is a prerequisite for distortion-free overlay between images. Therefore, it is necessary to extract the LINE_1 ST_START flag and the START_PIXEL flag of the video frame start from the input video stream, and drive the BT656 algorithm state machine after a fixed number of 27M clock cycles of delay to generate the overlaid video data stream.

[0047] The frame start flag only undergoes a positive transition from the falling edge of the 1728th 27M clock in the 625th row of each frame to the falling edge of the first 27M clock in the first row of the next frame, i.e., it is only pulled high for one clock cycle, thereby triggering the FPGA encoding algorithm state machine to clear the row label LINE to 1; the row start flag only goes high for one clock cycle from the falling edge of the 1728th 27M clock in each row to the falling edge of the first 27M clock in the next row, thereby triggering the FPGA encoding algorithm state machine to clear the column label pixels to 1.

[0048] The generation of the frame start flag is characterized by the falling edge of the odd field flag F, and the video scan switches from odd field to even field, which is the start of the first line (frame start); the parity field flag F signal is parsed by the CPLD through power-on initialization configuration, which is set to occur in EAV. According to the BT656 protocol, after the three preambles 8'hFF, 8'h00, and 8'h00 are detected in succession, the 6th bit of the 4th byte 8'hXY represents the change of the F signal; The generation of the line start flag is characterized by the falling edge of the line synchronization H. During each line scan, the video includes a line blanking area and a line valid data area. During the blanking area, the line synchronization H remains high, while the H signal is pulled low in the valid data area. Therefore, the falling edge of H represents the switching time from the blanking area to the first pixel of the valid data area in each line. The parsing of the line synchronization H signal is configured by the CPLD during power-on initialization. It is set to have a transition during the EAV synchronization code. According to the BT656 protocol, after the three preambles 8'hFF, 8'h00, and 8'h00 are detected consecutively, the fourth bit of the fourth byte 8'hXY represents the change of the H signal. like Figure 4 The diagram shown is a flowchart of a video overlay algorithm for a method of PAL video overlay based on FPGA according to the present invention.

[0049] In this example, after the system is powered on, the physical layer encoder chip GM7121-D and decoder chip GM7150A are first configured using the CPLD to operate in the expected mode, and each generates a configuration completion flag: GM7121_CFG_DONE and GM7150_CFG_DONE. If the configuration is not completed, the FPGA user logic is kept in a reset state, that is, it remains in the IDLE state of the image algorithm encoding state machine to avoid the generation of unknown undetermined states and cause the screen initialization to fail.

[0050] Specifically, since any physical layer decoder and external source are not ideal, the result of frame decoding may have a longer or shorter number of pixel clock cycles per line (for example, sometimes the decoded duration of one line is 1726 27M clock cycle lengths, and sometimes it may be decoded as 1729 27M clock cycle lengths for one line). This situation belongs to the hardware error itself, which can easily lead to an uncontrollable phase difference between the output of the subsequent superimposed video and the source video, and further cause irregular screen flashing and stripes to appear. Therefore, in this example, a strategy of power-on to synchronize the output video with the original video only once is adopted. Only during the IDLE state of the encoding state machine, the indication signals of the first line of the first frame: LINE_1ST_START and START_PIXEL are detected; the starting point of the superimposed output video encoding is found. During the subsequent encoding process, only the internal synchronization mode is relied on to update and clear the line index Lines and column index Pixels: that is, the column index of pixels is cleared after 1728, and the line index of lines is cleared when the line index is 625 and the column index is 1728 at this time.

[0051] Specifically, the encoding states required by the encoding state machine are as follows: IDLE state: Complete the initialization of the pixel row and column pointers (and clear operation), initialize the default value of the image pixels to 8’hFF, ensure that the encoder chip and decoder chip are configured, and if the row and column start flags are detected, the state machine jumps to the WORK state.

[0052] WORK state: Detect the trigger condition for the increment of the row and column pointers, and at the same time output the BT656 data.

[0053] EAV state (pixel pointer Pixels <= 4): End (not started) sync code state, including: Output the end sync code EAV1 = 8’hB6 for the back porch of the even field blanking; Output the end sync code EAV2 = 8’h9D for the end of the even field data; Output the end sync code EAV3 = 8’hB6 for the front porch of the end of the even field blanking; Output the end sync code EAV4 = 8’hF1 for the back porch of the end of the odd field blanking; Output the end sync code EAV5 = 8’hDA for the end of the odd field data; Output the end sync code EAV6 = 8’hF1 for the front porch of the end of the odd field blanking; VBLANKING state (4 < Pixels <= 284 for pixel pointer): Line blanking state, including: Output the filling code BLANK_ODD = 8’h10 for the odd pixel positions in the line blanking area; Output the filling code BLANK_EVEN = 8’h80 for the even pixel positions in the line blanking area; SAV state (pixel pointer 284 <Pixels <= 288): Start sync code state, including: Start sync code SAV1 = 8’hAB at the back porch of even field blanking; Start sync code SAV2 = 8’h80 at the start of even field data; Start sync code SAV3 = 8’hAB at the front porch of even field blanking; Start sync code SAV4 = 8’hEC at the back porch of odd field blanking; Start sync code SAV5 = 8’hC7 at the start of odd field data; Start sync code SAV6 = 8’hEC at the front porch of odd field blanking; DATA state (pixel pointer 288 <Pixels <= 1728): Picture data encoding state, including: Chrominance component Cb encoding state: EVEN; Luminance component Y1 encoding state: Y1; Chrominance component Cr encoding state: ODD; Luminance component Y2 encoding state: Y2; END state: End state when the picture completes 1 frame and 2 fields of scanning, will jump back to the WORK state and continuously loop to refresh the encoded picture.

[0054] When the 27M pixel clock pclk generated by the FPGA PLL is locked, and at this time the configuration timing of the encoder GM7121-D and the decoder GM7150A has been completed, the START_ENCODING flag signal is pulled high; if the line start flag and frame start flag of the input source have been pulled high by the decoding module at this time, the image encoder state machine is triggered to work, and the specific process is as follows: Step 1: The encoder state machine is in the IDLE state, initializing the pixel pointer Pixels = 0 and the line pointer Lines = 0. The encoder data state is default in the end of blanking code state EAV. When START_ENCODING = 1 and LINE_1ST_START and START_PIXEL are detected to be pulled high, the pixel pointer Pixels and the line pointer are set to 1, and jump to Step 2; Step 2: The encoder is in the WORK state. When the pixel pointer Pixels < 1728, it continuously increments by 1 at the falling edge of the encoder clock pclk. In the EAV state, when (Pixels <= 4), the preambles: 8’hff, 8’h00, 8’h00, EAVx are generated respectively. When the pixel pointer Pixels > 4, jump to Step 3; Step 3: The encoder enters the line blanking area. When the pixel pointer satisfies 5 <= Pixels <= 283, it generates the padding code 8'h10 when the value of the Pixels pointer is odd and generates the padding code 8'h80 when the value of the Pixels pointer is even. When the pixel pointer satisfies Pixels >= 284, it jumps to step 4. Step 4: The encoder enters the SAV state and, based on the number of lines currently encoded, enters the even field blanking start SAV1, even field data start SAV2, odd field blanking start SAV4, and odd field data start SAV5 states respectively. Similar to step 2, it generates preambles: 8'hff, 8'h00, 8'h00, and SAVx. When the pixel indicator Pixels > 288, it jumps to step 5. Step 5: The encoder enters the data encoding DATA state, and according to the YCbCr422 encoding format, it sequentially enters the EVEN state, Y1 state, ODD state, and Y2 state. In particular, for certain rows and columns belonging to the background area, the output pixel data comes from the original video data stored in the BARM, and must be read 10 clock cycles in advance of the corresponding clock number. For the active row area belonging to the operation, the value can be assigned according to the specific scene marking, thus completing the selection of the data source. When the pixel pointer Pixels >= 1728 is detected, the data state transitions to EAV, the line index Lines is incremented by 1, the pixel pointer Pixels is set to 1, and the process jumps to step 2. When the current encoding line number is detected to be 625, the encoding of one frame of image has been completed. The line index Lines is cleared by 1, and the process jumps to step 2 again. This cycle continues, constantly refreshing the screen to produce a video effect.

[0055] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are merely preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A method for PAL video overlay based on FPGA, characterized in that, The method is executed by a hardware system including an FPGA and a CPLD, and includes the following steps: The CPLD is used to power up and configure the video decoder and video encoder respectively, based on the heartbeat handshake signal generated after the FPGA is started. The configuration of the video decoder includes: configuring its registers through IIC timing so that the line synchronization signal and the field synchronization signal only change in the EAV code; Receives and decodes analog video signals to generate digital video streams conforming to the ITU-R BT656 protocol; The digital video stream is parsed to extract the start-of-frame and start-of-line markers; The digital video stream is cached in the block memory of the FPGA as background video data; The video overlay algorithm state machine is run. Based on the frame start flag and the row start flag, the row and column pointers are updated in the subsequent encoding using an internal synchronization mode. In specific row and column regions, the background video data or overlay marker data is selected for output to generate the overlaid digital video stream. The superimposed digital video stream is encoded to output an analog video signal.

2. The method for PAL video overlay based on FPGA according to claim 1, characterized in that: Configure the video decoder, including the following steps: The IIC timing is generated by the CPLD, and its registers are configured to make it work in internal synchronization mode and conform to the BT656 protocol. By configuring the register, the line synchronization signal H and the parity field flag signal F are locked to change only in the EAV code.

3. The method for PAL video overlay based on FPGA according to claim 2, characterized in that: Configure the video decoder, including the specific registers and values: Configure register at address 0x03 to 09h; Configure registers at addresses 0x11 and 0x13 to 04h, and configure registers at addresses 0x12 and 0x14 to 00h; Configure registers at addresses 0xA0, 0x69, and 0x6D to 55h, 40h, and 90h respectively.

4. The method for PAL video overlay based on FPGA according to claim 1, characterized in that: Configure the video encoder, including the following steps: After the CPLD detects the square wave heartbeat signal from the FPGA, it generates IIC timing to configure its registers. Configure its working mode as PAL, BT656 standard, and internal synchronization mode; Configure the subcarrier frequency, color difference phase, U / V component gain, black level, and blanking level parameters.

5. The method for PAL video overlay based on FPGA according to claim 4, characterized in that: Configure the video encoder, including at least one of the following registers and values: Configure address 0x3A to 13h to set internal synchronization mode; Configure address 0x61 as 06h to set PAL output; Configure registers at addresses 0x5A, 0x5B, 0x5C, 0x5D, and 0x5E as 00h, 6Dh, 9Fh, 0Eh, and 1Ch respectively to control the phase, gain, and level of the color difference. Configure registers at addresses 0x63, 0x64, 0x65, and 0x66 as CBh, 8Ah, 09h, and 2Ah respectively to configure the PAL subcarrier frequency.

6. The method for PAL video overlay based on FPGA according to claim 1, characterized in that: The extraction of the frame start flag and line start flag includes the following steps: The frame start flag is triggered by the falling edge of the parity field flag F. After continuously detecting the three preambles of 8'hFF, 8'h00, and 8'h00 in the BT656 data stream, the 6th bit of the 4th byte is read to determine the change of the F signal; The line start flag is triggered by the falling edge of the line sync signal H. After continuously detecting the three preambles of 8'hFF, 8'h00, and 8'h00 in the BT656 data stream, the 4th bit of the 4th byte is read to determine the change of the H signal.

7. The method for PAL video overlay based on FPGA according to claim 1, characterized in that: The video overlay algorithm state machine includes the following states: IDLE state: Initialize the pixel pointer Pixels = 0 and the line pointer Lines = 0, wait for the encoder and decoder configuration completion signals GM7121_CFG_DONE and GM7150_CFG_DONE, and detect the frame start flag and the line start flag; WORK state: Control the pixel pointer Pixels to increment at the falling edge of the pixel clock pclk, and perform state jumps according to the values of Pixels and Lines; EAV state: When Pixels <= 4, output the end sync code, including 8'hFF, 8'h00, 8'h00 and the EAVx code representing the field information; VBLANKING state: When 4 < Pixels <= 284, alternately output the line blanking area filling code 8'h10 or 8'h80 according to the parity of Pixels; SAV state: When 284 < Pixels <= 288, output the start sync code, including 8'hFF, 8'h00, 8'h00 and the SAVx code representing the field information; DATA state: When 288 < Pixels <= 1728, enter the EVEN, Y1, ODD, and Y2 sub-states in sequence according to the YCbCr422 format, and complete the data source selection and output of the background video data and the overlay marker data.

8. The method for PAL video overlay based on FPGA according to claim 7, characterized in that: In the DATA state, the specific method of data source selection is as follows: For the rows and columns belonging to the background area, the output pixel data is sourced from the original video data read from the BRAM 10 clock cycles in advance; For the rows and columns belonging to the overlay marker area, the output pixel data is the preset marker data.

9. The method for PAL video overlay based on FPGA according to claim 1, characterized in that: The rules for updating and clearing the row and column pointers in the internal sync mode are as follows: The pixel pointer Pixels increments by 1 at the falling edge of each pixel clock pclk. When Pixels accumulates to 1728, it is automatically cleared, and the line pointer Lines is incremented by 1; When the line pointer Lines accumulates to 625 and the pixel pointer Pixels is 1728, the line pointer Lines is cleared.

10. The method for PAL video overlay based on FPGA according to claim 1, characterized in that: In the hardware system, the FPGA uses the XILINX XC7A100T chip, the video decoder uses the GM7150A chip, the video encoder uses the GM7121-D chip, and the CPLD uses the紫光PGC7KD series chip.

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