Instruction processing method, processor, chip and electronic device

Abstract

The present disclosure provides an instruction processing method, a processor, a chip and an electronic device. The instruction processing method comprises: obtaining an input instruction and reading the instruction content; splitting the instruction into a first micro-operation and a second micro-operation; wherein the first micro-operation comprises a first fixed-point operation micro-operation (AL UOP), and the second micro-operation comprises a second fixed-point operation micro-operation (AL UOP) and a memory access micro-operation (AG UOP); and setting at least one temporary architecture register (T0), which is used to pass data between the first micro-operation and the second micro-operation. Thus, by separating the conditional judgment and the address generation, and introducing the temporary register T0, the AL unit and the AG unit can work independently, reducing the dependency relationship between them and improving the execution efficiency of the instruction.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to an instruction processing method, processor, chip, and electronic device. Background Technology

[0002] CFCMOVcc is an extension of the legacy instruction set CMOVCC. The CFCMOVCC instruction modifies the value of the destination register based on the state of the flag register. If the condition succeeds, the contents of the 64-bit register or memory are moved into the destination register; if the condition fails, the value of the destination register is retained. In case of a failed condition, any exceptions encountered during memory access are ignored.

[0003] However, when executing the CFCMOVcc instruction, there is a dependency between the AL and AG units, which increases the instruction execution latency. The AL unit needs to wait for the AG unit to complete address generation and memory access operations, while the AG unit needs to wait for the AL unit to complete condition checks. This serial execution method reduces the execution efficiency of the instruction, especially when the conditions are met. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an instruction processing method, processor, chip, and electronic device to solve the problem of reduced instruction execution efficiency due to the interdependence between the AL unit and the AG unit.

[0005] To achieve the above objectives, the present disclosure provides the following technical solutions.

[0006] Firstly, this disclosure provides An instruction processing method, characterized by comprising the following steps: Obtain the input command and read the command content; The instruction is broken down into a first micro-operation and a second micro-operation; wherein the first micro-operation includes a first fixed-point arithmetic micro-operation (AL UOP), and the second micro-operation includes a second fixed-point arithmetic micro-operation (AL UOP) and a memory access micro-operation (AG UOP). At least one temporary architecture register (T0) is provided for transferring data between the first micro-operation and the second micro-operation.

[0007] In a second aspect, this disclosure provides a processor, characterized in that it includes: The instruction fetch unit is used to acquire input instructions and read instruction content; The decoding unit is used to decode and decompose the instruction to obtain a first micro-operation and a second micro-operation, wherein the first micro-operation includes a first fixed-point arithmetic micro-operation (AL UOP), and the second micro-operation includes a second fixed-point arithmetic micro-operation (AL UOP) and a memory access micro-operation (AG UOP). The renaming unit is used to modify the mapping relationship between the target architecture register and the physical register in the renaming table according to the operation information carried by the first micro-operation and the second micro-operation. A micro-operation unit is used to execute the first micro-operation and the second micro-operation, and sets at least one temporary architecture register (T0) for transferring data between the first micro-operation and the second micro-operation.

[0008] Thirdly, this disclosure provides a CFCMOVcc instruction processing method, characterized by comprising the following steps: Set at least one temporary architecture register (T0); Move the data stored in the second logic register (R10) to the at least one temporary architecture register (T0). If the conditions are met, the target memory access address is obtained based on the address data stored in the first logical register (R9) and the address data stored in the at least one temporary architecture register (T0), and the data obtained based on the target memory access address is written into the third logical register (R8).

[0009] Fourthly, this disclosure provides a processor, including: The instruction fetch unit is used to fetch CFCMOVcc instructions; The decoding unit is used to decode and decompose the CFCMOVcc instruction; Micro-operation unit for setting at least one temporary architecture register (T0). Move the data stored in the second logic register (R10) to the at least one temporary architecture register (T0). If the conditions are met, the target memory access address is obtained based on the address data stored in the first logical register (R9) and the address data stored in the at least one temporary architecture register (T0), and the data obtained based on the target memory access address is written into the third logical register (R8).

[0010] Fifthly, this disclosure provides a chip including the processor described in the embodiments of this disclosure.

[0011] Sixthly, this disclosure provides an electronic device including the chip described in the embodiments of this disclosure.

[0012] The instruction processing method, processor, chip, and electronic device provided in this disclosure acquire an input instruction and read its content; the instruction is split into a first micro-operation and a second micro-operation; wherein the first micro-operation includes a first fixed-point arithmetic micro-operation (AL UOP), and the second micro-operation includes a second fixed-point arithmetic micro-operation (AL UOP) and a memory access micro-operation (AG UOP); at least one temporary architecture register (T0) is set up to transfer data between the first micro-operation and the second micro-operation. Thus, by separating condition judgment and address generation and introducing the temporary register T0, the AL unit and AG unit can work independently, reducing their dependencies and improving instruction execution efficiency. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a processor architecture; Figure 2 A schematic diagram showing the CFCMOVcc micro-operation process divided into DOUBLE LOW and DOUBLE HIGH; Figure 3a A schematic diagram illustrating the operation of DOUBLE LOW during the RENAMING and STORAGE stages; Figure 3b This is a diagram illustrating the operation of DOUBLE LOW during the ISSUE phase. Figure 4a A schematic diagram illustrating the operation of DOUBLE HIGH during the RENAMING and STORAGE stages; Figure 4b A schematic diagram illustrating the operation of DOUBLE HIGH during the ISSUE phase; Figure 5 This is a schematic diagram of the architecture of a processor provided in one embodiment of the present disclosure. Detailed Implementation

[0015] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0016] The Central Processing Unit (CPU) is the core of a computer architecture, responsible for computation and control. Examples include various Complex Instruction Set Computing (CISC) processors, Reduced Instruction Set Computing (RISC) processors, and Very Long Instruction Word (VLIW) processors. Processors are typically configured for pipelined operations, including instruction fetch, decode, rename, execute, and commit phases. The CPU consists of multiple subsystems and modules that work together to achieve efficient data processing and instruction execution. (Appendix) Figure 1 A detailed description of a typical CPU framework diagram, such as Figure 1 As shown in the diagram, this framework diagram illustrates the main components inside the CPU and the interactions between them.

[0017] The decoding unit 101 is the front-end of the CPU, responsible for translating machine instructions fetched from memory into micro-operations (micro-instructions). These micro-operations are the smallest units of operation that the CPU can execute; they can be arithmetic operations, logical operations, data transfers, etc. The decoding unit breaks down instructions into micro-operations and issues them to the renaming unit. Figure 1 In the middle, the decoding unit supports 6 transmits, that is, 6 micro-operations can be transmitted to the renaming unit in each cycle.

[0018] The primary function of the renaming unit 102 is to reduce register conflicts during instruction execution and improve instruction-level parallelism. It maps architectural registers (logical registers) to physical registers by querying the renaming mapping table DispMap 103. This process, called register renaming, allows multiple instructions to use the same logical registers simultaneously without conflict, as each instruction has its own physical register. The renaming unit then sends the renamed micro-operations to the fixed-point instruction issue queue and the memory access instruction issue queue, respectively.

[0019] The issue queue is a structure in the CPU used to temporarily store micro-operations to be executed. Figure 1 There are two types of issue queues: fixed-point instruction issue queue 104 and memory access instruction issue queue 105. Fixed-point instruction issue queue 104 corresponds to the fixed-point arithmetic unit ALU 106, while memory access instruction issue queue 105 corresponds to the address generation unit AGU 107. These queues ensure that micro-operations are issued to the execution unit in the correct order.

[0020] The fixed-point arithmetic unit (ALU106) is the part of the CPU that performs arithmetic and logical operations. Figure 1There are four ALU106s in the array, which can execute micro-operations in parallel. When all source registers for a micro-operation in an ALU106 are ready, the micro-operation can be issued to the corresponding ALU106 for execution. After the ALU106 completes its execution, the result is written back to the physical register queue PRFARRAY109.

[0021] The address generation unit AGU107 is responsible for generating the addresses for memory access. Figure 1 There are three AGU107 units, which can generate addresses in parallel. When all source registers for a micro-operation in an AGU107 unit are ready, the micro-operation can be issued to the corresponding AGU107 for execution. The address generated by the AGU107 is then sent to the memory access unit LSDC108 for memory access.

[0022] The memory access unit LSDC108 is the part of the CPU responsible for memory access. It receives the address from the AGU, accesses memory, and writes the acquired data (LoadData) back to the physical register queue PRFARRAY109. The memory access unit can handle multiple memory access requests simultaneously, improving memory access efficiency.

[0023] The physical register queue PRFARRAY109 is a set of physical registers used to store the execution results of ALU106 and AGU107. The flag register queue FLAGARRAY110 is used to store condition flags, such as the carry flag (CF) and the zero flag (ZF), which are crucial for operations such as conditional branching and data comparison.

[0024] The decoding unit breaks down instructions into micro-operations and maps logical registers to physical registers through a renaming unit and a renaming mapping table to reduce register conflicts. Fixed-point instruction issue queues and memory access instruction issue queues temporarily store the micro-operations to be executed and issue them to the ALU and AGU for execution, respectively. The ALU performs arithmetic and logical operations, while the AGU generates memory access addresses. The LSDC (Low-Speed ​​Memory Address Coordination Unit) handles memory access and writes data back to the physical register queue. Throughout this process, the physical register queue and flag register queue play crucial roles in storing and transferring data. This CPU design improves instruction-level parallelism and processor performance through register renaming, instruction issue queues, and parallel execution units. It allows multiple instructions to execute simultaneously without interference, thereby improving program execution efficiency. Furthermore, by breaking instructions down into micro-operations, the CPU can more flexibly schedule instruction execution order, optimize resource utilization, reduce latency, and further enhance performance. This design is the cornerstone of modern high-performance processors, providing higher execution efficiency and better scalability while maintaining instruction set architecture compatibility.

[0025] The CFCMOVcc instruction is a conditional move instruction in the x86 architecture. It determines whether to perform a data transfer operation based on specific condition flags (such as CF and ZF). This instruction can improve program execution efficiency in certain situations because it allows unnecessary memory accesses to be avoided when the conditions are not met.

[0026] Taking CFCMOVcc R8, [R9+R10] as an example, the meaning of this instruction is: if CF (carry flag) or ZF (zero flag) is 1, then the data at memory address [R9+R10] will be transferred to register R8; if neither CF nor ZF is 1, then no memory access will be performed, and the original data in register R8 will be retained.

[0027] Before renaming, the register mapping might be R8->P8, R9->P9, R10->P10, CF->P11, ZF->P12. After renaming, R8 might be mapped to P13. A key feature of the CFCMOVcc instruction is that when the condition is not met (i.e., neither CF nor ZF is 1), if an exception is encountered during memory access, these exceptions do not need to be handled. This differs from the CMOVcc instruction, where exceptions encountered during memory access are handled even if the condition is not met.

[0028] The CFCMOVcc instruction is designed to reduce memory accesses when conditions are not met, thus avoiding unnecessary memory exception handling, which can improve program execution efficiency in some cases. For example, if the program knows that memory access is unnecessary when conditions are not met, using the CFCMOVcc instruction can avoid exceptions caused by accessing invalid memory addresses.

[0029] During the execution of the CFCMOVcc instruction, a dependency exists between the Arithmetic Logic Unit (ALU) and the Address Generation Unit (AGU). This dependency stems from the instruction's reliance on the values ​​of condition flags (such as CF and ZF), which need to be calculated and updated by the ALU. Simultaneously, memory address generation is handled by the AGU. The CFCMOVcc instruction determines whether to perform a memory access based on the values ​​of the condition flags (CF or ZF). These flags are typically set by the ALU after performing arithmetic or logical operations. Therefore, the AGU must wait for the ALU to calculate and update these condition flags before generating the memory address. This dependency ensures that the memory access operation is only performed when the conditions are met. In the CFCMOVcc instruction, the value of the destination register (such as R8) may depend on the result of the memory access. If the conditions are met, the memory address generated by the AGU is used to access memory, and the result is written to the destination register. If the conditions are not met, the original value of the destination register is retained. This data dependency requires the ALU to wait for the AGU to complete the memory access before performing any data transfer. When the condition is not met, the CFCMOVcc instruction will not perform a memory access. Therefore, in this case, even if an exception is encountered during the memory access, no exception handling is required. However, if the traditional CMOVcc instruction is used, potential memory access exceptions need to be handled even if the condition is not met. This difference reduces the exception handling overhead of the CFCMOVcc instruction when the condition is not met.

[0030] Combined with appendix Figure 2 In the first embodiment of this disclosure, CFCMOVcc is split according to the double instruction, that is, split into two micro-operations, DOUBLELOW and DOUBLE HIGH, occupying two dispatch slots. DOUBLE LOW contains only the fixed-point arithmetic micro-operation ALUOP, called CMERGEBET0R10. DOUBLE HIGH contains one fixed-point arithmetic micro-operation ALUOP and a memory access micro-operation AGUOP, called CFCMOVBE R8, [R9+T0], and a temporary architecture register T0 is introduced at the same time.

[0031] Step S201, DOUBLE LOW: CMERGEBE T0 R10, mainly performs two functions: Condition flag remapping: Since CF and ZF may be stored in different physical registers, the CMERGEBE operation remaps these two condition flags to the same physical register. This is done to simplify subsequent condition evaluation.

[0032] Address reconstruction and condition judgment involve moving the lower 57 bits of the memory access operand R10 to the lower 57 bits of the temporary register T0. Simultaneously, the values ​​of CF and ZF are used to determine if the condition is met. If the condition is met (i.e., at least one of CF or ZF is 1), then bit 63 (the most significant bit) of T0 is set to 1, indicating that the condition is satisfied.

[0033] Step S202, DOUBLE HIGH: CFCMOVBE R8, [R9 +T0], divided into 1 AG and AL micro-operation: The AG micro-operation changes the original address, which was obtained by adding the lower 57 bits of R9 and R10, to an address obtained by adding the lower 57 bits of R9 and T0. Simultaneously, bit 63 of T0 is sent as a mask bit to LSDC (Load / StoreDataCache). If the mask bit is 1, it indicates that the condition is met; if an exception is encountered during memory access, it needs to be handled. If the mask bit is 0, it indicates that the condition is not met; even if an exception is encountered during memory access, it does not need to be handled.

[0034] The AL micro-operation is equivalent to executing the CMOVBE R8, DESTP1 operation. That is, if the condition is met, the data read from register DESTP1 is written to the target register R8. This operation depends on the result of the AG micro-operation and must wait for the memory access operation to complete before execution. Finally, if the condition is met, the value of register DESTP1 is written to the renamed target register corresponding to R8.

[0035] The following is combined Figure 3a and Figure 3b A detailed description of DOUBLE LOW: CMERGEBE T0 R10 is provided.

[0036] Appendix Figure 3aThe CMERGEBE command format is given as follows: The opcode OPCODE is MERGEBE, indicating a transfer operation. The DESTFLAG flag stores the values ​​of CF and ZF, where CF is the carry flag and ZF is the zero flag. The FLAG_C flag, or CarryFlag, indicates whether a carry occurred in the previous arithmetic operation. The FLAG_D flag, or ZeroFlag, indicates whether the result of the previous operation was zero. RegNumA is the register number of logical register R10, indicating that this micro-operation uses logical register R10 as the source register, and the value of R10 will be used for subsequent address calculations. RegNumB and RegNumC are the register numbers B and C, respectively; NULL indicates that registers B and C are not used in this micro-operation. DestNum is the destination register number T0, indicating that the target of this micro-operation is temporary register T0. T0 is an architectural temporary register, invisible to software, used only internally by the hardware for data transfer.

[0037] Combination Figure 3a It can be seen that during the renaming stages RENAMING301 and STORAGE302, the values ​​of the carry flag CarryFlag and the zero flag ZeroFlag are stored in the flag register queue FLAGARRAY, the register numbers storing the carry flag CarryFlag and the zero flag ZeroFlag are written to the fixed-point arithmetic second source operand AlBOP and the fixed-point arithmetic third source operand AlCOP, and the fixed-point arithmetic second source operand AlBOP and the fixed-point arithmetic third source operand AlCOP are stored in the fixed-point arithmetic instruction issue queue ALI SSUEQ.

[0038] Map the temporary architecture register T0 to the first physical register DESTP0 via PRNFREELIST, determine the number of the first physical register DESTP0, store the first physical register DESTP0 into the fixed-point arithmetic instruction issue queue A1 SSUEQ, and update the remapping table.

[0039] Find the second physical register number corresponding to the number logic register R10 by looking up the mapping table, write the second physical register number into the first source operand AlAOP of the fixed-point arithmetic, and store the first source operand AlAOP of the fixed-point arithmetic into the fixed-point arithmetic instruction issue queue AlI SSUEQ.

[0040] Combination Figure 3bIt can be seen that during the renaming ISSUE303 stage, the values ​​of the carry flag CarryFlag and the zero flag ZeroFlag are read according to the first source operand AlBOP and the third source operand AlCOP of the fixed-point operation. The values ​​of the carry flag CarryFlag and the zero flag ZeroFlag are combined to obtain the combined flag (CF&ZF). The combined flag is stored in the physical register FLAGP0 of the flag register queue FLAGP0.

[0041] For example, the values ​​of CF and ZF (CF=0, ZF=1) are read from FLAGP0 using AlBOP and AlCOP respectively, and then merged into a single physical register FLAGP0. The merged value can be represented as: The lower 57 bits (bits 0-56) of the address data stored in the number logic register R10 are obtained from the first source operand AlAOP of the fixed-point arithmetic operation. These lower 57 bits are then moved to the lower 57 bits (bits 0-56) of the first physical register DESTP0. The value of the 63rd bit of the first physical register DESTP0 is determined by the combined flag CF&ZF obtained from the values ​​of the carry flag CarryFlag and the zero flag ZeroFlag.

[0042] To better illustrate CMERGEBE TO R10, a specific embodiment is given below.

[0043] The register mappings before the renaming are as follows: R8->P8, R9->P9, R10->P10, CF->P11, ZF->P12; After renaming: R8->P13, T0->P14 (assuming that the physical register mapped to T0 is P14).

[0044] Assuming the current values ​​of CF and ZF are CF=0 and ZF=1 respectively; the instruction CMERGEBE is placed in the emit slot, and the values ​​of CF and ZF are mapped to the corresponding FLAGARRAY register numbers (P11 and P12) through AIBOP and AICOP, and stored in ALI SSUEQ.

[0045] T0, as the target register, is an architectural temporary register, invisible to software but visible to hardware. The free physical register number DESTP0 (let's assume it's P14) is located, and the remapping table T0->P14 is updated. R10, as the source operand, has its corresponding physical register number P10 stored in the issue slot via AICOP.

[0046] When all source operands are ready, the CMERGEBE micro-operation is issued from ALI SSUEQ to the execution unit. The values ​​of CF and ZF (CF=0, ZF=1) are read from FLAGARRAY via AlBOP and AlCOP respectively, and merged into a single physical register FLAGP0. The merged value can be represented as follows: if CF=1, ZF=0, then FLAGP0=0b01; if CF=0, ZF=1, then FLAGP0=0b10; if CF=1, ZF=1, then FLAGP0=0b11; if CF=0, ZF=0, then FLAGP0=0b00. In this example, CF=0, ZF=1, so FLAGP0=0b10.

[0047] The condition is determined based on the value of FLAGP0: if FLAGP0 = 0b01, 0b10, or 0b11, the condition is met (ConditionMeet), and ResBus

[63] is set to 1. If FLAGP0 = 0b00, the condition is not met (ConditionNotMeet), and ResBus

[63] is set to 0. In this example, FLAGP0 = 0b10, the condition is met, so ResBus

[63] = 1.

[0048] The value of R10 (assuming the value of R10 is 0x1234567890ABCDEF) is read from the physical register file PRFARRAY using AlAOP, and its lower 57 bits are placed into ResBus[56:0]. Therefore: ResBus[63:0]={CondMeet,6'b0,AOP[56:0]} ResBus[63:0]={1,6'b0,0x1234567890ABCDEF[56:0]} ResBus[63:0]={1,6'b0,0x1234567890ABCDEF[56:0]} Write ResBus[63:0] back to the physical register DESTP0 (i.e. P14) corresponding to T0. The value of P14 is: P14

[63] =1 (indicating that the condition is met) and P14[56:0]=0x1234567890ABCDEF[56:0] (the lower 57 bits of R10).

[0049] The following is combined Figure 4a and Figure 4b Detailed explanation of DOUBLE HIGH: CFCMOVBE R8, [R9 +T0].

[0050] Appendix Figure 4aThe CFCMOVBE command format is given, with the opcode MERGEBE, indicating a merge operation used to process conditional move instructions. The DESTFLAG field is NULL, meaning this micro-operation does not directly modify any condition flags. The FLAG_C and FLAG_D fields are NULL and the combination flags CF & ZF, respectively, used for conditional judgment. RegNumA is the R8 register number, the target register for the conditional move instruction. RegNumB is the R9 register number, the base address register involved in address calculation. RegNumC is the T0 temporary register number, a temporary architecture register introduced in the DOUBLE LOW stage to store the reconstructed address portion. DestNum is the R8 register number, the register where the final data will be written.

[0051] Combination Figure 4a It can be seen that during the renaming (RENAMING401) and storage (STORAGE402) stages, the first logical register R9 (RegNumB) and the temporary architecture register T0 (RegNumC) are written with the second source operand (AgBOP) and the third source operand (AgCOP) for address operations, respectively. These operands are then stored in the address operation instruction issue queue (AgISSUEQ). The temporary architecture register T0 contains the combined flag CF&ZF obtained based on the values ​​of the carry flag (CarryFlag) and the zero flag (ZeroFlag).

[0052] The first logic register R8, RegNumA, is written to the first source operand AlAOP for fixed-point arithmetic; the first source operand AlAOP for address arithmetic is then stored in the fixed-point arithmetic instruction issue queue AlI SSUEQ. The register number FLAG_D of the combination identifier (CF&ZF) is written to the third source operand AlCOP for fixed-point arithmetic; the third source operand AlCOP for address arithmetic is then stored in the fixed-point arithmetic instruction issue queue AlI SSUEQ.

[0053] The target register R8, register number DestNum, is mapped to the second source operand AlBOP and the second physical register DESTP1 via PRNFREELIST. The second source operand AlBOP and the second physical register DESTP1 are then stored in the fixed-point instruction issue queue A1 SSUEQ.

[0054] Combination Figure 4bAs can be seen, in the ISSUE403 stage, the source operand A stored in the physical register queue PRFARRAY and the source operand B stored in the first physical register DESTP0 are obtained based on the second source operand AgBOP and the third source operand AgCOP of the address operation; the lower 57 bits of source operand A and source operand B are added together to obtain the address data, and the address data is transferred to the memory access unit LSDC.

[0055] The memory access unit LSDC reads the 63rd bit (maskbit) of the source operand B stored in the first physical register DESTP0. If the 63rd bit (maskbit) of the source operand B is 1, the memory access unit LSDC reports an exception normally; if the 63rd bit (maskbit) of the source operand B is 0, the memory access unit LSDC ignores the exception and does not report it. The memory access unit LSDC obtains the data according to the address data and writes it into the second physical register DESTP1.

[0056] Based on the combined identifier CF&ZF read from the third source operand AlCOP of the fixed-point operation, determine whether the condition is met; When the condition is met, the source operand B stored in the second physical register DESTP1, indicated by the second source operand AlBOP of the fixed-point operation, is written back to the second physical register DESTP1; if the condition is not met, the source operand A stored in the register in the physical register queue PRFARRAY, indicated by the first source operand AlAOP of the fixed-point operation, is written to the second physical register DESTP1.

[0057] During the DOUBLE LOW phase, the CF and ZF flags have been merged into the temporary register T0. The 63rd bit (maskbit) of T0 indicates whether the condition is met (at least one of CF or ZF is 1); R9, R10 and T0 have been mapped to physical registers P9, P10 and P14.

[0058] The renaming and storage phase maps logical register R9 (base register) and temporary architecture register T0 (index register) to physical registers P9 and P14. R8 (destination register) is mapped to an empty physical register, let's say P15 (DESTP1).

[0059] Store the address generation unit AGU operands P9 and P14 into the address arithmetic instruction issue queue AgISSUEQ. Store the arithmetic logic unit ALU operand P8 (the original value of R8) and the combination identifier CF&ZF stored in FLAGP0 into the fixed-point arithmetic instruction issue queue AlI SSUEQ. Store DESTP1 into AlI SSUEQ as the final data write location.

[0060] During the execution phase, the AGU uses the values ​​of P9 and P14 to calculate the memory address and sends the address to the memory access unit LSDC. LSDC reads data from memory according to the address and stores it in DESTP1 (P15). LSDC checks bit 63 (maskbit) of P14; if it is 1, an exception is reported normally; if it is 0, the exception is ignored.

[0061] During the condition evaluation and write-back phase, the ALU determines whether the condition is met based on the CF & ZF values ​​in FLAGP0. If the condition is met (bit 63 of P14 is 1), the data in DESTP1 (P15) is written back to the new physical register P15 of R8. If the condition is not met (bit 63 of P14 is 0), the original value of R8 (stored in P8) is written back to P15.

[0062] In this way, the CFCMOVBE instruction determines whether to move memory data into the destination register based on the value of the condition flags during the DOUBLE HIGH stage, while avoiding unnecessary memory accesses and exception handling. This design improves instruction execution efficiency and processor performance.

[0063] The second aspect of this embodiment provides a processor, which specifically includes... The decoding unit is responsible for decoding the CFCMOVcc instruction into two micro-operations (UOPs), namely CMERGEcc (DOUBLELOW) and CFCMOVBE (DOUBLE HIGH). The decoding unit needs to identify the instruction and generate the corresponding opcode and operands.

[0064] The renaming unit, containing the renaming mapping table DispMap, is responsible for mapping logical registers to physical registers. During the DOUBLE LOW phase, CF and ZF are mapped to the same physical register (e.g., FLAGP0). During the DOUBLE HIGH phase, R8, R9, and T0 are mapped to their respective physical registers (e.g., P13, P9, and P14).

[0065] The issue queue consists of a fixed-point instruction issue queue and a memory access instruction issue queue. Micro-operations in the DOUBLE LOW phase are sent to the fixed-point instruction issue queue. Micro-operations in the DOUBLE HIGH phase are divided into ALUOP and AGUOP, and sent to the fixed-point instruction issue queue and the memory access instruction issue queue, respectively.

[0066] The fixed-point arithmetic unit (ALU) performs arithmetic and logical operations. In the DOUBLE LOW phase, the ALU merges the values ​​of CF and ZF into FLAGP0. In the DOUBLE HIGH phase, the ALU performs the CMOVBE operation, determining whether to move data from DESTP1 to the destination register P13 based on the condition flag values.

[0067] The address generation unit is responsible for generating memory access addresses. During the DOUBLE HIGH phase, the AGU uses the values ​​of R9 and T0 to calculate the memory address.

[0068] The physical register file stores the values ​​of the physical registers. During the DOUBLE LOW phase, PRFArray provides the value of R10 to the ALU. During the DOUBLE HIGH phase, PRFArray provides the values ​​of R9 and T0 to the AGU and stores the ALU's output.

[0069] The flag register file stores condition flags. During the DOUBLE LOW phase, FLAGArray provides the values ​​of CF and ZF to the ALU and receives the merged value FLAGP0.

[0070] The memory access unit is responsible for memory access. During the DOUBLE HIGH phase, LSDC uses the address generated by AGU to read data from memory and determines whether to handle exceptions based on the maskbit (bit 63 of T0).

[0071] The Physical Register Free List tracks the free status of physical registers. During the DOUBLE LOW and DOUBLE HIGH phases, the PRNFREELIST provides free physical registers to the renaming unit.

[0072] Figure 5 This is a schematic diagram of the architecture of a processor provided in an embodiment of the present disclosure. The processor includes: an instruction fetch unit 501, a decoding unit 502, a renaming unit 503, and a micro-operation unit 504.

[0073] Instruction fetch unit 501 is used to fetch input instructions; Decoding unit 502 is used to decode and decompose the input instruction to obtain a first micro-operation and a second micro-operation. The first micro-operation includes a first fixed-point arithmetic micro-operation ALUOP, and the second micro-operation includes a second fixed-point arithmetic micro-operation ALUOP and a memory access micro-operation AGUOP. The renaming unit 503 is used to modify the mapping relationship between the target architecture register and the physical register in the renaming table according to the operation information carried by the first micro-operation and the second micro-operation. The micro-operation unit 504 is used to execute the first micro-operation and the second micro-operation, and sets at least one temporary architecture register T0, which is used to transfer data between the first micro-operation and the second micro-operation.

[0074] The processor further includes: a flag register queue FLAGARRAY, used to store a combined flag CF&ZF of the carry flag and the zero flag; and to determine whether exception handling is required when an exception is encountered during memory access based on the combined flag CF&ZF.

[0075] The processor further includes: a first physical register DESTP0, used to store data in a temporary architecture register T0, wherein the 63rd bit of the data stored in the temporary architecture register T0 is a combination identifier CF&ZF, and bits 0 to 62 are bits 0 to 62 of the data stored in the second logic register R10.

[0076] The processor further includes a second physical register number DESTP0, used to store data obtained from a first target memory address, which is obtained by adding bits 0 to 56 of the data stored in the first logical register R9 and the first physical register DESTP0.

[0077] The micro-operation unit is further used to: determine whether the conditions are met based on the combined identifiers CF and ZF; When the condition is met, the data stored in the second physical register DESTP1, which is pointed to by the second source operand AlBOP of the fixed-point operation, is written back to the second physical register DESTP1. Otherwise, the data stored in the registers in the physical register queue PRFARRAY, which is referred to by the first source operand AlAOP in the fixed-point operation, is written to the second physical register DESTP1.

[0078] This design enables the processor to efficiently execute CFCMOVcc instructions while reducing the dependency between AL and AG, thus improving instruction execution efficiency and overall processor performance. This processor architecture allows for the avoidance of unnecessary memory accesses and exception handling when conditions are not met, thereby optimizing the overall instruction execution flow.

[0079] It should be noted that, Figure 5 The instruction fetch unit 501, decode unit 502, rename unit 503, and micro-operation unit 504 shown can be logic circuit units in a processor. Furthermore, it is understood that... Figure 5The processor is only shown as an example of some optional structures. The processor may also include other possible devices, such as other circuit devices that are not essential for understanding the contents of this disclosure. Since other circuit devices are not essential for understanding the contents of this disclosure, they will not be described in detail here.

[0080] The specific embodiments disclosed herein, by splitting the CFCMOVcc instruction into two micro-operations, DOUBLE LOW and DOUBLE HIGH, allow the processor to manage the instruction execution flow more efficiently. This splitting allows the processor to perform condition checks in the DOUBLE LOW stage and then execute possible memory accesses in the DOUBLE HIGH stage, thereby reducing invalid memory accesses caused by unmet conditions.

[0081] In traditional CMOVcc instruction execution, there may be a strong dependency between the AL unit and the AG unit, because the AL unit needs to wait for the address generated by the AG unit to decide whether to perform data movement. By introducing a temporary register T0, the processor can complete the condition judgment and address reconstruction in the DOUBLE LOW stage, thereby reducing the dependency between the AL and AG units.

[0082] During the DOUBLE HIGH phase, the processor can determine whether to handle exceptions encountered during memory access based on the 63rd bit (maskbit) of T0. If the condition is not met (maskbit is 0), the processor can choose to ignore these exceptions even if they are encountered during memory access, thus avoiding unnecessary exception handling overhead.

[0083] Because the DOUBLE LOW and DOUBLE HIGH phases can be executed relatively independently, the processor can schedule instructions more flexibly, improving instruction-level parallelism. This parallelism allows the processor to prepare and issue subsequent instructions while executing the current instruction, thereby improving overall execution efficiency.

[0084] By introducing a temporary register T0 and splitting the instruction execution phase, processor design becomes more modular, facilitating future expansion and optimization. For example, processors can more easily add more execution units or improve existing ones to adapt to changing computational needs.

[0085] By reducing invalid memory accesses and exception handling, processors can reduce unnecessary power consumption, thereby improving energy efficiency. This is especially important for mobile devices and energy-constrained environments.

[0086] Because the processor can make conditional judgments in advance during the DOUBLE LOW stage, the program's execution path becomes more predictable, which helps improve the determinism of program execution, especially in real-time systems.

[0087] In summary, the CFCMOVcc instruction decomposition method significantly improves processor execution efficiency, scalability, and energy efficiency by optimizing instruction execution flow, reducing dependencies between execution units, optimizing exception handling, and enhancing instruction-level parallelism. It also enhances the determinism of program execution. These technical effects make this method of significant application value in modern processor design.

[0088] As another optional implementation of the content disclosed in this disclosure, this disclosure provides a chip that includes the processor provided in any embodiment of this disclosure.

[0089] As another optional implementation of the content disclosed in this disclosure, this disclosure provides an electronic device that includes the chip provided in any embodiment of this disclosure. This electronic device can be a terminal device or a cloud server device.

[0090] The foregoing describes multiple embodiment schemes provided by the present disclosure. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and made public by the present disclosure.

[0091] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

[0092] Various changes, substitutions, and modifications can be made to the technology herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0093] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0094] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. An instruction processing method, characterized in that, Includes the following steps: Obtain the input command and read the command content; The instruction is broken down into a first micro-operation and a second micro-operation; wherein the first micro-operation includes a first fixed-point arithmetic micro-operation, and the second micro-operation includes a second fixed-point arithmetic micro-operation and a memory access micro-operation; Set at least one temporary architecture register to store the flag bits and address data; The first micro-operation stores the storage identifier bit and address data into the temporary architecture register, and the second micro-operation obtains the storage identifier bit and address data from the temporary architecture register.

2. The instruction processing method according to claim 1, characterized in that, The temporary architecture register stores a combination of carry and zero flags.

3. The instruction processing method according to claim 1, characterized in that, The instruction is the CFCMOVcc instruction.

4. The instruction processing method according to claim 1, characterized in that, The first fixed-point arithmetic micro-operation includes: Write the logical register numbers storing the carry and zero flags into the second and third source operands of the fixed-point arithmetic.

5. The instruction processing method according to claim 4, characterized in that, The first fixed-point arithmetic micro-operation includes: The temporary architecture register is mapped to the first physical register, and the remapping table is updated.

6. The instruction processing method according to claim 5, characterized in that, The first fixed-point arithmetic micro-operation includes: The physical register number mapped by the second logic register is written into the first source operand of the fixed-point arithmetic.

7. The instruction processing method according to claim 6, characterized in that, The first fixed-point arithmetic micro-operation includes: Read the values ​​of the carry flag and the zero flag based on the second source operand and the third source operand of the fixed-point arithmetic; The values ​​of the carry flag and the zero flag are combined to obtain a combined flag; the combined flag is stored in the third physical register.

8. The instruction processing method according to claim 7, characterized in that, The first fixed-point arithmetic micro-operation includes: The first source operand of the fixed-point operation is used to obtain the 0-56 bits of the data stored in the second logical register, and the 0-56 bits of the data stored in the second logical register are written into the 0-56 bits of the first physical register. The value of the 63rd bit of the first physical register is determined based on the combined identifier.

9. The instruction processing method according to claim 8, characterized in that, The memory access micro-operations include: The first logical register number and the temporary architecture register number are written into the second source operand and the third source operand of the address operation; The temporary architecture register contains the combined identifier.

10. The instruction processing method according to claim 9, characterized in that, The memory access micro-operations include: The data stored in the physical register queue and the data stored in the first physical register are read according to the second source operand and the third source operand of the address operation, respectively. The first target memory access address is obtained by adding the 0th to 56th bits of the data stored in the physical register queue and the data stored in the first physical register.

11. The instruction processing method according to claim 10, characterized in that, The memory access micro-operations include: The memory access unit reads the 63rd bit of the data stored in the first physical register; If the 63rd bit of the data is 1, the memory access unit will normally report an error. If the 63rd bit of the data is 0, the memory access unit ignores the exception and does not report it. The memory access unit writes the data obtained from the first target memory access address into the second physical register.

12. The instruction processing method according to claim 11, characterized in that, The second fixed-point arithmetic micro-operation includes: The first logic register number is written into the first source operand of the fixed-point arithmetic; The second physical register number is written into the second source operand of the fixed-point operation.

13. The instruction processing method according to claim 12, characterized in that, The second fixed-point arithmetic micro-operation includes: The combined identifier is written to the third physical register through the third source operand of the fixed-point operation.

14. The instruction processing method according to claim 13, characterized in that, The second fixed-point arithmetic micro-operation includes: Based on the combined identifier read from the third source operand of the fixed-point operation, determine whether the condition is met; When the condition is met, the data stored in the second physical register, which is represented by the second source operand of the fixed-point operation, is written back to the second physical register; Otherwise, the data stored in the register in the physical register queue referred to by the first source operand of the fixed-point operation is written to the second physical register.

15. A processor, characterized in that, include: The instruction fetch unit is used to acquire input instructions and read instruction content; The decoding unit is used to decode and decompose the instruction to obtain a first micro-operation and a second micro-operation, wherein the first micro-operation includes a first fixed-point arithmetic micro-operation, and the second micro-operation includes a second fixed-point arithmetic micro-operation and a memory access micro-operation. A micro-operation unit is used to execute the first micro-operation and the second micro-operation, and sets at least one temporary architecture register, which is used to transfer flag bits and address data between the first micro-operation and the second micro-operation.

16. The processor according to claim 15, characterized in that, The processor further includes: The flag register queue is used to store a combined flag of carry flag and zero flag; the combined flag is used to determine whether exception handling is required when an exception is encountered during memory access.

17. The processor according to claim 16, characterized in that, The processor further includes: The first physical register is used to store the data of the temporary architecture register. The 63rd bit of the data stored in the temporary architecture register is a combination identifier, and bits 0 to 62 are bits 0 to 62 of the data stored in the second logical register.

18. The processor according to claim 17, characterized in that, The processor further includes: The second physical register is used to store the data obtained from the first target memory access address, which is obtained by adding bits 0 to 56 of the data stored in the first logical register and the first physical register.

19. The processor according to claim 18, characterized in that, The micro-operation unit is further used for: Determine whether the conditions are met based on the combined identifier; When the condition is met, the data stored in the second physical register, which is represented by the second source operand of the fixed-point operation, is written back to the second physical register; Otherwise, the data stored in the registers in the physical register queue referred to by the first source operand of the fixed-point operation is written to the second physical register.

20. The processor according to claim 15, characterized in that, The processor further includes: The renaming unit is used to modify the mapping relationship between the target architecture register and the physical register in the renaming table according to the operation information carried by the first micro-operation and the second micro-operation.

21. A method for processing CFCMOVcc instructions, characterized in that, Includes the following steps: The CFCMOVcc instruction is decoded and decomposed; Set at least one temporary architecture register to store the flag bits and address data of the CFCMOVcc instruction; Move the data stored in the second logical register to the at least one temporary architecture register; If the conditions are met, the target memory access address is obtained based on the storage address data of the first logical register and the storage address data of the at least one temporary architecture register, and the data obtained based on the target memory access address is written into the third logical register.

22. The CFCMOVcc instruction processing method according to claim 21, characterized in that, Also includes: If the conditions are not met, the data stored in the third logic register remains unchanged.

23. A processor, characterized in that, include: The instruction fetch unit is used to fetch CFCMOVcc instructions; The decoding unit is used to decode and decompose the CFCMOVcc instruction; The micro-operation unit is used to set at least one temporary architecture register to store the flag bits and address data of the CFCMOVcc instruction; move the address data stored in the second logic register to the at least one temporary architecture register; if the conditions are met, obtain the target memory access address according to the address data stored in the first logic register and the address data stored in the at least one temporary architecture register, and write the data obtained according to the target memory access address into the third logic register.

24. The processor according to claim 23, characterized in that, The micro-operation unit is also used to keep the data stored in the third logic register unchanged if the condition is not met.

25. A chip, characterized in that, Includes the processor described in any one of claims 15-18, 23 and 24.

26. An electronic device, characterized in that, Includes the chip described in claim 25.

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