Parallel computing simulation acceleration method and device, electronic equipment and storage medium

Abstract

The application provides a parallel computing simulation acceleration method and device, electronic equipment and storage medium, relates to the chip design verification technical field, and includes the following steps: decomposing a current simulation task into multiple simulation processes; the multiple simulation processes include at least one host simulation process and at least one board card simulation process; each simulation process is independently run; a communication connection based on a network socket is established between each simulation process; and simulation data and control instructions are transmitted between each simulation process through the communication connection. The method and device provided by the application decompose the simulation task into multiple independently running simulation processes, and establish a communication connection between each simulation process through a network socket; true parallel computing simulation is realized, the simulation efficiency is greatly improved, and the simulation time is shortened; since each simulation process is independently run, the number of board cards can be flexibly simulated to increase or decrease, and the scalability and robustness of parallel computing simulation are enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design verification, and in particular to a parallel computing simulation acceleration method and device, an electronic device and a storage medium. BACKGROUND

[0002] In related technologies, when performing Electronic Design Automation (EDA) simulation on parallel computing of multiple computing cards, the actual physical connection mode between the multiple computing cards is simulated, the computing cards are interconnected, and all the computing cards are not independently running multiple simulation tasks, but are uniformly scheduled and managed under the same large simulation program. This simulation method is slow, inefficient, and has poor flexibility.

[0003] Therefore, how to improve the efficiency of parallel computing simulation of multiple computing cards has become a technical problem to be solved in the industry. SUMMARY

[0004] The present application provides a parallel computing simulation acceleration method and device, an electronic device and a storage medium, which are used to solve the technical problem of how to improve the efficiency of parallel computing simulation of multiple computing cards.

[0005] The present application provides a parallel computing simulation acceleration method, which comprises:

[0006] decomposing a current simulation task into multiple simulation processes; the multiple simulation processes comprise at least one host simulation process and at least one board card simulation process; each simulation process is independently run;

[0007] establishing a network socket-based communication connection between each simulation process;

[0008] transmitting simulation data and control instructions between each simulation process through the communication connection.

[0009] In some embodiments, the method further comprises:

[0010] configuring a verification intellectual property core inside each simulation process;

[0011] the verification intellectual property core is used to convert a data packet received through the communication connection into a protocol operation of a target hardware interface, and / or convert the protocol operation of the target hardware interface into a data packet for transmission through the communication connection;

[0012] the target hardware interface is a hardware interface configured by the host and / or a hardware interface configured by the board card.

[0013] In some embodiments, the protocol operation of the target hardware interface comprises a high-speed serial computer expansion bus protocol operation.

[0014] In some embodiments, each simulation process runs independently in the same physical computing device.

[0015] In some embodiments, each simulation process runs independently in different physical computing devices; the physical computing devices are connected through a network.

[0016] In some embodiments, the method comprises:

[0017] detecting a network socket connection request sent by a current board card simulation process while each simulation process is running; the current board card simulation process is a newly added board card simulation process in the current simulation task;

[0018] In response to the network socket connection request, establishing a network socket-based communication connection with the current board card simulation process in the case of detecting the network socket connection request.

[0019] In some embodiments, the method comprises:

[0020] continuously detecting the network socket state corresponding to each board card simulation process while each simulation process is running;

[0021] In the case of detecting that the network socket corresponding to any board card simulation process is disconnected, releasing the system resources corresponding to the network socket corresponding to the any board card simulation process.

[0022] The application provides a parallel computing simulation acceleration device, comprising:

[0023] a decomposition module, configured to decompose a current simulation task into a plurality of simulation processes; the plurality of simulation processes comprise at least one host simulation process and at least one board card simulation process; each simulation process runs independently;

[0024] a communication module, configured to establish a network socket-based communication connection between each simulation process;

[0025] a simulation module, configured to transmit simulation data and control instructions between each simulation process through the communication connection.

[0026] The application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor; when the processor executes the computer program, the parallel computing simulation acceleration method is realized.

[0027] The application provides a non-transitory computer readable storage medium, which stores a computer program; when the computer program is executed by a processor, the parallel computing simulation acceleration method is realized.

[0028] The parallel computing simulation acceleration method, device, electronic equipment and storage medium provided by the application divide a huge simulation task into multiple independently running simulation processes, including a mainboard simulation process and a board card simulation process, and establish a communication connection between the simulation processes through a network socket; so that different simulation processes can be scheduled to different cores or devices for simultaneous running, realizing real parallel computing simulation, greatly improving simulation efficiency and shortening simulation time; since each simulation process runs independently, the number of board cards can be flexibly simulated to be increased or decreased, and failure of a single board card simulation process will not cause the entire simulation system to crash, enhancing the scalability and robustness of parallel computing simulation. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0030] In order to more clearly illustrate the technical solutions in the application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other accompanying drawings according to these accompanying drawings without creative labor.

[0031] Figure 1 is a flowchart of the parallel computing simulation acceleration method provided by the application.

[0032] Figure 2 is a parallel computing simulation diagram in the related art provided by the application.

[0033] Figure 3 is one of the parallel computing simulation diagrams provided by the application.

[0034] Figure 4 is another parallel computing simulation diagram provided by the application.

[0035] Figure 5 is a third parallel computing simulation diagram provided by the application.

[0036] Figure 6 is a structural diagram of the parallel computing simulation acceleration device provided by the application.

[0037] Figure 7 is a structural diagram of the electronic equipment provided by the application. DETAILED DESCRIPTION

[0038] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, so that those skilled in the art can better understand the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0039] It should be noted that the terms "first", "second" and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units or modules does not necessarily have to include those steps or units or modules clearly listed, but can include other steps or units or modules not clearly listed or inherent to these processes, methods, products or devices.

[0040] ‌The related art parallelly calculates multiple computing cards, each computing card does not independently run a simulation task, but is uniformly scheduled and managed under the same large simulation program, the simulation speed is slow, the simulation efficiency is low, and the hot plug of the simulation simulation board card is not supported, and increasing or reducing any computing card needs the whole simulation program to be re-run.

[0041] In order to solve the problems of the related art, Figure 1 is a flowchart of the parallel computing simulation acceleration method provided by the present application, as Figure 1 shown, the method comprises steps 110, 120 and 130.

[0042] Step 110, the current simulation task is divided into multiple simulation processes; the multiple simulation processes include at least one host simulation process and at least one board card simulation process; each simulation process is independently run.

[0043] Specifically, the execution subject of the parallel computing simulation acceleration method provided by the embodiments of the present application is a parallel computing simulation acceleration device or system. The device can be realized by software, such as a parallel computing simulation acceleration program running in a computer system, or by hardware, such as a computer or server executing the parallel computing simulation acceleration method.

[0044] The board card in the embodiments of the present application is a computing card, which is a high-performance hardware module specially designed for specific computing tasks, and is a core engine of parallel computing, such as a general-purpose graphics processing unit (GPGPU) and the like.

[0045] The current simulation task is used to simulate parallel computing performed on multiple board cards. In parallel computing, a host is used to perform tasks such as control program flow, logical judgment, data preparation and scheduling, result processing and display, and the like; and a board card is used to perform large-scale and highly parallel computing tasks.

[0046] A process refers to an execution instance of a program, and has an independent memory address space, a data stack and other system resources. Unlike related technologies, the embodiments of the present application decompose the current simulation task into multiple simulation processes, and no longer compiles and runs simulation models of the host and all board cards in a unified program instance, but starts independent program instances for main logic units in the system.

[0047] The simulation processes obtained by decomposition include at least two types. One type is a host simulation process. The process is used to simulate the behavior of the host. For example, the host simulation process can include simulation models of a host processor, memory, an operating system, a driver program and the like, and the main function is to initiate access to the board card, data transmission requests and execution of upper-layer application software. The other type is a board card simulation process. The process is used to simulate the behavior of a single physical board card.

[0048] In a simulation task including multiple board cards, each board card can correspond to an independent board card simulation process. For example, if a simulation task needs to simulate a host and eight board cards, the task can be decomposed into one host simulation process and eight independent board card simulation processes, totaling nine simulation processes.

[0049] The host simulation process and the board card simulation process are independently run. Each simulation process has an independent memory space; is independently scheduled by an operating system, and can be allocated to different cores and executed in parallel; and the start, pause or abnormal crash of one simulation process does not necessarily cause interruption of other simulation processes.

[0050] Step 120, a network socket-based communication connection is established between the simulation processes.

[0051] Specifically, after the current simulation task is decomposed into multiple independent processes, a mechanism needs to be established to realize data interaction between the processes, otherwise the simulation cannot be performed. The embodiments of the present application use a network socket (Socket) as a communication means.

[0052] A network socket is a standard interface in computer network communication, which allows programs located in different processes (even different physical machines) to exchange data through network protocols. Each socket is usually uniquely identified by an Internet Protocol (IP) address and a port number.

[0053] The network socket-based communication connection is established between the simulation processes, including the communication connection between the host simulation process and the board simulation process, and the communication connection between the board simulation processes.

[0054] In a specific embodiment, a Client / Server model can be used to establish the network socket-based communication connection between the simulation processes. Taking the communication connection between the host simulation process and the board simulation process as an example, the host simulation process can be configured as a server. At the beginning of simulation, the host simulation process is started first and detects on one or more predefined ports, waiting for the connection request from the board simulation process. Then, each board simulation process is started as a client and initiates a network socket connection request to the host simulation process according to the configuration information (such as the IP address and port number of the machine where the host simulation process is located). After receiving the request, the host simulation process completes the handshake process, thereby establishing a point-to-point communication connection between the host and each board.

[0055] The embodiment of the present application selects the network socket for communication, which has the following effects compared with the related art:

[0056] (1) The network socket helps to decouple the simulation processes, and the crash of a single simulation process will not affect the running of other simulation processes, thus helping to support the hot plug of the simulation board.

[0057] (2) The network socket supports cross-machine device communication, and the simulation task can be distributed to different physical servers, allowing the resources of a computing cluster composed of different physical servers to be used to complete a simulation task together, and completely breaking the single-machine performance bottleneck.

[0058] (3) The application interface of the network socket is standardized in all mainstream operating systems and programming languages, simplifying the debugging of the communication process, facilitating the checking of when specific instructions or data are sent and whether they are correctly received, and improving the efficiency of problem positioning and analysis.

[0059] (4) The network socket can seamlessly integrate the host simulation model or the board simulation model written in any language and on any platform into the simulation system, supporting the mixed simulation of different sources of intellectual property cores.

[0060] Step 130, transmitting simulation data and control instructions between each simulation process through a communication connection.

[0061] Specifically, in parallel computing simulation, simulation data and control instructions can be transmitted between each simulation process through a communication connection established by a network socket, and the current simulation task is executed.

[0062] Simulation data refers to data that needs to be transmitted between a host and a board card, or between board cards during simulation. For example, a data block that the host writes into the memory of the board card, or state information or calculation results read from the board card.

[0063] Control instructions refer to commands used to coordinate and control the simulation process. For example, a read register instruction sent by the host simulation process to the board card simulation process, and the register address is specified; or a start data transmission instruction is sent, and parameters such as the source address, target address, and length of the transmission are attached.

[0064] The parallel computing simulation acceleration method provided by the embodiments of the present application divides a huge simulation task into multiple independently running simulation processes, including a host simulation process and a board card simulation process, and establishes a communication connection between each simulation process through a network socket; so that different simulation processes can be scheduled to different cores or devices to run simultaneously, realizing true parallel computing simulation, greatly improving simulation efficiency, and shortening simulation time; since each simulation process runs independently, it can simulate the addition or reduction of board cards flexibly, and the failure of a single board card simulation process will not cause the entire simulation system to crash, enhancing the scalability and robustness of parallel computing simulation.

[0065] It should be noted that each embodiment of the present application can be freely combined, the order can be changed, or each embodiment can be executed independently, and does not need to rely on or depend on a fixed execution order.

[0066] In some embodiments, the method further comprises:

[0067] configuring an intellectual property verification core inside each simulation process;

[0068] The verification intellectual property core is used to convert a data packet received through the communication connection into a protocol operation of a target hardware interface, and / or convert a protocol operation of the target hardware interface into a data packet for sending through the communication connection;

[0069] The target hardware interface is a hardware interface configured by the host and / or a hardware interface configured by the board card.

[0070] Specifically, Verification Intellectual Property (VIP), also known as verification IP core, is a reusable, pre-verified complex verification component used for simulating and verifying a specific standard interface protocol. It can be a software library, a hardware behavior model, or a combination of both. For example, there are corresponding verification IP cores for Peripheral Component Interconnect Express (PCIe) protocol, Advanced eXtensible Interface (AXI) protocol, Ethernet protocol, etc.

[0071] In the embodiments of the present application, the verification IP cores are instantiated inside each simulation process. For example, in the host simulation process, a verification IP core for simulating the interface behavior on the host side can be configured; in each board simulation process, a verification IP core for simulating the interface behavior on the board side can be configured. The embodiments of the present application do not make specific limitations on the types and quantities of verification IP cores.

[0072] The target hardware interface refers to the hardware interface configured by the host and / or the hardware interface configured by the board. The verification IP core is used to implement the conversion of simulation data or control instructions to operations, to replace the high-speed interface between boards with a virtual channel, and to convert complex physical signal interaction into more efficient and flexible logical data interaction, thereby bypassing some physical layer bottlenecks.

[0073] When a control command is issued or simulation data is received, the verification IP core can convert the data packet received through the communication connection into a protocol operation of the target hardware interface. The protocol operation refers to a series of bottom-layer signal interaction events that conform to the protocol specification and have a timing relationship on the target hardware interface. For example, a PCIE memory write operation involves a series of complex simulation behaviors such as generation of transaction layer data packet, sequence number verification of data link layer, and encoding and serial transmission on differential signal lines of physical layer.

[0074] In a specific embodiment, when the verification IP core of a board simulation process receives a high-level data packet (e.g., a data packet containing write data) through a network socket, the verification IP core parses the data packet. Subsequently, a protocol engine inside the verification IP core starts and "translates" the abstract command into a series of specific protocol operations on the target hardware interface. The verification IP core drives the interface signals of the to-be-simulated design connected thereto to accurately simulate a complete data write process that conforms to the protocol specification.

[0075] When sending simulation data, the verification IP core converts protocol operations of the target hardware interface into data packets to be sent through the communication connection.

[0076] In one specific embodiment, when the design to be simulated initiates an action that requires communication with the outside world (for example, the board needs to initiate data transmission to the host after completing the calculation), it will generate a series of protocol operations on its target hardware interface. The verification IP core connected to the interface will capture these protocol operations and identify the protocol events represented by the series of underlying signal changes. After identifying the protocol event, the verification IP core will abstract and encapsulate it into a high-level, general-purpose data packet containing event type, key parameters, etc. Finally, the verification IP core sends this data packet to the corresponding simulation process (for example, the host simulation process) through the network socket.

[0077] The parallel computing simulation acceleration method provided by the embodiments of the present application configures a verification IP core in each simulation process, separates the high-level, cross-process, network socket-based general-purpose message passing mechanism from the underlying, in-process, specific hardware protocol-based accurate simulation, converts complex physical signal interaction into more efficient and flexible logical data interaction, improves simulation efficiency, and shortens simulation time.

[0078] In some embodiments, the protocol operations of the target hardware interface include high-speed serial computer expansion bus protocol operations.

[0079] Specifically, in a computer system, the connection between the host and the high-performance board usually adopts a high-speed serial bus.

[0080] Correspondingly, the protocol operations of the target hardware interface can include high-speed serial computer expansion bus (PCIe) protocol operations.

[0081] The parallel computing simulation acceleration method provided by the embodiments of the present application, the verification IP core can convert the protocol operations including high-speed serial computer expansion bus protocol operations, can simulate a series of behaviors conforming to the PCIe standard specification on the PCIe interface of the design to be simulated, complete and accurate, so that the verification engineer does not need to consider the details of the underlying PCIe protocol, and improves the practicability and efficiency of parallel computing simulation.

[0082] In some embodiments, each simulation process is independently run in the same physical computing device.

[0083] Specifically, each simulation process can be independently run in the same physical computing device, such as a physical server, workstation or high-performance personal computer with powerful computing resources. The device has multiple processor cores, large memory and a standard operating system.

[0084] In one specific embodiment, all the required simulation processes can be started automatically by writing a script. For example, the script can first start the host simulation process, and then start a loop of the board simulation processes according to the number of the board to be simulated.

[0085] Since all the processes share the processor resources and memory resources of the same physical computing device, the operating system will be responsible for allocating resources among them. Users or system administrators can optimize performance through the tools of the operating system, for example, binding different simulation processes to different processor cores to avoid additional overhead due to the competition for processor resources between processes, thereby maximizing the efficiency of parallel execution.

[0086] When all simulation processes run on the same physical machine, the network socket communication between them becomes efficient. Communication data packets do not need to pass through physical network cards and external network switches, but are routed through the local loopback interface of the operating system kernel.

[0087] The parallel computing simulation acceleration method provided by the embodiments of the present application can make full use of the computing power of a multi-core computer, decompose different simulation tasks into different processes and bind them to different processor cores, and achieve efficient parallel processing. Since all simulation processes run on the same physical machine, low latency and high bandwidth are ensured for inter-process communication, which is very suitable for application scenarios with centralized computing resources and high simulation performance requirements.

[0088] In some embodiments, each simulation process is independently run in a different physical computing device; the physical computing devices are connected through a network.

[0089] Specifically, each simulation process can be independently run in a different physical computing device. Different physical computing devices can be multiple servers located in the same rack, multiple workstations distributed in the same local area network, or even multiple computers distributed in different geographic locations and interconnected through a wide area network or a dedicated network. Each physical computing device has an independent processor, memory and operating system. These physical computing devices can communicate with each other through standard network protocols.

[0090] Each simulation process can be flexibly deployed according to the resource status of each physical computing device and the characteristics of the simulation task. For example, the host simulation process with the heaviest computing and communication load can be deployed on a server with the strongest performance. Then, multiple board simulation processes can be grouped and deployed on other multiple servers. When each simulation process is started, it needs to be explicitly informed of the IP address and port number of the physical computing device where the communication counterpart (for example, the host simulation process) is located.

[0091] The parallel computing simulation acceleration method provided in the embodiments of the present application can effectively aggregate the scattered computing resources, form a unified and powerful simulation computing cluster, and improve the efficiency of parallel computing simulation.

[0092] In some embodiments, the method comprises:

[0093] While the simulation processes are running, a network socket connection request sent by a current board card simulation process is detected; the current board card simulation process is a newly added board card simulation process in a current simulation task;

[0094] In the case of detecting the network socket connection request, a network socket-based communication connection is established with the current board card simulation process in response to the network socket connection request.

[0095] Specifically, once the parallel computing simulation in the related art starts, the topology structure (i.e., which devices are included) of the simulation system is fixed and cannot be dynamically changed at runtime. The parallel computing simulation acceleration method in the embodiments of the present application can support board card hot plug-in.

[0096] At the start of simulation, the host simulation process can only establish a connection with a part of known board card simulation processes. However, in addition to processing the established connection (the simulation processes of the established connection continue to run), the host simulation process will also continuously maintain a detection state on its port. The network protocol stack of the operating system will automatically process new connection requests, and when a new client attempts to connect, the detection process (i.e., the host simulation process) will be awakened or notified.

[0097] The current board card simulation process is a newly added board card simulation process in a current simulation task. The process does not exist at the start of the initial simulation task, but is started manually or through a script by a user after the simulation is performed to a certain time.

[0098] When the host simulation process detects the network socket connection request sent by the current board card simulation process, it will perform a standard network socket acceptance operation. The operation will create a new dedicated socket, which is specially used for subsequent one-to-one communication with the current board card simulation process. The original detection socket continues to maintain a detection state to receive more possible new connection requests at any time.

[0099] After the communication connection is established, the host simulation process can dynamically add the new communication link and the corresponding board card information to the device list managed internally. Subsequently, the upper-layer software (such as a simulated operating system or a test program) of the host simulation process can discover the current board card and start interacting with the board card for simulation data and control instructions, as if the board card existed initially.

[0100] The parallel computing simulation acceleration method provided in the embodiments of the application realizes the real hardware hot insertion function at the simulation level, which greatly improves the flexibility and authenticity of the simulation.

[0101] In some embodiments, the method comprises:

[0102] While the respective simulation processes are running, the network socket state corresponding to each board card simulation process is continuously detected;

[0103] In the case where the network socket corresponding to any board card simulation process is disconnected, the system resource corresponding to the network socket corresponding to the board card simulation process is released.

[0104] Specifically, the parallel computing simulation acceleration method in the embodiments of the application can also support board card hot plug-out (HotPlug-out).

[0105] The host simulation process maintains a list of all currently connected board card simulation processes, and a dedicated socket for communication with each board card, and continuously detects the network socket state corresponding to each board card simulation process.

[0106] There can be two cases for the network socket corresponding to any board card simulation process to be disconnected. The first case is that the user actively plugs out. The user manually and normally terminates a certain board card simulation process in the simulation process in order to simulate hot plug-out. The process actively closes its network socket before exiting, thereby causing the host to detect that the connection is disconnected. The second case is abnormal disconnection. A certain board card simulation process abnormally crashes due to internal simulation logic errors, physical machine downtime or network failure, etc. This also causes the network socket connection corresponding to the process to be determined as disconnected by the operating system kernel.

[0107] The host simulation process continuously detects the network socket state corresponding to each board card simulation process while the respective simulation processes are running. In the case where the network socket corresponding to any board card simulation process is disconnected, the host simulation process can determine that the board card simulation process is possibly generated by the user plugging out the board card, release the system resource corresponding to the network socket corresponding to the board card simulation process, and remove the board card from the active device list maintained internally.

[0108] In this process, the communication between the host simulation process and other board card simulation processes is not affected at all, and continues normally.

[0109] The parallel computing simulation acceleration method provided in the embodiments of the present application successfully simulates the hardware "hot pullout" function through continuous detection of the network socket state and the corresponding resource release mechanism, so that the simulation system can process the dynamic removal of the simulation unit, and the fault tolerance, robustness and high availability of the simulation system are improved.

[0110] The parallel computing simulation acceleration method provided in the embodiments of the present application is described below by taking the simulation of a parallel computing system composed of one host and two board cards as an example.

[0111] Figure 2 is a parallel computing simulation schematic diagram provided in the related art, as shown in Figure 2 , the simulation method in the related art needs to construct a parallel computing environment composed of one host and two board cards, and needs to connect all the hardware in advance according to the configuration using hardware connection, and then compile into an integral simulation program for simulation, which is slow in simulation speed and low in simulation efficiency. Since as many board cards as possible are running in one simulation environment, the simulation speed will become slower and slower with the increase of the board cards.

[0112] Moreover, the hot plug of the simulation board card is not supported, and the topology structure of the simulation system needs to be adjusted again when any board card is added or removed, and the whole simulation program needs to be run again.

[0113] After the parallel computing simulation acceleration method provided in the present application is adopted, a huge simulation task can be divided into multiple independent simulation processes, including a host simulation process and a board card simulation process, and a communication connection is established between the simulation processes through a network socket; so that different simulation processes can be scheduled to different devices and run at the same time.

[0114] Figure 3 is one of the parallel computing simulation schematic diagrams provided in the present application, as shown in Figure 3 , the host simulation process can be started first, and then the board card simulation process is started.

[0115] Figure 4 is another parallel computing simulation schematic diagram provided in the present application, as shown in Figure 4 , the first board card simulation process is started. The process can run on any device connected to the host through a network. After the process connects to the host simulation process, the host allocates an address to the board card for socket communication.

[0116] Figure 5 is a third parallel computing simulation schematic diagram provided in the present application, as shown in Figure 5 , the second board card simulation process is started, The first card is started similarly, and the process can run on any device connected to the host and other cards via a network. The process requests a connection to the host simulation process, and after connecting to the host simulation process, the host assigns an address to the card for socket communication. Meanwhile, the process also requests a connection to other card simulation processes and obtains the communication addresses of the other card simulation processes.

[0117] A verification intellectual property (IP) core is configured in each simulation process.

[0118] After receiving a command or data from the host simulation process, the verification IP core in each card simulation process converts the command or data into a corresponding protocol operation and sends the operation to the card simulation process.

[0119] After receiving a command or data sent to the host simulation process, the verification IP core in each card simulation process packs the command or data into socket communication data and sends the data to the host simulation process.

[0120] After receiving a command or data from another card simulation process, the verification IP core in each card simulation process converts the command or data into a corresponding protocol operation and sends the operation to the card simulation process.

[0121] After receiving a command or data sent to another card simulation process, the verification IP core in each card simulation process packs the command or data into socket communication data and sends the data to the other card simulation process.

[0122] In related technologies, the simulation speed decreases linearly with the increase in the number of cards, while the method provided in the present application is basically not affected by the increase in the number of cards. In a specific embodiment, the EDA simulation of a graphics processing unit (GPU) takes days to simulate a test scenario. Assuming that one scene simulation of one GPU takes one day, for a scene simulation of eight GPUs, the multi-card simulation in related technologies takes eight days. Using the method provided in the present application, the simulation can be completed in only one day, greatly increasing the simulation speed.

[0123] The device provided in the embodiments of the present application is described below, and the device described below can be referred to in conjunction with the method described above.

[0124] Figure 6 is a structural schematic diagram of a parallel computing simulation acceleration device provided in the present application, as shown in Figure 6 The device includes:

[0125] The decomposition module 610 is configured to decompose the current simulation task into a plurality of simulation processes; the plurality of simulation processes include at least one host simulation process and at least one board card simulation process; and each simulation process is independently run.

[0126] The communication module 620 is configured to establish a network socket-based communication connection between the simulation processes.

[0127] The simulation module 630 is configured to transmit simulation data and control instructions between the simulation processes through the communication connection.

[0128] The parallel computing simulation acceleration device provided by the embodiment of the present application decomposes a huge simulation task into a plurality of independently run simulation processes, including a host simulation process and a board card simulation process, and establishes a communication connection between the simulation processes through a network socket; so that different simulation processes can be scheduled to different cores or devices to run simultaneously, realizing true parallel computing simulation, greatly improving simulation efficiency and shortening simulation time; since each simulation process is independently run, the number of board cards can be flexibly simulated to be increased or decreased, and failure of a single board card simulation process will not cause the entire simulation system to crash, enhancing the scalability and robustness of parallel computing simulation.

[0129] Figure 7 is a structural schematic diagram of an electronic device provided by the present application, as shown in Figure 7 The electronic device can include a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 complete mutual communication through the communication bus 740. The processor 710 can invoke a logical command in the memory 730 to execute the method described in the above embodiment, for example:

[0130] The current simulation task is decomposed into a plurality of simulation processes; the plurality of simulation processes include at least one host simulation process and at least one board card simulation process; each simulation process is independently run; a network socket-based communication connection is established between the simulation processes; and simulation data and control instructions are transmitted between the simulation processes through the communication connection.

[0131] In addition, the logic commands in the memory described above can be implemented in the form of a software function unit and sold or used as a separate product, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of commands to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0132] The processor in the electronic device provided by the embodiments of the present application can call the logic instructions in the memory to implement the above-mentioned method, and the specific implementation manners are consistent with the above-mentioned method implementation manners, and the same beneficial effects can be achieved, which will not be described here.

[0133] The embodiments of the present application also provide a computer-readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the method provided by each of the above embodiments.

[0134] The specific implementation manners are consistent with the above-mentioned method implementation manners, and the same beneficial effects can be achieved, which will not be described here.

[0135] The embodiments of the present application provide a computer program product, which includes a computer program. The computer program is executed by a processor to implement the above-mentioned method.

[0136] The device embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0137] Those skilled in the art can clearly understand the implementation of the various embodiments by means of software and the necessary general hardware platform from the above description of the embodiments, and of course, the embodiments can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that contributes to the technical solutions can be embodied in the form of a software product. The computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0138] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for accelerating parallel computing simulation, characterized in that, include: Decompose the current simulation task into multiple simulation processes; The plurality of simulation processes include at least one host simulation process and at least one board simulation process; Each simulation process runs independently; the host simulation process is used to simulate the behavior of the host. The host emulation process is used to initiate access to the board, data transmission requests, and execute upper-layer application software. The board simulation process is used to simulate the behavior of a single physical board. In a simulation task involving multiple boards, each board corresponds to an independent board simulation process; Establish network socket-based communication connections between various simulation processes; Simulation data and control commands are transmitted between various simulation processes through the communication connection; the simulation data is the data transmitted between the host and the board, or between the boards, during the simulation process. The control commands are commands used to coordinate and control the simulation process; The method further includes: Configure and verify intellectual property cores within each simulation process; The verification intellectual property core is used to convert data packets received through the communication connection into protocol operations of the target hardware interface, and / or to convert the protocol operations of the target hardware interface into data packets for transmission through the communication connection; The target hardware interface is the hardware interface configured on the host and / or the hardware interface configured on the board. The method includes: While each simulation process is running, the host simulation process detects network socket connection requests sent by the current board simulation process; the current board simulation process is the board simulation process newly added in the current simulation task. Upon detecting the network socket connection request, in response to the network socket connection request, a network socket-based communication connection is established with the current board emulation process; After the host emulation process establishes a communication connection with the current board emulation process, the host emulation process dynamically adds the new communication link and the board information corresponding to the current board emulation process to the device list managed internally by the host emulation process. The method includes: While each simulation process is running, the host simulation process continuously monitors the network socket status corresponding to each board simulation process. If the network socket corresponding to any board emulation process is detected to be disconnected, the system resources corresponding to the network socket of that board emulation process will be released.

2. The parallel computing simulation acceleration method according to claim 1, characterized in that, The protocol operations of the target hardware interface include high-speed serial computer extended bus protocol operations.

3. The parallel computing simulation acceleration method according to claim 1, characterized in that, Each simulation process runs independently on the same physical computing device.

4. The parallel computing simulation acceleration method according to claim 1, characterized in that, Each simulation process runs independently on a different physical computing device; the physical computing devices are connected via a network.

5. A parallel computing simulation acceleration device, characterized in that, include: The decomposition module is used to decompose the current simulation task into multiple simulation processes; The plurality of simulation processes include at least one host simulation process and at least one board simulation process; Each simulation process runs independently; the host simulation process is used to simulate the behavior of the host. The host emulation process is used to initiate access to the board, data transmission requests, and execute upper-layer application software. The board simulation process is used to simulate the behavior of a single physical board. In a simulation task involving multiple boards, each board corresponds to an independent board simulation process; The communication module is used to establish network socket-based communication connections between various simulation processes; The simulation module is used to transmit simulation data and control commands between various simulation processes through the communication connection; the simulation data is the data transmitted between the host and the board, or between the boards, during the simulation process; the control commands are commands used to coordinate and control the simulation process. The device is also used for: Configure and verify intellectual property cores within each simulation process; The verification intellectual property core is used to convert data packets received through the communication connection into protocol operations of the target hardware interface, and / or to convert the protocol operations of the target hardware interface into data packets for transmission through the communication connection; The target hardware interface is the hardware interface configured on the host and / or the hardware interface configured on the board. The device is also used for: While each simulation process is running, the host simulation process detects network socket connection requests sent by the current board simulation process; the current board simulation process is the board simulation process newly added in the current simulation task. Upon detecting the network socket connection request, in response to the network socket connection request, a network socket-based communication connection is established with the current board emulation process; After the host emulation process establishes a communication connection with the current board emulation process, the host emulation process dynamically adds the new communication link and the board information corresponding to the current board emulation process to the device list managed internally by the host emulation process. The device is also used for: While each simulation process is running, the host simulation process continuously monitors the network socket status corresponding to each board simulation process. If the network socket corresponding to any board emulation process is detected to be disconnected, the system resources corresponding to the network socket of that board emulation process will be released.

6. The parallel computing simulation acceleration device according to claim 5, characterized in that, The protocol operations of the target hardware interface include high-speed serial computer extended bus protocol operations.

7. The parallel computing simulation acceleration device according to claim 5, characterized in that, Each simulation process runs independently on the same physical computing device.

8. The parallel computing simulation acceleration device according to claim 5, characterized in that, Each simulation process runs independently on a different physical computing device; the physical computing devices are connected via a network.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the parallel computing simulation acceleration method according to any one of claims 1 to 4.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the parallel computing simulation acceleration method according to any one of claims 1 to 4.

Images