Method and apparatus for generating a timing constraint file, electronic device, and storage medium

Abstract

This invention proposes a method, apparatus, electronic device, and storage medium for generating timing constraint files, relating to the field of chip design technology. The method includes obtaining the chip's hierarchical structure and timing constraint parameters for each module; generating clock connection relationships for each module based on the chip's hierarchical structure and timing constraint parameters; generating timing constraint files for each module based on the clock connection relationships and timing constraint parameters; integrating the timing constraint files of each module according to the chip's hierarchical structure, and performing missing and conflict detection on the timing constraint files of each module during the integration process, ultimately outputting a global timing constraint file that meets convergence conditions. This invention achieves automated generation and integration of timing constraint files, and performs missing and conflict detection during the integration process, greatly improving efficiency and reducing the probability of errors compared to manually writing timing constraint files.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically, to a method, apparatus, electronic device, and storage medium for generating timing constraint files. Background Technology

[0002] In recent years, as electronic chips have become increasingly larger in scale, the complexity of circuit design has also increased significantly. To facilitate circuit design and maintenance, a hierarchical design is often adopted, where the entire chip is divided into multiple layers of modules. Timing constraints, as a critical aspect of chip design, directly affect the chip's performance and functional implementation.

[0003] In existing technologies, the generation and integration of timing constraint files mainly rely on manual operations by designers. Different levels of modules are often the responsibility of different designers. Therefore, during the integration process, it is often necessary for the personnel responsible for different levels of design to attend multiple meetings to confirm the integration information and methods. When facing large-scale and hierarchical chip designs, this approach not only increases the workload of designers but also increases the probability of errors, and significantly lengthens the chip design cycle. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method, apparatus, electronic device and storage medium for generating timing constraint files, so as to solve the problems of low efficiency and easy error caused by manually writing timing constraint files in the prior art.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, the present invention provides a method for generating a timing constraint file, the method comprising:

[0007] Obtain the hierarchical structure of the chip and the timing constraint parameters of each module of the chip;

[0008] The clock connection relationship of each module of the chip is generated based on the chip's hierarchical structure and timing constraint parameters.

[0009] Based on the clock connection relationship and the timing constraint parameters, a timing constraint file for each module of the chip is generated;

[0010] The timing constraint files of each module of the chip are integrated according to the chip's hierarchical structure. During the integration process, the timing constraint files of each module of the chip are checked for missing information and conflicts. Finally, a global timing constraint file that meets the convergence conditions is output.

[0011] In an optional implementation, the timing constraint files for each module of the chip are integrated according to the chip's hierarchical structure, including:

[0012] Starting from the bottom-level modules of the chip, the timing constraint files of each level of modules are integrated step by step to the top-level module according to the chip's hierarchical structure.

[0013] In an optional implementation, the step of performing missing and conflict detection on the timing constraint files of each module of the chip during integration includes:

[0014] During the integration process, it is detected whether each module of the chip is missing a timing constraint file, and whether there are conflicts between the timing constraint files of each module.

[0015] In an optional implementation, the timing constraint parameters include clock parameters, and the step of generating the clock connection relationship of each module of the chip based on the chip's hierarchical structure and the timing constraint parameters includes:

[0016] Based on the chip's hierarchical structure and clock parameters, obtain the port binding relationships between modules at different levels of the chip and the clock associated with each port;

[0017] A clock tree diagram is constructed based on the port binding relationship and the clock associated with each port; wherein, the clock tree diagram represents the clock connection relationship of each module of the chip, the clock tree diagram is a directed acyclic graph, each node in the clock tree diagram represents a clock and each node has only one parent node.

[0018] In an optional implementation, the timing constraint parameters further include delay parameters for input / output ports and exceptional timing constraint parameters; the timing constraint file includes a clock definition constraint file, a port delay constraint file, and an exceptional timing constraint file; generating timing constraint files for each module of the chip based on the clock connection relationship and the timing constraint parameters includes:

[0019] The nodes in the clock tree diagram are sorted according to a preset topology sorting algorithm to obtain the sorting result, and the clock definition constraint files of each module of the chip are generated according to the sorting result.

[0020] Based on the delay parameters of the input and output ports, a port delay constraint file for each module of the chip is generated;

[0021] Based on the exceptional timing constraint parameters, exceptional timing constraint files for each module of the chip are generated.

[0022] In an optional implementation, the chip's hierarchical structure is obtained based on an input project-level structure representation file, the clock parameters are obtained based on an input clock form, the input / output port delay parameters are obtained based on an input / output port delay form, and the exception timing constraint parameters are obtained based on an input exception timing constraint form.

[0023] In an optional implementation, the timing constraint parameters may further include rare constraint parameters, which are obtained based on the input custom interface file.

[0024] In a second aspect, the present invention provides a timing constraint file generation apparatus, the apparatus comprising:

[0025] The data acquisition module is used to acquire the hierarchical structure of the chip and the timing constraint parameters of each module of the chip;

[0026] A clock connection relationship generation module is used to generate the clock connection relationship of each module of the chip according to the chip's hierarchical structure and timing constraint parameters.

[0027] A timing constraint generation module is used to generate timing constraint files for each module of the chip based on the clock connection relationship and the timing constraint parameters.

[0028] The timing constraint integration module is used to integrate the timing constraint files of each module of the chip according to the chip's hierarchical structure. During the integration process, the timing constraint files of each module of the chip are checked for missing information and conflicts. Finally, a global timing constraint file that meets the convergence conditions is output.

[0029] Thirdly, the present invention provides an electronic device including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the timing constraint file generation method as described in any of the foregoing embodiments.

[0030] Fourthly, the present invention provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the timing constraint file generation method as described in any of the foregoing embodiments.

[0031] This invention provides a method, apparatus, electronic device, and storage medium for generating timing constraint files. The method includes obtaining the hierarchical structure of a chip and timing constraint parameters for each module of the chip; generating clock connection relationships for each module of the chip based on the chip's hierarchical structure and timing constraint parameters; generating timing constraint files for each module of the chip based on the clock connection relationships and timing constraint parameters; integrating the timing constraint files of each module of the chip according to the chip's hierarchical structure, and performing missing and conflict detection on the timing constraint files of each module during the integration process; and finally outputting a global timing constraint file that meets the convergence conditions. This invention achieves automated generation and integration of timing constraint files, and performs missing and conflict detection during the integration process, greatly improving efficiency and reducing the probability of errors compared to manually writing timing constraint files.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 An example diagram of existing timing constraint file integration is shown;

[0035] Figure 2 This invention illustrates a flowchart of a timing constraint file generation method provided in an embodiment of the present invention.

[0036] Figure 3 This invention illustrates a functional block diagram of a timing constraint file generation apparatus provided in an embodiment of the present invention.

[0037] Figure 4 A block diagram of an electronic device provided in an embodiment of the present invention is shown.

[0038] Icons: 100 - Electronic device; 110 - Memory; 120 - Processor; 130 - Communication module; 600 - Timing constraint file generation device; 610 - Data acquisition module; 620 - Clock connection relationship generation module; 630 - Timing constraint generation module; 640 - Timing constraint integration module. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0041] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0042] The generation and integration of existing timing constraint files mainly rely on manual operations by designers. Different levels of modules are often the responsibility of different designers. Therefore, during the integration process, it is often necessary for personnel responsible for different levels of design to attend multiple meetings to confirm the integration information and methods. Figure 1 The diagram illustrates a simple design consisting of a top-level module and a bottom-level module, showing the interaction between the top-level and bottom-level modules and the process of integrating and converging timing constraint files. Real-world designs often have more layers and a huge number of modules. Therefore, when facing large-scale and hierarchical chip designs, this approach not only increases the workload for designers but also increases the probability of errors, significantly lengthening the chip design cycle.

[0043] Based on this, embodiments of the present invention provide a method, apparatus, electronic device, and storage medium for generating timing constraint files. Through the automated generation and integration of timing constraint files, the delivery cycle of chip timing constraints is significantly shortened, reducing the need for repeated communication and iteration by designers. Furthermore, missing data and conflict detection are performed during the integration process, further reducing the probability of errors compared to manually writing timing constraint files.

[0044] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0045] Please refer to Figure 2 This is a schematic flowchart illustrating a timing constraint file generation method provided in an embodiment of the present invention. It should be noted that the timing constraint file generation method of the present invention does not rely on... Figure 2 The specific order described below is a limitation. It should be understood that in other embodiments, the order of some steps in the timing constraint file generation method of the present invention can be interchanged according to actual needs, or some steps can be omitted or deleted. This timing constraint file generation method can be applied to electronic devices such as laptops, tablets, PCs (Personal Computers), and servers. The following will describe... Figure 2 The specific process shown will be explained in detail.

[0046] Step S201: Obtain the chip's hierarchical structure and the timing constraint parameters of each module of the chip.

[0047] In this embodiment, timing constraint parameters may include clock parameters, input / output port delay parameters, and exceptional timing constraint parameters, as well as rare constraint parameters. The chip's hierarchical structure and the timing constraint parameters of each module of the chip can be obtained based on the following three types of input files: project-level structure representation files, module-level constraint forms, and custom interface files.

[0048] The project-level structure representation file primarily defines the hierarchical division of the chip project. For example, a chip may contain CPU (Central Processing Unit) / GPU (Graphics Processing Unit) / DDR (Double Data Rate) subsystems. The DDR subsystem may contain Controller and PHY (Physical Layer) modules. Therefore, the chip's hierarchical structure can be obtained from the input project-level structure representation file, including the module names, types (top-level, intermediate, or bottom-level modules), and path locations of each module at each level of the chip project. It should be noted that the chip's hierarchical structure is determined at the beginning of the chip project but can be changed at various stages of the project.

[0049] Module-level constraint forms are filled out by the designers of each module. These forms include clock forms (with parameters such as clock name, clock group, master clock source, frequency, division ratio, duty cycle, and port binding relationships), input / output port delay forms (with parameters such as port name, direction, and delay value), and exception timing constraint forms (with parameters such as constraint type and start / end points). These forms characterize the timing requirements within and at the module boundaries. Therefore, clock parameters can be obtained from the input clock forms, including clock name, clock group, master clock source, physical port, and port binding relationships; input / output port delay parameters can be obtained from the input input / output port delay forms, including port name, direction, and delay value; and exception timing constraint parameters can be obtained from the input exception timing constraint forms, including constraint type and start / end points.

[0050] Custom interface files support personalized extensions of rare constraints to handle uncommon constraint requirements. Therefore, rare constraint parameters can be obtained from the input custom interface file. It can be understood that custom interface files are interface-type files reserved for more personalized needs, mainly targeting the expression of certain very rare timing constraints. Users can fill in such timing constraints in this file, and finally, through the timing constraint file generation method of this embodiment, this file is automatically integrated into the overall timing constraints of the module.

[0051] Step S202: Generate the clock connection relationship of each module of the chip according to the chip's hierarchical structure and timing constraint parameters.

[0052] In this embodiment, based on the chip's hierarchical structure and timing constraints, the clock connection relationships of each module can be automatically derived using a port link backtracking algorithm.

[0053] Step S203: Generate timing constraint files for each module of the chip based on clock connection relationships and timing constraint parameters.

[0054] In this embodiment, after obtaining the clock connection relationship of each module of the chip, the timing constraint file of each module of the chip is generated based on the clock connection relationship and timing constraint parameters.

[0055] Step S204: The timing constraint files of each module of the chip are integrated according to the chip's hierarchical structure. During the integration process, the timing constraint files of each module of the chip are checked for missing information and conflicts. Finally, a global timing constraint file that meets the convergence conditions is output.

[0056] In this embodiment, the timing constraint files of each generated module are integrated according to the chip's hierarchical structure. During the integration process, missing and conflicting timing constraint files are detected, and corresponding errors are presented in detailed error logs. Users can check the logs to correct errors, such as issues with the clock form, input / output port delay form, or exception timing constraint form. These forms are then corrected, and based on the chip's hierarchical structure and timing constraint parameters of each module after correction, the timing constraint files for each module are regenerated. These timing constraint files are then integrated until no errors are detected during integration, ultimately outputting a global timing constraint file that meets the convergence criteria. Meeting the convergence criteria can be understood as no missing or conflicting timing constraint files being detected during the integration process.

[0057] In this way, through the iterative generation, integration, and testing process of timing constraint files, it can be ensured that timing constraints at different levels (such as the Controller module and the PHY module, and the DDR subsystem and its lower-level Controller module and PHY module) are automatically matched, and finally a converged global timing constraint file is output.

[0058] As can be seen, the timing constraint file generation method provided in this embodiment of the invention obtains the chip's hierarchical structure and the timing constraint parameters of each module of the chip; generates the clock connection relationships of each module of the chip based on the chip's hierarchical structure and timing constraint parameters; generates timing constraint files for each module of the chip based on the clock connection relationships and timing constraint parameters; integrates the timing constraint files of each module of the chip according to the chip's hierarchical structure, and performs missing and conflict detection on the timing constraint files of each module of the chip during the integration process, finally outputting a global timing constraint file that meets the convergence conditions. This invention achieves automated generation and integration of timing constraint files, and also performs missing and conflict detection during the integration process, which greatly improves efficiency and reduces the probability of errors compared to manually writing timing constraint files.

[0059] In one embodiment, step S202 specifically includes:

[0060] Based on the chip's hierarchical structure and clock parameters, the port binding relationships between modules at different levels of the chip and the clocks associated with each port are obtained. A clock tree diagram is constructed based on the port binding relationships and the clocks associated with each port. The clock tree diagram represents the clock connection relationships of each module of the chip. The clock tree diagram is a directed acyclic graph, and each node in the clock tree diagram represents a clock and each node has only one parent node.

[0061] For example, for a chip's underlying module A, its port AP has a clock C1. C1 has a sub-clock G1 on its internal path within the underlying module A. C1 and G1 establish a natural connection within module A. After the internal clock connection of the underlying module A is established, if there is a subsystem module S that contains one underlying module A, and S has a clock SC1 on its port SP, and port SP is bound to port AP, then clock SC1 will be sent to port AP of the underlying module A through the internal path of S. At the subsystem S level, the three clocks SC1, A / C1, and A / G1 establish a topological connection, i.e., SC1→A / C1→A / G1.

[0062] It is understandable that the above example only demonstrates a simple three-point linear connection relationship from the upper-level module to the lower-level module. This invention supports not only this type of connection but also bottom-up connections, connections between sub-modules, and mixed-mode connections in complex scenarios such as tree structures. This invention iterates through all clocks and updates the connection relationship of each clock based on the integrated underlying data, ultimately generating an abstract clock tree diagram. This clock tree diagram is a Directed Acyclic Graph (DAG), where each node has only one parent node and can have multiple child nodes.

[0063] For a large chip project, the clock structure is essentially a tree diagram, or a forest. During the generation of the clock tree diagram, it checks for loops or whether the current node has more than one parent node, displaying corresponding prompts in the logs to help designers resolve such issues. Once the forest update process is complete and no errors are reported, it proves that there are no logical errors in the clock connections.

[0064] In one implementation, the timing constraint file includes a clock definition constraint file, a port delay constraint file, and an exceptional timing constraint file. Step S203 may include:

[0065] The nodes in the clock tree diagram are sorted according to a preset topology sorting algorithm to obtain the sorting result. Based on the sorting result, clock definition constraint files for each module of the chip are generated. Based on the delay parameters of the input and output ports, port delay constraint files for each module of the chip are generated. Based on the exception timing constraint parameters, exception timing constraint files for each module of the chip are generated.

[0066] In this embodiment, the topology sorting algorithm can be the Kahn algorithm. The Kahn algorithm sorts all nodes in the clock tree diagram, and based on the sorting result, generates clock definition constraint files for each module of the chip. This ensures that when generating timing constraint commands, the parent clock is defined first, followed by the child clocks, guaranteeing a reasonable and conflict-free order in the generation of timing constraint commands, ultimately resulting in clock definition constraint files for each module of the chip. Based on the delay parameters of the input / output ports, standard input / output delay setting instructions can be obtained, leading to port delay constraint files for each module of the chip. Based on exceptional timing constraint parameters, such as start and end point parameters, exceptional timing constraint commands are generated, resulting in exceptional timing constraint files for each module of the chip.

[0067] In one implementation, the integration of timing constraint files for each module of the chip according to the chip's hierarchical structure in step S204 above may include:

[0068] Starting from the bottom-level modules of the chip, the timing constraint files of each level of modules are integrated into the top-level module step by step according to the chip's hierarchical structure.

[0069] In this embodiment, timing constraint files can be integrated step by step from the bottom module (such as the PHY module) to the top module according to the chip's hierarchical structure. That is, the upper-level module automatically retrieves the timing constraint files of its lower-level sub-modules and integrates them (such as integrating the timing constraint files of the PHY module into the DDR subsystem).

[0070] It is understandable that after each integration, the timing constraint file of the current level will be automatically updated and passed upwards until the top-level module completes the final integration. During this process, the top-level module not only integrates the original constraint information of all sub-modules, but also performs necessary constraint derivation and updates based on the actual connection relationships between modules, such as establishing cross-level clock connection relationships, mapping input and output port delays, and passing on exceptional constraints.

[0071] In one implementation, the step S204 above, which involves performing missing and conflict detection on the timing constraint files of each module of the chip during the integration process, may include:

[0072] During the integration process, it is necessary to check whether each module of the chip is missing timing constraint files, and to check whether there are conflicts between the timing constraint files of each module.

[0073] In this embodiment, during the hierarchical integration of timing constraint files, missing timing constraint files are detected for each module of the chip, while conflict detection detects conflicts between the timing constraint files of different modules. For example, an error is reported if a lower-level module does not provide a clock definition, or if the clock of the PHY module conflicts with the clock of the Controller module.

[0074] As can be seen, this invention significantly reduces the workload of designers manually writing constraints by automating the generation and integration of timing constraint files in chip design. It also avoids frequent information exchange and synchronization processes between multiple levels of designers, thus shortening the timing constraint generation and integration work for ultra-large-scale designs, which originally required several weeks, to within a few days. By detecting missing and conflicting information in the timing constraint files, it effectively identifies and prevents syntax errors and integration omissions that may occur during manual writing by users, improving the accuracy and completeness of the timing constraint files.

[0075] Furthermore, since timing constraint files at all levels are uniformly generated by the timing constraint file generation method provided by this invention, the constraint structure and syntax style from the bottom-level modules to the top-level modules remain highly consistent, greatly improving the readability and review efficiency of subsequent timing constraint files. This invention also supports multiple modes of timing constraint generation and integration. For example, chip design engineers can define constraints based on functional requirements, while chip testability design engineers can independently or incrementally complete the corresponding timing constraint definitions, generation, and integration based on testability requirements, thereby meeting diverse needs in different application scenarios.

[0076] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a timing constraint file generation device is given below. Please refer to... Figure 3 This is a functional block diagram of a timing constraint file generation device 600 provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the timing constraint file generation device 600 provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. The timing constraint file generation device 600 includes: a data acquisition module 610, a clock connection relationship generation module 620, a timing constraint generation module 630, and a timing constraint integration module 640.

[0077] The data acquisition module 610 is used to acquire the chip's hierarchical structure and the timing constraint parameters of each module of the chip.

[0078] It is understood that the data acquisition module 610 can perform the above step S201.

[0079] The clock connection relationship generation module 620 is used to generate the clock connection relationship of each module of the chip according to the chip's hierarchical structure and timing constraint parameters.

[0080] It is understood that the clock connection relationship generation module 620 can perform the above step S202.

[0081] Timing constraint generation module 630 is used to generate timing constraint files for each module of the chip based on clock connection relationships and timing constraint parameters.

[0082] It is understandable that the timing constraint generation module 630 can execute the above step S203.

[0083] The timing constraint integration module 640 is used to integrate the timing constraint files of each module of the chip according to the chip's hierarchical structure. During the integration process, it performs missing and conflict detection on the timing constraint files of each module of the chip, and finally outputs a global timing constraint file that meets the convergence conditions.

[0084] It is understood that the timing constraint integration module 640 can perform the above step S204.

[0085] Optionally, the timing constraint integration module 640 is specifically used to integrate the timing constraint files of each level of the chip to the top level of the chip, starting from the bottom-level modules of the chip and in accordance with the chip's hierarchical structure.

[0086] Optionally, the timing constraint integration module 640 is also specifically used to detect whether each module of the chip is missing a timing constraint file during the integration process, and to detect whether there are conflicts between the timing constraint files of each module.

[0087] Optionally, the timing constraint parameters include clock parameters. The clock connection relationship generation module 620 is specifically used to obtain the port binding relationship between modules at different levels of the chip and the clock associated with each port based on the chip's hierarchical structure and clock parameters; and to construct a clock tree diagram based on the port binding relationship and the clock associated with each port. The clock tree diagram represents the clock connection relationship of each module of the chip. The clock tree diagram is a directed acyclic graph, and each node in the clock tree diagram represents a clock and each node has only one parent node.

[0088] Optionally, the timing constraint parameters also include input / output port delay parameters and exceptional timing constraint parameters; the timing constraint files include clock definition constraint files, port delay constraint files, and exceptional timing constraint files. Specifically, the timing constraint generation module 630 is used to sort the nodes in the clock tree diagram according to a preset topology sorting algorithm, obtain the sorting result, generate clock definition constraint files for each module of the chip based on the sorting result; generate port delay constraint files for each module of the chip based on the input / output port delay parameters; and generate exceptional timing constraint files for each module of the chip based on the exceptional timing constraint parameters.

[0089] Optionally, the chip's hierarchical structure is obtained from the input project-level structure characterization file, the clock parameters are obtained from the input clock form, the input / output port delay parameters are obtained from the input / output port delay form, and the exception timing constraint parameters are obtained from the input exception timing constraint form.

[0090] Optionally, the timing constraint parameters also include rare constraint parameters, which are obtained from the input custom interface file.

[0091] Please refer to Figure 4 This is a block diagram of an electronic device 100 provided in an embodiment of the present invention. The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, processor 120, and communication module 130 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0092] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0093] The processor 120 is used to read / write data or programs stored in the memory 110 and to perform corresponding functions. For example, when a computer program stored in the memory 110 is executed by the processor 120, the timing constraint file generation method disclosed in the above embodiments can be implemented.

[0094] The communication module 130 is used to establish a communication connection between the electronic device 100 and other devices via a network, and to send and receive data via the network.

[0095] It should be understood that, Figure 4 The structure shown is only a schematic diagram of the electronic device 100. The electronic device 100 may also include components that are larger than... Figure 4 The more or fewer components shown, or having the same Figure 4 The different configurations shown. Figure 4 The components shown can be implemented using hardware, software, or a combination thereof.

[0096] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by processor 120, implements the timing constraint file generation method disclosed in the above embodiments.

[0097] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0098] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0099] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for generating time-series constraint files, characterized in that, The method includes: Obtain the hierarchical structure of the chip and the timing constraint parameters of each module of the chip; The clock connection relationships of each module of the chip are generated based on the chip's hierarchical structure and timing constraint parameters. The timing constraint parameters include clock parameters. Generating the clock connection relationships of each module of the chip based on the chip's hierarchical structure and timing constraint parameters includes: obtaining the port binding relationships between modules at different levels of the chip and the clocks associated with each port based on the chip's hierarchical structure and the clock parameters; constructing a clock tree diagram based on the port binding relationships and the clocks associated with each port; wherein, the clock tree diagram represents the clock connection relationships of each module of the chip, the clock tree diagram is a directed acyclic graph, each node in the clock tree diagram represents a clock and each node has only one parent node. The timing constraint files for each module of the chip are generated based on the clock connection relationships and the timing constraint parameters. The timing constraint parameters also include input / output port delay parameters and exceptional timing constraint parameters. The timing constraint files include clock definition constraint files, port delay constraint files, and exceptional timing constraint files. Generating the timing constraint files for each module of the chip based on the clock connection relationships and the timing constraint parameters includes: sorting the nodes in the clock tree diagram according to a preset topology sorting algorithm to obtain a sorting result; generating clock definition constraint files for each module of the chip based on the sorting result; generating port delay constraint files for each module of the chip based on the input / output port delay parameters; and generating exceptional timing constraint files for each module of the chip based on the exceptional timing constraint parameters. The timing constraint files of each module of the chip are integrated according to the chip's hierarchical structure. During the integration process, the timing constraint files of each module of the chip are checked for missing information and conflicts. Finally, a global timing constraint file that meets the convergence conditions is output.

2. The method for generating timing constraint files according to claim 1, characterized in that, The timing constraint files for each module of the chip are integrated according to the chip's hierarchical structure, including: Starting from the bottom-level modules of the chip, the timing constraint files of each level of modules are integrated step by step to the top-level module according to the chip's hierarchical structure.

3. The method for generating timing constraint files according to claim 1, characterized in that, The step of performing missing and conflict detection on the timing constraint files of each module of the chip during integration includes: During the integration process, it is detected whether each module of the chip is missing a timing constraint file, and whether there are conflicts between the timing constraint files of each module.

4. The method for generating timing constraint files according to claim 1, characterized in that, The chip's hierarchical structure is obtained from the input project-level structure representation file, the clock parameters are obtained from the input clock form, the input / output port delay parameters are obtained from the input / output port delay form, and the exception timing constraint parameters are obtained from the input exception timing constraint form.

5. The method for generating timing constraint files according to claim 4, characterized in that, The timing constraint parameters also include rare constraint parameters, which are obtained based on the input custom interface file.

6. A timing constraint file generation device, characterized in that, The device includes: The data acquisition module is used to acquire the hierarchical structure of the chip and the timing constraint parameters of each module of the chip; A clock connection relationship generation module is used to generate clock connection relationships between various modules of the chip based on the chip's hierarchical structure and timing constraint parameters. The timing constraint parameters include clock parameters. The clock connection relationship generation module is used to obtain port binding relationships between modules at different levels of the chip and the clocks associated with each port based on the chip's hierarchical structure and the clock parameters. A clock tree diagram is constructed based on the port binding relationships and the clocks associated with each port. The clock tree diagram represents the clock connection relationships between various modules of the chip. The clock tree diagram is a directed acyclic graph, where each node in the clock tree diagram represents a clock and each node has only one parent node. A timing constraint generation module is used to generate timing constraint files for each module of the chip based on the clock connection relationship and the timing constraint parameters. The timing constraint parameters also include delay parameters for input / output ports and exception timing constraint parameters. The timing constraint files include clock definition constraint files, port delay constraint files, and exception timing constraint files. The timing constraint generation module is used to sort the nodes in the clock tree diagram according to a preset topology sorting algorithm to obtain a sorting result, and generate clock definition constraint files for each module of the chip based on the sorting result; generate port delay constraint files for each module of the chip based on the delay parameters of the input / output ports; and generate exception timing constraint files for each module of the chip based on the exception timing constraint parameters. The timing constraint integration module is used to integrate the timing constraint files of each module of the chip according to the chip's hierarchical structure. During the integration process, the timing constraint files of each module of the chip are checked for missing information and conflicts. Finally, a global timing constraint file that meets the convergence conditions is output.

7. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, it implements the steps of the timing constraint file generation method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of the timing constraint file generation method as described in any one of claims 1-5.

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