Clock synchronization method and system, network clock device and network equipment

Abstract

The embodiment of the invention provides a clock synchronization method and system, a network clock device and network equipment. The method comprises the following steps: determining a target clock source for clock synchronization according to source selection strategy parameters of at least two input clock sources, wherein the source selection strategy parameters comprise at least one of a synchronization state message level, an input clock source priority and an input interface identifier. And synchronizing a local clock based on the target clock source, and outputting a clock signal according to the synchronized local clock, thereby improving the selection efficiency and accuracy of the input clock source in the clock synchronization process, and further improving the stability and flexibility of clock synchronization.

Description

Technical Field

[0001] This application relates to the field of clock synchronization technology, and in particular to a clock synchronization method, system, network clock, and network device. Background Technology

[0002] With the development of communication technology, the importance of clock synchronization in network systems is increasing daily. For example, in a network system, base stations and the core network need to ensure time alignment to prevent data loss during terminal handover between base stations; or multiple base station collaboration requires synchronizing the time of multiple base stations to achieve functions such as joint transmission and interference coordination. However, current clock synchronization solutions applied to base stations use network clock devices with only a single interface design, meaning they only support one external clock source input for clock synchronization. This results in poor stability and low flexibility, making it difficult to meet the current clock synchronization requirements of network systems.

[0003] Therefore, improving the stability and flexibility of clock synchronization is an urgent problem to be solved. Summary of the Invention

[0004] The clock synchronization method, system, network clock, and network device provided in this application are intended to improve the stability and flexibility of clock synchronization.

[0005] In a first aspect, embodiments of this application provide a clock synchronization method, including:

[0006] The target clock signal for clock synchronization is determined based on source selection strategy parameters of at least two input clock signals, wherein the source selection strategy parameters include at least one of synchronization status message level, input clock source priority, and input interface identifier.

[0007] Synchronize the local clock based on the target clock signal;

[0008] The clock signal is output based on the synchronized local clock.

[0009] Optionally, the source selection strategy parameters include the synchronization status message level, and determining the target clock signal for clock synchronization based on the source selection strategy parameters of at least two input clock signals includes:

[0010] The target clock signal is determined from the first input clock signal whose synchronization status message level is greater than or equal to a preset level.

[0011] Optionally, the source selection strategy parameters further include the input clock source priority, and determining the target clock signal from the first input clock signals whose synchronization status message level is greater than or equal to a preset level includes:

[0012] The target clock signal is determined based on the input clock source priority of the first input clock signal.

[0013] Optionally, determining the target clock signal based on the input clock source priority of the first input clock signal includes:

[0014] The target clock signal is determined from a second input clock signal whose input clock source priority is greater than or equal to a preset priority in the first input clock signal.

[0015] Optionally, the source selection strategy parameters further include the input interface identifier, and determining the target clock signal from second input clock signals whose input clock source priority is greater than or equal to a preset priority in the first input clock signal includes:

[0016] The target clock signal is determined based on the input interface identifier of the second input clock signal.

[0017] Optional, also includes:

[0018] If at least two of the input clock signals fail, the local clock signal shall be used as the target clock signal.

[0019] Optionally, the local clock signal is generated based on a high-stability crystal oscillator.

[0020] Optional, also includes:

[0021] Based on the user-defined clock source configuration, the input clock signal specified in the clock source configuration is determined as the target clock signal.

[0022] Optionally, synchronizing the local clock based on the target clock signal includes:

[0023] Based on the phase difference and instantaneous frequency deviation between the target clock signal and the local clock signal, the phase and frequency of the local clock signal are adjusted to synchronize with the target clock signal.

[0024] Optionally, adjusting the phase and frequency of the local clock signal to synchronize with the target clock signal based on the phase difference and instantaneous frequency deviation between the target clock signal and the local clock signal includes:

[0025] The instantaneous frequency deviation between the target clock signal and the local clock signal is determined based on the signal time interval between the target clock signal and the local clock signal.

[0026] Based on the instantaneous frequency deviation, a control voltage for the local clock is determined, and the control voltage is used to reduce the instantaneous frequency deviation to less than or equal to a frequency deviation threshold.

[0027] Based on the phase difference between the target clock signal and the local clock signal, adjust the phase of the local clock signal so that the phase difference between it and the target clock signal is less than or equal to a preset difference.

[0028] Optional, also includes:

[0029] In the event that at least two of the input clock signals fail, predicted clock data is obtained based on the historical clock data of the local clock.

[0030] The local clock is corrected based on the predicted clock data.

[0031] Optionally, obtaining the predicted clock data based on the historical clock data of the local clock includes:

[0032] Based on the historical clock data, historical offset data of the local clock signal related to temperature and aging degree is obtained;

[0033] The predicted compensation data for the local clock signal is determined based on the historical offset data;

[0034] The predicted clock data is obtained based on the local clock signal and the predicted compensation data.

[0035] Secondly, embodiments of this application provide a clock synchronization system, the system comprising: a clock synchronization module;

[0036] The clock synchronization module is used to receive at least two input clock signals, determine the target clock signal for clock synchronization according to the source selection strategy parameters of the input clock signals, and output a clock signal after synchronizing the local clock based on the target clock signal. The source selection strategy parameters include at least one of the following: synchronization status message level, input clock source priority, and input interface identifier.

[0037] Thirdly, embodiments of this application provide a network clock, which includes a clock synchronization system as described in any of the second aspects.

[0038] Fourthly, embodiments of this application provide a network device, which includes a network clock as described in the third aspect.

[0039] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0040] In a sixth aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0041] The clock synchronization method, system, network clock generator, and network device provided in this application determine the target clock source for clock synchronization based on selection strategy parameters of at least two input clock sources. These selection strategy parameters include at least one of synchronization status message level, input clock source priority, and input interface identifier. The local clock is synchronized based on the target clock source, and a clock signal is output according to the synchronized local clock. This enables parallel access and intelligent switching of multiple input clock sources. Compared to the existing technology that only allows access to a single clock source, this improves the stability and flexibility of clock synchronization, thereby enhancing the efficiency and accuracy of input clock source selection during the clock synchronization process. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0043] Figure 1 This is a schematic diagram of the structure of a clock synchronization system provided in an embodiment of this application;

[0044] Figure 2 This is a schematic diagram of another clock synchronization system provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of another clock synchronization system provided in an embodiment of this application;

[0046] Figure 4 A flowchart illustrating a clock synchronization method provided in an embodiment of this application;

[0047] Figure 5 A flowchart illustrating another clock synchronization method provided in an embodiment of this application;

[0048] Figure 6 A flowchart illustrating yet another clock synchronization method provided in this application embodiment;

[0049] Figure 7 This is a flowchart illustrating another clock synchronization method provided in an embodiment of this application.

[0050] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0051] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0052] Currently, clock synchronization solutions used in base stations employ a single-interface design for network clock devices, meaning they only support one external clock source input for clock synchronization. Taking the existing ICX-D technology as an example, its input interface only supports 1PPS pulse signal input (accuracy ±100ns) or SyncE 25MHz clock input (clock recovery via the Ethernet physical layer).

[0053] However, existing clock synchronization solutions cannot receive complete time information from the upstream clock, such as year / month / day / hour / minute / second; they can only synchronize the second pulse phase, which greatly limits the application of devices in complex time synchronization scenarios. Meanwhile, current hybrid time synchronization networks in scenarios such as 5G base stations and industrial IoT require devices to flexibly access multiple clock sources to meet the demands of complex and ever-changing network environments. The existing single-interface design cannot meet these application scenarios. Furthermore, network clock devices with a single interface design cannot synchronize based on an external clock source when that source fails, leading to reduced accuracy of the output clock signal and thus decreased clock synchronization stability.

[0054] Therefore, current clock synchronization solutions used in base stations suffer from poor stability and low flexibility, making it difficult to meet the clock synchronization requirements of current network systems.

[0055] In view of this, embodiments of this application provide a clock synchronization method. The method determines a target clock source for clock synchronization based on selection strategy parameters of at least two input clock sources. These selection strategy parameters include at least one of synchronization status message level, input clock source priority, and input interface identifier. A local clock is synchronized based on the target clock source, and a clock signal is output according to the synchronized local clock. This achieves the function of parallel access and intelligent switching of multiple input clock sources. Compared to the prior art method of accessing only a single clock source, this method improves the stability and flexibility of clock synchronization, thereby enhancing the efficiency and accuracy of input clock source selection during the clock synchronization process.

[0056] Figure 1 This is a schematic diagram of a clock synchronization system provided in an embodiment of this application. Figure 1 As shown, the clock synchronization system includes a clock synchronization module.

[0057] The clock synchronization module is used to receive at least two input clock signals (such as...) Figure 1 The input clock signal consists of input clock signal 1, input clock signal 2, ..., input clock signal N. The target clock signal for clock synchronization is determined based on the source selection strategy parameters of the input clock signals. After synchronizing the local clock based on the target clock signal, the clock signal is output. The source selection strategy parameters include at least one of the following: synchronization status message level, input clock source priority, and input interface identifier.

[0058] The aforementioned input clock signal may include at least two of the following: a 1-second pulse (PPS) clock signal, a 10MHz clock signal, and a SyncE 25MHz clock signal.

[0059] A 1PPS clock signal refers to a clock signal that emits one pulse per second. The rising or falling edge of this pulse can serve as a time reference point for time synchronization between different devices or systems. A 1PPS clock signal can be output from a satellite timing system based on a Global Navigation Satellite System (GNSS), such as GPS, GLONASS, BDS, or Galileo. Satellites broadcast precise time information, which is then parsed by receiving devices to generate a 1PPS signal. Alternatively, a 1PPS clock signal can be synchronized via a Precision Time Protocol (PTP) network, such as the IEEE 1588 protocol based on a System-on-a-Chip (SoC). This involves the interaction and processing of PTP messages within the network, with relevant hardware or software modules generating the 1PPS signal. Alternatively, the 1PPS clock signal can be output from an external clock card. For example, it can be input to the clock synchronization module through a corresponding external clock card in scenarios where multiple devices are cascaded or extended with clock cards (such as server clusters or distributed system scenarios).

[0060] A 10MHz clock signal is a clock signal with a frequency of 10 megahertz. It is a high-frequency clock signal that can be used as a frequency reference to provide a stable frequency reference for various circuits and modules in electronic systems. It also supports functions such as frequency synthesis by modules like phase-locked loops.

[0061] The SyncE25MHz clock signal is a type of synchronous Ethernet clock signal with a frequency of 25 MHz. Based on the physical layer code stream carrying and recovering frequency information, it can achieve high-precision frequency synchronization between network devices and meet the frequency synchronization requirements of wireless access services. For example, it can be the input of network devices such as base stations and data centers into the clock synchronization system.

[0062] The clock synchronization module features a multi-source input interface design, meaning it integrates multiple interfaces to receive different types of input clock signals. Specifically, the clock synchronization module includes at least two input interfaces corresponding to the aforementioned at least two types of input clock signals. For example, the clock synchronization module may include at least two of the following: an RS422 interface for receiving a 10MHz clock signal, a Soc interface for receiving a SyncE 25MHz clock signal, an RS422 interface for receiving a 1PPS clock signal, and / or a GNSS interface and / or a Soc1588 interface and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0063] For example, the clock synchronization module may include an RS422 interface to support 1PPS+TOD (Time of day) timecode input, an IEEE1588v2 hardware protocol stack to implement 1PPS clock signal parsing and phase alignment, and a SyncE25MHz interface to enable parallel access of three independent clock signals.

[0064] Correspondingly, the clock synchronization module may also include an output interface for outputting the synchronized clock signal. Optionally, the clock synchronization module can output the synchronized clock signal based on different input clock signals through one output interface, or it can output the synchronized clock signal based on different input clock signals through multiple output interfaces (such as one output interface for each type of input clock signal, or one output interface for some types of input clock signals).

[0065] If each type of input clock signal corresponds to an output interface after synchronization, then the type of the output interface is the same as the type of the corresponding input clock signal input interface, which will not be elaborated here.

[0066] Specifically, how the clock synchronization module selects a source based on the source selection strategy parameters of the input clock signal and how it performs clock synchronization based on the target clock signal determined by the source selection can be found in the following method embodiments, and will not be elaborated here.

[0067] Optionally, the clock synchronization module can also have cascading expansion capabilities, supporting cascading topologies of master and slave clock cards through the PCIeSlot cascading interface of the clock card, to meet the needs of large-scale base station networking.

[0068] The clock synchronization system provided in this application provides an input interface for the clock synchronization module that can accept multiple input clock signals. This allows the clock synchronization module to access clock signals from multiple different types of external clock sources in parallel, and enables the reference clock signal required for clock synchronization to be selected and switched among multiple input clock signals. Compared with the prior art, which can only access a single external clock source through a single interface, the clock synchronization system of this application enhances the flexibility of clock synchronization. Even if a certain input clock signal fails, it can switch to other valid input clock signals to ensure the effectiveness of clock synchronization, thereby improving the stability of clock synchronization.

[0069] Figure 2 This is a schematic diagram of another clock synchronization system provided in an embodiment of this application. Figure 2 As shown, the clock synchronization system also includes a clock holding module.

[0070] The clock hold module's output is connected to the clock hold input interface of the clock synchronization module, and its input is connected to the clock hold output interface of the clock synchronization module. For example, there is signal interaction between the clock hold module and the clock synchronization module. The clock hold module can receive a 1PPS_IN signal from the clock synchronization module and output a 1PPS_OUT signal to the clock synchronization module, thus realizing clock signal transmission and collaborative operation between the two.

[0071] The clock hold module is used to obtain predicted clock data based on historical clock data of the local clock and to correct the local clock based on the predicted clock data when at least two input clock sources fail.

[0072] The clock hold module can include two operating modes: locked mode and hold mode. In locked mode, when at least one input clock source is active, the clock hold module can dynamically adjust the local clock frequency and phase based on that input clock source. When all input clock sources fail, it can switch to hold mode, using clock steering technology to dynamically correct the frequency and phase deviation of the local clock, achieving high-precision clock hold functionality. The core of clock steering lies in using historical data from the reference source (i.e., the input clock signal) to predict the local crystal oscillator drift and maintain synchronization accuracy when the reference source fails.

[0073] Specifically, the method by which the clock holding module performs clock holding can be found in the subsequent method embodiments. Figures 6-7 The details will not be elaborated here.

[0074] The clock synchronization system provided in this application embodiment, through the collaborative work of the clock holding module and the clock synchronization module, can achieve high-precision clock synchronization in various scenarios, ensuring that a stable clock output can still be maintained when the external clock source fails, meeting the needs of different application scenarios, thereby improving the stability of clock synchronization.

[0075] For ease of understanding, the complete structure of an exemplary clock synchronization system according to an embodiment of this application is given below. Figure 3 This is a schematic diagram of another clock synchronization system provided in an embodiment of this application. Figure 3 As shown, the clock synchronization system includes a clock synchronization module and a clock holding module.

[0076] The clock synchronization module features a multi-source input interface to receive various input clock signals. These input interfaces may include: an oscillator interface, a clock hold module interface, an RS422 interface, a GNSS interface, a PCIe interface, a differential signal interface, and a serial communication interface. The following is a description of each input interface:

[0077] Oscillator Interface: Used to receive the PPM clock signal output from TCXO oscillators, crystal oscillators, etc. The 12.8MHz 1PPM clock signal output from the TCXO oscillator is input to the clock synchronization module through the OCXO / TXCO interface, and the 48MHz 1PPM clock signal output from the crystal oscillator is input to the clock synchronization module through the XA / XB interface, providing a basic clock frequency reference for the system.

[0078] Clock hold module interface: Used to connect to the clock hold module and receive the 1PPS clock signal input from the clock hold module, such as... Figure 3 The IN0P interface of the clock synchronization module is connected to the 1PPS_OUT interface of the clock hold module to transmit the 1PPS clock signal output by the clock hold module, serving as one of the important input sources for system time synchronization.

[0079] RS422 interface: Receives a 10MHz clock signal; e.g. Figure 3 The IN0N interface can receive a 10MHz clock signal transmitted externally via an RS422 interface. As a high-frequency clock signal, the 10MHz clock signal can serve as a frequency reference, providing a stable frequency reference for modules such as phase-locked loops (PLLs) in electronic systems. It supports PLL frequency synthesis and other functions, meeting the system's requirements for different frequency signals and ensuring that all circuits and modules within the system operate in a stable frequency environment. Alternatively, it can be used to receive a 1PPS clock signal: such as... Figure 3The IN3N interface can receive an externally input 1PPS clock signal via an RS422 interface. This 1PPS clock signal can be used as a backup clock source or redundant clock input. When the primary 1PPS clock source fails or becomes unavailable, the system can switch to this backup 1PPS clock signal to ensure the continuity and stability of clock synchronization, improve system reliability, and prevent system time synchronization interruption due to the failure of a single clock source.

[0080] GNSS interface: Used to receive 1PPS clock signals based on GNSS, such as... Figure 3 The IN2N interface is related to GNSS signal input. Satellites broadcast precise time information, which the GNSS receiver then analyzes to generate a 1PPS clock signal, which is input to this interface. This 1PPS clock signal is used for high-precision time synchronization. In satellite timing systems, it can provide high-precision time synchronization with an accuracy of less than 20 nanoseconds, providing a precise time reference for the system and meeting the time synchronization needs of applications with extremely high time accuracy requirements, such as high-frequency trading in finance and aerospace.

[0081] PCIe interface: Used to receive a 1PPS clock signal input through the PCIe slot interface, such as Figure 3 The IN4P / N interface is related to the PCIe interface. This 1PPS clock signal can be output from an external clock card, suitable for scenarios involving cascading multiple devices or expanding clock cards, such as server clusters and distributed systems. For high-precision time synchronization requirements in wireless base stations, servers can support multiple clock synchronization modes. The PCIe interface can retain pins to transmit a portion of the clock synchronization signal, reducing overall installation complexity and cable costs. This enables efficient transmission and access of the 1PPS clock signal between different devices, meeting the clock synchronization requirements of large-scale system networking.

[0082] Differential signal interface: Used to receive the SyncE 25MHz clock signal. As shown in the figure, the IN1P / N interface is the differential signal interface, which can receive the SyncE 25MHz clock signal input through the SoC interface. The SyncE 25MHz clock signal is a type of synchronous Ethernet clock signal with a frequency of 25 MHz. Based on the physical layer code stream carrying and recovering frequency information, it can achieve high-precision frequency synchronization between network devices, meeting the frequency synchronization requirements of wireless access services. In scenarios such as 5G base stations and data centers, it ensures the collaborative operation of network devices and the stability of data transmission. After the clock synchronization module processes this input signal, it can output a clock signal synchronized with the 25MHz input clock signal through SoC interfaces such as OUT1P, providing a precise clock reference for network devices, ensuring data transmission and collaborative operation between network devices, and meeting the clock synchronization requirements of the network system.

[0083] Serial communication interface: Used for communication with electrically erasable programmable read-only memory (EEPROM), such as the SCLK / SDIO interface shown in the figure. The EEPROM can store clock synchronization configuration information, historical data of the input clock source, etc. Through this serial communication interface, the clock synchronization module can read or write relevant data so that the system can perform corresponding configuration and status management, realize intelligent configuration and operation monitoring of the system, such as optimizing the clock synchronization strategy based on historical data.

[0084] Correspondingly, the clock signal output by the clock synchronization module and its corresponding interface may include:

[0085] OUT0P interface: Used to output the synchronized clock signal to the clock hold module, providing a data source for the clock hold module, so that the clock hold module can implement the clock hold function and ensure that the system can still maintain a certain time synchronization capability when the external clock source fails.

[0086] OUT1P, OUT1N, OUT2P, OUT2N, OUT3P, and OUT3N interfaces are all SoC interfaces used to output clock signals synchronized with a 25MHz input clock signal. These interfaces can be used for clock synchronization in network devices such as 5G base stations and data centers, providing a precise 25MHz synchronization clock signal to ensure high-precision frequency synchronization between network devices and guarantee the stability of data transmission and processing.

[0087] OUT4P Interface: This is an RS422 interface used to output a clock signal synchronized with a 10MHz input clock signal. The clock signal output from this interface can be used with external devices, such as some industrial control equipment, to provide a stable 10MHz synchronous clock signal, ensuring precise time control in industrial production processes.

[0088] OUT5P and OUT5N interfaces: These are Soc1588 interfaces used to output clock signals synchronized with a high-precision 1PPS clock signal. Suitable for industrial automation control systems with extremely high time synchronization requirements, they ensure precise coordination between devices, improving production efficiency and product quality.

[0089] OUT6P Interface: This is an RS422 interface used to output a clock signal synchronized with a 1PPS clock signal input. It can provide a synchronized 1PPS clock signal for devices requiring 1PPS-level time synchronization, such as certain test and measurement equipment, ensuring the accuracy and time correlation of their test results.

[0090] OUT7P and OUT8P interfaces are PCIe interfaces that output clock signals synchronized with the 1PPS clock signal input through the PCIe slot interface. They are suitable for scenarios involving cascading multiple devices or expanding clock cards, such as server clusters and distributed systems.

[0091] The following is based on Figure 3 Taking the clock synchronization system shown as an example, the technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems will be described in detail through specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0092] Figure 4 This is a flowchart illustrating a clock synchronization method provided in an embodiment of this application. Figure 4 As shown, the method may include:

[0093] S401. Determine the target clock signal for clock synchronization based on the source selection strategy parameters of at least two input clock signals.

[0094] The source selection strategy parameters include at least one of the following: synchronization status message level, input clock source priority, and input interface identifier. The input clock signal may include at least two of the following: 1PPS clock signal, 10MHz clock signal, SyncE25MHz clock signal, etc.

[0095] A 1PPS clock signal refers to a clock signal that emits one pulse per second. The rising or falling edge of this pulse can be used as a time reference point to achieve time synchronization between different devices or systems. These signals come from various sources. For example, they can be output from GNSS-based satellite timing systems (such as GPS, GLONASS, BeiDou, Galileo, etc.), where satellites broadcast precise time information, which is then parsed by receiving devices to generate a 1PPS signal. Alternatively, they can be synchronized via Precision Time Protocol (PTP) networks, such as those generated using the IEEE 1588 protocol based on SoCs. Through the interaction and processing of PTP messages in the network, relevant hardware or software modules generate the 1PPS signal. They can also be output from an external clock card. When the 1PPS clock signal is input to the clock synchronization module from an external clock card, it can be input through the PCIe slot of the clock synchronization module in scenarios involving multiple cascaded or expanded clock cards (such as server clusters or distributed systems).

[0096] A 10MHz clock signal is a clock signal with a frequency of 10 megahertz. It is a high-frequency clock signal that can be used as a frequency reference to provide a stable frequency reference for various circuits and modules in the system. It supports functions such as frequency synthesis by modules such as phase-locked loops and can be input through RS422 interfaces.

[0097] The SyncE25MHz clock signal is a type of synchronous Ethernet clock signal with a frequency of 25 MHz. Based on the physical layer code stream carrying and recovering frequency information, it can achieve high-precision frequency synchronization between network devices, meeting the frequency synchronization requirements of wireless access services. It can be output by network devices such as base stations and data centers, and input to the clock synchronization system through SoC interfaces (differential).

[0098] Synchronization status message levels refer to information used to identify the synchronization quality and level of a clock source. Different levels represent different levels of accuracy and reliability of the clock source, and can be used to judge the quality of the clock source. For example, synchronization status message levels may include: Reference Clock (PRC) > Switchboard Slave Clock (SSU-A) > Local Switchboard Slave Clock (SSU-B) > Synchronization Device Clock (SEC) > Unknown Level (UNKNOWN) > Unsynchronizable (DNU). Here, PRC is the most accurate and reliable reference clock source, while DNU indicates that the clock source cannot be used for synchronization.

[0099] Input clock source priority is a user-defined priority based on actual application scenarios and needs. It is used to distinguish and select different input clock sources when synchronization status messages have the same level or do not participate in source selection. Users can assign a corresponding priority identifier or value to each input clock source through the system configuration interface or other methods. For example, the smaller the identifier or value corresponding to the priority, the higher the priority of the input clock source.

[0100] The input interface identifier is a unique identifier for the interface through which each input clock source connects to the clock synchronization module, used to distinguish different physical access ports. This identifier can be, for example, the physical number of the input interface, such as IN0P, IN0N, IN1P / N, etc. In one possible implementation, the smaller the physical number of the input interface, the higher the priority of the corresponding input clock source in terms of interface identifier.

[0101] When multiple input clock signals are valid, the source of multiple input clock signals can be selected based on the above source selection strategy parameters.

[0102] One possible implementation is to use any of the above-mentioned source selection strategy parameters to select the source of multiple input clock signals. For example, the target clock signal can be selected from multiple valid input clock signals based solely on the synchronization status message level; or the target clock signal can be selected based solely on the input clock source priority; or the target clock signal can be selected based solely on the input interface identifier, using the input clock signal with the smallest interface physical number as the reference clock signal for subsequent clock synchronization.

[0103] Another possible implementation is to use at least two of the above-mentioned source selection strategy parameters to select the source of multiple input clock signals. For example, the source selection of multiple input clock signals can be carried out by comprehensively considering the synchronization status message level and the input clock source priority. First, the synchronization status message levels of each input clock signal are compared, and the group with the highest level is selected. If there are multiple clock signals in this group, the highest priority clock signal is selected from the group according to the input clock source priority. Alternatively, the source selection of multiple input clock signals can be carried out by comprehensively considering the synchronization status message level and the input interface identifier. First, clock signals that meet the requirements are filtered according to the synchronization status message level. If there are multiple clock signals, the one with the smallest interface number is selected according to the input interface identifier. Alternatively, the source selection of multiple input clock signals can be carried out by comprehensively considering the input clock source priority and the input interface identifier. First, the input clock source priority is selected. If there are multiple clock signals with the same priority, the input interface identifier is used to determine the source. Alternatively, the source selection of multiple input clock signals can be carried out by comprehensively considering the synchronization status message level, the input clock source priority, and the input interface identifier.

[0104] Specifically, different source selection strategies can be set to determine the priority of each strategy when multiple source selection strategy parameters are available. For example, source selection can begin by using the synchronization status message level to filter out the input clock signal with the highest synchronization status message level. If a unique target clock signal cannot be determined (i.e., multiple input clock signals with the same and highest synchronization status message level exist), further source selection can be performed using the input clock source priority, choosing the signal with the highest priority from these signals. If a unique target clock signal still cannot be determined after source selection using the input clock source priority (i.e., multiple input clock signals with the same and highest synchronization status message level and the same input clock source priority exist), then the target clock signal can be further determined based on the input interface identifier, selecting the one with the smallest interface physical number as the target clock signal.

[0105] S402, Synchronize the local clock based on the target clock signal.

[0106] The local clock refers to the clock unit within the clock synchronization module used to maintain its own time and frequency; the local clock signal it generates serves as the time reference for the system's internal operation. This step involves adjusting the local clock signal to synchronize with the target clock signal, achieving consistency in both frequency and phase.

[0107] Specifically, the synchronization process needs to consider the phase difference and instantaneous frequency deviation between the target clock signal and the local clock signal. The phase difference refers to the difference in phase between the two clock signals at the same moment, such as the time interval between the rising edges of the target clock signal and the local clock signal. The instantaneous frequency deviation refers to the difference in frequency between the two clock signals at a certain moment, reflecting the degree of deviation of the local clock signal frequency relative to the target clock signal frequency. By measuring and adjusting these two parameters, the frequency and phase of the local clock signal are gradually aligned with the target clock signal, thereby achieving synchronization.

[0108] S403: Output clock signal according to the synchronized local clock.

[0109] In this step, after the local clock is synchronized with the target clock signal, the synchronized local clock signal needs to be output through the corresponding output interface to meet the clock synchronization requirements of other devices or systems.

[0110] There are several ways to output the clock signal. For example, the synchronized local clock signal can be directly output through a specific output interface, which can be a system-preset interface used to provide clock signals to the outside world. Alternatively, the synchronized local clock signal can be output through the output interface corresponding to the target clock source, depending on the interface type of the input target clock signal. For example, if the target clock signal is input through the input interface corresponding to SyncE25MHz, the synchronized clock signal can be output through the output interface corresponding to SyncE25MHz.

[0111] The method provided in this application determines the target clock source for clock synchronization based on the source selection strategy parameters of at least two input clock sources, synchronizes the local clock based on the target clock source, and outputs a clock signal based on the synchronized local clock, so as to realize the function of parallel access and intelligent switching of multiple input clock sources. Compared with the existing technology of only accessing a single clock source, it improves the stability and flexibility of clock synchronization, thereby improving the efficiency and accuracy of input clock source selection during clock synchronization.

[0112] Optionally, when the clock synchronization module synchronizes the local clock based on the target clock signal, it can adopt the SyncE frequency synchronization + 1588PTP phase synchronization scheme. This scheme combines the advantages of SyncE and 1588PTP technologies, while meeting the high precision requirements of frequency and phase, and achieving nanosecond-level time synchronization.

[0113] SyncE achieves frequency synchronization by carrying and recovering frequency information based on the physical layer bitstream, unaffected by upper-layer protocols, data network congestion, packet loss, or latency. 1588PTP transmits frequency and phase information via PTP messages, working in conjunction with hardware to achieve high-precision time synchronization. Compared to using 1588PTP alone, this solution improves clock accuracy to the nanosecond level and enhances the reliability of the entire clock system. Since both SyncE and 1588PTP have frequency synchronization capabilities, devices prioritize using SyncE for frequency synchronization. If the SyncE clock source or link fails, 1588PTP frequency synchronization can be activated. Both can share a clock source or use independent clock sources. Even when a 1588PTP malfunction causes time signal loss, SyncE can still operate, maintaining device frequency synchronization and keeping time deviations within acceptable limits.

[0114] The following section provides a detailed explanation of how the target clock signal for clock synchronization is determined based on the source selection strategy parameters of at least two input clock signals in step S401, using the source selection strategy parameters including synchronization status message level, input clock source priority, and input interface identifier as examples. Figure 5 A flowchart illustrating another clock synchronization method provided in this application embodiment is shown below. Figure 5 As shown, the aforementioned step S401 may specifically include:

[0115] S501. Determine the target clock signal from the first input clock signal whose synchronization status message level is greater than or equal to the preset level.

[0116] The preset level is a threshold value for the synchronization status message level that the system pre-sets based on actual application requirements. It is used to filter out input clock signals that meet basic synchronization requirements. For example, continuing with the example of synchronization status message levels including Reference Clock (PRC) > Switching Station Slave Clock (SSU-A) > Local Station Slave Clock (SSU-B) > Synchronization Device Clock (SEC) > Unknown Level (UNKNOWN) > Unsynchronized (DNU), assuming the preset level can be set to SEC, then input clock signals with synchronization status message levels of PRC, SSU-A, SSU-B, and SEC all belong to the first input clock signal category.

[0117] After determining the first input clock signal, if there is only one clock signal among the first input clock signals, then that clock signal is directly determined as the target clock signal; if there are multiple first input clock signals with a synchronization status message level greater than or equal to the preset level, then one can be selected according to the actual situation, or step S202 can be executed for further filtering.

[0118] S502. If there are multiple first input clock signals, then determine the target clock signal from the second input clock signals whose input clock source priority is greater than or equal to the preset priority.

[0119] For the first input clock signals selected in step S201, their input clock source priorities are compared. Each first input clock signal has a corresponding priority identifier or value. By comparing these identifiers or values, their priorities can be determined.

[0120] Specifically, the target clock signal can be determined from the second input clock signals whose input clock source priority is greater than or equal to a preset priority in the first input clock signal. The preset priority is a priority threshold set by the user or the system to further filter out clock signals with higher priority. For example, the preset priority can be set to 3, then the first input clock signals with input clock source priorities of 1, 2, and 3 all belong to the second input clock signals. If there is only one second input clock signal, then that signal is the target clock signal; if there are multiple second input clock signals, then step S203 is executed.

[0121] S503. If there are multiple second input clock signals, the target clock signal is determined according to the input interface identifier of the second input clock signal.

[0122] For the second input clock signals obtained in step S202, their input interface identifiers are compared. Each second input clock signal corresponds to a physical number of an input interface. By comparing these physical numbers, the second input clock signal corresponding to the input interface with the smallest number is selected as the target clock signal.

[0123] In one possible implementation, the local clock signal is used as the target clock signal when at least two input clock signals fail.

[0124] Input clock signal failure refers to the input clock signal failing to meet the system's synchronization requirements, such as signal interruption or signal quality degradation to the point of being unusable. When at least two of the input clock signals are detected to be in a failed state, the clock synchronization system cannot obtain a valid clock reference from the outside. In this case, in order to maintain the system's basic clock function, the local clock signal generated by the local clock itself can be used as the target clock signal for subsequent clock synchronization processes.

[0125] The local clock signal can be generated based on a high-stability crystal oscillator (also known as a high-stability crystal oscillator) in the clock synchronization system. This high-stability crystal oscillator can be, for example, an oven-controlled crystal oscillator (OCXO) or any other type of high-stability crystal oscillator. A high-stability crystal oscillator is an electronic component capable of generating stable frequency signals with a low frequency drift rate, maintaining a stable output frequency for a certain period. Generating a local clock signal based on a high-stability crystal oscillator allows the local clock signal to maintain high stability even without an external valid clock reference, thus ensuring the system's clock synchronization accuracy over a short period.

[0126] In another possible implementation, the target clock signal can be determined based on the user-defined clock signal configuration, specifying the input clock signal in the clock signal configuration.

[0127] User-defined clock source configuration refers to users manually specifying one or more input clock signals as the preferred clock source through system-provided configuration interfaces. When selecting a source, the system prioritizes the user-specified input clock signal. If the specified input clock signal is valid, it is directly selected as the target clock signal; if the specified input clock signal is invalid, other source selection strategies are then used to determine the target clock signal. This method is suitable for scenarios where users have specific clock source requirements and can meet personalized synchronization needs.

[0128] The following section provides a detailed explanation of how the local clock is synchronized based on the target clock signal in step S402.

[0129] Specifically, the phase and frequency of the local clock signal can be adjusted to synchronize with the target clock source based on the phase difference and instantaneous frequency deviation between the target clock signal and the local clock signal.

[0130] In this implementation method, it can be achieved through the following Figure 6 The steps shown implement the above method. Figure 6 A flowchart illustrating another clock synchronization method provided in this application embodiment is shown below. Figure 6 As shown, this implementation method may specifically include:

[0131] S601. Determine the instantaneous frequency deviation between the target clock signal and the local clock signal based on the signal time interval between the target clock signal and the local clock signal.

[0132] The signal time interval refers to the time difference between the target clock signal and the local clock signal within the same period. For example, a series of time interval data, such as T1, T2, T3...T, can be obtained by measuring the time interval between the rising edges of multiple consecutive pulses of two clock signals. n T1 is the time interval within the first cycle, T2 is the time interval within the second cycle, and so on.

[0133] The instantaneous frequency deviation can be calculated based on these signal time interval data. Assuming the target clock signal frequency is f0 and the local clock signal frequency is f1, and within one cycle, the period of the target clock signal is 1 / f0 and the period of the local clock signal is 1 / f1, then the signal time interval ΔT can be expressed as (1 / f1 - 1 / f0). By processing ΔT, such as calculating the average rate of change per unit time, the instantaneous frequency deviation Δf can be obtained, where Δf = f1 - f0.

[0134] S602. Determine the control voltage of the local clock based on the instantaneous frequency deviation. The control voltage is used to reduce the instantaneous frequency deviation to less than or equal to the frequency deviation threshold.

[0135] Local clocks typically employ voltage-controlled oscillators (such as voltage-controlled modules based on high-stability crystal oscillators), whose output frequency changes with the control voltage. Based on the instantaneous frequency deviation Δf, the required control voltage can be determined using a specific control algorithm.

[0136] For example, a proportional-integral-derivative (PID) control algorithm can be used to determine the control voltage of the local clock. The output of the PID algorithm is the control voltage V of the local clock. The proportional term is proportional to the instantaneous frequency deviation Δf, the integral term is proportional to the integral of the instantaneous frequency deviation Δf, and the derivative term is proportional to the rate of change of the instantaneous frequency deviation Δf. That is, the control voltage can be calculated using the following formula 1:

[0137] (1)

[0138] in, This is the proportionality coefficient. The integral coefficient is... These are the differential coefficients. By adjusting these three coefficients, the control voltage can effectively compensate for instantaneous frequency deviations. Reduce it to within the frequency deviation threshold, which is a maximum allowable frequency deviation value set by the system, such as ±1ppm.

[0139] S603. Based on the phase difference between the target clock signal and the local clock signal, adjust the phase of the local clock signal so that the phase difference between the target clock signal and the local clock signal is less than or equal to a preset difference.

[0140] The phase difference can be measured using devices such as a time-to-digital converter (TDC) to obtain the phase difference data between the target clock signal and the local clock signal, such as... 1. 2. 3、…、 n.

[0141] Based on the measured phase difference, a phase compensation algorithm, such as interpolation, is used for adjustment. By inserting or deleting certain pulses during the output of the local clock signal, the phase of the local clock signal is fine-tuned, gradually reducing the phase difference between the two signals. The preset difference is a maximum allowable phase difference set by the system, such as ±10ns. Continuous adjustment is made until the phase difference is less than or equal to this preset difference.

[0142] Figure 7 This is a flowchart illustrating another clock synchronization method provided in an embodiment of this application. Figure 7 As shown, the method may further include:

[0143] S701. When at least two input clock signals fail, predict clock data is obtained based on the historical clock data of the local clock.

[0144] Historical clock data refers to the data recorded by the local clock when it is synchronized with a valid external input clock signal over a period of time. This includes the frequency and phase of the local clock signal, as well as the corresponding timestamp, ambient temperature, and device uptime.

[0145] One possible approach is to analyze and predict historical clock data using time series forecasting algorithms. For example, frequency data of the local clock signal can be extracted from historical clock data, arranged in timestamp order to form a frequency time series, and then an algorithm such as an autoregressive moving average (ARMA) model can be used to model this frequency time series. The model can then predict the frequency change trend of the local clock signal over a future period, thereby obtaining the predicted clock data.

[0146] Another possible implementation can be achieved through the following sub-steps:

[0147] S7011. Based on historical clock data, obtain historical offset data of the local clock signal related to temperature and aging degree.

[0148] Extract the offset of the local clock signal under different temperature conditions and the offset under different device operating times (reflecting aging) from historical clock data. For example, the frequency offset Δf1 and phase offset of the local clock signal relative to the target clock signal can be recorded at temperature T1 and operating time t1. 1; At temperature T2 and running time t2, frequency offset Δf2 and phase offset 2. Generate historical offset data.

[0149] S7012. Determine the prediction compensation data for the local clock signal based on historical offset data.

[0150] Analyze historical offset data to establish a model relating local clock signal offset to temperature and aging level. For example, a multiple linear regression model can be used, with temperature and aging level as independent variables and clock signal offset as the dependent variable. By fitting the model to historical offset data, the parameters are obtained. Then, based on the current temperature and equipment operating time (i.e., the current aging level), substitute them into the model to calculate the possible offset of the local clock signal. This offset is the predicted compensation data.

[0151] S7013. Based on the local clock signal and prediction compensation data, the predicted clock data is obtained.

[0152] The current clock signal output by the local clock is combined with the prediction compensation data. For example, if the prediction compensation data consists of frequency compensation and phase compensation, then the frequency of the prediction clock data is the current frequency of the local clock signal plus the frequency compensation, and the phase is the current phase of the local clock signal plus the phase compensation, thus obtaining the compensated prediction clock data.

[0153] S702, Correct the local clock based on the predicted clock data.

[0154] The predicted clock data is used as a reference to adjust the operating parameters of the local clock. For example, based on the frequency and phase of the predicted clock data, the control voltage of the local clock is adjusted to ensure that the actual clock signal output by the local clock is consistent with the predicted clock data, thereby maintaining the accuracy of the local clock as much as possible in the absence of an external effective clock reference.

[0155] The method provided in this application, when at least two input clock signals fail, obtains historical offset data of the local clock signal related to temperature and aging degree based on historical clock data, determines predictive compensation data of the local clock signal based on the historical offset data, obtains predictive clock data based on the local clock signal and the predictive compensation data, and corrects the local clock based on the predictive clock data. In order to intelligently compensate and correct the local clock using historical data and predictive models when the input clock signal fails, the accuracy and stability of the clock signal are not affected by the failure of external inputs, thereby improving the reliability and operational stability of the system in complex environments and reducing system failures or performance degradation caused by clock signal loss or deviation.

[0156] This application also provides a network clock that includes a clock synchronization system as described in any of the foregoing embodiments.

[0157] This application also provides a network device that includes the aforementioned network clock.

[0158] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0159] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0160] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0161] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0162] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0163] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0164] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0165] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0166] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0167] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A clock synchronization method, characterized in that, The method includes: The target clock signal for clock synchronization is determined based on source selection strategy parameters of at least two input clock signals, wherein the source selection strategy parameters include at least one of synchronization status message level, input clock source priority, and input interface identifier. Synchronize the local clock based on the target clock signal; The clock signal is output based on the synchronized local clock.

2. The method according to claim 1, characterized in that, The source selection strategy parameters include the synchronization status message level, and the step of determining the target clock signal for clock synchronization based on the source selection strategy parameters of at least two input clock signals includes: The target clock signal is determined from the first input clock signal whose synchronization status message level is greater than or equal to a preset level.

3. The method according to claim 2, characterized in that, The source selection strategy parameters also include the input clock source priority, and determining the target clock signal from the first input clock signals whose synchronization status message level is greater than or equal to a preset level includes: The target clock signal is determined based on the input clock source priority of the first input clock signal.

4. The method according to claim 3, characterized in that, Determining the target clock signal based on the input clock source priority of the first input clock signal includes: The target clock signal is determined from a second input clock signal whose input clock source priority is greater than or equal to a preset priority in the first input clock signal.

5. The method according to claim 4, characterized in that, The source selection strategy parameters also include the input interface identifier. Determining the target clock signal from second input clock signals whose input clock source priority is greater than or equal to a preset priority in the first input clock signal includes: The target clock signal is determined based on the input interface identifier of the second input clock signal.

6. The method according to claim 1, characterized in that, Also includes: If at least two of the input clock signals fail, the local clock signal shall be used as the target clock signal.

7. The method according to claim 6, characterized in that, The local clock signal is generated based on a high-stability crystal oscillator.

8. The method according to claim 1, characterized in that, Also includes: Based on the user-defined clock source configuration, the input clock signal specified in the clock source configuration is determined as the target clock signal.

9. The method according to claim 1, characterized in that, The synchronization of the local clock based on the target clock signal includes: Based on the phase difference and instantaneous frequency deviation between the target clock signal and the local clock signal, the phase and frequency of the local clock signal are adjusted to synchronize with the target clock signal.

10. The method according to claim 9, characterized in that, The step of adjusting the phase and frequency of the local clock signal to synchronize with the target clock signal based on the phase difference and instantaneous frequency deviation between the target clock signal and the local clock signal includes: The instantaneous frequency deviation between the target clock signal and the local clock signal is determined based on the signal time interval between the target clock signal and the local clock signal. Based on the instantaneous frequency deviation, a control voltage for the local clock is determined, and the control voltage is used to reduce the instantaneous frequency deviation to less than or equal to a frequency deviation threshold. Based on the phase difference between the target clock signal and the local clock signal, adjust the phase of the local clock signal so that the phase difference between it and the target clock signal is less than or equal to a preset difference.

11. The method according to claim 1, characterized in that, Also includes: In the event that at least two of the input clock signals fail, predicted clock data is obtained based on the historical clock data of the local clock. The local clock is corrected based on the predicted clock data.

12. The method according to claim 11, characterized in that, The step of obtaining the predicted clock data based on the historical clock data of the local clock includes: Based on the historical clock data, historical offset data of the local clock signal related to temperature and aging degree is obtained; The predicted compensation data for the local clock signal is determined based on the historical offset data; The predicted clock data is obtained based on the local clock signal and the predicted compensation data.

13. A clock synchronization system, characterized in that, The system includes: a clock synchronization module; The clock synchronization module is used to receive at least two input clock signals, determine the target clock signal for clock synchronization according to the source selection strategy parameters of the input clock signals, and output a clock signal after synchronizing the local clock based on the target clock signal. The source selection strategy parameters include at least one of the following: synchronization status message level, input clock source priority, and input interface identifier.

14. The system according to claim 13, characterized in that, The system also includes: a clock holding module; The output of the clock holding module is connected to the clock holding input interface of the clock synchronization module, and the input is connected to the clock holding output interface of the clock synchronization module. The clock holding module is used to obtain predicted clock data based on historical clock data of the local clock and correct the local clock based on the predicted clock data when at least two of the input clock sources fail.

15. A network clock, characterized in that, The network clock includes the clock synchronization system as described in any one of claims 13-14.

16. A network device, characterized in that, The network device includes the network clock as described in claim 15.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-12.

18. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method described in any one of claims 1-12.

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