A half-duplex signal driving circuit, chip and device

Abstract

The application discloses a half-duplex signal driving circuit, a chip and equipment. A switchable load module composed of a switch and a matching resistor is introduced, and a same common-mode control circuit and a current source are multiplexed, so that the switchable load module continuously works in two modes of sending and receiving. Since the control subject and the execution unit continuously work in the mode switching process, reference inconsistency and establishment delay caused by switching different control loops are completely avoided, so that the common-mode voltage is switched without jumping and is quickly and stably switched, and the signal quality and reliability of the half-duplex communication link are obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a half-duplex signal driving circuit, a chip and a device. BACKGROUND

[0002] In the field of vehicle-mounted communication, half-duplex AC coupled low voltage differential signal (LVDS) communication has become a key technology for data interaction between devices due to its strong anti-interference ability, high transmission rate, and adaptation to long-distance transmission. In such scenarios, the stability of the common-mode voltage of the signal is a core element to ensure communication quality. That is, the common-mode voltage needs to be maintained at a fixed reference value to ensure the effective generation, transmission, and recognition of the differential signal, and to avoid signal distortion or errors caused by common-mode offset. To achieve common-mode voltage control, the existing technology generally adopts a design idea of independent control in different modes, that is, for the sending mode and the receiving mode, independent common-mode reference circuits or control loops are configured respectively. For example, the receiving mode stabilizes the common-mode voltage of the sending signal through a dedicated common-mode feedback loop, and the sending mode relies on another independent common-mode reference source to provide a reference level for the receiving end to meet the signal characteristic requirements in the respective modes.

[0003] However, this independent control mechanism has significant defects. Since the common-mode control circuits of the sending and receiving modes are independent of each other, the reference parameters (such as reference voltage, feedback gain, etc.) of the two circuits are difficult to be completely consistent. When the half-duplex communication switches between the sending and receiving modes, the common-mode voltage will jump significantly due to the reference difference. This jump directly destroys the continuity of the signal - at the switching moment, the receiving end cannot quickly lock the effective differential signal, which is easy to cause signal recognition errors; for high-speed communication scenarios, the transient interference caused by the jump also prolongs the signal stabilization time, reduces the communication efficiency, and even cannot meet the application requirements of vehicle-mounted signal communication which has strict requirements on timing accuracy.

[0004] Therefore, how to eliminate the common-mode voltage jump when switching between the sending or receiving mode in half-duplex AC coupled LVDS communication has become a technical problem to be solved in the field. SUMMARY

[0005] Based on the above problems, the present application provides a half-duplex signal driving circuit, a chip and a device.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] The first aspect of the embodiments of the present application provides a half-duplex signal driving circuit, comprising:

[0008] The first current source is connected to the first end of the first switch, the first end of the second switch, and the first end of the fifth switch, respectively, for providing a controlled current;

[0009] The common point between switch three and switch one is connected to the first internal termination resistance and the OUT_P pin, the other end of switch one is connected to the first current source, and the other end of switch three is connected to the second current source;

[0010] The common point between switch two and switch four is connected to the second internal termination resistance and the OUT_N pin, the other end of switch two is connected to the first current source, and the other end of switch four is connected to the second current source;

[0011] The first end of the first internal termination resistance is connected to the common point between switch three and switch one, the second end of the first internal termination resistance is connected to the first end of the second internal termination resistance, and the second end of the second internal termination resistance is connected to the common point between switch two and switch four;

[0012] The first end of switch five is connected to the first current source, and the second end is connected to the first end of the third internal termination resistance; the first end of switch six is connected to the second end of the fourth internal termination resistance, and the second end is connected to the second current source; the second end of the third internal termination resistance and the first end of the fourth internal termination resistance are connected in series to form a common mode monitoring node, the common mode monitoring node is connected to the first end of a common mode control circuit, and the second end of the common mode control circuit is connected to the first current source.

[0013] In a possible implementation, the first current source is a slave current source, and the second current source is a master current source, and the slave current source is used to provide a controlled current adjusted by the common mode control circuit.

[0014] In a possible implementation, in a receiving mode, switch one, switch two, switch three and switch four are turned off, and switch five and switch six are turned on; the current output by the slave current source flows into the third internal termination resistance through switch five, and then flows into the master current source through the common mode monitoring node, the fourth internal termination resistance and switch six in sequence; the common mode control circuit monitors the voltage through the common mode monitoring node, adjusts the current output by the slave current source, and adjusts the common mode voltage to a preset common mode voltage value.

[0015] In a possible implementation, when a differential signal 1 is transmitted, switch one and switch four are turned on, and switch two, switch three, switch five and switch six are turned off; the current output by the slave current source flows out through switch one, a first part of which flows into the master current source through the first internal termination resistance, the second internal termination resistance and switch four to form a DC bias, and a second part of which flows out through OUT_P and then flows into the master current source through OUT_N after passing through a receiving end termination resistance and switch four.

[0016] In a possible implementation, when the differential signal 0 is sent, the switch two and the switch three are turned on, and the switch one, the switch four, the switch five and the switch six are turned off. The current output from the current source flows out through the switch two. A first part of the current flows into the main current source through the first internal termination resistor, the second internal termination resistor and the switch three to form a DC bias. A second part of the current flows out through the OUT_P and flows into the main current source through the switch three after passing through the receiving end termination resistor R.

[0017] In a possible implementation, the first current source is a main current source, and the second current source is a slave current source. The slave current source is configured to provide a controlled current, which is adjusted by the common-mode control circuit.

[0018] In a possible implementation, the common-mode control circuit adjusts the first current source in the following manner:

[0019] The voltage signal of the common-mode monitoring node is obtained, and the voltage signal of the common-mode monitoring node is compared with a preset common-mode voltage. An adjustment signal is output to the first current source according to a difference between the voltage signal of the common-mode monitoring node and the preset common-mode voltage. The adjustment signal is used to instruct to adjust the output current of the first current source until the voltage of the common-mode monitoring node is stabilized at the preset common-mode voltage.

[0020] In a possible implementation, the third internal termination resistor and the fourth internal termination resistor each have a resistance of R / 2. The total resistance after being connected in series is R, which matches the resistance of an equivalent termination resistor formed by the termination resistor of the sending end and the termination resistor of the receiving end, and is used to match the total termination resistance on the signal path in the sending mode and reduce the influence of impedance fluctuation on the working point of the current source.

[0021] The second aspect of the embodiment of the application provides a chip integrated with the half-duplex signal driving circuit as described in the first aspect.

[0022] The third aspect of the embodiment of the application provides an electronic device including the chip as described in the second aspect.

[0023] Compared with the prior art, the application has the following beneficial effects:

[0024] The circuit provided in the application only has one common mode control circuit and one first current source controlled thereby. This directly discards the complex structure of two independent mechanisms in the prior art at the hardware level, and physically eliminates the common mode voltage jump caused by the inherent differences between circuit A and circuit B, such as device mismatch and reference deviation. In the transmission mode, the common mode control circuit controls the first current source to stabilize the common mode voltage by monitoring the output voltage. In the receiving mode, the monitoring point of the same common mode control circuit is naturally switched to the midpoint of the matching resistance network, and the new common mode voltage is quickly locked at the target value by adjusting the same first current source. Mode switching only changes the monitoring and control objects of the common mode control circuit, i.e. from driving external loads to driving internal matching resistors, while the control subject itself continues to work uninterruptedly and continuously. Therefore, the regulation of the common mode voltage is a continuous and smooth transition process, rather than a process of jumping from one stable state to another and then re-establishing in the prior art. This makes the common mode voltage extremely fast and the establishment time extremely short. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 The application scenario schematic diagram provided for the embodiments of the application;

[0027] Figure 2 The initial signal separation schematic diagram of the differential line signal stabilization process at the receiving end provided for the embodiments of the application;

[0028] Figure 3 The initial signal coincidence schematic diagram of the differential line signal stabilization process at the receiving end provided for the embodiments of the application;

[0029] Figure 4 The first specific circuit implementation schematic diagram of the half-duplex signal driving circuit provided for the embodiments of the application;

[0030] Figure 5 The second specific circuit implementation schematic diagram of the half-duplex signal driving circuit provided for the embodiments of the application;

[0031] Figure 6 The third specific circuit implementation schematic diagram of the half-duplex signal driving circuit provided for the embodiments of the application;

[0032] Figure 7 The first circuit implementation schematic diagram provided for the embodiments of the application;

[0033] Figure 8 A second circuit implementation schematic diagram provided for the embodiments of the present application;

[0034] Figure 9 A control signal timing diagram provided for the embodiments of the present application. DETAILED DESCRIPTION

[0035] In order to make the person skilled in the art better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor are within the protection scope of the present application.

[0036] In order to facilitate the understanding of the technical solutions provided by the embodiments of the present application, the technical terms related to the embodiments of the present application will be described first.

[0037] LVDS: low voltage differential signal, a kind of serial differential signal interface, can send or receive serial high-speed signal, low power consumption, good reliability. The amplitude of serial signal is about 100 mV~600 mV, and the common mode voltage is about 1.2 V.

[0038] Differential signal: two cables send two signals with the same amplitude but opposite trends, which constitute a differential signal, commonly known as positive (P) and negative (N).

[0039] Common mode voltage: the middle level of serial signal, for example, the highest signal is 1.5 V, and the lowest is 1 V, and the common mode is 1.25 V.

[0040] Common mode jitter: the amount of change of common mode voltage during signal transmission. If the common mode jitter is too large, it will affect the signal quality.

[0041] AC couple: AC coupling, high-speed signal transmission link uses capacitive isolation. The advantage is that the DC voltage on both sides of the capacitor cannot be communicated, only high-speed AC signal can pass through, which improves the versatility of the chips at the sending and receiving ends. Using multiple capacitive isolation can also transmit power and ground between the capacitors to supply power to the other interface.

[0042] Common mode clamping: through a feedback circuit, the common mode of the output signal is forced to be fixed at a certain set value.

[0043] Half duplex transmission: the two ends of the signal transmission line, chip A and B, can be used as sending or receiving chips. In a certain period of time, A chip sends, and B chip receives. In the next period of time, B sends, and A receives. The half duplex transmission of the signal on the same signal line is completed.

[0044] TX: transmission end;

[0045] RX: receiving end.

[0046] Rterm: termination resistance, current flowing to generate a voltage signal.

[0047] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the background art related to the embodiments of the present application will be described first.

[0048] In one possible application scenario, two LVDS interface chips are used to realize half duplex communication, and the transmission line is used to transmit power supply ground for the other party, which requires AC coupling for DC isolation.

[0049] Specifically, referring to Figure 1 , Figure 1 The application scenario provided by the embodiments of the present application is shown in the figure, which has two LVDS A and LVDS B. LVDS is a high-speed low-power signal interface technology, commonly used in scenarios requiring high-speed transmission (such as vehicle-mounted electronics). The transmission line is connected in series with a capacitor at both ends, which is used to realize AC coupling and play a role in DC isolation, while not affecting the transmission of alternating current signals (communication signals). The LVDS A side has a power supply and ground module, and the LVDS B side has a power receiving and ground receiving module, which realizes power supply for the other party during communication. This architecture is used to realize half duplex communication (only one end can send and the other end can receive at the same time, and then the direction is switched), which meets the multiple requirements of high-speed signal transmission, power supply and DC isolation in the vehicle-mounted environment.

[0050] The following analysis is based on the application scenario of half duplex communication of the AC couple link.

[0051] Half duplex communication, the LVDS interface will include sending and receiving states. To ensure stable signal transmission and reception, the common mode level of the LVDS signal must always be maintained at a fixed value. Once the common mode level is unstable or jumps, it will directly affect the normal transmission and reception of the signal. In order to ensure the normal transmission and reception of the signal, the following problems exist:

[0052] First, if the sending end does not equalize the differential line voltage before sending the signal, the P and N signals of the receiving end will be separated by the initial charging and discharging current after the sending of the signal, and an effective differential voltage cannot be formed in the initial stage, affecting the normal reception of the RX end. With the extension of time, the common-mode voltage will gradually coincide to form a differential voltage. Therefore, before sending the signal, the P and N levels of the sending end should be consistent. As shown below Figure 2 Figure 2 The initial signal separation diagram of the receiving end differential line signal stabilization process provided by the embodiment of the application. Figure 3 The initial signal coincidence diagram of the receiving end differential line signal stabilization process provided by the embodiment of the application.

[0053] Second, the receiving end needs to provide a termination voltage as the common-mode voltage of the input signal in the AC coupling mode, otherwise the unstable common-mode voltage will affect the reception effect. Third, after the sending end sends the signal and turns into the receiving end mode, the common-mode voltage in the two modes may not be equal, which will introduce common-mode voltage jump, and the establishment of the common-mode voltage may need a long stabilization time. Fourth, after the receiving end receives the signal and turns into the sending end mode, the common-mode voltage in the two modes may not be equal, which will introduce common-mode voltage jump, and the establishment of the common-mode voltage may need a long stabilization time. Fifth, the second and fourth points will affect the sending and receiving quality of the signal.

[0054] To solve these problems, the core inventive concept of the application is to completely abandon the traditional scheme of setting up independent common-mode control loops for the sending and receiving modes, and instead creatively reuse the original high-performance common-mode control circuit and current source of the sending end, so that it continues to work in the receiving mode, thereby providing a fixed, fast and jump-free common-mode voltage in the mode switching process.

[0055] ​Directly use the original common mode clamping circuit of the sending end, continue to play a role in the receiving mode - when sending, the circuit stabilizes the common mode voltage of the sending signal; when receiving, reuse the same circuit to provide the receiving end with a common mode level reference identical to the sending mode. Since a set of circuits is shared, the reference difference caused by two independent common mode control circuits is avoided, realizing the undifferentiated conversion of the common mode voltage between TX and RX modes, and eliminating the common mode jump during mode switching from the root. With the strong charging and discharging capability of the sending end drive circuit itself, the charging demand of the common mode voltage is quickly responded during the mode switching process. When the common mode voltage needs to be adjusted when switching from TX to RX or vice versa, the TX drive circuit can provide sufficient current to complete fast charging and discharging, greatly shortening the establishment time of the common mode voltage and avoiding signal transmission abnormalities caused by long stabilization time. Therefore, without adding additional complex circuits, the application ensures the consistency of the TX / RX mode common mode voltage and realizes the rapid stabilization of the common mode voltage, effectively solves the influence of mode switching on signal quality, and improves the reliability of half-duplex AC coupling communication.

[0056] It should be noted that the half-duplex signal drive circuit, system, product, device and medium provided by the application can be applied to the field of communication technology. The above is only an example and does not limit the application of the half-duplex signal drive circuit, system, product, device and medium provided by the application.

[0057] In order to make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0058] The half-duplex signal drive circuit provided by the application is described below through an embodiment. Referring to Figure 4 , the Figure 4 The first specific circuit implementation schematic diagram of the half-duplex signal drive circuit provided by the embodiments of the application is shown in the figure, which mainly includes the following core components:

[0059] Switch one, switch two, switch three and switch four, which constitute a first switch group, are core drive switches, used to switch the current path to output differential signals "1" or "0" in the sending mode. Switch five and switch six, which constitute a second switch group, are used to connect the matching resistance network to the circuit in the receiving mode.

[0060] The first internal termination resistor R and the second internal termination resistor R are located inside the chip and form a current path together with external resistors in the transmitting mode. The third internal termination resistor R / 2 and the fourth internal termination resistor R / 2 are connected in series and have a resistance of R / 2, are connected through switches five and six in the receiving mode, are used for simulating the load in the transmitting mode, and provide a common-mode termination voltage for the input signal. The common-mode control circuit monitors the voltage at the output end, and always stabilizes the output common-mode voltage at a preset value (such as 1.2 V) by adjusting the current source. OUT_P and OUT_N are the differential signal output / input pins of the circuit. It should be noted that LVDS must be used in pairs, that is, a transmitting end and a receiving end are required, and the transmitting end and the receiving end each have a set of R+R termination resistors, that is, 2R. After the link is formed, the 2R of the transmitting end and the receiving end is actually in parallel connection, and the total effect after the parallel connection is R, so two R / 2 are used in series here, and the purpose is to match the total termination resistance value on the signal path in the transmitting mode, and to reduce the influence of impedance fluctuation on the working point of the current source.

[0061] Regarding the connection relationship, the first current source is connected to the first end of switch one, the first end of switch two, and the first end of switch five, and is used for providing a controlled current; a common point between switch three and switch one is connected to the first internal termination resistor and the OUT_P pin, the other end of switch one is connected to the first current source, and the other end of switch three is connected to the second current source; a common point between switch two and switch four is connected to the second internal termination resistor and the OUT_N pin, the other end of switch two is connected to the first current source, and the other end of switch four is connected to the second current source; the first end of the first internal termination resistor is connected to the common point between switch three and switch one, the second end of the first internal termination resistor is connected to the first end of the second internal termination resistor, and the second end of the second internal termination resistor is connected to the common point between switch two and switch four; the first end of switch five is connected to the first current source, and the second end is connected to the first end of the third internal termination resistor; the first end of switch six is connected to the second end of the fourth internal termination resistor, and the second end is connected to the second current source; the second end of the third internal termination resistor and the first end of the fourth internal termination resistor are connected in series to form a common-mode monitoring node, the common-mode monitoring node is connected to the first end of the common-mode control circuit, and the second end of the common-mode control circuit is connected to the first current source.

[0062] In a possible implementation, referring to Figure 5 , Figure 5 is a second specific circuit implementation schematic diagram of the half-duplex signal driving circuit of the embodiment of the present application, the first current source is a slave current source, the second current source is a master current source, the slave current source is used for providing a controlled current and is adjusted by a common-mode control circuit. In a possible implementation, referring to Figure 6 , Figure 6For the third specific circuit implementation of the half-duplex signal driving circuit of the embodiments of the present application, the first current source is the main current source, and the second current source is the slave current source, which is used to provide a controlled current adjusted by the common-mode control circuit. Figure 5 and Figure 6 The two different architectures shown differ in the position of the main and slave current sources. The main current source is used to provide the main current required for driving the differential signal. The slave current source is adjusted by the common-mode control circuit and is used to accurately control the common-mode voltage. It needs to be explained that, Figure 5 and Figure 6 In the two cases, the internal termination resistors are denoted by the resistance values R and R / 2, respectively, Figure 5 and Figure 6 The settings of other working modules in the two cases are described in the foregoing Figure 4 related description, which will not be repeated here.

[0063] Regarding the different modes of the circuit:

[0064] First, when transmitting a differential "1" signal, the switch one control signal control one is high, the switch four control signal control four is high, the switch one and the switch four are turned on, and the other control signals are low, and the other switches are turned off. That is, the switch one and the switch four are turned on, and the switch two, the switch three, the switch five, and the switch six are turned off.

[0065] After the current flows out from the power supply through the switch one, it is divided into two paths:

[0066] Internal path (DC biasing): flows through the internal termination resistor R, passes through the switch four downward, flows into the main current source to the ground, and forms a DC biasing.

[0067] External path (signal path): flows out from the OUT_P pin, passes through the external transmission line and the termination resistor R of the receiving end, flows into the OUT_N pin, and then flows into the main current source to the ground through the switch four. The OUT_P and the OUT_N form a differential "1" signal.

[0068] Second, when transmitting a differential "0" signal, the control signals "control two and control three" are high, that is, the switch two and the switch three are turned on, and the switch one, the switch four, the switch five, and the switch six are turned off.

[0069] After the current flows out through the switch two, it is divided into two paths:

[0070] The current flows out from the switch two, part of which flows into the main current source through the internal termination resistor R and the switch three, forming a DC biasing.

[0071] The other part flows out from the OUT_P terminal, passes through the termination resistor R of the receiving end, flows into the OUT_N terminal, and then flows into the main current source through the switch three.

[0072] Third, the receiving mode.

[0073] The control signals of switch one, switch two, switch three, and switch four are all 0, and the four switches are all turned off. The control signals of switch five and switch six are control five and control six, which are high, that is, switch five and switch six are turned on, and two R / 2 resistors are connected in series between switch five and switch six, and the total resistance value matches the termination resistance R in the transmission mode, R / 2+R / 2=R.

[0074] The common-mode control circuit is used to control the current source, so that the common-mode level is maintained at 1.2V. Since a common-mode control circuit is used, the circuit will not be turned off in the receiving mode, and the operating point of the circuit will not change significantly, thereby realizing fast switching between the transmission and receiving modes.

[0075] Referring to Figure 7 , Figure 7 The first circuit implementation schematic provided by the embodiment of the application is shown in the figure, and the most core device is an operational amplifier. Its function is to serve as a high-gain comparator and error amplifier. The non-inverting input terminal (+) is connected to a ReferenceVoltage (reference voltage). This is a very stable and accurate DC voltage source, and its value is set to the common-mode voltage target value required by the system, for example, 1.2V. The inverting input terminal (-) is connected to the common-mode feedback voltage from the output stage. This voltage is obtained by sampling the average value (i.e., the common-mode voltage) of the differential output terminals (for example, OUT_P and OUT_N) of the circuit. In Figure 6 or Figure 5 the complete architecture, this point is usually the midpoint of the series connection of the matching resistors R / 2. The output terminal of the operational amplifier is directly connected to the control terminal of the current source.

[0076] The circuit monitors the common-mode voltage (V_cm_fb) of the output terminal in real time. The operational amplifier compares the sampled common-mode voltage (V_cm_fb) with the accurate reference voltage (V_ref). If V_cm_fbV_ref, the operational amplifier outputs an increased control voltage, so that the current provided by the current source increases, thereby pulling up the output common-mode voltage. If V_cm_fb>V_ref, the operational amplifier outputs a decreased control voltage, so that the current provided by the current source decreases, thereby pulling down the output common-mode voltage. Through this continuous negative feedback adjustment process, the operational amplifier will force V_cm_fb to be infinitely close to V_ref, thereby accurately and stably locking the output common-mode voltage at the target value (1.2V).

[0077] Referring to Figure 8 , Figure 8 The second circuit implementation schematic provided by the embodiment of the application is shown in the figure, and it needs to be explained that, Figure 8 the principle of the common-mode feedback control loop shown in the figure, the components and working principle thereof are the same as those of the first circuit implementation schematicFigure 7 The same, the core device is an operational amplifier (opamp), as a high-gain error comparator, is the control core of the feedback loop. The non-inverting input (+) is connected to the Reference Voltage (reference voltage). This voltage is the target common-mode voltage set by the system, for example, 1.2V. The inverting input (-) is connected to the common-mode feedback voltage sampled from the output of the circuit. The output of the operational amplifier is connected to the control end of the current source. This is a standard voltage negative feedback system, and its working process is as follows: real-time monitoring of the output common-mode voltage. The operational amplifier compares the sampled common-mode voltage with the reference voltage to obtain the error value. After amplifying the error value, the output control signal is output to adjust the current of the current source. Through closed-loop control, the output common-mode voltage is forced to always track and stabilize at the reference voltage value.

[0078] Reference Figure 9 , Figure 9 A control signal timing diagram provided by the embodiment of the present application corresponds to Figure 8 、 Figure 9 The timing control of the circuit is used to illustrate the switching logic of the circuit between the transmission mode (tx_mode) and the reception mode (rx_mode), and the specific content is as follows:

[0079] tx_mode_en is a transmission mode enable signal, and when it is at a high level, the tx_mode (transmission mode) is entered, and when it is at a low level, the rx_mode (reception mode) is entered. IC_P and IC_N are used to control the signals of the PMOS switch and the NMOS switch.

[0080] In the transmission mode (tx_mode), IC_P is at a high level and IC_N is at a low level, at this time, the PMOS switch and the NMOS switch are disconnected, and the circuit enters the transmission state, and outputs the differential signal from the OUT_P / OUT_N pin.

[0081] In the reception mode (rx_mode), IC_P is at a low level and IC_N is at a high level, at this time, the PMOS switch and the NMOS switch are turned on, the matching resistance network is connected, and the circuit enters the reception state, and is ready to receive the external differential signal. Therefore, the timing diagram directly reflects the control signal timing of the "transmission→reception" mode switching of the half-duplex circuit, and the switching of the transmission / reception path is realized through the level change of IC_P and IC_N, thereby guaranteeing the logical integrity of the half-duplex communication.

[0082] In summary, the embodiment of the present application has the following beneficial effects:

[0083] The application adds a load matching circuit composed of switch five, switch six and two R / 2 resistors in the original LVDS driving architecture. The additional circuit structure is extremely simple, only two switch elements and two small resistance resistors need to be added on the basis of the existing mature circuit layout, without introducing complex active modules. This makes the incremental chip area cost of the application minimized, greatly saving the manufacturing cost. At the same time, the matching resistance network structure is symmetrical, easy to realize accurate matching in circuit layout design, which is beneficial to improve the stability of common mode signal, and further improve the performance consistency of the circuit.

[0084] The core advantage of the application is that in the sending and receiving modes, the same set of high-performance common mode control circuit and current source is reused to maintain the stability of the common mode voltage. This method discards the complex scheme of using two independent common mode control loops in the prior art. Therefore, it fundamentally eliminates the problems of common mode level jump and long establishment time caused by the mismatch of the two control loops, ensuring the rapid and smooth transition of the common mode voltage during mode switching. This not only simplifies the overall architecture of the circuit, greatly reduces the design difficulty and verification cost, but also improves the reliability of the system.

[0085] In cooperation with the above-mentioned circuit architecture, the application provides a simple and clear timing control logic. By switching between the sending mode and the receiving mode through specific control signals (such as IC_P and IC_N), the control logic is direct, reliable and easy to integrate, ensuring the correct execution of the circuit function and the reliable switching of the mode.

[0086] Therefore, the application successfully solves the common mode voltage stability problem caused by mode switching in the AC coupled half-duplex link through simple and ingenious circuit improvement and system architecture reuse, while achieving a balance in chip area, design complexity and performance, which is suitable for cost, area and power sensitive application scenarios.

[0087] Based on any of the above embodiments, the application also provides a chip and an electronic device.

[0088] The chip integrates the half-duplex signal driving circuit as described above on the same silicon wafer through a semiconductor integrated circuit manufacturing process. The circuit, as the interface core of the chip, is connected to the pins of the chip through its differential output terminals (OUT_P and OUT_N) for high-speed half-duplex communication with external systems. Due to the simple structure, small size and fast common mode switching of the driving circuit, the chip containing the circuit has the advantages of low cost and high reliability while realizing high-performance interface functions.

[0089] An electronic device, for example, can be an in-vehicle audio bus device, a high-speed data acquisition module, or a communication terminal, which comprises the chip as described above. The chip serves as a communication interface of the device, responsible for transmitting and receiving data with external devices. Thanks to the excellent common-mode stability performance of the internal drive circuit of the chip in the AC-coupled half-duplex link, the electronic device can maintain low bit error rate and stable signal quality in complex communication environment.

[0090] It should be noted that the various embodiments described in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0091] It should be understood that in this application, at least one (item) refers to one or more, and more refers to two or more. And / or is used to describe the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The characters / generally represent the relationship between the associated objects before and after them. The following at least one (item) or similar expressions refer to any combination of these items, including any combination of single (item) or multiple (item). For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0092] It should be understood that the terms center, longitudinal, transverse, upper, lower, front, rear, left, right, vertical, horizontal, top, bottom, inner, outer, and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0093] It should be noted that unless otherwise explicitly specified and limited, the terms mounting, connecting, and connecting should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between the two elements inside. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0094] It is also to be noted that, as used in the specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless otherwise indicated. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or "contains" are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as an aid in

[0095] The embodiments disclosed herein can each be implemented as a method, apparatus, or article of manufacture using programming instructions. The embodiments disclosed herein can be implemented using software, firmware, hardware, or a combination thereof. The embodiments disclosed herein can be implemented in a computer system that includes one or more processors that are configured with instructions that, once implemented in hardware, cause the computer system to carry out the steps described herein. The instructions can be stored on a computer readable medium, such as a floppy disk, a hard disk, a CD-ROM, a DVD, a memory, a solid state drive, or a magnetic tape. The instructions can also be downloaded from the Internet. The instructions can be implemented in a plurality of languages, including machine code, assembly code, high level languages, and / or interpreted code.

[0096] The above description of disclosed embodiments provides enough information to enable one of ordinary skill in the art to practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Accordingly, the application is not to be restricted based on the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A half-duplex signal driving circuit, characterized in that, include: The first current source is connected to the first terminal of switch one, the first terminal of switch two, and the first terminal of switch five, respectively, to provide controlled current. The common point between switch three and switch one is connected to the first internal terminating resistor and the OUT_P pin. The other end of switch one is connected to the first current source, and the other end of switch three is connected to the second current source. The common point between switch 2 and switch 4 is connected to the second internal termination resistor and the OUT_N pin. The other end of switch 2 is connected to the first current source, and the other end of switch 4 is connected to the second current source. The first end of the first internal termination resistor is connected to the common point between switch three and switch one. The second end of the first internal termination resistor is connected to the first end of the second internal termination resistor. The second end of the second internal termination resistor is connected to the common point between switch two and switch four. The first end of switch five is connected to the first current source, and the second end is connected to the first end of the third internal terminating resistor; the first end of switch six is ​​connected to the second end of the fourth internal terminating resistor, and the second end is connected to the second current source; the second end of the third internal terminating resistor and the first end of the fourth internal terminating resistor are connected in series to form a common-mode monitoring node, the common-mode monitoring node is connected to the first end of the common-mode control circuit, and the second end of the common-mode control circuit is connected to the first current source.

2. The half-duplex signal driving circuit according to claim 1, characterized in that, The first current source is a slave current source, and the second current source is a master current source. The slave current source is used to provide controlled current, which is regulated by a common-mode control circuit.

3. The half-duplex signal driving circuit according to claim 2, characterized in that, In receive mode, switches 1, 2, 3, and 4 are off, while switches 5 and 6 are on. The current output from the current source flows through switch 5 into the third internal termination resistor, and then sequentially through the common-mode monitoring node, the fourth internal termination resistor, and switch 6 into the main current source. The common-mode control circuit monitors the voltage through the common-mode monitoring node, adjusts the current output from the current source, and adjusts the common-mode voltage to the preset common-mode voltage value.

4. The half-duplex signal driving circuit according to claim 2, characterized in that, When differential signal 1 is sent, switches 1 and 4 are turned on, while switches 2, 3, 5 and 6 are turned off. The current output from the current source flows out through switch 1. The first part flows into the main current source through the first internal termination resistor, the second internal termination resistor, and switch 4 to form a DC bias. The second part flows out through OUT_P, flows into the OUT_N terminal after passing through the receiving terminal termination resistor, and flows into the main current source through switch 4.

5. The half-duplex signal driving circuit according to claim 2, characterized in that, When the differential signal 0 is sent, switches 2 and 3 are turned on, while switches 1, 4, 5, and 6 are turned off. The current output from the current source flows out through switch 2. The first part flows through the first internal termination resistor, the second internal termination resistor, and switch 3 into the main current source to form a DC bias. The second part flows out through OUT_P, passes through the receiving end termination resistor R, and then flows into the OUT_N terminal, and then into the main current source through switch 3.

6. The half-duplex signal driving circuit according to claim 1, characterized in that, The first current source is the main current source, and the second current source is the slave current source. The slave current source is used to provide controlled current, which is regulated by the common-mode control circuit.

7. The half-duplex signal driving circuit according to claim 1, characterized in that, The common-mode control circuit adjusts the first current source in the following ways: The voltage signal of the common-mode monitoring node is acquired, and the voltage signal of the common-mode monitoring node is compared with a preset common-mode voltage. Based on the difference between the voltage signal of the common-mode monitoring node and the preset common-mode voltage value, an adjustment signal is output to the first current source. The adjustment signal is used to indicate the adjustment of the output current of the first current source until the voltage of the common-mode monitoring node stabilizes at the preset common-mode voltage value.

8. The half-duplex signal driving circuit according to claim 1, characterized in that, The resistance values ​​of the third and fourth internal termination resistors are both R / 2, and the total resistance after being connected in series is R. This resistance matches the equivalent termination resistance formed by connecting the termination resistors of the transmitting end and the receiving end in parallel. This is used to match the total termination resistance value on the signal path in the transmission mode, thereby reducing the impact of impedance fluctuations on the operating point of the current source.

9. A chip, characterized in that, It integrates a half-duplex signal driving circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

Images