Ethernet service data interleaving method and chip

Abstract

The application provides an Ethernet service data interleaving method and a chip. The method comprises the following steps: a PCS input generation module processes acquired upstream data and outputs a plurality of first PCS channel signals; a data interleaving module processes the plurality of first PCS channel signals and outputs interleaved data; and a PMA data sending module processes the interleaved data and outputs first serial data. The interleaved data comprises a plurality of data units with the same bit width. The bit value of each position of the data unit is from the same bit sequence of different first PCS channel signals. The bit values of all the same positions between two adjacent data units are from different first PCS channel signals. The application disperses errors to the corresponding first PCS channel signals of each pcs channel, thereby improving the overall error correction capability of the data link. The chip can accept higher channel loss, the tolerance to power supply noise and crosstalk is improved, and the number of PCB layers or material cost is reduced.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of communication, in particular to an Ethernet service data interleaving method and a chip. BACKGROUND

[0002] In an Ethernet physical layer (PHY) architecture, a physical coding sublayer (PCS) is mainly responsible for data coding / decoding, scrambling / descrambling and providing a media-independent interface function, a physical medium attachment sublayer (PMA) is mainly responsible for high-speed data serialization / deserialization (SerDes function) processing, and a physical medium dependent sublayer (PMD) is mainly responsible for processing specific signal transmission details and ensuring that data can be reliably stored on different types of physical media. The three closely cooperate, when data is sent, the PCS layer transmits parallel data to the PMA layer after completing service data coding, the PMA layer converts the parallel data into a high-speed serial signal and then transmits the high-speed serial signal to the PMD layer, and the PMD layer drives the signal to be transmitted through a physical medium. When data is received, the reverse processing procedure is performed, and the three together constitute a complete physical layer function.

[0003] The PMA layer is responsible for bit multiplexer (bit_mux) interleaving and multiplexing the data of multiple pcs lanes output by the PCS layer through bit multiplexer (bit_mux) into a physical lane. Taking the bit_mux in the data sending direction as an example, 4:1 is taken as an example, that is, 4 pcs lanes of 25G need to form a pma lane of 100G through bit_mux logic, and the data bit width of each pcs lane is 10 bits. The data of the first pcs lane pcs0_lane is a0a1a2a3a4a5a6a7a8a9, the data of the second pcs lane pcs1_lane is b0b1b2b3b4b5b6b7b8b9, the data of the third pcs lane pcs2_lane is c0c1c2c3c4c5c6c7c8c9, and the data of the fourth pcs lane pcs3_lane is d0d1d2d3d4d5d6d7d8d9. The data of the pma lane obtained after the bit_mux is a0b0c0d0a1b1c1d1a2b2c2d2a3b3c3d3a4b4c4d4a5b5c5d5a6b6c6c6d6a7b7c7d7a8b8c8d8a9b9c9d9, as shown in FIG. 1. Figure 1, data of same color represents from same pcs lane, for example, data of yellow represents from 1st pcs lane, data of blue represents from 2nd pcs lane, data of cyan represents from 3rd pcs lane, data of orange represents from 4th pcs lane, it can be seen that data of fixed data bit in each period of pma lane is from same pcs lane. For example, 1st data a0 in data of 1st period is yellow, from 1st pcs lane, 1st data a1 in data of 2nd period is yellow, from 1st pcs lane, 1st data a9 in data of 10th period is yellow, also from 1st pcs lane. For example, 2nd data b0 in data of 1st period is blue, from 2nd pcs lane, 2nd data b8 in data of 9th period is blue, from 2nd pcs lane, 2nd data b9 in data of 10th period is blue, also from 2nd pcs lane.

[0004] However, there may be error codes in data transmission and reception. According to the error code distribution characteristics, it can be divided into random error, burst error and periodic error. Random error means that each bit error is independent, and the probability distribution is uniform, which is usually caused by thermal noise, quantization noise, etc. For example, in the AWGN (Additive White Gaussian Noise) channel, the randomness of noise leads to single bit error. Burst error means that multiple consecutive bits are simultaneously error in a short time, which is common in scenarios such as multipath fading of wireless channel, clock drift, etc. For example, continuous bit error is caused by interference waveband intrusion of wireless signal. Periodic error is caused by various factors, including external periodic interference sources (such as ground problems caused by alternating current noise), clock synchronization error (such as phase-locked loop jitter, data-dependent jitter, and unstable clock recovery at the receiving end), signal reflection (waveform distortion caused by discontinuous transmission line impedance), channel attenuation (insufficient equalization in long-distance transmission), and environmental interference (such as temperature drift or power supply noise fluctuation).

[0005] Periodic error is particularly significant in ultra-high-speed SerDes, and is currently the core technical problem that puzzles the industry. Periodic error will cause the overall system error rate to rise, which may exceed the design tolerance (such as the error rate from 1e -12 to 1e -9), affecting the reliability of data transmission. If the error code triggers the retransmission mechanism (such as Retry of PCIe or FEC error correction of Ethernet), it will cause the actual available throughput to decrease. Periodic errors are not only a signal integrity problem, but also may trigger a chain reaction of protocol, clock, and system reliability. Its concealment and periodicity make it more difficult to diagnose than random errors, and it needs to be analyzed and solved comprehensively in time domain, frequency domain, and protocol layer. For example, the above bit mux outputs in a 4:1 manner, which cannot effectively deal with the problem of periodic error occurrence, and may cause the problem of error after the bit mux, that is, the periodic error occurs on the same pcs channel, which causes the pcs bit error rate to be too high to effectively correct errors, and finally causes the data link transmission to be abnormal and cannot communicate normally. For example, in the design of 56G PAM4 SerDes, periodic errors (interval 1us) caused by 1MHz power supply switching ripple coupling to CDR circuit are observed, which causes the bit error rate (BER) to be as high as 1e -6 and the basic forward error correction (FEC) cannot be corrected. The temporary measure is to reduce the bit error rate to 1e -12 , and the long-term solution is to completely eliminate the noise source by optimizing the power tree layout, and finally remove the FEC to reduce power consumption. SUMMARY

[0006] The first object of the present application is to provide an Ethernet service data interleaving method which can reduce data transmission errors.

[0007] The second object of the present application is to provide a chip for implementing the above-mentioned Ethernet service data interleaving method.

[0008] The third object of the present application is to provide another chip for implementing the above-mentioned Ethernet service data interleaving method.

[0009] In order to achieve the first object, the present application provides an Ethernet service data interleaving method, which comprises: a PCS input generation module processing the obtained upstream data and outputting a plurality of first PCS channel signals; a data interleaving module processing the output of the plurality of first PCS channel signals and outputting interleaved data; and a PMA data sending module processing the interleaved data and outputting first serial data; wherein the interleaved data comprises a plurality of data units with the same bit width, the bit value of each position of the same data unit comes from the same bit sequence of different first PCS channel signals, and the bit values of all the same positions between adjacent two data units come from different first PCS channel signals.

[0010] From the above scheme, it can be seen that the interleaved data is dispersed to the corresponding first PCS channel signal of each pcs channel, thereby improving the error correction capability of the whole data link, because the bit value of each position of each data unit of the interleaved data comes from different first PCS channel signals, and the bit value of all the same positions between adjacent two data units comes from different first PCS channel signals. Because the error correction capability is improved, the chip allows higher channel loss, the tolerance to power noise and crosstalk is also improved, and the number of PCB layers or material cost can be reduced.

[0011] A further scheme is that for the shifted data unit obtained by circularly shifting one data unit by one position, there is an adjacent data unit adjacent to the shifted data unit, and the bit values of all the same positions of the adjacent data unit and the shifted data unit come from the same first PCS channel signal.

[0012] It can be seen that the two adjacent data units only differ by one position, which facilitates the parsing of the first serial data obtained by the interleaved data.

[0013] A further scheme is that when the data interleaving module processes the interleaved data output by the plurality of first PCS channel signals, the data interleaving module comprises: a first selection circuit unit of the data interleaving module acquires the plurality of first PCS channel signals, and a first channel selection control unit of the data interleaving module controls the first selection circuit unit to select the output according to the set first data routing table, to obtain the interleaved data.

[0014] It can be seen that it can be directly realized according to the set first data routing table, which is convenient to implement.

[0015] A further scheme is that the number of cells in each row of the first data routing table corresponds to the bit width of the data unit, and the value of the cell indicates the corresponding first PCS channel signal.

[0016] It can be seen that the first data routing table can be conveniently set.

[0017] A further scheme is that the first selection circuit unit comprises a first selection matrix circuit same as the number of first PCS channel signals, and the first selection matrix circuit comprises a first multiplexer, and the input end of the first multiplexer is uniquely corresponding to one first PCS channel signal.

[0018] It can be seen that each first PCS channel signal is directly output through a separate first selection matrix circuit, thereby improving the data processing efficiency.

[0019] A further scheme is that the number of first PCS channel signals is 8; the number of first selection matrix circuits is 8, and the first multiplexer is an 8-to-1 multiplexer.

[0020] Further, the PMA data receiving module processes the obtained second serial data to output parallel data; the data deinterleaving module processes the parallel data to output a plurality of second PCS channel signals; and the PCS output generating module processes the second PCS channel signals to output downstream data.

[0021] Further, the second selection circuit unit of the data deinterleaving module obtains the parallel data, and the second channel selection control unit of the data deinterleaving module controls the second selection circuit unit to select and output according to a set second data routing table, thereby obtaining a plurality of second PCS channel signals.

[0022] Therefore, the error in the data receiving process can be reduced, and the error correction capability can be improved.

[0023] To achieve the above-mentioned second object, the application provides a chip, which comprises a PCS input generating module, a data interleaving module and a PMA data sending module; the PCS input generating module is connected to the data interleaving module, and the data interleaving module is connected to the PMA data sending module; and the PCS input generating module, the data interleaving module and the PMA data sending module cooperate to realize the above-mentioned Ethernet service data interleaving method.

[0024] To achieve the above-mentioned third object, the application provides a chip, which comprises a data sending module and a data receiving module; the data sending module comprises a PCS input generating module, a data interleaving module and a PMA data sending module; the PCS input generating module is connected to the data interleaving module, and the data interleaving module is connected to the PMA data sending module; the data receiving module comprises a PCS output generating module, a data deinterleaving module and a PMA data receiving module; the PCS output generating module is connected to the data deinterleaving module, and the data deinterleaving module is connected to the PMA data receiving module; and the data sending module and the data receiving module realize the above-mentioned Ethernet service data interleaving method. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a schematic diagram of a data interleaving method of the prior art.

[0026] Figure 2 is a schematic diagram of a physical layer chip in an embodiment of the application.

[0027] Figure 3 is a specific schematic diagram of a data sending module in an embodiment of the application.

[0028] Figure 4 is a structural diagram of a first selection matrix circuit in an embodiment of the application.

[0029] Figure 5 is a specific schematic diagram of a data receiving module in an embodiment of the application.

[0030] Figure 6 is a schematic diagram of the interleaved data in the embodiment of the present application.

[0031] The present application will be further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0032] The Ethernet service data interleaving method of the present application disperses the error code to each pcs channel by interleaving the signals of each pcs channel, thereby improving the error correction capability. The present application also provides a physical layer chip for implementing the above method.

[0033] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0034] Referring to Figure 2 The physical layer chip 100 of the present embodiment comprises a data sending module 10 and a data receiving module 20. The data sending module 10 is used for encoding and modulating the data from the MAC layer and sending the data out through the physical medium. The data receiving module 20 is used for receiving the signal from the physical medium, demodulating and decoding the signal and then transferring the signal to the MAC layer.

[0035] Referring to Figure 3 The data sending module 10 comprises a PCS input generating module 101, a data interleaving module and a PMA data sending module 102. The data interleaving module comprises a first selection circuit unit 1031 and a first channel selection control unit 1032. The PCS input generating module is connected to the first selection circuit unit 1031 of the data interleaving module. The first channel selection control unit 1032 of the data interleaving module is connected to the first selection circuit unit 1031. The first selection circuit unit 1031 is connected to the PMA data sending module 102.

[0036] The PCS input generating module 101 is used for processing the obtained upstream data and outputting a plurality of first PCS channel signals to the data interleaving module. The data interleaving module is used for processing the plurality of first PCS channel signals and outputting interleaved data to the PMA data sending module 102. The PMA data sending module 102 processes the interleaved data and outputs first serial data. The first serial data is then sent through the physical medium. In this way, the data sending function of the data sending module 10 is realized.

[0037] The interleaved data comprises a plurality of data units with same bit width, and the bit value of each position of the data unit is from the value on the same bit sequence of different first PCS channel signals, and the bit values of all the same positions between adjacent two data units are from different first PCS channel signals. For adjacent first and second data units, the bit values of all the same positions of the first data unit after cyclic shift by one position are from the same first PCS channel signal as the second data unit.

[0038] The first selection circuit unit 1031 obtains a plurality of first PCS channel signals, and the first channel selection control unit 1032 controls the first selection circuit unit 1031 to select and output according to the set first data routing table, to obtain the interleaved data. The number of cells in each row of the first data routing table corresponds to the bit width of the data unit, and the value of the cell indicates a specific first PCS channel signal.

[0039] The first selection circuit unit 1031 comprises a plurality of first selection matrix circuits corresponding to the number of first PCS channel signals. The first selection matrix circuit comprises a first multiplexer, and the input end of the first multiplexer corresponds to one first PCS channel signal, so that the specific value in the corresponding first PCS channel signal is selected and output.

[0040] Referring to Figure 4 , the first selection matrix circuit comprises a plurality of inputs and a plurality of outputs, and a multiplexer is arranged at each output, and the output of the first selection matrix circuit corresponds to the output end of the corresponding multiplexer. After one first PCS channel signal enters the first selection matrix circuit, each bit of the first PCS channel signal enters the input end of each multiplexer, and each multiplexer selects and outputs according to the routing information of the first data routing table. For example, with 1 byte as the granularity, one first selection matrix circuit comprises 8 inputs and 8 outputs, and 1 8-to-1 multiplexer is arranged at each output, and the data corresponding to each input is a0, a1, a2, a3, a4, a5, a6, and a7, respectively. Therefore, the required data can be selected according to the routing information.

[0041] Referring to Figure 5 , the data receiving module 20 comprises a PCS output generation module 201, a data deinterleaving module, and a PMA data receiving module 202, and the data deinterleaving module comprises a second selection circuit unit 2031 and a second channel selection control unit 2032. The PCS output generation module 201 is connected to the second selection circuit unit 2031 of the data deinterleaving module, the second channel selection control unit 2032 of the data deinterleaving module is connected to the second selection circuit unit 2031, and the second selection circuit unit 2031 is connected to the PMA data receiving module 202.

[0042] The PCS output generation module 201 is configured to process the second serial data obtained through the physical medium and output parallel data. The deinterleaving module processes the parallel data and outputs a plurality of second PCS channel signals. The PCS output generation module 201 receives and processes the second PCS channel signals and finally outputs downstream data. In this way, the data transmission function of the data receiving module 20 is realized.

[0043] The first serial data is serial data transmitted by the physical layer chip to the outside, and the second serial data is serial data received by the physical layer chip from the outside. In actual application, the specific data content of the first serial data and the second serial data is determined by the data actually required to be transmitted by the physical layer chip. For example, taking data transmission between computer A and computer B as an example, computer A transmits data to computer B and receives data transmitted by computer B through the physical layer chip of the embodiment. Specifically, the upstream data generated by computer A is transmitted to computer B in the form of first serial data through the physical layer chip of the embodiment, and the data transmitted by computer B enters the physical layer chip of the embodiment in the form of second serial data to form downstream data, which is received by computer A.

[0044] The second selection circuit unit 2031 obtains the parallel data, and the second channel selection control unit 2032 controls the second selection circuit unit to select and output according to the set second data routing table, to obtain a plurality of second PCS channel signals.

[0045] The second selection circuit unit 2031 includes a second selection matrix circuit with the same number of parallel unit data as the number of parallel unit data in the parallel data. The second selection matrix circuit includes a second multiplexer, and the input end of the second multiplexer uniquely corresponds to one parallel unit data, so as to select and output the specific value in the corresponding parallel unit data.

[0046] The second selection matrix circuit is similar to the first selection matrix circuit, and also includes a plurality of inputs and a plurality of outputs, and a multiplexer is arranged at each output. The output of the second selection matrix circuit is the output end of the corresponding multiplexer.

[0047] In the embodiment, taking 200GE service data transmission as an example, the number of first PCS channel signals is 8, the bit width of the data unit is 8 bits, the number of first selection matrix circuits is 8, the first multiplexer is an 8-to-1 multiplexer, the number of second PCS channel signals is 8, the bit width of the parallel unit data is 8 bits, the number of second selection matrix circuits is 8, and the second multiplexer is an 8-to-1 multiplexer.

[0048] The following will continue to combine Figure 3 The data transmission process will be described in detail.

[0049] Referring to Figure 3 The PCS input generation module 101 obtains upstream data from the MAC layer, processes to form a plurality of parallel data, i.e., a plurality of first PCS channel signals, and outputs the first PCS channel signals to a plurality of pcs channels respectively. The first PCS channel signal corresponding to the signal of the first pcs channel is denoted as pcs_ln0, the first PCS channel signal corresponding to the signal of the second pcs channel is denoted as pcs_ln1, and so on, and the first PCS channel signal corresponding to the signal of the eighth pcs channel is denoted as pcs_ln7.

[0050] Specifically, the data of pcs_ln0 is a0, a1, a2, a3, a4, a5, a6, and a7; the data of pcs_ln1 is b0, b1, b2, b3, b4, b5, b6, and b7; the data of pcs_ln2 is c0, c1, c2, c3, c4, c5, c6, and c7; the data of pcs_ln3 is d0, d1, d2, d3, d4, d5, d6, and d7; the data of pcs_ln4 is e0, e1, e2, e3, e4, e5, e6, and e7; the data of pcs_ln5 is f0, f1, f2, f3, f4, f5, f6, and f7; the data of pcs_ln6 is g0, g1, g2, g3, g4, g5, g6, and g7; and the data of pcs_ln7 is h0, h1, h2, h3, h4, h5, h6, and h7.

[0051] The data interleaving module selects and outputs the signals of the plurality of PCS channel signals according to a set first data routing table. Referring to Table 1, the first data routing table of the present embodiment is an 8*8 cell, and the value of each cell indicates that the corresponding interleaved data is derived from which pcs channel. For example, the element corresponding to the first row and the first column is 1, which indicates that the data corresponding to the first row and the first column in the interleaved data is derived from the first pcs channel, so that the first channel selection control unit controls the output of the first 8-to-1 selector bit_mux(8:1) in the selection matrix circuit BIT_MUX #0 according to the output of the corresponding routing information; for example, the element corresponding to the fifth row and the sixth column is 2, which indicates that the data corresponding to the fifth row and the sixth column in the interleaved data is derived from the second pcs channel, so that the first channel selection control unit controls the output of the first 8-to-1 selector bit_mux(8:1) in the selection matrix circuit BIT_MUX #1 according to the output of the corresponding routing information. The number of cells in each row corresponds to the bit width of the data unit, and the number of cells in each row in the present embodiment is 8, and the bit width of the data unit is 8 bits.

[0052] Table 1. First data routing table

[0053]

[0054] After the data interleaving module completes the data interleaving according to the first data routing table of Table 1, the output interleaved data is shown in Table 2. Figure 6 . Figure 6 In Table 2, each row of data corresponds to a data unit, and includes eight data units. The same color parts in different data units represent that the bit values of the positions of the data units come from the same pcs channel, i.e., from the same PCS channel signal. For example, Figure 6 In Table 2, the bit values (e.g., a0 and a7) at the red color positions all come from pcs_ln0, the bit values (e.g., b1 and b3) at the dark gray color positions all come from cs_ln1, the bit values (e.g., c3 and c7) at the orange color positions all come from pcs_ln2, the bit values (e.g., d1 and d2) at the green color positions all come from pcs_ln3, and the bit values (e.g., h0 and h7) at the light gray color positions all come from pcs_ln7.

[0055] As can be seen, for each data unit, the bit values of the positions of the data unit come from the values at the same bit sequence between different first PCS channel signals. For example, in the bit values a0, b0, c0, d0, e0, f0, g0, h0 of all positions of the first data unit, the bit value a0 at the first position comes from the value a0 at the first output bit sequence of pcs_ln0, the bit value b0 at the second position comes from the value b0 at the first output bit sequence of pcs_ln1, the bit value c0 at the third position comes from the value c0 at the first output bit sequence of pcs_ln2, the bit value d0 at the fourth position comes from the value d0 at the first output bit sequence of pcs_ln3, the bit value e0 at the fifth position comes from the value e0 at the first output bit sequence of pcs_ln4, the bit value f0 at the sixth position comes from the value f0 at the first output bit sequence of pcs_ln5, the bit value g0 at the seventh position comes from the value g0 at the first output bit sequence of pcs_ln6, and the bit value h0 at the eighth position comes from the value h0 at the first output bit sequence of pcs_ln7. For example, the bit values h1, a1, b1, c1, d1, e1, f1, g1 of all positions of the second data unit all come from the values at the first output bit sequence of pcs_ln7, pcs_ln0, pcs_ln1, pcs_ln2, pcs_ln3, pcs_ln4, pcs_ln5, and pcs_ln6, respectively.

[0056] It can be seen that the bit values at the same positions of the two adjacent data units come from different first PCS channel signals. For example, the red color corresponding to the first position of the first data unit is different from the light gray color corresponding to the first position of the second data unit, the bit values come from different first PCS channel signals, the dark gray color corresponding to the second position of the first data unit is different from the red color corresponding to the second position of the second data unit, the bit values come from different first PCS channel signals, and so on, the light gray color corresponding to the eighth position of the first data unit is different from the yellow color corresponding to the eighth position of the second data unit, the bit values come from different first PCS channel signals.

[0057] Therefore, the interleaved data of the embodiment can disperse errors into each pcs channel, thereby improving the error correction capability of the entire data link. For example, assuming that the same periodic error is caused by the power supply switching ripple coupled to the CDR circuit, the periodic error of the embodiment appears at the first position of each data unit of the interleaved data, that is, the first column from left to right in the following table Figure 6 Since the bit values at the positions of the first column come from different first PCS channel signals, subsequent error correction can be performed by the FEC error correction mode. For example, the error appears at the position of the first row and the first column (the bit value a0 should originally correspond to the position), while the other bit values a1, a2, a3, a4, a5, a6, and a7 of the first PCS channel signal are normally transmitted, so that the bit value a0 can be recovered by the FEC error correction mode, thereby reliably working on a channel with a higher error rate relative to the previous scheme (for example, the error appears at the first column from left to right, and the error comes from the same pcs channel, which is easy to exceed the error correction limit). Figure 1 In addition, since the power supply noise and crosstalk are typical burst interference sources inside the chip, the interleaved data of the embodiment can disperse these sudden interferences, so that the existing error correction mode can be coped with, thereby relaxing the requirements for power supply noise and isolation design of the physical layer chip design, improving the tolerance to power supply noise and crosstalk, and reducing the design cost.

[0058] In addition, for the two adjacent data units, the bit values at all the same positions of one data unit cyclically shifted by one position and the other data unit come from the same first PCS channel signal, that is, for the shifted data unit obtained by cyclically shifting one data unit by one position, there is an adjacent data unit adjacent to the shifted data unit, and the bit values at all the same positions of the adjacent data unit and the shifted data unit come from the same first PCS channel signal. For example, the shifted data unit obtained by cyclically shifting the first data unit by one position is as follows Figure 6The second data unit in the second row from top to bottom is circularly shifted left by 1 position to obtain a shifted data unit, and the shifted data unit stores a1, b1, c1, d1, e1, f1, g1, h1 in the 0th to 7th positions respectively. For the shifted data unit, the corresponding adjacent data unit is Figure 6 The first data unit in the first row from top to bottom is circularly shifted left by 1 position to obtain a shifted data unit, and the shifted data unit stores a0, b0, c0, d0, e0, f0, g0, h0 in the 0th to 7th positions respectively, so that the bit values in the same position of the first data unit and the second data unit are from the same PCS channel signal.

[0059] The interleaved output is output as first serial data by the PMA data sending module 102. In this embodiment, the first serial data is obtained by outputting in the order determined by each data unit (for example, the first data unit is determined first, and the first data unit is output first, and then the second data unit is output) and is specifically: a0b0c0d0e0f0g0h0h1a1b1c1d1e1f1g1g2h2a2b2c2d2e2f2f3g3h3a3b3c3d3e3e4f4g4h4a4b4c4d4d5e5f5g5h5a5b5c5c6d6e6f6g6h6a6b6b7c7d7e7f7g7h7a7.

[0060] Therefore, the data sending module 10 implements the data sending process.

[0061] The data receiving module 20 implements the data receiving process, which is the inverse process of the same principle as the data sending process, and will not be described here. It should be noted that after the PMA data receiving module 202 completes the serial-parallel conversion of the second serial data, the data deinterleaving module functions similarly to the data interleaving module, and the 8 parallel unit data of the parallel data is input into 8 second selection matrix circuits, and then every 8-bit parallel unit data is input into the input end of each 8-to-1 multiplexer of the corresponding second selection matrix circuit, and then according to the second data routing table, it is determined which PCS channel each second selection matrix circuit should output to at present.

[0062] In addition, those skilled in the art can understand that if it is necessary to increase the bit width of the data unit in the interleaved data, the selection matrix circuit and the data routing table can be adjusted accordingly. For example, in the data sending process of the above embodiment, the bit width requirement of the data unit is 160 bits, so 20 data interleaving modules as described above need to be adjusted in the data sending module 10, and the bit width requirement of the data unit is 320 bits, so 40 data interleaving modules as described above need to be adjusted in the data sending module 10.

[0063] In summary, the Ethernet service data interleaving method of the present application disperses errors to the first PCS channel signals corresponding to each pcs channel, thereby improving error correction capability, and enabling the chip implementing the method to accept higher channel loss, and improving tolerance to power supply noise and crosstalk, reducing the number of PCB layers or material cost.

[0064] Finally, it should be emphasized that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for Ethernet service data interleaving, characterized in that, include: The PCS input generation module processes the acquired upstream data and outputs multiple first PCS channel signals. The PCS input generation module obtains the upstream data from the MAC layer; The data interleaving module processes multiple first PCS channel signals and outputs interleaved data, including: the first selection circuit unit of the data interleaving module acquires multiple first PCS channel signals, and the first channel selection control unit of the data interleaving module controls the first selection circuit unit to select the output according to a set first data routing table to obtain the interleaved data; The PMA data transmission module processes the interleaved data and outputs the first serial data. The interleaved data includes multiple data units with the same bit width. The bit value at each position of the same data unit comes from the value at the same bit sequence between different first PCS channel signals. The bit values ​​at all the same positions between two adjacent data units come from different first PCS channel signals.

2. The Ethernet service data interleaving method as described in claim 1, characterized in that: For a shifted data unit obtained by cyclically shifting one of the data units by one position, there exists an adjacent data unit that is adjacent to the shifted data unit. The bit values ​​of the adjacent data unit and the shifted data unit at all the same positions all come from the same first PCS channel signal.

3. The Ethernet service data interleaving method as described in claim 1, characterized in that: The number of cells in each row of the first data routing table corresponds to the bit width of the data unit, and the value of the cell indicates the corresponding first PCS channel signal.

4. The Ethernet service data interleaving method as described in claim 1, characterized in that: The first selection circuit unit includes a first selection matrix circuit with the same number of first PCS channel signals. The first selection matrix circuit includes a first multiplexer, and the input of the first multiplexer uniquely corresponds to one of the first PCS channel signals.

5. The Ethernet service data interleaving method as described in claim 4, characterized in that: The number of signals in the first PCS channel is 8; The number of the first selection matrix circuits is 8, and the first multiplexer is an 8-to-1 multiplexer.

6. The Ethernet service data interleaving method according to any one of claims 1 to 5, characterized in that, Also includes: The PMA data receiving module processes the acquired second serial data and outputs parallel data. The data deinterleaving module processes the parallel data and outputs multiple second PCS channel signals; The PCS output generation module processes the second PCS channel signal and outputs downstream data.

7. The Ethernet service data interleaving method as described in claim 6, characterized in that: The second selection circuit unit of the data deinterleaving module acquires the parallel data, and the second channel selection control unit of the data deinterleaving module controls the second selection circuit unit to select the output according to the set second data routing table, thereby obtaining multiple second PCS channel signals.

8. A chip, characterized in that, include: PCS input generation module, data interleaving module, and PMA data transmission module; The PCS input generation module is connected to the data interleaving module, and the data interleaving module is connected to the PMA data transmission module; the PCS input generation module, the data interleaving module, and the PMA data transmission module cooperate to implement the Ethernet service data interleaving method according to any one of claims 1 to 5.

9. A chip, characterized in that, include: Data transmission module and data reception module; The data transmission module includes a PCS input generation module, a data interleaving module, and a PMA data transmission module; the PCS input generation module is connected to the data interleaving module, and the data interleaving module is connected to the PMA data transmission module. The data receiving module includes a PCS output generation module, a data deinterleaving module, and a PMA data receiving module; the PCS output generation module is connected to the data deinterleaving module, and the data deinterleaving module is connected to the PMA data receiving module. The data transmission module and the data reception module implement the Ethernet service data interleaving method according to any one of claims 1 to 7.

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