Video processing systems, methods, apparatus, electronic devices, and storage media
By integrating a cache queue and introducing a credit counting and task scheduling unit into the front end of the video core of the video processing subsystem, the communication delay problem between the instruction distribution unit and the video core is solved, enabling efficient instruction acquisition and processing of the video core and improving the overall performance of the video processing system.
CN121239876BActive Publication Date: 2026-06-19SHANGHAI BIREN TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2025-12-03
- Publication Date
- 2026-06-19
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Figure CN121239876B_ABST
Abstract
This invention relates to the field of computer technology and provides a video processing system, method, apparatus, electronic device, and storage medium. The system includes: an instruction dispatch unit for managing and distributing video processing instructions; and a video processing subsystem connected to the instruction dispatch unit via a bus. The video processing subsystem includes at least one video core and a cache queue corresponding to each video core. The cache queue is used to temporarily store video processing instructions sent by the instruction dispatch unit via the bus. The video core is used to read and execute video processing instructions from the cache queue. This invention constructs a decoupled access architecture by integrating a corresponding cache queue at the front end of the video core in the video processing subsystem. This allows the instruction dispatch unit to transmit video processing instructions via the bus in advance and temporarily store them in the downstream cache queue, effectively masking bus transmission latency and greatly improving the time utilization of the video core and the overall video processing performance of the system.
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Citation Information
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