Display device and method of manufacturing same

Abstract

A display apparatus and a method of manufacturing the same are provided. The display device includes: a substrate; a display element layer disposed on the substrate and including a first electrode, a light emitting layer, and a second electrode; a phase retardation layer disposed on the display element layer; and a wire grid polarizer disposed on the phase retardation layer and including a wire grid pattern in which an insulating pattern and a grid pattern are stacked, where the insulating pattern and the grid pattern contain doped ions.

Description

Technical Field

[0001] This disclosure relates to a display device and a method of manufacturing the display device. Background Technology

[0002] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to focus an image at close range in front of the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0003] Head-mounted displays magnify images displayed on small display devices using multiple lenses, and then display the magnified image. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), as high-resolution small organic light-emitting display devices, are used in head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) is disposed. Summary of the Invention

[0004] This disclosure provides a display device capable of providing a high-quality linear grid polarizer, and also provides a method for manufacturing the display device.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0006] According to one aspect of this disclosure, a display device includes: a substrate; a display element layer disposed on the substrate and including a first electrode, a light-emitting layer, and a second electrode; a phase retardation layer disposed on the display element layer; and a wire grid polarizer disposed on the phase retardation layer and including a wire grid pattern, wherein an insulating pattern and a grid pattern are stacked in the wire grid pattern. The insulating pattern and the grid pattern contain doped ions.

[0007] In this embodiment, the doped ions include boron ions.

[0008] In one implementation, the concentration of doped ions contained in the insulating pattern is different from the concentration of doped ions contained in the grid pattern.

[0009] In one embodiment, the concentration of doped ions contained in the insulating pattern is greater than the concentration of doped ions contained in the grid pattern.

[0010] In one embodiment, the concentration of doped ions contained in the insulating pattern gradually increases from the top surface to the bottom surface of the insulating pattern.

[0011] In one embodiment, the concentration of doped ions contained in the grid pattern gradually increases from the top surface to the bottom surface of the grid pattern.

[0012] In one embodiment, the concentration of doped ions contained in the insulating pattern is equal to the concentration of doped ions contained in the grid pattern.

[0013] In one embodiment, an insulating pattern is disposed on a grid pattern, and the thickness of the insulating pattern is less than the thickness of the grid pattern.

[0014] In this implementation, the width of the insulating pattern is equal to the width of the grid pattern.

[0015] In one embodiment, the display device further includes: a planarization layer disposed on the linear grid polarizer; and a capping layer disposed below the linear grid polarizer. The linear grid polarizer includes an air layer disposed in the region defined by the capping layer, the linear grid pattern, and the planarization layer.

[0016] According to one aspect of this disclosure, a display device includes a display area and a non-display area. The display device comprises: a substrate; a display element layer disposed in the display area and including a first electrode, a light-emitting layer, and a second electrode; an encapsulation layer disposed on the display element layer and in both the display area and the non-display area; a phase retardation layer disposed on the encapsulation layer; and a wire-gated polarizer disposed on the phase retardation layer. In the encapsulation layer, a first region overlapping the display area does not contain ions, and a second region overlapping the non-display area contains ions.

[0017] In one embodiment, the wire grid polarizer includes a wire grid pattern, in which an insulating pattern and a grid pattern are stacked, and the insulating pattern and the grid pattern contain ions.

[0018] In this embodiment, the ions include boron ions.

[0019] In this implementation, the concentration of ions contained in the insulating pattern is different from the concentration of ions contained in the grid pattern.

[0020] In one embodiment, the concentration of ions contained in the insulating pattern is greater than the concentration of ions contained in the grid pattern.

[0021] In this embodiment, the concentration of ions contained in the insulating pattern is equal to the concentration of ions contained in the grid pattern.

[0022] According to one aspect of this disclosure, a method for manufacturing a display device includes: preparing a target substrate having at least a display element layer; sequentially forming a metal material layer, an insulating material layer, and a resin layer on the target substrate; forming a resin pattern on the resin layer using a mold; performing a first etching on the resin layer to form a resin mask pattern; performing an ion doping process on the target substrate; performing a second etching on the insulating material layer to form a hard mask pattern; and performing a third etching on the metal material layer to form a grid pattern.

[0023] In this embodiment, the ions used in the ion doping process include boron ions, and the dose of boron ions is 5E15 / cm². 2 Up to 1E16 / cm 2 Within the range.

[0024] In this implementation, the ion doping process is performed with an accelerating voltage of 10 keV to 20 keV.

[0025] In one implementation, a third etching process is used to form a hard mask pattern as an insulating pattern disposed on a grid pattern to form a wire grid polarizer on a target substrate.

[0026] In the display device and the method of manufacturing the display device according to the embodiments, by doping ions into the resin mask pattern to stabilize the resin mask pattern for the etching process, the resin mask pattern can function as a mask trap and can ensure process margins due to enhanced etch selectivity. Therefore, by forming the grid pattern of the wire grid polarizer with uniform spacing and width, the transmittance and polarization degree of the wire grid polarizer can be improved.

[0027] However, the effects of the embodiments according to this disclosure are not limited to those of the examples above, and various other effects are incorporated herein. Attached Figure Description

[0028] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0029] Figure 1 This is an exploded perspective view showing a display device according to an embodiment.

[0030] Figure 2 This is a block diagram illustrating a display device according to an embodiment.

[0031] Figure 3 This is the equivalent circuit diagram of the first pixel according to the implementation method.

[0032] Figure 4 This is a layout diagram showing an example of a display panel according to an embodiment.

[0033] Figure 5 It is shown Figure 4 A layout diagram illustrating the implementation of the display area.

[0034] Figure 6 It shows along Figure 5 A cross-sectional view of an example display panel, taken by line X-X'.

[0035] Figure 7 yes Figure 6 A magnified view of region A.

[0036] Figure 8 This is a schematic plan view of the display panel according to an embodiment.

[0037] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a diagram illustrating a method for manufacturing a display device according to an embodiment.

[0038] Figure 19 This is a planar image of a wire grid polarizer manufactured according to a comparative example.

[0039] Figure 20 This is a planar image of a wire grid polarizer according to an embodiment.

[0040] Figure 21 This is a perspective view showing a head-mounted display according to an embodiment.

[0041] Figure 22 It is shown Figure 21 An exploded stereoscopic view of an example of a head-mounted display.

[0042] Figure 23 This is a perspective view showing a head-mounted display according to an embodiment. Detailed Implementation

[0043] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which embodiments of the inventive concept are illustrated. However, the inventive concept may be practiced in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0044] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there may be an intervening layer. Throughout the specification, the same reference numerals denote the same components.

[0045] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of the inventive concept, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0046] Each of the features in the various embodiments of this disclosure can be combined, either partially or entirely, or with each other, and various interlocks and drives are technically possible. Each embodiment can be implemented independently of each other, or can be implemented together in an associated relationship.

[0047] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0048] Figure 1 This is an exploded perspective view of the display device 10 according to an embodiment. Figure 2 This is a block diagram illustrating a display device 10 according to an embodiment.

[0049] refer to Figure 1 and Figure 2 The display device 10 according to the embodiment is a device for displaying moving or still images. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic managers, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to the embodiment can be used as a display unit for televisions, laptop computers, monitors, billboards, or Internet of Things (IoT) terminals. In the embodiment, the display device 10 can be applied to smartwatches, smartwatch phones, head-mounted displays (HMDs) for realizing virtual and augmented reality, etc.

[0050] The display device 10 according to the embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400 (sometimes referred to as a timing controller 400) and a power supply circuit 500 (sometimes referred to as a power supply unit 500).

[0051] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0052] like Figure 2 As shown, the display panel 100 may include a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0053] The display area (DAA) can include multiple unit pixels (UPX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0054] Multiple unit pixels (UPX) can be arranged in a matrix on the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend on the first direction DR1 and be arranged on the second direction DR2. Multiple data lines (DL) can extend on the second direction DR2 and be arranged on the first direction DR1.

[0055] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL can include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0056] Each of the multiple unit pixels UPX can include multiple pixels PX1, PX2, and PX3. Each of the multiple pixels PX1, PX2, and PX3 can be as follows: Figure 3 The diagram shows multiple pixel transistors, which are formed using semiconductor processes and can be disposed on a semiconductor substrate SSUB (see [reference]). Figure 6 For example, the multiple pixel transistors of the data driver 700 can be formed of complementary metal-oxide-semiconductor (CMOS).

[0057] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0058] The non-display area NDA may include a scan driver 610, a transmit driver 620, and a data driver 700.

[0059] The scan driver 610 may include multiple scan transistors, and the emitter driver 620 may include multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor model]). Figure 6 On ), for example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS. Although in Figure 2 The diagram shows a scan driver 610 positioned on the left side of the display area DAA and a transmit driver 620 positioned on the right side of the display area DAA, but this disclosure is not limited thereto. For example, the scan driver 610 and the transmit driver 620 may be positioned on both the left and right sides of the display area DAA.

[0060] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0061] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 may generate a first transmit control signal based on the transmit timing control signal ECS and output them sequentially to a first transmit control line EL1. The second transmit control driver 622 may generate a second transmit control signal based on the transmit timing control signal ECS and output them sequentially to a second transmit control line EL2.

[0062] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 6 For example, multiple data transistors can be formed using CMOS.

[0063] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 610, and data voltages can be provided to the selected pixels PX1, PX2, and PX3.

[0064] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include layers of graphite and metals with high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al).

[0065] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [link]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 can be the opposite end of the other end of the circuit board 300, which is connected to the first pad portion PDA1 of the display panel 100 (see [link to PDA1]) using a conductive adhesive member. Figure 4 Multiple first pads PD1 (see) Figure 4 ).

[0066] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. The timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS, used to control the display panel 100 in response to the timing signals. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0067] The power supply circuit 500 can generate multiple panel driving voltages based on the power voltage from an external source. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and provide them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0068] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be provided to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be provided to the display panel 100 through the circuit board 300.

[0069] In this implementation, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor model]). Figure 6 On the CMOS, for example, multiple sequential transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the data driver 700 and the first pad portion of PDA1 (see Figure 4 )between.

[0070] Figure 3 This is the equivalent circuit diagram of the first pixel PX1 according to the implementation method.

[0071] refer to Figure 3 The first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first pixel PX1 can be connected to the first drive voltage line VSL, the second drive voltage line VDL, and the third drive voltage line VIL. A first drive voltage VSS, corresponding to a low potential voltage, is applied to the first drive voltage line VSL; a second drive voltage VDD, corresponding to a high potential voltage, is applied to the second drive voltage line VDL; and a third drive voltage VINT, corresponding to the initialization voltage, is applied to the third drive voltage line VIL. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT, and the second drive voltage VDD can be higher than the third drive voltage VINT.

[0072] The first pixel PX1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0073] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and its second electrode can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a micro light-emitting diode.

[0074] The first transistor T1 may be a drive transistor that controls the source-drain current (hereinafter referred to as the "drive current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode. The first transistor T1 may include a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0075] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect that electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to that electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to that electrode of the first capacitor CP1.

[0076] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. For this purpose, since the gate and source electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0077] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be provided to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0078] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0079] A sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal of the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0080] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0081] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0082] The first node N1 is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and the electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0083] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. In an embodiment, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0084] Despite Figure 3 The diagram shows that the first pixel PX1 includes six transistors T1 to T6 and two capacitors C1 and C2. However, it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to... Figure 3 The example shown. For instance, the number of transistors and capacitors in the first pixel PX1 is not limited to... Figure 3 The example shown.

[0085] Furthermore, the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 can be combined with... Figure 3 The equivalent circuit diagram of the first pixel PX1 is substantially the same. Therefore, in this disclosure, the description of the equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 will be omitted.

[0086] Figure 4 This is a layout diagram showing an example of a display panel 100 according to an embodiment.

[0087] refer to Figure 4 The display area DAA of the display panel 100 according to the embodiment may include a plurality of pixels PX1, PX2 and PX3 arranged in a matrix. The non-display area NDA of the display panel 100 according to the embodiment may include a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1 and a second pad portion PDA2.

[0088] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, this disclosure is not limited thereto, and at least one of the scan driver 610 and the transmit driver 620 can be disposed on both the first and second sides of the display area DAA.

[0089] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0090] The first pad portion of PDA1 can be positioned on the outside of the data driver 700 on the second direction DR2. That is, the first pad portion of PDA1 can be positioned closer to the edge of the display panel 100 than the data driver 700.

[0091] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to detect whether the display panel 100 is operating normally. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0092] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0093] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX1, PX2, and PX3 in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0094] Figure 5 It is shown Figure 4 A layout diagram of the implementation method of the display area DAA.

[0095] refer to Figure 5 Each of the multiple unit pixels UPX may include a first emission region EA1 as the emission region of a first pixel PX1, a second emission region EA2 as the emission region of a second pixel PX2, and a third emission region EA3 as the emission region of a third pixel PX3. In other words, a unit pixel UPX may include a unit emission region UEA, and the unit emission region UEA may include the aforementioned first emission region EA1, second emission region EA2, and third emission region EA3.

[0096] Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular planar shape, but the shape of each of the emission regions EA1, EA2, and EA3 is not limited to these.

[0097] The maximum length of the first launch region EA1 in the first direction DR1 can be less than the maximum length of the second launch region EA2 in the first direction DR1 and the maximum length of the third launch region EA3 in the first direction DR1. The maximum length of the second launch region EA2 in the first direction DR1 and the maximum length of the third launch region EA3 in the first direction DR1 can be substantially the same.

[0098] The maximum length of the first transmission region EA1 in the second direction DR2 can be greater than the maximum length of the second transmission region EA2 in the second direction DR2 and the maximum length of the third transmission region EA3 in the second direction DR2. The maximum length of the second transmission region EA2 in the second direction DR2 can be greater than the maximum length of the third transmission region EA3 in the second direction DR2. This disclosure is not limited thereto, and the maximum length of the first transmission region EA1 in the second direction DR2 can be less than the maximum length of the second transmission region EA2 in the second direction DR2.

[0099] In the implementation, in the plan view, the first transmission region EA1, the second transmission region EA2, and the third transmission region EA3 can have the following characteristics: Figure 5 The hexagonal shape formed by the six straight lines shown is illustrated, but this disclosure is not limited thereto. In embodiments, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or atypical shapes other than hexagons in a plan view.

[0100] In this implementation, in each of the plurality of unit pixels UPX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0101] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light in the blue wavelength range, the second color light can be light in the green wavelength range, and the third color light can be light in the red wavelength range. For example, the blue wavelength range can be the wavelength range of light whose main peak wavelength is in the range of approximately 380 nm to approximately 480 nm, the green wavelength range can be the wavelength range of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red wavelength range can be the wavelength range of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0102] exist Figure 5 The illustration shows that each of the plurality of unit pixels UPX includes three emission regions EA1, EA2, and EA3, but this disclosure is not limited thereto. That is, each of the plurality of unit pixels UPX may include four emission regions.

[0103] Furthermore, the emission region settings of multiple unit pixel UPXs are not limited to, for example, Figure 5 The diagram shows a hexagonal structure with hexagonal emission regions arranged in a planar view. For example, the emission regions of multiple unit pixels UPX can be a stripe structure in which the emission regions are arranged in a first direction DR1, or in which the emission regions are arranged in a rhomboid shape. Structural setup.

[0104] Figure 6 It shows along Figure 5A cross-sectional view of an example of display panel 100, taken by line X-X'. Figure 7 yes Figure 6 A magnified view of region A.

[0105] refer to Figure 6 and Figure 7 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), and an optical layer (OPL). The semiconductor backplane (SBP) and the light-emitting element backplane (EBP) may be referred to as substrates.

[0106] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may be a reference. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0107] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity mentioned above. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. In this embodiment, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0108] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to its drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0109] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0110] Each of the source region SA and drain region DA can be a region doped with type I impurities. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0111] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the lower insulating film BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, the length of the channel region CH in each of the pixel transistors PTRs can be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by short channels.

[0112] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be made of silicon carbide (SiCN) or based on silicon oxide (SiO2). x Inorganic membrane formation, but this disclosure is not limited thereto.

[0113] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2) x Inorganic membrane formation, but this disclosure is not limited thereto.

[0114] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0115] A third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed without being covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2) based material. x Inorganic membrane formation, but this disclosure is not limited thereto.

[0116] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0117] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. Furthermore, the backplane (EBP) may include multiple insulating films INS1 to INS9 disposed between the first conductive layer ML1 to the eighth conductive layer ML8.

[0118] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 4 The circuitry of the first pixel PX1 shown is illustrated. For example, first transistors T1 to sixth transistors T6 are formed only in the semiconductor backplane SBP, and the connection between first transistors T1 to sixth transistors T6 and first capacitor C1 and second capacitor C2 is achieved through first conductive layers ML1 to eighth conductive layers ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of fourth transistor T4, the source region corresponding to the source electrode of fifth transistor T5, and the first electrode of the light-emitting element LE is also achieved through first conductive layers ML1 to eighth conductive layers ML8.

[0119] A first insulating film INS1 may be disposed on a semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0120] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second through-holes VA2 can penetrate the second insulating film INS2 and connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can connect to the second through-hole VA2.

[0121] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third through-holes VA3 can penetrate the third insulating film INS3 and connect to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 and can be connected to the third through-hole VA3.

[0122] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can penetrate the fourth insulating film INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can connect to the fourth via VA4.

[0123] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can penetrate the fifth insulating film INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can connect to the fifth via VA5.

[0124] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can penetrate the sixth insulating film INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can connect to the sixth via VA6.

[0125] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can penetrate the seventh insulating film INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can connect to the seventh via VA7.

[0126] An eighth insulating film INS8 may be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth through-holes VA8 may penetrate the eighth insulating film INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating film INS8 and may connect to the eighth through-hole VA8.

[0127] The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. The first through-holes VA1 to VA8 can be made of substantially the same material. The first insulating film INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membrane formation, but this disclosure is not limited thereto.

[0128] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first through-hole VA1, the second through-hole VA2, the third through-hole VA3, the fourth through-hole VA4, the fifth through-hole VA5, and the sixth through-hole VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately... The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately The thickness of each of the following through holes can be approximated: first through hole VA1, second through hole VA2, third through hole VA3, fourth through hole VA4, fifth through hole VA5, and sixth through hole VA6.

[0129] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 can be approximately

[0130] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2) based material. x Inorganic membrane formation, but this disclosure is not limited thereto.

[0131] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the ninth via VA9 can be approximately...

[0132] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include: light-emitting elements (LE), each including a reflective electrode layer (RRL), a tenth insulating film (INS10) and an eleventh insulating film (INS11), a tenth through-hole (VA10), a first electrode (AND), a light-emitting stack (ES), and a second electrode (CAT); a pixel defining film (PDL); and multiple trenches (TRC).

[0133] The reflective electrode layer RRL can be disposed on the ninth insulating film INS9. The reflective electrode layer RRL can include at least one of reflective electrodes RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RRL can be as follows: Figure 6 The diagram shows a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0134] Each of the first reflective electrodes RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth through hole VA9. The first reflective electrodes RL1 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0135] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the second reflective electrode RL2 may include aluminum (Al).

[0136] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0137] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0138] Since the second reflective electrode RL2 is the electrode that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately... Furthermore, the thickness of the second reflective electrode RL2 can be approximately...

[0139] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between horizontally adjacent reflective electrode layers RRL. The tenth insulating film INS10 can be disposed on the reflective electrode layer RRL in the third pixel PX3. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x Inorganic membrane formation, but this disclosure is not limited thereto.

[0140] The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode layer RRL. The eleventh insulating film INS11 can be made of silicon oxide (SiO2) x The inorganic film is formed, but this disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RRL passes in the light emitted from the light-emitting element LE.

[0141] In order to match the resonant distance of light emitted from the light-emitting element LE in at least one of the first pixel PX1, the second pixel PX2 and the third pixel PX3, the tenth insulating film INS10 and the eleventh insulating film INS11 may not be provided below the first electrode AND of the first pixel PX1.

[0142] The first electrode AND of the first pixel PX1 can be directly set on the reflective electrode layer RRL.

[0143] The eleventh insulating film INS11 can be disposed below the first electrode AND of the second pixel PX2. The tenth insulating film INS10 and the eleventh insulating film INS11 can be disposed below the first electrode AND of the third pixel PX3.

[0144] In summary, the distance between the first electrode AND and the reflective electrode layer RRL can be different in the first pixel PX1, the second pixel PX2, and the third pixel PX3. To adjust the distance from the reflective electrode layer RRL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, in... Figure 6 The diagram shows that the distance between the first electrode AND and the reflective electrode layer RRL in the third pixel PX3 is greater than the distance between the first electrode AND and the reflective electrode layer RRL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RRL in the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RRL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RRL in the first pixel PX1, but this disclosure is not limited thereto.

[0145] Furthermore, although the tenth insulating film INS10 and the eleventh insulating film INS11 are shown in this disclosure, a twelfth insulating film may be added and disposed below the first electrode AND of the first pixel PX1. In this case, the eleventh insulating film INS11 and the twelfth insulating film may be disposed below the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film may be disposed below the first electrode AND of the third pixel PX3.

[0146] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second pixel PX2 and the third pixel PX3, and can be connected to the exposed reflective electrode layer RRL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the tenth via VA10 in the second pixel PX2 can be less than the thickness of the tenth via VA10 in the third pixel PX3.

[0147] The first electrode AND of each of the light-emitting elements LE can be disposed on the tenth insulating film INS10 and connected to the tenth through-hole VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth through-hole VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first through-hole VA1 to the ninth through-hole VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0148] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge of the first electrode AND of each of the light-emitting elements (LEs). The PDL can be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0149] The first emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0150] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The inorganic film is formed, but this disclosure is not limited thereto. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have approximately The thickness.

[0151] When the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 form a single pixel-defining film, the height of this single pixel-defining film increases, making the first encapsulating inorganic film TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the greater the likelihood that the film will be cut at the inclined portion.

[0152] Therefore, to prevent the first encapsulated inorganic film TFE1 from being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining film PDL1 can be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 can be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length defined by the first pixel defining film PDL1 in the first direction DR1 and the second direction DR2.

[0153] Each of the plurality of trench TRCs can penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, each of the plurality of trench TRCs can penetrate the eleventh insulating film INS11. The tenth insulating film INS10 can be partially recessed at each of the plurality of trench TRCs.

[0154] At least one trench TRC can be set between adjacent pixels PX1, PX2, and PX3. Although Figure 6 Two trench TRCs are shown positioned between adjacent pixels PX1, PX2, and PX3, but this disclosure is not limited thereto.

[0155] A light-emitting stacked ES can include multiple intermediate layers. Figure 6 The illustration shows a light-emitting stacked ES having a triple tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, the light-emitting stacked ES may have a double tandem structure including two intermediate layers.

[0156] In a three-tiered cascade structure, the light-emitting stack ES can have a cascaded structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack ES may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a second color, and a third stacked layer IL3 that emits light of a third color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0157] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are stacked in sequence. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are stacked in sequence. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are stacked in sequence. In this case, the light-emitting stack ES may emit white light, which is a mixture of light of the first color (e.g., red light) from the first organic light-emitting layer, light of the second color (e.g., green light) from the second organic light-emitting layer, and light of the third color (e.g., blue light) from the third organic light-emitting layer. Therefore, white light may be emitted from each of the first emission region EA1, the second emission region EA2, and the third emission region EA3. Here, white light that has passed through the first emission region EA1 may be incident on the first color filter CF1, white light that has passed through the second emission region EA2 may be incident on the second color filter CF2, and white light that has passed through the third emission region EA3 may be incident on the third color filter CF3.

[0158] A first charge generation layer for providing charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer that provides electrons to the first stacked layer IL1 and a P-type charge generation layer that provides holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0159] A second charge generation layer for providing charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that provides electrons to the second stacked layer IL2 and a P-type charge generation layer that provides holes to the third stacked layer IL3.

[0160] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and can be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be separated between adjacent pixels PX1, PX2, and PX3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be separated between adjacent pixels PX1, PX2, and PX3. Holes ESS or empty spaces can be provided between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC, and can be configured to cover the second stacked layer IL2 in each of the trench TRCs. For example, in a three-in-a-row structure, each of the plurality of trench TRCs can be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent pixels PX1, PX2, and PX3. Furthermore, in the dual-series structure, each of the trench TRCs can be a structure for cutting off the charge-generating layer disposed between the lower intermediate layer and the upper intermediate layer, as well as the lower intermediate layer.

[0161] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To cut the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 of the display element layer EML between adjacent pixels PX1, PX2, and PX3, an alternative structure can exist to replace the trench TRCs. For example, instead of trench TRCs, reverse tapered partition walls can be provided on the pixel defining film PDL.

[0162] The number of stacked layers IL1, IL2, and IL3 that emit different light is not limited to Figure 6 The quantities shown are as described. For example, the light-emitting stack ES may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for providing electrons to one intermediate layer and charge to the other intermediate layer may be disposed between the two intermediate layers.

[0163] also, Figure 6The diagram shows that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but this disclosure is not limited thereto. For example, the first stacked layer IL1 may be disposed in the first emission region EA1 and may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, the second stacked layer IL2 may be disposed in the second emission region EA2 and may be omitted from the first emission region EA1 and the third emission region EA3. Furthermore, the third stacked layer IL3 may be disposed in the third emission region EA3 and may be omitted from the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0164] The second electrode CAT can be disposed on the third stacked layer IL3. The second electrode CAT can be disposed on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be improved due to the microcavity effect.

[0165] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE2 to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0166] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is selected. x ), silicon oxynitride (SiON) and silicon oxide (SiO) x A multilayer of one or more inorganic films alternately stacked. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0167] The second encapsulating inorganic film TFE2 can be disposed on the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO) xThe second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0168] Organic film APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. Organic film APL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0169] The optical layer OPL may include a color filter layer CFL, a lens layer LSL, a filler layer FIL, a capping layer CVL, a phase delay layer QWP, and a wire grid polarizer WGP.

[0170] The color filter layer CFL may include multiple color filters CF1, CF2, and CF3. These multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the organic membrane APL.

[0171] The first color filter CF1 may overlap with the first emission region EA1 (e.g., a red light emission region) of the first pixel PX1. The first color filter CF1 can transmit light of a first color, for example, light in the red wavelength band. The red wavelength band may be from about 600 nm to about 750 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0172] The second color filter CF2 can overlap with the second emission region EA2 (e.g., the green light emission region) of the second pixel PX2. The second color filter CF2 can transmit light of a second color, for example, light in the green wavelength band. The green wavelength band can be from about 480 nm to about 560 nm. Therefore, the second color filter CF2 can transmit light of a second color emitted from the second emission region EA2.

[0173] The third color filter CF3 can overlap with the third emission region EA3 (e.g., the blue light emission region) of the third pixel PX3. The third color filter CF3 can transmit light of a third color, such as light in the blue wavelength band. The blue wavelength band can be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 can transmit light of a first color emitted from the first emission region EA1.

[0174] A planarization layer (PLL) can be disposed on the color filter layer (CFL). The PLL can be used to planarize the stepped portions at the bottom. The PLL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0175] A lens layer LSL can be disposed on a planarization layer PLL. The lens layer LSL may include multiple lenses LNS. The multiple lenses LNS may be disposed on a first color filter CF1, a second color filter CF2, and a third color filter CF3, respectively. Each of the multiple lenses LNS may be a structure for increasing the proportion of light directed to the front of the display device 10. Each of the multiple lenses LNS may have a cross-sectional shape that convexes in the upward direction.

[0176] A filler layer (FIL) can be disposed on a lens layer (LSL). For example, a filler layer (FIL) can be disposed on multiple lens layers (LNS). The filler layer (FIL) can have a predetermined refractive index such that light propagates in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens layers (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0177] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FIL.

[0178] A phase retardation layer QWP (or retardation plate or retardation film) can be disposed on the color filter layer CFL. For example, the phase retardation layer QWP can be disposed between the color filter layer CFL and the wire grating polarizer WGP. The phase retardation layer QWP can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. The phase retardation layer QWP can be formed, for example, by a coating method.

[0179] In an embodiment, the phase retardation layer QWP may include an alignment film ALL, a liquid crystal layer LC disposed on the alignment film ALL, and a capping layer CPL disposed on the liquid crystal layer LC. The alignment film ALL can be used to align the liquid crystal layer LC disposed on the alignment film ALL. For example, the alignment film ALL has reactions such as photoisomerization and photocrosslinking that occur anisotropically when irradiated with polarized light, and thus can generate anisotropy on the polymer surface, which can induce the molecular arrangement of the liquid crystal in one direction. The liquid crystal layer LC can be formed by coating the alignment film ALL with a liquid crystal material containing the reactive liquid crystal origin (RM) to be aligned and polymerizing them.

[0180] The capping layer (CPL) is used to protect the liquid crystal layer (LC). The capping layer (CPL) may include inorganic insulating materials. For example, the capping layer (CPL) may include silicon nitride (SiN). x ), silicon oxynitride (SiON) and silicon oxide (SiO) x The capping layer CPL can be any of the following materials. The capping layer CPL can have a predetermined thickness (e.g., 50 to 1000 nm) to protect the liquid crystal layer LC. In an embodiment, the capping layer CPL can have a thickness of 100 to 500 nm.

[0181] A wire-grid polarizer (WGP) can be disposed on the phase retardation layer (QWP), for example, between the phase retardation layer (QWP) and the planarization layer (PLL). The wire-grid polarizer (WGP) and the phase retardation layer (QWP) can constitute a polarization member. For example, the polarization member according to an embodiment may include the phase retardation layer (QWP) and the wire-grid polarizer (WGP).

[0182] A wire grid polarizer (WGP) can include multiple wire grid patterns (GP). For example... Figure 5 As shown, each wire grid pattern GP can have a rectangular shape extending along the second direction DR2. Furthermore, as... Figure 5 As shown, the wire grid pattern GP can be arranged along the first direction DR1. The wire grid patterns GP can be arranged to be spaced apart from each other in the first direction DR1.

[0183] A wire-grid polarizer (WGP) can transmit light with a specific polarization direction while reflecting light with another polarization direction for recycling. This type of WGP can be used as a reflective polarizer because it exhibits higher polarization separation performance than other polarizers. For example, a WGP is a device that uses a conductive wire grid to generate polarization and can have a structure in which multiple lines made of conductive material are periodically arranged parallel to each other at nanoscale on a phase retardation layer (QWP) to form a wire grid pattern (GP).

[0184] In a wire-grid polarizer (WGP) comprising multiple wire-grid patterns GP, no diffraction of the incident light occurs if the period of the wire-grid patterns GP is less than the wavelength of the incident light. Therefore, the wire-grid polarizer WGP can transmit components of the incident light with vibration directions orthogonal to the conductive wire-grid patterns GP (such as transverse magnetic (TM) polarization (e.g., P-wave)) while reflecting components with vibration directions parallel to the wire-grid patterns GP (such as transverse electric (TE) polarization (e.g., S-wave)). In other words, when the arrangement period of the wire-grid patterns GP is shorter than the wavelength of the electromagnetic wave incident on the wire-grid polarizer WGP, the wire-grid polarizer WGP can reflect polarization components parallel to the wire-grid patterns GP (e.g., S-wave) while transmitting polarization components perpendicular to the wire-grid patterns GP (e.g., P-wave). Because the wire-grid polarizer WGP uses wire-grid patterns GP made of metal, its light reflection efficiency is very high. Therefore, since the reflected light can be reflected again, the light can be recycled so that all the light becomes a single polarized light.

[0185] The wire grid patterns GP can be configured to be spaced apart from each other by a first spacing P1 in the first direction DR1. The first spacing P1 can be the distance between the centers of adjacent wire grid patterns GP. The first spacing P1 of the wire grid patterns GP can be 50 to 150 nm. In an embodiment, the first spacing P1 of the wire grid patterns GP can be 50 to 100 nm. In all wire grid patterns GP, the first spacing P1 can be the same, or some can be different from each other.

[0186] The wire grid patterns GP can be configured to be spaced apart from each other in the first direction DR1, with a separation distance equal to the second spacing P2. The second spacing P2 can be the distance between the side edges of adjacent wire grid patterns GP. The second spacing P2 of the wire grid patterns GP can be 40 to 100 nm. In an embodiment, the second spacing P2 of the wire grid patterns GP can be 40 to 50 nm. In all wire grid patterns GP, the second spacing P2 can be the same, or some can be different from each other.

[0187] Considering process characteristics, reflection properties, etc., the wire grid pattern GP can have a predetermined thickness. The thickness TK1 of the wire grid pattern GP can be from 10 to 1000 nm. In an embodiment, the thickness TK1 of the wire grid pattern GP can be from 100 to 300 nm. In all wire grid pattern GPs, the thickness TK1 can be the same, or some can be different from each other.

[0188] The grid pattern GP can include the grid pattern GPL and the insulating pattern IPL.

[0189] A grid pattern GPL can form the lower layer of a wire grid pattern GP and essentially perform the functions of the wire grid pattern GP. The grid pattern GPL can be disposed between a capping layer CPL and an insulating pattern IPL, or directly on the capping layer CPL. The grid pattern GPL can include a material with high reflectivity to perform the aforementioned light reflection function. For example, the grid pattern GPL can include one selected from the group consisting of aluminum (Al), chromium (Cr), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), cobalt (Co), and molybdenum (Mo), or alloys thereof. The thickness TK2 of the grid pattern GPL can be from 10 to 1000 nm.

[0190] An insulating pattern IPL can form the upper portion of a wire grid pattern GP and can be used as a mask during the patterning process of a grid pattern GPL. An insulating pattern IPL can be disposed between a planarization layer PLL and a grid pattern GPL. An insulating pattern IPL can also be disposed directly on the grid pattern GPL.

[0191] The insulating pattern IPL may include an inorganic insulating material. For example, the insulating pattern IPL may include silicon oxide nitride, silicon oxide, or silicon nitride. The insulating pattern IPL may have a thickness TK3 in the range of 1 nm to 1000 nm. In embodiments, considering adhesion, reliability, and transmittance, the thickness TK3 of the insulating pattern IPL may be set to 10 nm to 100 nm. Furthermore, the thickness TK3 of the insulating pattern IPL may be less than the thickness TK2 of the grid pattern GPL. Since the insulating pattern IPL acts as a mask during the patterning process of the grid pattern GPL, the width of the insulating pattern IPL may be substantially the same as the width of the grid pattern GPL.

[0192] The wire grid pattern (GP) may include doped ions. For example, the grid pattern (GPL) and the insulating pattern (IPL) may include ions. Ions may be infiltrated into the wire grid pattern (GP) during a doping process described later. Ions may include, for example, boron ions.

[0193] Within the wire gate pattern GP, ​​the ion concentration can vary. For example, the concentration of ions included in the insulating pattern IPL can differ from the concentration of ions included in the grid pattern GPL. Because the ion doping process is performed in the upper portion of the substrate, the ion concentration in the insulating pattern IPL of the upper portion forming the wire gate pattern GP can be greater than the ion concentration in the grid pattern GPL of the lower portion forming the wire gate pattern GP.

[0194] In an embodiment, the ion concentration in the wire grid pattern GP can gradually increase from the top to the bottom of the wire grid pattern GP. For example, the ion concentration in the insulating pattern IPL can gradually increase from the top surface to the bottom surface of the insulating pattern IPL, and the ion concentration in the grid pattern GPL can gradually increase from the top surface to the bottom surface of the grid pattern GPL. In an embodiment, the ion concentration in the lower portion of the insulating pattern IPL can be greater than the ion concentration in the upper portion of the grid pattern GPL.

[0195] In an embodiment, the amount of ions in the insulating pattern IPL of the upper portion forming the wire grid pattern GP can be equal to the amount of ions in the grid pattern GPL of the lower portion forming the wire grid pattern GP. Since the wire grid pattern GP is very thin (thickness in the range of a few nanometers to several hundred nanometers), the amount of ions in the grid pattern GPL and the amount of ions in the insulating pattern IPL can be substantially the same and indistinguishable.

[0196] The wire grid polarizer WGP may include an air layer AIL. The air layer AIL may be disposed between the wire grid patterns GP. Specifically, the air layer AIL may be disposed in the region defined by the capping layer CPL, the wire grid patterns GP, and the planarization layer PLL. The air layer AIL may be disposed between the wire grid patterns GP and extend in a second direction DR2 parallel to the wire grid patterns GP. The air layers AIL may be configured to be spaced apart from each other in a first direction DR1, with the wire grid patterns GP interposed between them. The air layer AIL may act as a path through which light emitted from the internal light-emitting stack ES is transmitted.

[0197] Figure 8 This is a schematic plan view of the display panel 100 according to an embodiment.

[0198] Combination Figure 6 refer to Figure 8 The encapsulation layer TFE can be disposed in the display area DAA and the non-display area NDA. The optical layer OPL can be mainly disposed in the display area DAA, and may not be disposed in a portion of the non-display area NDA. The wire grid polarizer WGP included in the optical layer OPL can also be disposed in the display area DAA, and may not be disposed in a portion of the non-display area NDA, for example, at the edge of the non-display area NDA.

[0199] When forming the wire grid polarizer WGP, the ion doping process described below can be performed. Since the ion doping process is performed entirely without using a separate mask, ions can be doped not only in the display area DAA where the wire grid polarizer WGP is formed, but also in the non-display area NDA. Therefore, the encapsulation layer TFE can have regions containing ions and regions not containing ions. Here, the encapsulation layer TFE can refer to at least one of a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0200] In this implementation, the first region of the encapsulation layer TFE that overlaps with the display area DAA may not contain ions, while the second region of the encapsulation layer TFE that overlaps with the non-display area NDA may contain ions. Here, the second region of the encapsulation layer TFE containing ions may be a region that does not overlap with the optical layer OPL, and the first region of the encapsulation layer TFE that does not contain ions may be a region that overlaps with the optical layer OPL. In other words, the second region of the encapsulation layer TFE containing ions may be a region that does not overlap with the wire grid polarizer WGP, and the first region of the encapsulation layer TFE that does not contain ions may be a region that overlaps with the wire grid polarizer WGP.

[0201] In this implementation, ions may be included throughout the entire encapsulation layer TFE. In this case, the ion concentration in the first region of the encapsulation layer TFE that overlaps with the display area DAA may be lower than the ion concentration in the second region that overlaps with the non-display area NDA. In the first region of the encapsulation layer TFE that overlaps with the display area DAA, since the organic film APL, the color filter layer CFL, and the phase retardation layer QWP are disposed between the encapsulation layer TFE and the wire grid polarizer WGP, the concentration of ions penetrating into the encapsulation layer TFE may be low. On the other hand, in the second region of the encapsulation layer TFE that overlaps with the non-display area NDA, since no other layers are disposed on top of the encapsulation layer TFE, the ion concentration may be high.

[0202] The ion doping process described below can be confirmed by checking whether the wire grid polarizer WGP includes ions and / or whether the encapsulation layer TFE of the non-display area NDA includes ions.

[0203] The method for manufacturing a display device according to the above embodiments will be described below.

[0204] Figures 9 to 18 This is a diagram illustrating a method for manufacturing a display device according to an embodiment. In the following figures, descriptions of the manufacturing processes for the semiconductor backplane (SBP), light-emitting element backplane (EBP), display element layer (EML), encapsulation layer (TFE), color filter layer (CFL), and phase retardation layer (QWP) will be omitted, focusing instead on the description of the manufacturing process for the wire grid polarizer (WGP).

[0205] refer to Figure 9 A metal material layer MTL and an insulating material layer HML are formed on the target substrate TSUB.

[0206] The target substrate TSUB can be formed on it as follows Figure 6 The semiconductor backplane (SBP), light-emitting element backplane (EBP), display element layer (EML), encapsulation layer (TFE), color filter layer (CFL), and phase retardation layer (QWP) shown are substrates. The top surface of the target substrate (TSUB) (e.g., the surface on which a metal material layer (MTL) is formed) can be the phase retardation layer (QWP).

[0207] Metallic Material Layer (MTL) is used to form Figure 7 The grid pattern GPL shown may contain metallic materials. For example, the metallic material layer MTL may include one selected from the group consisting of aluminum (Al), chromium (Cr), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), cobalt (Co), and molybdenum (Mo), or alloys thereof. The metallic material layer MTL may be formed using common metallic material lamination methods (e.g., sputtering, chemical vapor deposition (CVD), or evaporation).

[0208] The insulating material layer HML is used for etching. Figure 7 The grid pattern GPL shown is a hard mask and may contain inorganic insulating materials. For example, the insulating material layer HML may contain silicon oxynitride (SiON), silicon oxide (SiO2), etc. x ) or silicon nitride (SiN) x The insulating material layer HML can be formed using methods such as chemical vapor deposition (CVD).

[0209] Next, refer to Figure 10 A resin layer RL is formed on an insulating material layer HML. The resin layer RL can be formed using solution processes such as inkjet printing, spin coating, slot coating, or gravure coating. Among these, inkjet printing is suitable as a method for forming the resin layer RL because it can apply the desired amount of resin to the desired portion. When the resin material is applied to the insulating material layer HML by inkjet printing, the resin can be dispersed on the insulating material layer HML to form a resin layer RL with a uniform thickness.

[0210] Then, the mold IPM is aligned on the resin layer RL. The mold IPM can be used as an impression that can form a specific shape in the resin layer RL by pressing it through an embossing process. For example, a flexible mold can be used as the mold IPM.

[0211] The mold IPM may include protrusions PPM and recesses EPM. The protrusions PPM may form recesses in the resin layer RL, and the recesses EPM may form protrusions in the resin layer RL. The protrusions PPM and recesses EPM of the mold IPM may have predetermined widths and spacings, such that a resin pattern RP with predetermined widths and spacings can be formed in the imprinting process described below (see...). Figure 12 ) resin layer RL.

[0212] Subsequently, reference Figure 11 and Figure 12 The resin layer RL can be extruded using a die IPM. With the protrusions PPM of the die IPM aligned with the resin layer RL, the die IPM can press against the resin layer RL. In the process of pressing the die IPM, the die IPM can be extruded vertically or sequentially from one side to the other using a roller device.

[0213] When the mold IPM extrudes the resin layer RL, the resin of the resin layer RL can be filled into the recessed part EPM of the mold IPM, and the excess resin can be distributed to the surrounding area, so that the recessed part EPM of the mold IPM can be completely filled with resin.

[0214] Subsequently, when the mold IPM separates from the resin layer RL, the resin pattern RP can be transferred to the resin layer RL, such as... Figure 12 As shown in the diagram, the resin layer RL may include not only the resin pattern RP, but also a portion of the resin layer RL between the resin patterns RP that covers the insulating material layer HML.

[0215] Next, refer to Figure 13 A first etch (first etch) is performed on the resin layer RL to form a resin mask pattern RMP.

[0216] To illustrate in detail, the resin layer RL with the resin pattern RP is etched to reduce the size of the resin pattern RP and remove portions of the remaining resin layer RL. The first etching (first etch) can be performed using a dry etching process. The dry etching process can utilize, for example, plasma etching. Plasma etching can utilize fluorine (F), but is not limited to this.

[0217] In the first etching (first etch) process, the size of the resin pattern RP (such as its height and width) can be reduced to form a smaller resin mask pattern RMP. Furthermore, the remaining resin layer RL (e.g., the resin remaining besides the resin pattern RP) can be removed, thereby fully exposing the underlying insulating material layer HML.

[0218] Next, refer to Figures 14 to 16 An ion doping process was performed on the target substrate TSUB. Figure 14 This illustrates the ion doping process. Figure 15 This illustrates how the resin compound changes when ions are doped into it. - A schematic diagram of the cross-linked state, and Figure 16 It is a graph showing the etching rate and etching thickness according to the amount of ion doping.

[0219] Ion doping is a process of doping ions into a resin mask pattern (RMP). Ions used in ion doping can include boron (B) ions. The ions can be at a concentration of 5E15 / cm². 2 Up to 1E16 / cm 2 Doping doses can be within a range of 5E16 / cm². For example, boron ion doses can be as low as 5E16 / cm². 2 Up to 1E16 / cm 2 Within the range. If the dose of boron ions is equal to or greater than 5E16 / cm². 2 This may induce resin cross-linking within the resin mask pattern RMP, thereby making the resin mask pattern RMP etch-resistant, and if the boron ion dose is equal to or less than 1E16 / cm 2 This prevents the ion doping process from becoming too time-consuming. Furthermore, the accelerating voltage for ion doping can range from 10 keV to 20 keV.

[0220] like Figure 15 As shown, when a resin (such as polythiophene) is doped with ions (X... - When organic compounds undergo molecular forces, chain breakage occurs, and bonds such as carbon-carbon, carbon-nitrogen, and carbon-oxygen bonds in the chain may break. The broken carbon atoms may then chemically bond with another broken carbon atom or the end of the chain. Therefore, due to the increased molecular forces in the organic compounds, the strength of the resin can be enhanced, and changes in physical properties, such as increased etching selectivity, may occur.

[0221] from Figure 16 As can be seen, the etching rate and etching thickness of the ion-doped resin decrease with the increase of the amount of ion doping.

[0222] In this embodiment, by doping the resin mask pattern RMP with ions, the resin mask pattern RMP can be stabilized for the etching process. That is, the resin mask pattern RMP can become stable to perform its function as a mask trap, and process margins can be ensured due to the increased etch selectivity.

[0223] Next, refer to Figure 17 In the insulating material layer HML (e.g., see Figure 14 A second etch (second etch) is performed on the surface to form a hard mask pattern (HMP).

[0224] Specifically, the insulating material layer HML, which is not masked by the resin mask pattern RMP, is etched using a resin mask pattern RMP as a mask. The second etching (the second etch) can be achieved using a dry etching process. Dry etching processes can utilize, for example, plasma etching. Plasma etching can utilize fluorine (F), but is not limited to this.

[0225] In the second etching process (second etching), the resin mask pattern RMP and the insulating material layer HML can be etched simultaneously. In this embodiment, since the resin mask pattern RMP is doped with ions to reduce etch selectivity, it can be etched to a degree where its thickness is slightly reduced during the etching process. That is, since the resin mask pattern RMP is not completely removed by the etching process, it can effectively perform its function as a mask for forming the hard mask pattern HMP.

[0226] All areas of the insulating material layer HML not masked by the resin mask pattern RMP can be removed, allowing the formation of the hard mask pattern HMP. The hard mask pattern HMP is the area overlapping with the resin mask pattern RMP and can be formed to have substantially the same width as the resin mask pattern RMP. With the formation of the resin mask pattern RMP, a portion of the underlying metallic material layer MTL may be exposed.

[0227] Next, refer to Figure 18 A third etch (third etch) is performed on the metal material layer MTL to form the grid pattern GPL.

[0228] Specifically, a resin mask pattern (RMP) and a hard mask pattern (HMP) are used as masks to etch the metal material layer (MTL). The third etch (third etch) can be achieved using a dry etching process. Dry etching processes can utilize, for example, plasma etching. Plasma etching can utilize chlorine (Cl), but is not limited to this.

[0229] In the third etch (third etch) process, the resin mask pattern RMP, the hard mask pattern HMP, and the metal material layer MTL can be etched simultaneously. For example, in the third etch (third etch) process, the resin mask pattern RMP is completely etched and removed, and the hard mask pattern HMP can be partially etched to a slightly reduced thickness. That is, since the resin mask pattern RMP is also used as a mask in the third etch (third etch) process, the hard mask pattern HMP can be retained, thus effectively performing its masking function for the metal material layer MTL.

[0230] It can remove all areas of the metal material layer MTL that are not masked by the resin mask pattern RMP and the hard mask pattern HMP, allowing the formation of the grid pattern GPL. The remaining hard mask pattern HMP ( Figure 17An insulating pattern IPL can be formed on a grid pattern GPL. Figure 18 The grid pattern GPL is the area that overlaps with the insulating pattern IPL, and can be formed to have substantially the same width as the insulating pattern IPL. Furthermore, the thickness of the grid pattern GPL can be greater than the thickness of the insulating pattern IPL. When the grid pattern GPL and the insulating pattern IPL are formed, a wire grid polarizer WGP can be obtained.

[0231] Subsequently, they can be formed sequentially. Figure 6 The planarization layer PLL, lens layer LSL, filler layer FIL, and cover layer CVL shown are used to manufacture a display device.

[0232] According to the manufacturing method of the aforementioned display device, by doping ions into the resin mask pattern RMP to increase etch selectivity, the resin mask pattern RMP can function as a mask even in multiple etch processes. Therefore, by forming the grid pattern GPL of the wire grid polarizer WGP with uniform spacing and width, the transmittance and polarization degree of the wire grid polarizer WGP can be improved.

[0233] Figure 19 This is a planar image of a wire grid polarizer manufactured according to a comparative example. Figure 20 This is a planar image of a wire grid polarizer according to an embodiment.

[0234] Figure 19 and Figure 20 Planar images are shown of wire-grid polarizers fabricated using and without processes that dope boron ions into a resin mask pattern (RMP). Figure 19 In the comparative example, boron ion doping is not performed on the resin mask pattern RMP, and... Figure 20 In one embodiment, boron ion doping is performed on a resin mask pattern RMP to fabricate a wire grid polarizer.

[0235] like Figure 19 As shown, the wire-grid polarizer according to the comparative example was found to have a discontinuous grid pattern with an irregular width and a spacing of approximately 33.9 nm. On the other hand, as... Figure 20 As shown, the wire grid polarizer according to this embodiment has a grid pattern that is continuously formed without interruption and has a relatively uniform width. Furthermore, the measured spacing of the grid pattern is approximately 41.1 nm, indicating that the grid pattern is formed more precisely.

[0236] Based on this result, it is confirmed that a grid pattern GPL for a wire grid polarizer WGP with uniform spacing and width can be formed by performing an ion doping process on a resin mask pattern RMP.

[0237] Figure 21 This is a perspective view showing a head-mounted display 1000 according to an embodiment. Figure 22 It is shown Figure 21 An exploded stereoscopic view of an example of a head-mounted display 1000.

[0238] refer to Figure 21 and Figure 22 According to an embodiment, the head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0239] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 The display devices 10 described are substantially the same, so the descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0240] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0241] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0242] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert an externally input image source into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0243] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. In an embodiment, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0244] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 21 and Figure 22 The first eyepiece 1210 and the second eyepiece 1220 are shown to be disposed separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0245] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0246] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can be as follows: Figure 23 The setup shown is an eyeglass frame, which will be described later, rather than a headband 1300.

[0247] In addition, the head-mounted display 1000 may also include a battery for providing power, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0248] Figure 23 This is a perspective view showing a head-mounted display 1000_1 according to an embodiment.

[0249] refer to Figure 23 The head-mounted display 1000_1 according to the embodiment can be an eyeglasses-type display device, wherein the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to the embodiment may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0250] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the optical path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its optical path is changed by the optical path changing component 1070, provided to the user's right eye via the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines the virtual image displayed on the display device 10_3 with the real image seen through the right eye lens 1020.

[0251] Figure 23 The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, in which case the image displayed on the display device 10_3 can be provided to the user's left eye. In an embodiment, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0252] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed embodiments of the inventive concept are used in a general and descriptive sense only and are not intended to be limiting.

Claims

1. A display device comprising: a substrate; a display element layer provided over the substrate, and including a first electrode, a light-emitting layer, and a second electrode; a phase retardation layer provided over the display element layer; and a wire grid polarizer provided over the phase retardation layer, and including a wire grid pattern in which an insulating pattern and a lattice pattern are stacked, wherein the insulating pattern and the lattice pattern contain doped ions. The doped ions contain boron ions.

2. The display device of claim 1, wherein, A concentration of the doped ions contained in the insulating pattern is different from a concentration of the doped ions contained in the lattice pattern.

3. The display device of claim 1, wherein, The concentration of the doped ions contained in the insulating pattern is greater than the concentration of the doped ions contained in the lattice pattern.

4. The display device of claim 1, wherein, The concentration of the doped ions contained in the insulating pattern gradually increases from a top surface to a bottom surface of the insulating pattern.

5. The display device of claim 1, wherein, The concentration of the doped ions contained in the lattice pattern gradually increases from a top surface to a bottom surface of the lattice pattern.

6. The display device of claim 1, wherein, The concentration of the doped ions contained in the insulating pattern is equal to the concentration of the doped ions contained in the lattice pattern.

7. The display device of claim 1, wherein, The insulating pattern is provided on the lattice pattern, and a thickness of the insulating pattern is smaller than a thickness of the lattice pattern.

8. The display device of claim 1, wherein, A width of the insulating pattern is equal to a width of the lattice pattern.

9. The display device of claim 1, wherein, 10. The display device according to claim 1, further comprising: a planarization layer provided over the wire grid polarizer; and a capping layer provided under the wire grid polarizer, wherein the wire grid polarizer includes an air layer provided in a region defined by the capping layer, the wire grid pattern, and the planarization layer.

11. A display device including a display region and a non-display region, the display device comprising: a substrate; a display element layer provided in the display region, and including a first electrode, a light-emitting layer, and a second electrode; an encapsulation layer provided over the display element layer, and provided in the display region and the non-display region; a phase retardation layer provided over the encapsulation layer; and a wire grid polarizer provided over the phase retardation layer, wherein in the encapsulation layer, a first region overlapping with the display region does not contain ions, and a second region overlapping with the non-display region contains the ions. The wire grid polarizer includes a wire grid pattern in which an insulating pattern and a lattice pattern are stacked, and the insulating pattern and the lattice pattern contain the ions. The ions contain boron ions. A concentration of the ions contained in the insulating pattern is different from a concentration of the ions contained in the lattice pattern.

12. The display device of claim 11, wherein, The concentration of the ions contained in the insulating pattern is greater than the concentration of the ions contained in the lattice pattern.

13. The display device of claim 12, wherein, The concentration of the ions contained in the insulating pattern is equal to the concentration of the ions contained in the lattice pattern.

14. The display device of claim 12, wherein, 17. A method of manufacturing a display device, comprising:

15. The display device of claim 12, wherein, preparing a target substrate provided with at least a display element layer; 16. The display device of claim 12, wherein, forming a metal material layer, an insulating material layer, and a resin layer in this order over the target substrate; forming a resin pattern on the resin layer using a mold; and forming a wire grid polarizer on the resin pattern. ​ ​ performing a first etching on the resin layer to form a resin mask pattern; performing an ion doping process on the target substrate; performing a second etching on the insulating material layer to form a hard mask pattern; and performing a third etching on the metal material layer to form a grid pattern.

18. The method of claim 17, wherein, The ions used in the ion doping process include boron ions, and the dose of the boron ions is in the range of 5E15 / cm 2 to 1E16 / cm 2 .

19. The method of claim 17, wherein, The ion doping process is performed with an acceleration voltage of 10 KeV to 20 KeV.

20. The method of claim 17, wherein, Through the third etching, the hard mask pattern is formed as an insulating pattern disposed on the grid pattern to form a wire grid polarizer on the target substrate.

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