A method and apparatus for handling DMA memory access requests

By assigning numbers to DMA memory access requests and establishing request lists and pop queues, the problem of translation response backlog when the I/O bridge is blocked is solved, ensuring the sequential processing of DMA memory access requests and the timely transmission of translation responses.

CN121255685BActive Publication Date: 2026-05-26ZHIHEXINGYI TECHNOLOGY (SHANGHAI) CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
ZHIHEXINGYI TECHNOLOGY (SHANGHAI) CO LTD
Filing Date
2025-12-03
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

In the prior art, when the I/O bridge processes DMA memory access requests, the translation unit needs to support the sequential requirements of the memory access request protocol, and the translation response is prone to backlog when the bus is blocked, which can block subsequent translation requests.

Method used

By assigning numbers to memory access requests and establishing request lists and pop queues in the I/O bridge, the order of requests is maintained by sequential groups. Translation responses are buffered in the pop queue and broadcast, allowing translation units to not support the order requirements of the request protocol, and ensuring that all translation responses can still be received under downstream backpressure.

Benefits of technology

This ensures that upstream requests are not blocked when internal resources are not exhausted, thus guaranteeing timely delivery of translation responses and preventing response blocking in translation units.

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Abstract

This invention provides a DMA memory access request processing method and apparatus applied to an I / O bridge. The method includes: upon receiving a memory access request from an external device, assigning a number to the memory access request; sending a memory access address translation request to a translation unit through a translation interface; adding the memory access request to a corresponding linked list in the request channel according to the assigned number, with each sequence group corresponding to one linked list and one pop queue, and memory access requests sequentially entering the pop queue corresponding to their respective sequence groups; when a memory access request in the pop queue is triggered by a translation response, it is popped from the pop queue, and the translation response carrying the number corresponding to the memory access request is cached. The translation response carries the number information corresponding to the memory access request and the translated physical address; after the memory access request is popped from the pop queue, it is sent to the bus according to the physical address. This scheme ensures that upstream request delivery will not be blocked when internal resources are not exhausted.
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