An optoelectronically hermetically sealed optical computing system

Abstract

The application belongs to the technical field of chip packaging, and particularly relates to an optoelectronic combined optical computing system, which comprises a substrate, a first interlayer, at least one photonic chip, at least two second interlayers and at least two electronic chips; the second interlayers and the photonic chips are staggered on the upper surface of the substrate, a first gap is formed between the second interlayers and the photonic chips, the first interlayer covers the upper surfaces of the photonic chips and the second interlayers, and the electronic chips are arranged on the upper surface of the first interlayer. The application provides a "bridging type" three-dimensional packaging structure for a chip packaging structure (especially in the case that the size of the photonic chip is limited) with more complex functions or larger data processing capacity, which can improve the heat dissipation performance, dynamically optimize signal transmission according to task requirements, and comprehensively improve the performance, reliability and flexibility of the packaging structure.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and specifically relates to an optoelectronically packaged optical computing system. Background Technology

[0002] With the continuous development of integrated circuit technology, three-dimensional (3D) packaging technology has gradually become an important direction for high-performance chip packaging due to its advantages in improving integration density, shortening interconnect length, and improving signal integrity. In the field of optoelectronic integration, packaging optical chips (PIC) and electrical chips (EIC) together has become a key path to achieve high-speed, high-bandwidth data communication.

[0003] In existing optoelectronic 3D packaging structures, a mainstream approach is to directly stack and interconnect optical and electrical chips, where the electrical chip is flip-chip mounted directly onto the optical chip via interconnect structures such as bumps. While this "direct stacking" approach offers short interconnect paths, its inherent limitations are becoming increasingly apparent when pursuing higher system performance.

[0004] With the development of the data-driven era, higher performance requirements are being placed on chips. The performance of optical chips is usually directly proportional to the number of integrated photonic computing units. To achieve high performance, the size of optical chips needs to be increased. However, due to limitations in wafer manufacturing and packaging processes, the size of optical chips cannot be increased indefinitely. When the performance of a single optical chip reaches a bottleneck, the natural approach is to package multiple optical chips into a single system. However, in the aforementioned direct stacking architecture, each optical chip requires an electrical chip of a matching size to directly cover it. This not only places extremely high demands on the manufacturing yield of large-area electrical chips but also leads to a complex overall package structure and difficulties in yield control.

[0005] In addition, the aforementioned structure of directly stacking optical and electrical chips also suffers from at least insufficient heat dissipation and rigid signal transmission paths.

[0006] Therefore, there is an urgent need for a new type of optoelectronic encapsulation structure to meet the needs of big data processing while ensuring the reliability of the encapsulation structure. Summary of the Invention

[0007] The purpose of this invention is to provide an optoelectronically packaged optical computing system to partially alleviate or solve the above-mentioned problems, so as to meet the needs of big data processing while ensuring the reliability of the packaging structure.

[0008] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution:

[0009] An optoelectronically integrated optical computing system includes:

[0010] A substrate, a first interposer, at least one photonic chip, at least two second interposers, and at least two electronic chips;

[0011] The second interposer layer and the photonic chip are alternately disposed on the upper surface of the substrate, a first gap is formed between the second interposer layer and the photonic chip, the first interposer layer covers the upper surface of the photonic chip and the second interposer layer, and the electronic chip is disposed on the upper surface of the first interposer layer;

[0012] The upper and lower surfaces of the second interposer are connected to the first interposer and the substrate, respectively. The upper surface of the photonic chip is connected to the first interposer, and the lower surface of the electronic chip is connected to the first interposer, thereby forming a first signal transmission path that sequentially passes through the substrate, the second interposer, the first interposer, the electronic chip, and the first interposer, and finally reaches the photonic chip.

[0013] As an improvement, a signal connection is established between the lower surface of the photonic chip and the substrate to form a second signal transmission path from the substrate to the photonic chip.

[0014] As an improvement, a first connection structure is provided between the second interposer and the substrate, a second connection structure is provided between the second interposer and the first interposer, a third connection structure is provided between the first interposer and the electronic chip, a fourth connection structure is provided between the first interposer and the photonic chip, and a fifth connection structure is provided between the photonic chip and the substrate.

[0015] As an improvement, the first to fifth connection structures are selected from at least one of bumps, through-silicon vias, bonding wires, solder balls, or hybrid bonding structures.

[0016] As an improvement, the electronic chip is provided with a first functional area and a second functional area. The first functional area integrates a receiver, a transmitter, a transimpedance amplifier, and a digital interface. The second functional area integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter, and an analog-to-digital converter. The first functional area is close to the photonic chip, and the second functional area is close to the second interposer layer.

[0017] As an improvement, the upper surface of the photonic chip is divided into a first region and a second region, with the electronic chip located above the first region and the second region used for connection with an external optical fiber.

[0018] As an improvement, the second region extends outside the first intermediary layer, so that the top of the second region is unobstructed.

[0019] As an improvement, a second gap is provided between two adjacent electronic chips.

[0020] As an improvement, a connection layer is provided between the photonic chip and the substrate, and the connection layer is filled with a dielectric adhesive material.

[0021] As an improvement, the dielectric adhesive material is a DAF film.

[0022] The principle and beneficial technical effects of this invention are as follows:

[0023] Unlike existing technologies that directly stack photonic and electronic chips, this application provides a "bridged" three-dimensional packaging structure for chip packaging structures with more complex functions or larger data processing volumes (especially when the size of photonic chips is limited). This structure physically forms two selectable signal transmission paths and, in conjunction with the functional partitioning of the electronic chip, improves heat dissipation performance while enabling the system to dynamically optimize signal transmission according to task requirements. This comprehensively enhances the performance, reliability, and flexibility of the packaging structure, making it particularly suitable for fixed-function scenarios with stringent requirements for integration density, heat dissipation, and manufacturing yield, such as high-speed optical communication transceiver modules and wearable devices.

[0024] First, this invention effectively breaks through the size limit of a single photonic chip due to process limitations by using a layout of "one (large interposer) carrying multiple (electrical chips)". In other words, the electronic chip and the photonic chip are partially connected by bridging, and the upper surface of the photonic chip can be fully utilized. At the same time, two distinct signal transmission paths are formed within the entire packaging structure. That is, by constructing a first signal transmission path (via the second interposer and the electrical chip) and a second signal transmission path (directly via the photonic chip), this structure provides a dual-channel path option, ensuring data transmission efficiency.

[0025] Furthermore, the electrical chip is mounted across the second interposer and the photonic chip, with the first and second gaps forming between them introducing vertical heat dissipation channels within the tightly integrated three-dimensional structure. This allows for more efficient airflow or cooling medium circulation, significantly improving the heat dissipation efficiency of the core heat source (especially the electrical chip) and fundamentally alleviating the problem of concentrated heat sources and difficulty in heat dissipation in traditional stacked structures.

[0026] Furthermore, this solution partitions the internal structure of the electronic chip, enabling the matching of different signal transmission paths for different functions. In other words, it provides a distribution scheme with paths of varying lengths within the chip. Specifically, components with higher speed requirements (such as receivers, transmitters, transimpedance amplifiers, and digital interfaces) are placed in the first region with shorter paths, while components with lower processing speed requirements (such as power supplies, clocks, drivers, grounding terminals, digital-to-analog converters, and analog-to-digital converters) are placed in the second region with longer paths. This solution provides a dual-path selection scheme, preventing heat buildup at the source while ensuring efficient data transmission and processing. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0028] Figure 1 This is a schematic diagram of an optoelectronically encapsulated optical computing system according to an exemplary embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of an optoelectronically encapsulated optical computing system according to another exemplary embodiment of the present invention;

[0030] Figure 3 This is a top view of the optoelectronically encapsulated optical computing system in an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the partition structure of the electrical chip in an embodiment of the present invention;

[0032] Figure 5 This is a top view of an optoelectronically encapsulated optical computing system according to another embodiment of the present invention;

[0033] Figure 6 This is a top view of an optoelectronically encapsulated optical computing system according to another embodiment of the present invention;

[0034] Figure 7 This is a flowchart illustrating the working method of the optoelectronic co-packed optical computing system in an embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of an optical computing system including a control module in an embodiment of the present invention.

[0036] In the diagram, the markings are as follows: 100, substrate; 200, first interposer; 300, second interposer; 400, photonic chip; 410, first region; 420, second region; 500, electronic chip; 510, first functional area; 520, second functional area; 610, first connection structure; 620, second connection structure; 630, third connection structure; 640, fourth connection structure; 650, fifth connection structure; 700, optical fiber; 800, first gap; 900, second gap. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0038] In this document, suffixes such as "module," "component," or "unit" used to denote elements are used solely for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "component," or "unit" may be used interchangeably. In this document, terms such as "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," and "connected," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. In this document, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0040] Example 1

[0041] For fixed-function scenarios with stringent requirements for integration density, heat dissipation, and manufacturing yield, such as high-speed optical communication transceiver modules, co-packaged optical (CPO) switching equipment, and customized computing accelerator cards, this embodiment provides an optoelectronically packaged optical computing system. In these scenarios, the system's task type and load are relatively stable. This structure, through predefined physical paths and optimized heat dissipation channels, can integrate more computing units per unit area, significantly improve long-term thermal reliability, and reduce the risk of performance degradation and failure due to high heat density.

[0042] Specifically, this embodiment provides an optoelectronically packaged optical computing system, see [link to relevant documentation]. Figures 1-6 ,include:

[0043] The substrate 100, the first interposer 200, at least one photonic chip 400 (also referred to herein as an optical chip), at least two second interposers 300, and at least two electronic chips 500 (also referred to herein as electronic chips).

[0044] The second interposer layer 300 and the photonic chip 400 are alternately disposed on the upper surface of the substrate 100, a first gap 800 is formed between the second interposer layer 300 and the photonic chip 400, the first interposer layer 200 covers the upper surfaces of the photonic chip 400 and the second interposer layer 300, and the electronic chip 500 is disposed on the upper surface of the first interposer layer 200.

[0045] The upper and lower surfaces of the second interposer 300 are connected to the first interposer 200 and the substrate 100, respectively. The upper surface of the photonic chip 400 is connected to the first interposer 200, and the lower surface of the electronic chip 500 is connected to the first interposer 200. This forms a first signal transmission path that sequentially passes through the substrate 100, the second interposer 300, and the first interposer 200 to the electronic chip 500 for signal processing, and then through the first interposer 200 to the photonic chip 400 (see...). Figure 1 (middle path a).

[0046] The substrate 100 serves as the mechanical support and electrical foundation of the system. The first intermediary layer serves as a signal bridging layer between the upper electronic chip 500 and the lower photonic chip 400. The photonic chip 400 is used to perform optical computing and optical signal processing. The second intermediary layer 300 is used for signal relay and electrical connection. The electronic chip 500 is used for electrical signal processing and control.

[0047] In other words, unlike the stacked structure in existing technologies, this invention provides a cross-connection structure. Through the cooperation between the second interposer layer 300 and the photonic chip 400, and through the indirect bridging of electrical chips on the upper layer of the second interposer layer 300, on the one hand, the first gap 800 formed between the second interposer layer 300 and the optical chip, and the second gap 900 formed between multiple electrical chips (if any), the two gaps serve as channels for heat convection and radiation, which can improve the heat dissipation performance of the packaging structure. On the other hand, with the rapid development of modern computer networks, higher requirements are placed on chip performance. The above-mentioned cross-connection scheme can enable multiple electrical chips to be integrated with the optical chip at the same time. That is, even if the size of the optical chip is limited or the packaging capability is limited, and it is not possible to manufacture larger-sized optical chips, the need for efficient heat dissipation under the requirements of large data transmission and processing can still be met.

[0048] In some embodiments, the lower surface of the photonic chip 400 is connected to the substrate 100 to form a second signal transmission path from the substrate 100 to the photonic chip 400 (see [reference]). Figure 2 (middle path b).

[0049] In this process, an external controller or the logic circuit inside the chip can guide the signal to select a shorter second signal transmission path or a longer first signal transmission path, based on the signal type (such as high-speed data signal / low-speed control signal) or task load, by controlling the switching circuit or pre-designed wiring rules.

[0050] In other words, this application also provides a dual-path scheme, which forms signal transmission paths of different lengths through the above structure. For task types with high data processing speed requirements, a second signal transmission path with a shorter signal transmission path can be selected. Correspondingly, for task types with low data processing speed requirements, a first signal transmission path with a shorter signal transmission path can be selected, thereby optimizing the flexibility of data processing and alleviating the serious heat generation problem caused by excessive concentration of data transmission pressure to a certain extent.

[0051] In some embodiments, a first connection structure 610 is provided between the second interposer 300 and the substrate 100, a second connection structure 620 is provided between the second interposer 300 and the first interposer 200, a third connection structure 630 is provided between the first interposer 200 and the electronic chip 500, a fourth connection structure 640 is provided between the first interposer 200 and the photonic chip 400, and a fifth connection structure 650 is provided between the photonic chip 400 and the substrate 100.

[0052] In some embodiments, the first to fifth connection structures (the first connection structure 610, the second connection structure 620, the third connection structure 630, the fourth connection structure 640, and the fifth connection structure 650) are selected from at least one of bumps, through-silicon vias, bonding wires, solder balls, or hybrid bonding structures. That is, they can be selected according to specific needs to achieve a reliable electrical connection; for example, the first to fourth connection structures 640 may use bumps, and the fifth connection structure 650 may use solder balls.

[0053] In some embodiments, the electronic chip 500 is provided with a first functional area 510 and a second functional area 520. The first functional area 510 integrates a receiver, a transmitter, a transimpedance amplifier, and a digital interface. The second functional area 520 integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter, and an analog-to-digital converter. The first functional area 510 is located near the photonic chip 400, and the second functional area 520 is located near the second interposer layer 300. In other words, the electronic chip is divided into a first functional area 510 and a second functional area 520. The optical chip is connected to the first functional area 510 through a fourth interconnect structure, and the second interposer layer 300 is connected to the second functional area 520 through a third interconnect structure. The first functional area is located near the photonic chip 400 in horizontal projection, and the second functional area is located near the second interposer layer 300 in horizontal projection.

[0054] Specifically, signals that need to interact with the optical chip at high speed, received from the second interposer layer 300, can be processed directly into the first functional area 510 within the electrical chip with the shortest wiring distance, and then quickly output to the optical chip through the first interposer layer 200 below. For signals that need to be processed in the second functional area 520 (such as power distribution and clock driving), the signals need to be transmitted from the entry point to the second functional area 520, which is relatively far from the optical chip, within the electrical chip. After processing, they can then be routed to the first functional area 510 or directly managed, depending on the need, via a potentially longer internal path.

[0055] Therefore, this application creates a dual-path system within the electronic chip by partitioning low-speed and high-speed components. Specifically, components with higher speed requirements (such as receivers, transmitters, transimpedance amplifiers, and digital interfaces) are placed in the first region 410, which has a shorter path, while components with lower processing speed requirements (such as power supplies, clocks, drivers, grounding terminals, digital-to-analog converters, and analog-to-digital converters) are placed in the second region 420, which has a longer path. In other words, this application further optimizes the flexibility of data processing by providing a dual-path selection scheme.

[0056] In some embodiments, the upper surface of the photonic chip 400 is divided into a first region 410 and a second region 420. The electronic chip 500 is located above the first region 410, and the second region 420 is used for connection with an external optical fiber 700. This enables the input and output of optical signals. By partitioning the optical chip, heat dissipation is improved while facilitating the access of the external optical fiber 700. Preferably, the external optical fiber 700 is vertically connected to the optical fiber 700 array interface.

[0057] In some embodiments, see Figure 5 One photonic chip 400 can correspond to four electronic chips 500; see [link / reference] Figure 6 Two or more photonic chips 400 can be packaged on the same substrate 100, and multiple electronic chips 500 can be connected to one photonic chip 400, thereby meeting the needs of big data processing even when the size of the photonic chip 400 is limited.

[0058] In some embodiments, the second region 420 extends outside the first intermediary layer 200, such that the top of the second region 420 is unobstructed, so that the external optical fiber 700 can be accessed without obstruction.

[0059] In some embodiments, a second gap 900 is provided between two adjacent electronic chips 500. In some specific embodiments, at least two second interposers 300 are provided, and the at least two second interposers 300 are respectively located on a first side and a third side of the optical chip, with the first side and the third side disposed opposite to each other; correspondingly, at least two electronic chips 500 are provided, and a second gap 900 is provided between two adjacent electronic chips 500.

[0060] In some embodiments, a connection layer is provided between the optical chip and the substrate 100, and the connection layer is filled with a dielectric adhesive material (preferably a DAF film, i.e., a Die Attach Film, but other materials may also be used).

[0061] In some embodiments, the electrical chip 500 is selected from at least one of a wDAC chip, an xADC chip, an xDAC chip, an ASIC chip, and an I / O chip. When multiple electrical chips are available, these chips can be combined to adapt to different application scenarios. Specifically, a wDAC chip refers to a weighted digital-to-analog converter chip; an xADC chip refers to an arbitrary or programmable analog-to-digital converter chip; an xDAC chip refers to an arbitrary or programmable digital-to-analog converter chip; an ASIC chip refers to an application-specific integrated circuit chip; and an I / O chip refers to an input / output interface chip.

[0062] In summary, this application provides a "bridging" three-dimensional packaging structure for chip packaging structures with more complex functions or larger data processing volumes (especially when the size of optical chips is limited). This structure improves heat dissipation performance and enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability, and flexibility of the packaging structure.

[0063] Example 2

[0064] For dynamic scenarios with large task load fluctuations, complex environments, and extremely high requirements for energy efficiency and reliability, such as cloud computing data centers, edge computing nodes, intelligent driving vehicle computing platforms, and industrial real-time control systems, this invention also provides a dynamically adjustable high-performance optical computing system. In these scenarios, computing tasks exhibit high uncertainty and suddenness in terms of type, quantity, and time distribution. The intelligent control method provided in this embodiment enables the system to perceive its own state (e.g., temperature, load) and external demands (e.g., task type) in real time, dynamically allocate signal paths, and achieve an optimal balance between performance, power consumption, and heat dissipation, significantly improving the system's adaptability and overall energy efficiency ratio in changing environments.

[0065] Specifically, this embodiment provides an optoelectronically packaged optical computing system, see [link to relevant documentation]. Figure 8 Based on the hardware structure (optical-electric integrated optical computing system) described in Embodiment 1, this system may further include the following functional modules to achieve intelligent path management; that is, unlike the optical computing system in Embodiment 1, this system also includes:

[0066] The processing volume acquisition module is configured to acquire the processing volume of tasks in the current work task.

[0067] The first path selection module is configured to determine whether the task processing volume is greater than the preset data processing volume; if so, the first signal transmission path and the second signal transmission path are opened simultaneously.

[0068] The task type acquisition module is configured to acquire the number of type I and type II tasks in the current work task when the task processing volume is less than or equal to a preset data processing volume, wherein the processing speed requirement of type I tasks is greater than the processing speed requirement of type II tasks.

[0069] The second path selection module is configured to determine whether the number of the first type of tasks is greater than the number of the second type of tasks. If so, the second signal transmission path is opened and the first signal transmission path is closed; otherwise, the first signal transmission path is opened and the second signal transmission path is closed.

[0070] In some embodiments, it also includes:

[0071] Temperature monitoring module: configured to acquire the operating temperature of the optical chip.

[0072] Signal switching module: configured to determine whether the operating temperature exceeds a preset temperature threshold; if so, to close the second signal transmission path and open the first signal transmission path.

[0073] In some embodiments, it also includes:

[0074] The detection module is configured to periodically send detection signals to the first signal transmission path and / or the second signal transmission path; and determine whether a response signal corresponding to the detection signal is received within a preset time; if so, maintain the current working state; otherwise, mark the path as a fault path, mark the other paths as normal paths, close the fault path, and open the normal path.

[0075] In some embodiments, it also includes:

[0076] The prompting module is configured to determine whether both the first signal transmission path and the second signal transmission path are in a closed state. If so, it prompts the user to perform maintenance or replacement; otherwise, it maintains the current working mode.

[0077] In some embodiments, it also includes:

[0078] Line allocation module: configured to be used when the first signal transmission path is in the open state;

[0079] The data type transmitted through the first signal transmission path is obtained. This data type includes two categories: Category I data and Category II data. The processing speed requirement for Category I data is shorter than that for Category II data. Specifically, Category I data refers to data requiring high speed and low latency (such as core computing instructions and cache synchronization data), while Category II data refers to data with relatively lower speed requirements (such as device status control signals and analog-to-digital conversion data collected by sensors). A corresponding sub-channel is matched based on the data type. When the data type is Category I data, it is assigned to the first sub-path for transmission; when the data type is Category II data, it is assigned to the second sub-path for transmission.

[0080] In summary, this application provides a multi-level path selection scheme for a cross-platform optoelectronic co-packaged optical computing system, which controls temperature, faults, and other aspects. While improving heat dissipation performance, it enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability, and flexibility of the packaging structure.

[0081] Example 3

[0082] This embodiment provides a working method for an optoelectronically sealed optical computing system. (See also...) Figure 7 The optical computing system based on the photoelectric packaging in Embodiment 1 or 2 includes the following steps: S100, obtaining the task processing volume in the current work task; wherein, the task processing volume may be the number of data packets to be processed, the total data size, or the number of calculation operations, etc.

[0083] S200: Determine whether the task processing volume exceeds the preset data processing volume. If so, it indicates that the system is facing a high-load task, and the first signal transmission path and the second signal transmission path are simultaneously activated. Otherwise, proceed to step S300. The preset data processing volume can be pre-set by the user or system designer based on the theoretical maximum throughput of the encapsulation structure, historical operating data statistics, or the performance requirements of a specific application scenario. For example, this threshold can be set to 60%-80% of the system's saturated processing capacity to ensure that the dual-path parallel mode is activated in advance before a high load occurs, avoiding a sudden performance drop.

[0084] S300, obtain the number of Category 1 and Category 2 tasks in the current work tasks, wherein the processing speed requirement of Category 1 tasks is greater than that of Category 2 tasks; wherein, Category 1 tasks may be artificial intelligence model calculation, real-time data stream processing, etc.; and Category 2 tasks may be system status recording, data storage management, device control command execution, etc.

[0085] S400, determine whether the number of the first type of task is greater than the number of the second type of task. If so, open the second signal transmission path and close the first signal transmission path; otherwise, open the first signal transmission path and close the second signal transmission path.

[0086] In other words, this application provides a dual-path selection scheme. First, it performs an initial screening based on the workload. When the workload is large, both channels (the first and second signal transmission paths) are activated simultaneously to meet operational requirements while mitigating heat concentration to some extent. Furthermore, when only one channel needs to be activated, the task is divided according to its type. The second signal transmission path (via the optical chip) provides a more direct and lower-latency channel for high-speed signals. Prioritizing this path for high-speed tasks fully leverages the advantages of optical transmission, meeting its stringent processing speed requirements and optimizing the system's response performance to high-priority tasks. For tasks with moderate speed requirements, the first signal transmission path (electrical interconnect path) is sufficient. Disabling the second signal transmission path related to the optical chip allows it to enter a low-power state, directly reducing overall system power consumption and operating heat, extending the optical chip's lifespan, and improving heat dissipation within the packaging structure.

[0087] In some embodiments, the steps further include:

[0088] S500, obtain the operating temperature of the optical chip; wherein, the operating temperature can be obtained in real time by a temperature sensor integrated near or inside the optical chip.

[0089] S510, determine whether the operating temperature exceeds a preset temperature threshold (e.g., 85°C). If so, close the second signal transmission path and open the first signal transmission path. When the operating temperature is detected to return to below the preset temperature threshold again, switch the signal transmission path from the first signal transmission path back to the second signal transmission path. The preset temperature threshold is mainly determined by the reliable operating temperature range of the optical chip, material properties, and the heat dissipation capacity of the package. It can be set by the user after obtaining the maximum junction temperature (Tjmax) from the optical chip's product specifications and reserving a certain safety margin (e.g., 10°C to 15°C below Tjmax).

[0090] In other words, this application also provides an active thermal management strategy. When the optical chip overheats due to continuous high-load operation, the system can promptly switch it out of the working circuit, allowing it to "rest" and cool down, while the first signal transmission path takes over the data transmission task. This effectively prevents the optical chip from being damaged by overheating, greatly improves the reliability and stability of the system under high-temperature environments or long-term high-load operation, and achieves a dynamic balance between performance and heat dissipation.

[0091] In some embodiments, the working method further includes the step of:

[0092] S600, periodically sends detection signals to the first signal transmission path and / or the second signal transmission path. For example, a detection signal such as a heartbeat packet or test sequence is sent every 2 seconds.

[0093] S610, determine whether a response signal corresponding to the detection signal is received within a preset time; if yes, maintain the current working state; otherwise, mark the path as a fault path, mark the other paths as normal paths, close the fault path, and open the normal path.

[0094] In other words, this application also provides a fault self-checking mechanism. Even if a signal path fails due to physical damage, aging or other reasons, the system can automatically detect it and quickly switch to a healthy backup path, ensuring the continuity of data transmission and the availability of system services, reducing dependence on external intervention, and is particularly suitable for application scenarios that require high reliability.

[0095] In some embodiments, after S610, the following step is further included:

[0096] The system determines whether both the first and second signal transmission paths are in a closed state (or marked as faulty paths). If so, it prompts the user to perform maintenance or replacement (e.g., through indicator lights or management software interface). Otherwise, it maintains the current operating mode. When both paths fail, the system can promptly notify the user, preventing the system from operating silently in a completely failed state and facilitating rapid problem location and maintenance.

[0097] In some embodiments, the electrical chip is provided with a first functional area and a second functional area. The first functional area integrates a receiver, a transmitter, a transimpedance amplifier, and a digital interface. The second functional area integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter, and an analog-to-digital converter. The optical chip is connected to the first functional area, and the second interposer is connected to the second functional area. Accordingly, a first sub-path is formed between the substrate, the first interposer, the second interposer, the first functional area of ​​the electrical chip, and the optical chip. This path is mainly designed for low latency and high bandwidth requirements. A second sub-path is formed between the substrate, the first interposer, the second interposer, the second functional area of ​​the electrical chip, and the optical chip. This path is mainly used to handle tasks that do not require high speed but require stable power supply or analog interaction. The working method further includes:

[0098] S700, determine whether the first signal transmission path is in an open state; if so, proceed to S710.

[0099] S710, acquire the data type that has passed through the first signal transmission path, the data type includes a first type of data and a second type of data; the processing speed requirement time for the first type of data is less than the processing speed requirement time for the second type of data, that is, the first type of data refers to data that requires high speed and low latency (such as core computing instructions and cache synchronization data), and the second type of data refers to data with relatively low speed requirements (such as device status control signals and analog-to-analog conversion data collected by sensors).

[0100] S720, Match the corresponding sub-channel according to the data type, wherein when the data type is a type 1 data, the type 1 data is assigned to the first sub-path for transmission, and when the data type is a type 2 data, the type 2 data is assigned to the second sub-path for transmission.

[0101] In other words, this application provides a multi-level signal routing and allocation mechanism. First, data is allocated from the packaging level to the first / second signal transmission path. Then, the data entering the first signal transmission path is allocated at the chip level inside the chip. Through multi-level path selection, the optimal distribution of data flow at the macro and micro levels is achieved, while providing high flexibility and scalability to cope with more complex and diverse computing tasks.

[0102] In summary, this application provides a multi-level path selection scheme for a cross-platform optoelectronic co-packaged optical computing system, which controls temperature, faults, and other aspects. While improving heat dissipation performance, it enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability, and flexibility of the packaging structure.

[0103] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0104] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A photoelectric integrated optical computing system, characterized in that, include: The substrate (100), the first interposer (200), at least one photonic chip (400), at least two second interposers (300) and at least two electronic chips (500). The second interposer (300) and the photonic chip (400) are alternately disposed on the upper surface of the substrate (100), a first gap (800) is formed between the second interposer (300) and the photonic chip (400), the first interposer (200) covers the upper surfaces of the photonic chip (400) and the second interposer (300), and the electronic chip (500) is disposed on the upper surface of the first interposer (200); The upper and lower surfaces of the second interposer (300) are connected to the first interposer (200) and the substrate (100) respectively. The upper surface of the photonic chip (400) is connected to the first interposer (200), and the lower surface of the electronic chip (500) is connected to the first interposer (200), thereby forming a first signal transmission path that passes sequentially through the substrate (100), the second interposer (300), the first interposer (200), the electronic chip (500), and the first interposer (200), finally reaching the photonic chip (400). The lower surface of the photonic chip (400) is connected to the substrate (100) to form a second signal transmission path from the substrate (100) to the photonic chip (400).

2. The optoelectronic co-packed optical computing system according to claim 1, characterized in that, A first connection structure (610) is provided between the second interposer (300) and the substrate (100), a second connection structure (620) is provided between the second interposer (300) and the first interposer (200), a third connection structure (630) is provided between the first interposer (200) and the electronic chip (500), a fourth connection structure (640) is provided between the first interposer (200) and the photonic chip (400), and a fifth connection structure (650) is provided between the photonic chip (400) and the substrate (100).

3. The optoelectronic co-packed optical computing system according to claim 2, characterized in that, The first connection structure (610), the second connection structure (620), the third connection structure (630), the fourth connection structure (640), and the fifth connection structure (650) are selected from at least one of bumps, through-silicon vias, bonding wires, solder balls, or hybrid bonding structures.

4. The optoelectronic co-packed optical computing system according to claim 1, characterized in that, The electronic chip (500) is provided with a first functional area (510) and a second functional area (520). The first functional area (510) integrates a receiver, a transmitter, a transimpedance amplifier and a digital interface. The second functional area (520) integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter and an analog-to-digital converter. The first functional area (510) is close to the photonic chip (400) and the second functional area (520) is close to the second interposer (300).

5. The optoelectronic co-packed optical computing system according to claim 1, characterized in that, The upper surface of the photonic chip (400) is divided into a first region (410) and a second region (420), the electronic chip (500) is located above the first region (410), and the second region (420) is used to connect to an external optical fiber (700).

6. The optoelectronic co-packed optical computing system according to claim 5, characterized in that, The second region (420) extends outside the first intermediary layer (200), so that the top of the second region (420) is unobstructed.

7. The optoelectronic co-packed optical computing system according to claim 1, characterized in that, A second gap (900) is provided between two adjacent electronic chips (500).

8. The optoelectronic co-packed optical computing system according to claim 1, characterized in that, A connection layer is provided between the photonic chip (400) and the substrate (100), and the connection layer is filled with dielectric adhesive material.

9. The optoelectronic co-packed optical computing system according to claim 8, characterized in that, The dielectric adhesive material is a DAF film.

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