Schottky diode device and preparation method thereof
By optimizing the structural design of Schottky diodes, including trench etching and overlapping arrangement of P-type regions, the problems of current concentration and overheating of traditional MPS diodes under high surge current conditions are solved, achieving low on-state voltage drop and low reverse leakage current while improving the stability and reliability of the device.
Patent Information
- Application Number
- CN202511533427.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-01-06
AI Technical Summary
Traditional MPS diodes are prone to problems such as current concentration and local overheating under high surge current conditions, making it difficult to simultaneously optimize the forward voltage drop and reverse leakage current.
The structure is designed with an N-type substrate layer, an N-type buffer layer, first and second N-type epitaxial layers, first and second P-type regions, an anode ohmic metal contact layer, and an anode Schottky metal contact layer. The Schottky metal contact area is increased by trench etching, and the P-type regions are overlapped in the vertical direction to form a continuous depletion layer, ensuring low on-state voltage drop and low reverse leakage current.
It significantly improves the stability and reliability of the device under high surge current, while taking into account both low on-state voltage drop and low reverse leakage current, thus enhancing surge resistance.
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Figure CN121284984A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power semiconductor technology, specifically relating to a Schottky diode device and its fabrication method. Background Technology
[0002] In the field of power semiconductor devices, MPS (Merged PiN Schottky) diodes are widely used in high-efficiency power conversion systems due to their high breakdown voltage, low on-state voltage drop, and fast recovery characteristics. However, the layout of the P-type injection region and the Schottky metal contact region in traditional MPS diodes is limited, making it difficult to simultaneously optimize the on-state voltage drop and reverse leakage current. Furthermore, under high surge current conditions, traditional structures are prone to current concentration and localized overheating, affecting device reliability and lifespan. Therefore, a new device structure is urgently needed that can improve surge immunity while maintaining low on-state voltage drop and low reverse leakage current. Summary of the Invention
[0003] The purpose of this application is to provide a Schottky diode device and its fabrication method, which can solve the problem of simultaneously optimizing the forward voltage drop and reverse leakage current of a diode device.
[0004] In a first aspect, embodiments of this application provide a Schottky diode device, comprising: N-type substrate layer; An N-type buffer layer is disposed above the N-type substrate layer; The first N-type epitaxial layer is disposed above the N-type buffer layer; The first P-type region is located inside the first N-type epitaxial layer; the upper surface of the first P-type region is flush with the upper surface of the first N-type epitaxial layer. A second N-type epitaxial layer is disposed above the first N-type epitaxial layer; the upper surface of the second N-type epitaxial layer includes a plurality of trenches; The second P-type region is disposed inside the second N-type epitaxial layer; the upper surface of the second P-type region is flush with the upper surface of the second N-type epitaxial layer, and the lower surface of the second P-type region is flush with the lower surface of the second N-type epitaxial layer; the center position of the second P-type region is aligned with the center position of the first P-type region, and the size of the second P-type region is less than or equal to the size of the first P-type region. An anode ohmic metal contact layer is disposed above the second P-type region; An anode Schottky metal contact layer is disposed above the anode ohmic metal contact layer and the second N-type epitaxial layer; An anode metal layer is disposed above the anode Schottky metal contact layer; A cathode metal layer is disposed below the N-type substrate layer.
[0005] Optionally, there may be multiple first P-type regions, and the first P-type regions do not contact each other.
[0006] Optionally, the N-type substrate layer is made of 4H-SiC, 6H-SiC, or 3C-SiC single crystal substrate.
[0007] Optionally, the doping concentration of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer.
[0008] Optionally, the doping concentration of the second P-type region is higher than that of the first P-type region.
[0009] Secondly, embodiments of this application provide a method for fabricating a Schottky diode device, the method comprising: Forming an N-type substrate layer; An N-type buffer layer is formed above the N-type substrate layer; A first N-type epitaxial layer is formed above the N-type buffer layer; A first P-type region is formed inside the first N-type epitaxial layer; the upper surface of the first P-type region is flush with the upper surface of the first N-type epitaxial layer; A second N-type epitaxial layer is formed above the first N-type epitaxial layer; the upper surface of the second N-type epitaxial layer includes a plurality of trenches; A second P-type region is formed inside the second N-type epitaxial layer; the upper surface of the second P-type region is flush with the upper surface of the second N-type epitaxial layer, and the lower surface of the second P-type region is flush with the lower surface of the second N-type epitaxial layer; the center position of the second P-type region is aligned with the center position of the first P-type region, and the size of the second P-type region is less than or equal to the size of the first P-type region; An anode ohmic metal contact layer is formed above the second P-type region; An anode Schottky metal contact layer is formed above the anode ohmic metal contact layer and the second N-type epitaxial layer; An anode metal layer is formed above the anode Schottky metal contact layer; A cathode metal layer is formed beneath the N-type substrate.
[0010] Optionally, there may be multiple first P-type regions, and the first P-type regions do not contact each other.
[0011] Optionally, the N-type substrate layer is made of 4H-SiC, 6H-SiC, or 3C-SiC single crystal substrate.
[0012] Optionally, the doping concentration of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer.
[0013] Optionally, the doping concentration of the second P-type region is higher than that of the first P-type region.
[0014] Thirdly, embodiments of this application provide a chip including the aforementioned Schottky diode device.
[0015] The embodiments of this application have the following advantages: The Schottky diode device in this application embodiment includes: an N-type substrate layer, an N-type buffer layer, a first N-type epitaxial layer, a first P-type region, a second N-type epitaxial layer, a second P-type region, an anode ohmic metal contact layer, an anode Schottky metal contact layer, an anode metal layer, and a cathode metal layer.
[0016] The upper surface of the second N-type epitaxial layer includes multiple trenches. Through trench etching, the Schottky metal contact area and the Ohm metal contact area are increased without changing the chip size, which can reduce the on-state voltage drop and improve the device's surge resistance.
[0017] The bilayer epitaxial structure of the first N-type epitaxial layer and the second N-type epitaxial layer increases the doping concentration at the Schottky metal-semiconductor interface, narrows the depletion layer at the Schottky contact surface, increases the hot electron emission current, reduces the effective barrier height, enhances the tunneling effect, and decreases the on-state voltage drop.
[0018] During reverse withstand voltage, the first P-type region and the first epitaxial layer, and the second P-type region and the second epitaxial layer deplete each other to form a depletion layer. As the reverse bias increases, the depletion layer gradually widens. When a certain withstand voltage is reached, the depletion layers connect to each other, shielding the Schottky barrier from the high electric field, preventing the Schottky barrier reduction effect, and ensuring low reverse leakage current.
[0019] In the vertical direction, the second P-type region overlaps with the first P-type region, with the center of the second P-type region aligned with the center of the first P-type region. The size of the second P-type region is less than or equal to the size of the first P-type region. The smaller size of the second P-type region increases the proportion of the contact area between the Schottky metal and the second N-type epitaxial layer, ensuring a low on-state voltage drop. The larger size of the first P-type region can disperse the current path and distribute the current evenly under high current conditions, preventing excessive current density and localized overheating, thereby significantly improving the device's surge protection capability.
[0020] This application features a full-ohmic P-type region design, meaning that the entire surface of the second P-type region forms ohmic contact with the metal layer. Compared to the traditional MPS diode structure combining a large-ohmic P-type region and a small-ohmic P-type region, this application's structure is more conducive to current sharing and heat dissipation, and offers superior surge resistance, while maintaining the same total P-type region area ratio. This application significantly improves the stability and reliability of the device under high surge currents while balancing low on-state voltage drop and low reverse leakage current. Attached Figure Description
[0021] Figure 1 This is a structural block diagram of a Schottky diode device according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the steps of a method for fabricating a Schottky diode device according to an embodiment of the present invention; Figure 3 This is a structural block diagram of another Schottky diode device according to an embodiment of the present invention; Figure 4 This is a structural block diagram of another Schottky diode device according to an embodiment of the present invention; Figure 5 This is a structural block diagram of another Schottky diode device according to an embodiment of the present invention; Figure 6 This is a structural block diagram of another Schottky diode device according to an embodiment of the present invention; Figure 7 This is a structural block diagram of another Schottky diode device according to an embodiment of the present invention.
[0022] Explanation of reference numerals in the attached figures: 1. N-type substrate layer; 2. N-type buffer layer; 3. First N-type epitaxial layer; 4. First P-type region; 5. Second N-type epitaxial layer; 6. Second P-type region; 7. Anode ohmic metal contact layer; 8. Anode Schottky metal contact layer; 9. Anode metal layer; 10. Cathode metal layer. Detailed Implementation
[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0024] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0025] The following description, in conjunction with the accompanying drawings, details a Schottky diode device and its fabrication method provided in this application through specific embodiments and application scenarios.
[0026] Reference Figure 1 This diagram illustrates a structural block diagram of a Schottky diode device according to an embodiment of the present invention. The Schottky diode device includes: N-type substrate layer 1; An N-type buffer layer 2 is disposed above the N-type substrate layer 1; The first N-type epitaxial layer 3 is disposed above the N-type buffer layer 2; The first P-type region 4 is disposed inside the first N-type epitaxial layer 3; the upper surface of the first P-type region 4 is flush with the upper surface of the first N-type epitaxial layer 3. The second N-type epitaxial layer 5 is disposed above the first N-type epitaxial layer 3; the upper surface of the second N-type epitaxial layer 5 includes a plurality of trenches; The second P-type region 6 is disposed inside the second N-type epitaxial layer 5; the upper surface of the second P-type region 6 is flush with the upper surface of the second N-type epitaxial layer 5, and the lower surface of the second P-type region 6 is flush with the lower surface of the second N-type epitaxial layer 5; the center position of the second P-type region 6 is aligned with the center position of the first P-type region 4, and the size of the second P-type region 6 is less than or equal to the size of the first P-type region 4. An anode ohmic metal contact layer 7 is disposed above the second P-type region 6; An anode Schottky metal contact layer 8 is disposed above the anode ohmic metal contact layer 7 and the second N-type epitaxial layer 5; An anode metal layer 9 is disposed above the anode Schottky metal contact layer 8; A cathode metal layer 10 is disposed below the N-type substrate layer 1.
[0027] In this embodiment, the Schottky diode device includes: an N-type substrate layer, an N-type buffer layer, a first N-type epitaxial layer, a first P-type region, a second N-type epitaxial layer, a second P-type region, an anode ohmic metal contact layer, an anode Schottky metal contact layer, an anode metal layer, and a cathode metal layer.
[0028] The N-type substrate layer serves as the physical base of the entire device structure, providing mechanical strength and stability.
[0029] An N-type buffer layer is used to form a transition region of doping concentration between a heavily doped substrate and a lightly doped epitaxial layer.
[0030] The trench structure of the second N-type epitaxial layer increases the surface area of the Schottky metal contact with the N-type semiconductor, thereby effectively increasing the cross-sectional area of the Schottky junction per unit area, which helps to reduce the forward conduction resistance and voltage drop; at the same time, it provides space for the second P-type region, enabling it to be aligned vertically with the first P-type region to form a continuous electric field modulation.
[0031] The second P-type region and the first P-type region below it are aligned vertically to form a continuous P-type columnar region that penetrates the first and second N-type epitaxial layers. Under reverse bias, the P-pillars and N-type regions deplete each other, generating an almost uniform electric field distribution, which can greatly improve the breakdown voltage without significantly increasing the on-resistance.
[0032] The anode ohmic metal contact layer forms an ohmic contact with the P-type region, and a non-rectifying contact with very low resistance is formed on top of the second P-type region, ensuring that holes can be effectively extracted or injected from the P-type region.
[0033] The Schottky barrier exists at the interface between the Schottky metal and the semiconductor. The anode Schottky metal contact layer and the second N-type epitaxial layer form the Schottky barrier, which is responsible for the device's low forward voltage drop and fast switching characteristics. Under forward bias, electrons can cross the relatively low barrier, forming a large current; under reverse bias, the current is blocked.
[0034] The anode metal layer connects the anode Schottky metal contact layer and the anode ohmic metal contact layer, providing a unified, low-resistance anode interface for external circuit connection. The cathode metal layer forms a low-resistance ohmic contact with the N-type substrate layer, completing the vertical current path.
[0035] This embodiment of the application increases the Schottky metal contact area and the ohmic metal contact area by creating trenches on the upper surface of the second N-type epitaxial layer without changing the chip size, thereby reducing the on-state voltage drop and improving the device's surge resistance. The bilayer epitaxial structure of the first and second N-type epitaxial layers increases the doping concentration at the Schottky metal-semiconductor interface, narrows the depletion layer at the Schottky contact surface, increases the thermionic emission current, reduces the effective barrier height, enhances the tunneling effect, and decreases the on-state voltage drop. During reverse breakdown, the first P-type region depletes with the first epitaxial layer, and the second P-type region depletes with the second epitaxial layer, forming a depletion layer. As the reverse bias increases, the depletion layer gradually widens. When a certain breakdown voltage is reached, the depletion layers interconnect, shielding the Schottky barrier from the high electric field, preventing the Schottky barrier reduction effect, and ensuring low reverse leakage current. In the vertical direction, the second P-type region overlaps with the first P-type region, with the center of the second P-type region aligned with the center of the first P-type region. The size of the second P-type region is less than or equal to that of the first P-type region. The smaller size of the second P-type region increases the proportion of the contact area between the Schottky metal and the second N-type epitaxial layer, ensuring a low on-state voltage drop. The larger size of the first P-type region can disperse the current path and evenly distribute the current under high current conditions, preventing excessive current density and localized overheating, thus significantly improving the device's surge resistance. Furthermore, this application features a full-ohmic P-type region design, meaning that the entire surface of the second P-type region forms an ohmic contact with the metal layer. Compared to the traditional MPS diode structure combining large and small P-type regions, this application's structure is more conducive to current equalization and heat dissipation, resulting in superior surge resistance, while maintaining the same total P-type region area ratio. This application significantly improves the stability and reliability of the device under high surge currents while balancing low on-state voltage drop and low reverse leakage current.
[0036] In one embodiment, there are multiple first P-type regions 4, and the individual first P-type regions 4 do not contact each other.
[0037] In this embodiment, under reverse bias, each independent first P-type region forms a parallel PN junction with its surrounding N-type epitaxial layer. The depletion regions of these PN junctions extend laterally. When multiple P-type regions are arranged closely and isolated, their depletion regions influence and connect with each other, forming a uniform and continuous depletion layer across the entire lateral plane of the device. The use of multiple isolated small P-type regions, with the region between these P-type regions being an N-type semiconductor, allows for the formation of an effective Schottky junction with the overlying anode Schottky metal.
[0038] In one embodiment, the N-type substrate layer is made of 4H-SiC, 6H-SiC, or 3C-SiC single crystal substrate.
[0039] In this embodiment, the silicon carbide substrate enables the Schottky diode to simultaneously achieve extremely high reverse breakdown voltage and extremely low forward voltage drop, resulting in efficiency far exceeding that of silicon-based devices. 4H-SiC exhibits high electron mobility and isotropic electrical properties. 3C-SiC, a cubic SiC, can be heteroepitaxially grown on a silicon substrate at a lower cost.
[0040] In one embodiment, the doping concentration of the second N-type epitaxial layer 5 is higher than that of the first N-type epitaxial layer 3.
[0041] In this embodiment, the anode Schottky metal forms a Schottky junction through direct contact with the second N-type epitaxial layer. The second N-type epitaxial layer, as the first station for vertical current flow, has a resistance that is a significant component of the device's total series resistance. Increasing the doping concentration of the second N-type epitaxial layer directly reduces its bulk resistance, resulting in less resistance for electrons flowing through the Schottky junction and into the semiconductor bulk. Consequently, under the same forward current, the forward voltage drop of the device is significantly reduced.
[0042] The low-doped first N-type epitaxial layer is the main depletion region, bearing most of the reverse voltage. The high-doped second N-type epitaxial layer, due to its high doping concentration, has a very thin depletion layer. This pushes the peak region of the high electric field away from the Schottky contact interface, which is extremely sensitive to defects and electric fields, and confines it within the more uniform and bulk-area first N-type epitaxial layer. The high electric field is the main cause of the Schottky barrier reduction and the surge in reverse leakage current. Keeping this high-electric-field region away from the interface can effectively suppress reverse leakage current, protect the Schottky interface from high electric field stress, and extend device lifetime.
[0043] In one embodiment, the doping concentration of the second P-type region 6 is higher than that of the first P-type region 4.
[0044] In this embodiment, under reverse bias, the P-type region provides positive charge (holes) and the N-type region provides negative charge (electrons). Ideally, they achieve dynamic equilibrium in the depletion region, meaning the total amount of positive and negative charge is equal, but their distribution varies with the bias voltage. As mentioned earlier, the second N-type epitaxial layer has a higher doping concentration, meaning it has more negative charge per unit volume. To effectively deplete this region under reverse bias, the adjacent second P-type region needs to provide a higher density of positive charge to balance it. By increasing the doping concentration of the second P-type region, precise charge balance can be ensured in the upper region near the Schottky junction. This prevents premature electric field concentration or breakdown due to charge imbalance, resulting in a smoother electric field transition from the upper to the lower layers.
[0045] Moreover, the total charge in the P-type region is determined by both its doping concentration and volume. Given the need to provide the same total charge, a higher doping concentration means that the lateral dimensions of the second P-type region can be made smaller. A smaller P-type region size leaves more area for the contact between the anode Schottky metal and the second N-type epitaxial layer, which directly increases the effective Schottky junction area and helps to further reduce the device's on-resistance and forward voltage drop.
[0046] Reference Figure 2 The diagram illustrates a step-by-step flowchart of a method for fabricating a Schottky diode device according to an embodiment of the present invention. The method may specifically include the following steps: Step 201: Form an N-type substrate layer; Step 202: An N-type buffer layer is formed on top of the N-type substrate layer; Reference Figure 3 The diagram illustrates a structural block diagram of another Schottky diode device according to an embodiment of the present invention. Figure 3 The first epitaxial growth is performed on the upper surface of the N-type substrate layer 1 to obtain the N-type buffer layer 2.
[0047] Step 203: A first N-type epitaxial layer is formed above the N-type buffer layer; Step 204: A first P-type region is formed inside the first N-type epitaxial layer; the upper surface of the first P-type region is flush with the upper surface of the first N-type epitaxial layer. Reference Figure 4 The diagram illustrates a structural block diagram of another Schottky diode device according to an embodiment of the present invention. Figure 4 A second epitaxial growth is performed on the upper surface of the N-type buffer layer 2 to obtain the first N-type epitaxial layer 3. After cleaning the first N-type epitaxial layer 3, an oxide layer is deposited on its upper surface, and photoresist is spin-coated on the upper surface of the oxide layer. The first P-type region 4 implantation window is formed by photolithography and etching processes. The photoresist is removed, and the oxide layer is retained as a mask. P-type ion implantation is performed, and the mask is removed to obtain the first P-type region 4.
[0048] Step 205: A second N-type epitaxial layer is formed above the first N-type epitaxial layer; the upper surface of the second N-type epitaxial layer includes a plurality of trenches; Step 206: A second P-type region is formed inside the second N-type epitaxial layer; the upper surface of the second P-type region is flush with the upper surface of the second N-type epitaxial layer, and the lower surface of the second P-type region is flush with the lower surface of the second N-type epitaxial layer; the center position of the second P-type region is aligned with the center position of the first P-type region, and the size of the second P-type region is less than or equal to the size of the first P-type region. Reference Figure 5The diagram illustrates a structural block diagram of another Schottky diode device according to an embodiment of the present invention. Figure 5 A third epitaxial growth is performed on the surface of the first N-type epitaxial layer 3 to obtain the second N-type epitaxial layer 5. An oxide layer is deposited on its upper surface, and photoresist is spin-coated onto the oxide layer. Trapezoidal trenches are formed through photolithography and etching processes, and the photoresist and oxide layer are removed. Another oxide layer is deposited, and photoresist is spin-coated onto its upper surface. An implantation window for the second P-type region 6 is formed through photolithography and etching processes, the photoresist is removed, and the oxide layer is retained as a mask for P-type ion implantation. The mask is removed, and a sacrificial oxide layer is formed on the surface of the second N-type epitaxial layer. A carbon film is then deposited to protect the SiC material surface during thermal annealing. Thermal annealing is then performed, and after activating the implanted ions, the carbon film is removed to obtain the second P-type region 6. In the horizontal direction, the center of the second P-type region 6 is flush with the center of the first P-type region 4, and the size of the second P-type region 6 is less than or equal to the size of the first P-type region 4. In the vertical direction, the second P-type region 6 overlaps the first P-type region 4 vertically.
[0049] Step 207: Form an anode ohmic metal contact layer above the second P-type region; Reference Figure 6 The diagram illustrates a structural block diagram of another Schottky diode device according to an embodiment of the present invention. Figure 6 A nickel (Ni) metal layer is sputtered onto the surface of the second N-type epitaxial layer 5, and then photoresist is spin-coated onto its surface. After photolithography and development, the exposed nickel metal layer is removed by dry etching. The photoresist is removed and the metal layer is thermally annealed to form the anode ohmic metal contact layer 7.
[0050] Step 208: An anode Schottky metal contact layer is formed over the anode ohmic metal contact layer and the second N-type epitaxial layer; Step 209: An anode metal layer is formed above the anode Schottky metal contact layer; Step 210: A cathode metal layer is formed beneath the N-type substrate layer.
[0051] Reference Figure 7 The diagram illustrates a structural block diagram of another Schottky diode device according to an embodiment of the present invention. Figure 7A titanium (Ti) metal layer is sputtered onto the surface of the second N-type epitaxial layer 5, and an aluminum (Al) metal layer is sputtered onto the surface of the titanium metal layer. Then, photoresist is spin-coated onto the surface of the aluminum metal layer. After photolithography and development, the exposed aluminum metal layer is removed by dry etching or wet etching to form the anode metal layer 9. The exposed titanium metal layer is then removed by dry etching to form the anode Schottky metal contact layer 8. Next, the substrate thickness of the N-type substrate layer 1 is reduced by one or more methods such as mechanical grinding, chemical etching, or ICP etching to decrease the resistance of the N-type substrate layer 1. A cathode metal layer 10 is formed on the thinned surface of the N-type substrate layer 1 by sputtering, wherein the cathode metal layer 10 is made of one or more of nickel, titanium, and silver.
[0052] This embodiment of the application increases the Schottky metal contact area and the ohmic metal contact area by creating trenches on the upper surface of the second N-type epitaxial layer without changing the chip size, thereby reducing the on-state voltage drop and improving the device's surge resistance. The bilayer epitaxial structure of the first and second N-type epitaxial layers increases the doping concentration at the Schottky metal-semiconductor interface, narrows the depletion layer at the Schottky contact surface, increases the thermionic emission current, reduces the effective barrier height, enhances the tunneling effect, and decreases the on-state voltage drop. During reverse breakdown, the first P-type region depletes with the first epitaxial layer, and the second P-type region depletes with the second epitaxial layer, forming a depletion layer. As the reverse bias increases, the depletion layer gradually widens. When a certain breakdown voltage is reached, the depletion layers interconnect, shielding the Schottky barrier from the high electric field, preventing the Schottky barrier reduction effect, and ensuring low reverse leakage current. In the vertical direction, the second P-type region overlaps with the first P-type region, with the center of the second P-type region aligned with the center of the first P-type region. The size of the second P-type region is less than or equal to that of the first P-type region. The smaller size of the second P-type region increases the proportion of the contact area between the Schottky metal and the second N-type epitaxial layer, ensuring a low on-state voltage drop. The larger size of the first P-type region can disperse the current path under high current conditions, uniformly distributing the current and preventing excessive current density that could lead to localized overheating, thus significantly improving the device's surge resistance. Furthermore, the high concentration of the second P-type region reduces the resistance within the P-type region, reducing heat generation and improving surge reliability under large surge current conditions. This application also features a full-ohmic P-type region design, meaning that the entire surface of the second P-type region forms an ohmic contact with the metal layer. Compared to the traditional MPS diode structure combining large and small P-type regions, this application's structure is more conducive to current equalization and heat dissipation, resulting in superior surge resistance, while maintaining the same total P-type region area ratio. This application significantly improves the stability and reliability of the device under high surge current while balancing low on-state voltage drop and low reverse leakage current.
[0053] In one embodiment, there are multiple first P-type regions 4, and the individual first P-type regions 4 do not contact each other.
[0054] In this embodiment, under reverse bias, each independent first P-type region forms a parallel PN junction with its surrounding N-type epitaxial layer. The depletion regions of these PN junctions extend laterally. When multiple P-type regions are arranged closely and isolated, their depletion regions influence and connect with each other, forming a uniform and continuous depletion layer across the entire lateral plane of the device. The use of multiple isolated small P-type regions, with the region between these P-type regions being an N-type semiconductor, allows for the formation of an effective Schottky junction with the overlying anode Schottky metal.
[0055] In one embodiment, the N-type substrate layer is made of 4H-SiC, 6H-SiC, or 3C-SiC single crystal substrate.
[0056] In this embodiment, the silicon carbide substrate enables the Schottky diode to simultaneously achieve extremely high reverse breakdown voltage and extremely low forward voltage drop, resulting in efficiency far exceeding that of silicon-based devices. 4H-SiC exhibits high electron mobility and isotropic electrical properties. 3C-SiC, a cubic SiC, can be heteroepitaxially grown on a silicon substrate at a lower cost.
[0057] In one embodiment, the doping concentration of the second N-type epitaxial layer 5 is higher than that of the first N-type epitaxial layer 3.
[0058] In this embodiment, the anode Schottky metal forms a Schottky junction through direct contact with the second N-type epitaxial layer. The second N-type epitaxial layer, as the first station for vertical current flow, has a resistance that is a significant component of the device's total series resistance. Increasing the doping concentration of the second N-type epitaxial layer directly reduces its bulk resistance, resulting in less resistance for electrons flowing through the Schottky junction and into the semiconductor bulk. Consequently, under the same forward current, the forward voltage drop of the device is significantly reduced.
[0059] The low-doped first N-type epitaxial layer is the main depletion region, bearing most of the reverse voltage. The high-doped second N-type epitaxial layer, due to its high doping concentration, has a very thin depletion layer. This pushes the peak region of the high electric field away from the Schottky contact interface, which is extremely sensitive to defects and electric fields, and confines it within the more uniform and bulk-area first N-type epitaxial layer. The high electric field is the main cause of the Schottky barrier reduction and the surge in reverse leakage current. Keeping this high-electric-field region away from the interface can effectively suppress reverse leakage current, protect the Schottky interface from high electric field stress, and extend device lifetime.
[0060] In one embodiment, the doping concentration of the second P-type region 6 is higher than that of the first P-type region 4.
[0061] In this embodiment, under reverse bias, the P-type region provides positive charge (holes) and the N-type region provides negative charge (electrons). Ideally, they achieve dynamic equilibrium in the depletion region, meaning the total amount of positive and negative charge is equal, but their distribution varies with the bias voltage. As mentioned earlier, the second N-type epitaxial layer has a higher doping concentration, meaning it has more negative charge per unit volume. To effectively deplete this region under reverse bias, the adjacent second P-type region needs to provide a higher density of positive charge to balance it. By increasing the doping concentration of the second P-type region, precise charge balance can be ensured in the upper region near the Schottky junction. This prevents premature electric field concentration or breakdown due to charge imbalance, resulting in a smoother electric field transition from the upper to the lower layers.
[0062] Moreover, the total charge in the P-type region is determined by both its doping concentration and volume. Given the need to provide the same total charge, a higher doping concentration means that the lateral dimensions of the second P-type region can be made smaller. A smaller P-type region size leaves more area for the contact between the anode Schottky metal and the second N-type epitaxial layer, which directly increases the effective Schottky junction area and helps to further reduce the device's on-resistance and forward voltage drop.
[0063] This embodiment of the application increases the Schottky metal contact area and the ohmic metal contact area by creating trenches on the upper surface of the second N-type epitaxial layer without changing the chip size, thereby reducing the on-state voltage drop and improving the device's surge resistance. The bilayer epitaxial structure of the first and second N-type epitaxial layers increases the doping concentration at the Schottky metal-semiconductor interface, narrows the depletion layer at the Schottky contact surface, increases the thermionic emission current, reduces the effective barrier height, enhances the tunneling effect, and decreases the on-state voltage drop. During reverse breakdown, the first P-type region depletes with the first epitaxial layer, and the second P-type region depletes with the second epitaxial layer, forming a depletion layer. As the reverse bias increases, the depletion layer gradually widens. When a certain breakdown voltage is reached, the depletion layers interconnect, shielding the Schottky barrier from the high electric field, preventing the Schottky barrier reduction effect, and ensuring low reverse leakage current. In the vertical direction, the second P-type region overlaps with the first P-type region, with the center of the second P-type region aligned with the center of the first P-type region. The size of the second P-type region is less than or equal to that of the first P-type region. The smaller size of the second P-type region increases the proportion of the contact area between the Schottky metal and the second N-type epitaxial layer, ensuring a low on-state voltage drop. The larger size of the first P-type region can disperse the current path under high current conditions, uniformly distributing the current and preventing excessive current density that could lead to localized overheating, thus significantly improving the device's surge resistance. Furthermore, the high concentration of the second P-type region reduces the resistance within the P-type region, reducing heat generation and improving surge reliability under large surge current conditions. This application also features a full-ohmic P-type region design, meaning that the entire surface of the second P-type region forms an ohmic contact with the metal layer. Compared to the traditional MPS diode structure combining large and small P-type regions, this application's structure is more conducive to current equalization and heat dissipation, resulting in superior surge resistance, while maintaining the same total P-type region area ratio. This application significantly improves the stability and reliability of the device under high surge current while balancing low on-state voltage drop and low reverse leakage current.
[0064] This application also provides a chip, including the Schottky diode device described above.
[0065] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0066] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0067] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.
Claims
1. A Schottky diode device, characterized by, Comprising: an N-type substrate layer; an N-type buffer layer disposed above the N-type substrate layer; a first N-type epitaxial layer disposed above the N-type buffer layer; a first P-type region disposed inside the first N-type epitaxial layer; an upper surface of the first P-type region is flush with an upper surface of the first N-type epitaxial layer; a second N-type epitaxial layer disposed above the first N-type epitaxial layer; an upper surface of the second N-type epitaxial layer comprises a plurality of trenches; a second P-type region disposed inside the second N-type epitaxial layer; an upper surface of the second P-type region is flush with an upper surface of the second N-type epitaxial layer, and a lower surface of the second P-type region is flush with a lower surface of the second N-type epitaxial layer; a center position of the second P-type region is aligned with a center position of the first P-type region, and a size of the second P-type region is less than or equal to a size of the first P-type region; an anode ohmic metal contact layer disposed above the second P-type region; an anode Schottky metal contact layer disposed above the anode ohmic metal contact layer and the second N-type epitaxial layer; an anode metal layer disposed above the anode Schottky metal contact layer; a cathode metal layer disposed below the N-type substrate layer.
2. The Schottky diode device of claim 1, wherein, The number of the first P-type regions is a plurality, and each of the first P-type regions is not in contact with each other.
3. The Schottky diode device of claim 1, wherein, The material of the N-type substrate layer is a 4H-SiC, 6H-SiC or 3C-SiC single crystal substrate.
4. The Schottky diode device of claim 1, wherein, The doping concentration of the second N-type epitaxial layer is higher than the doping concentration of the first N-type epitaxial layer.
5. The Schottky diode device of claim 1, wherein, The doping concentration of the second P-type region is higher than the doping concentration of the first P-type region.
6. A method of fabricating a Schottky diode device, characterized by, A method for manufacturing a Schottky diode device as claimed in any one of claims 1 to 5, the method comprising: forming an N-type substrate layer; forming an N-type buffer layer above the N-type substrate layer; forming a first N-type epitaxial layer above the N-type buffer layer; forming a first P-type region inside the first N-type epitaxial layer; an upper surface of the first P-type region is flush with an upper surface of the first N-type epitaxial layer; forming a second N-type epitaxial layer above the first N-type epitaxial layer; an upper surface of the second N-type epitaxial layer comprises a plurality of trenches; forming a second P-type region inside the second N-type epitaxial layer; an upper surface of the second P-type region is flush with an upper surface of the second N-type epitaxial layer, and a lower surface of the second P-type region is flush with a lower surface of the second N-type epitaxial layer; a center position of the second P-type region is aligned with a center position of the first P-type region, and a size of the second P-type region is less than or equal to a size of the first P-type region; forming an anode ohmic metal contact layer above the second P-type region; forming an anode Schottky metal contact layer above the anode ohmic metal contact layer and the second N-type epitaxial layer; forming an anode metal layer above the anode Schottky metal contact layer; forming a cathode metal layer below the N-type substrate layer.
7. The method of claim 6, wherein the metal layer is formed by a process selected from the group consisting of sputtering, evaporation, and plating. The number of the first P-type regions is a plurality, and each of the first P-type regions is not in contact with each other.
8. The method of claim 6, wherein the metal layer is formed by a process selected from the group consisting of sputtering, evaporation, and plating. The material of the N-type substrate layer is a 4H-SiC, 6H-SiC or 3C-SiC single crystal substrate.
9. The method of claim 6, wherein the metal layer is formed by a process selected from the group consisting of sputtering, evaporation, and plating. The second N-type epitaxial layer has a higher doping concentration than the first N-type epitaxial layer.
10. The method of claim 6, wherein the metal layer is formed by a process selected from the group consisting of sputtering, evaporation, and electroplating. The second P-type region has a higher doping concentration than the first P-type region.
11. A chip, characterized by A Schottky diode device comprising any one of the above claims 1 to 5.