Time synchronization apparatus and communication device

Abstract

The application discloses a time synchronization device and communication equipment, a PTP sending module receives an Ethernet frame to output a first sending data packet start identification signal and a first sending signal; a time stamp processing module assigns a first current time stamp to a first sending time latch signal, and assigns the first sending time latch signal to a time stamp t1 register; a processor acquires the time stamp t1 to stamp a synchronization message / follow-up message, a PCS receiving module receives to output a first receiving data packet start identification signal; a PTP receiving module analyzes a delay request message to output the first receiving data packet start identification signal; the time stamp processing module assigns a second current time stamp to a first receiving time latch signal, and assigns the first receiving time latch signal to a time stamp t4 register; the processor acquires the time stamp t4 to stamp a delay response message. The application can realize high-precision time synchronization.

Description

Technical Field

[0001] This application relates to the field of time synchronization technology, and more particularly to a time synchronization device and communication equipment. Background Technology

[0002] With the development of network technology, the requirements for time synchronization accuracy of critical equipment in packet-switched networks or data processing systems are becoming increasingly stringent. Currently, high-precision time synchronization is mainly achieved based on the Precision Time Protocol (PTP) of network measurement and control systems.

[0003] In related technical solutions, time synchronization through software or hardware PTP has the following problems: software solutions are usually affected by operating system scheduling and interrupt delays, resulting in low timestamp accuracy. Hardware solutions (such as dedicated PHY chips) have problems such as poor flexibility and high cost, making it difficult to meet the requirements of microsecond or even nanosecond level synchronization accuracy when the device is in a complex network environment (such as high load, link asymmetry, etc.). Summary of the Invention

[0004] The purpose of this application is to provide a time synchronization device that can achieve high-precision time synchronization.

[0005] In a first aspect, this application provides a time synchronization device applied to a master clock node in a Precision Time Protocol (PTP) domain, wherein the PTP domain further includes slave clock nodes. The device includes a processor and an FPGA, wherein the FPGA includes:

[0006] A time counter used to generate timestamps in real time;

[0007] The PTP transmission module is configured to output a first transmit data packet start identifier (SOP) signal in response to receiving a first Ethernet frame output by the processor, and to output a first transmit signal in response to parsing the synchronization message in the first Ethernet frame.

[0008] The timestamp processing module is used to, in response to the first transmit SOP signal, assign the first current timestamp obtained from the time counter to the first transmit time latch signal, and in response to the first transmit signal, assign the first transmit time latch signal to the timestamp t1 register.

[0009] The processor is configured to read the first transmission time latch signal from the timestamp t1 register as timestamp t1, timestamp t1 on the synchronization message / follower message, and output the first Ethernet frame to the slave clock node through the FPGA;

[0010] The FPGA also includes:

[0011] The PCS receiving module is configured to output a first receive data packet start identifier (SOP) signal in response to receiving the second Ethernet frame output from the clock node;

[0012] The PTP receiving module is used to output a first receiving signal in response to parsing the delay request message in the second Ethernet frame;

[0013] The timestamp processing module is used to, in response to the first receive SOP signal, assign the second current timestamp obtained from the time counter to the first receive time latch signal, and in response to the first receive signal, assign the first receive time latch signal to the timestamp t4 register.

[0014] The processor is configured to read the first receive time latch signal from the timestamp t4 register as timestamp t4, stamp the delayed response message with the timestamp t4, and output the third Ethernet frame carrying the delayed response message to the slave clock node through the FPGA.

[0015] Optionally, the timestamp processing module includes a timestamp t1 pulse register, and the processor is configured to support single-step mode.

[0016] When the PTP transmitting module parses the SOP identifier of the first Ethernet frame, it outputs the first transmit SOP signal.

[0017] The timestamp processing module responds to the rising edge of the first transmit SOP signal by obtaining the first current timestamp from the time counter and assigning the first current timestamp to the first transmit time latch signal.

[0018] The PTP sending module continues to parse the synchronization message in the first Ethernet frame, and outputs the first sending signal in response to the MsgType field value being 0 in the synchronization message.

[0019] The timestamp processing module responds to the rising edge of the first transmission signal by assigning the first transmission time latch signal to the first transmission time marker signal and sending it to the PTP transmission module.

[0020] The PTP sending module uses byte counting to obtain the byte position of the OriginTimestamp field in the synchronization message, adds the timestamp t1 represented by the first transmission time stamp signal to the byte position, and outputs the first Ethernet frame carrying the synchronization message to the slave clock node.

[0021] Optionally, the timestamp processing module includes a timestamp t1 pulse register and a timestamp t1 register, and the processor is configured to support two-step mode.

[0022] When the PTP transmitting module parses the SOP identifier of the first Ethernet frame, it outputs the first transmit SOP signal;

[0023] The timestamp processing module responds to the rising edge of the first transmit SOP signal by obtaining the first current timestamp from the time counter and assigning the first current timestamp to the first transmit time latch signal.

[0024] The PTP sending module continues to parse the synchronization message in the first Ethernet frame. In response to the MsgType field value being 0 in the synchronization message, it outputs a first sending signal and sends the first Ethernet frame to the slave clock node.

[0025] The timestamp processing module responds to the rising edge of the first transmission signal by assigning the first transmission time latch signal to the first transmission time marker signal;

[0026] After the processor sends the synchronization message, it sets the timestamp t1 pulse signal in the timestamp t1 pulse register to 1;

[0027] The timestamp processing module responds to the rising edge of the timestamp t1 pulse signal by triggering the latching of the first transmission time stamp signal into the timestamp t1 register;

[0028] The processor reads the timestamp t1 register, uses the first transmission time stamp signal as timestamp t1, stamps the follow-up message with the timestamp t1, and outputs the fourth Ethernet frame carrying the follow-up message to the slave clock node through the PTP transmission module.

[0029] Optionally, the timestamp processing module includes a timestamp t4 pulse register and a timestamp t4 register.

[0030] When the PCS receiving module parses the SOP identifier in the second Ethernet frame, it outputs the first receive data packet start identifier SOP signal.

[0031] In response to the rising edge of the first receive SOP signal, the timestamp processing module assigns the second current timestamp obtained from the time counter to the first receive time latch signal.

[0032] When the MsgType field value in the delay request message of the second Ethernet frame is 0x01, the PTP receiving module outputs a first receiving signal and sends the delay request message to the processor.

[0033] The timestamp processing module responds to the rising edge of the first received signal by assigning the first received time latch signal to the first received time marker signal.

[0034] After receiving the delay request message, the processor sets the timestamp t4 pulse signal in the timestamp t4 pulse register to 1;

[0035] The timestamp processing module responds to the rising edge of the timestamp t4 pulse signal by triggering the latching of the first received time stamp signal into the timestamp t4 register;

[0036] The processor reads the timestamp t4 register, uses the read first received time stamp signal as timestamp t4, stamps the delayed response message with the timestamp t4, and outputs the delayed response message to the slave clock node through the PTP sending module via a third Ethernet frame.

[0037] Secondly, this application provides a time synchronization device applied to a slave clock node in a Precision Time Protocol (PTP) domain. The PTP domain also includes a master clock node. The device comprises a processor and an FPGA. The FPGA includes a time counter, a PCS receiving module, a PTP receiving module, a PTP transmitting module, and a timestamp processing module.

[0038] A time counter used to generate timestamps in real time;

[0039] The PCS receiving module is used to output a second receive data packet start identifier (SOP) signal in response to receiving the fifth Ethernet frame sent by the master clock node.

[0040] The PTP receiving module is used to output a second receiving signal when it parses out the synchronization message with time stamp t1 carried in the fifth Ethernet frame.

[0041] The timestamp processing module is used to, in response to the second receive SOP signal, assign the third current timestamp obtained from the time counter to the second receive time latch signal, and in response to the second receive signal, assign the second receive time latch signal to the second receive time marker signal, and assign the second receive time marker signal as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 register, wherein the timestamp t1 is obtained based on the synchronization message or the received follow message;

[0042] The processor is used to generate the sixth Ethernet frame carrying a delay request message;

[0043] The PTP transmission module is used to output a second transmit data packet start identifier (SOP) signal in response to the sixth Ethernet frame, and to output a second transmit signal when the delay request message is parsed, and to output the sixth Ethernet frame to the master clock node;

[0044] The timestamp processing module is used to assign the fourth current timestamp obtained from the time counter to the second transmission time latch signal in response to the second transmission SOP signal, and to assign the second transmission time latch signal to the second transmission time mark signal in response to the second transmission signal.

[0045] The PTP receiving module is used to parse out the timestamp t4 carried in the delayed response message in the seventh Ethernet frame sent by the master clock node;

[0046] The timestamp processing module is used to assign the second transmission time stamp signal as the timestamp t3 of this round, and the timestamp t4 of this round together to the timestamp t34 register;

[0047] The processor is configured to read timestamps t1, t2, t3, and t4 from the timestamp t12 register and the timestamp t34 register, and calculate the time offset;

[0048] A time counter performs time synchronization based on the time offset.

[0049] Optionally, the timestamp processing module includes a timestamp t12 latch register and a timestamp t12 register, and the processor is configured to support single-step mode.

[0050] When the PCS receiving module parses the SOP identifier in the fifth Ethernet frame, it outputs a second receive data packet start identifier SOP signal.

[0051] In response to the rising edge of the second receive SOP signal, the timestamp processing module assigns the third current timestamp obtained from the time counter to the second receive time latch signal.

[0052] The PTP receiving module continues to parse the synchronization message in the fifth Ethernet frame, and outputs a second receiving signal in response to the MsgType field value being 0 in the synchronization message.

[0053] The timestamp processing module responds to the rising edge of the second received signal by assigning the second received time latch signal to the second received time marker signal;

[0054] The PTP receiving module continues to parse the synchronization message, obtain the timestamp t1 in the synchronization message, and output the receive data packet end identifier EOP signal when it parses the data packet end identifier EOP;

[0055] In response to the timestamp t12 latch enable signal being 1, the MsgType field value being 0, and the received EOP signal being 1, the timestamp processing module assigns the second received time stamp signal as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 latch register, and sets the timestamp t12 latch enable signal to zero. The timestamp t12 latch enable signal is used to indicate the latch enable of the timestamp t12 latch register.

[0056] After receiving the synchronization message, the processor sets the timestamp t12 latch enable signal to 1, and refreshes the timestamps t1 and t2 in the timestamp t12 latch register to the timestamp t12 register.

[0057] Optionally, the timestamp processing module includes a timestamp t12 latch register and a timestamp t12 register, and the processor is configured to support two-step mode.

[0058] When the PCS receiving module parses the SOP identifier in the fifth Ethernet frame, it outputs a second receive data packet start identifier SOP signal.

[0059] In response to the rising edge of the second receive SOP signal, the timestamp processing module assigns the third current timestamp obtained from the time counter to the second receive time latch signal.

[0060] The PTP receiving module continues to parse the synchronization message in the fifth Ethernet frame, and outputs a second receiving signal in response to the MsgType field value being 0 in the synchronization message.

[0061] The timestamp processing module responds to the rising edge of the second received signal by assigning the second received time latch signal to the second received time marker signal;

[0062] The PTP receiving module parses the MsgType field value of the follow-up message in the eighth Ethernet frame sent by the master clock node as 8, obtains the timestamp t1 in the follow-up message, and outputs the receive data packet end identifier EOP signal when it parses the data packet end identifier EOP.

[0063] In response to the timestamp t12 latch enable signal being 1, the MsgType field value being 8, and the received EOP signal being 1, the timestamp processing module assigns the second received time stamp signal as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 latch register, and sets the timestamp t12 latch enable signal to zero. The timestamp t12 latch enable signal is used to indicate the latch enable of the timestamp t12 latch register.

[0064] After receiving the synchronization message, the processor sets the timestamp t12 latch enable signal to 1, and refreshes the timestamps t1 and t2 in the timestamp t12 latch register to the timestamp t12 register.

[0065] Optionally, the timestamp processing module includes a timestamp t34 latch register and a timestamp t34 register.

[0066] The PTP transmitting module is used to output a second data packet start identifier SOP signal when it parses the SOP identifier in the sixth Ethernet frame.

[0067] The timestamp processing module is used to assign the fourth current timestamp obtained from the time counter to the second transmission time latch signal in response to the rising edge of the second transmission SOP signal.

[0068] The PTP sending module continues to parse the delay request message in the sixth Ethernet frame, and in response to the MsgType field value of 0x01 in the synchronization message, outputs a second sending signal and outputs the sixth Ethernet frame to the master clock node;

[0069] The timestamp processing module responds to the rising edge of the second transmission signal by assigning the second transmission time latch signal to the second transmission time marker signal;

[0070] The PTP receiving module parses the MsgType field value of the delayed response message in the seventh Ethernet frame sent by the master clock node as 9, obtains the timestamp t4 in the follow message, and outputs the receive data packet end identifier EOP signal when it parses the data packet end identifier EOP.

[0071] In response to the timestamp t34 latch enable signal being 1, the MsgType field value being 9, and the receive EOP signal being 1, the timestamp processing module assigns the second transmit time stamp signal as the timestamp t3 of the current round, together with the timestamp t4 of the current round, to the timestamp t34 latch register, and sets the timestamp t34 latch enable signal to zero. The timestamp t34 latch enable signal is used to indicate the latch enable of the timestamp t34 latch register.

[0072] After receiving the delayed response message, the processor sets the timestamp t34 latch enable signal to 1, and refreshes the timestamps t3 and t4 in the timestamp t34 latch register to the timestamp t34 register.

[0073] Optionally, the time counter includes a second counter, a nanosecond counter, a second offset register, and a nanosecond offset register, wherein,

[0074] The nanosecond counter outputs the current nanosecond value;

[0075] The second counter outputs the current second value;

[0076] The processor writes the second offset value in the time offset into the second offset register, and writes the nanosecond offset value in the time offset into the nanosecond offset register, wherein the highest bit of the nanosecond offset register is the sign bit;

[0077] If the sign bit indicates a positive offset, calculate the temporary nanosecond adjustment value, where the temporary nanosecond adjustment value = current nanosecond value + nanosecond offset value + 8, and...

[0078] If the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value = temporary nanosecond adjustment value - 1, and the adjusted second value = current second value + second offset value + 1;

[0079] If the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value = the current second value + the second offset value;

[0080] If the sign bit indicates a negative offset, calculate the temporary nanosecond adjustment value, where the temporary nanosecond adjustment value = current nanosecond value + (1 - nanosecond offset value) + 8, where...

[0081] If the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value = temporary nanosecond adjustment value - 1, and the adjusted second value = current second value - second offset value;

[0082] If the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value = current second value - second offset value - 1;

[0083] The nanosecond counter performs nanosecond synchronization based on the adjusted nanosecond value, and the second counter performs second synchronization based on the adjusted second value.

[0084] Thirdly, this application provides a communication device, including the time synchronization device as described above and the time synchronization device as described above.

[0085] This application uses multi-level locking based on the timestamp of PTP messages to extract and send high-precision timestamps. It utilizes a high-speed clock and register chain to achieve fixed-point capture of hardware timestamps, avoiding uncertainties across clock domains and ensuring the stability and accuracy of time. It dynamically adjusts the time deviation of the local clock, enabling the local clock to gradually converge and synchronize with the time of the master clock node, achieving high-precision time synchronization with an accuracy of up to 4ns. Attached Figure Description

[0086] Figure 1 A first system block diagram of a time synchronization device provided in an embodiment of this application;

[0087] Figure 2 A second system block diagram of the time synchronization device provided in the embodiments of this application;

[0088] Figure 3 A third system block diagram of a time synchronization device provided in an embodiment of this application. Detailed Implementation

[0089] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0090] First, some terms used in the embodiments of this application will be explained to facilitate understanding by those skilled in the art.

[0091] The 1588 protocol, defined by the Institute of Electrical and Electronics Engineers (IEEE), can be abbreviated as the Precision Time Protocol (PTP). It should be noted that the 1588 protocol / standards involved in this application may include, but are not limited to, IEEE 1588-2008 (1588v2 standard), IEEE 1588-2019 (1588v2.1 standard), or other future evolutions of the 1588 standard.

[0092] A network that uses the PTP protocol is called a PTP domain. A PTP domain has one and only one clock source, and all devices within the domain are synchronized with this clock. Nodes in a PTP domain are called clock nodes, and the interfaces on these clock nodes that run the PTP protocol are called PTP interfaces.

[0093] In a time synchronization path, clocks can be divided into master clocks and slave clocks based on their communication relationship. The master clock provides the source time for the next-level slave clocks to synchronize. The slave clocks correct their local time by exchanging message information with the master clock, based on the message timestamp information provided by the master clock. The core idea of ​​IEEE 1588v2 time synchronization is to use a master-slave clock approach, leveraging network symmetry and delay measurement technology to achieve master-slave time synchronization through bidirectional message exchange.

[0094] The lower 4 bits of the first byte of a PTP message defined in IEEE 1588v2 represent the message type value. IEEE 1588v2 message types are divided into two types: event messages and general messages. Message type values ​​of 0x00~0x03 represent event messages, and values ​​of 0x08~0x0D represent general messages. Specifically: 0x00 represents a synchronization message, 0x01 represents a delay request message, 0x03 represents a peer-to-peer delayed response message, 0x08 represents a follow message, and 0x09 represents a delayed response message. Event messages are time-sensitive messages and require a precise timestamp, while general messages are not time-sensitive messages and do not generate timestamps. Bytes 35-44 of the PTP message contain the timestamp field.

[0095] The time synchronization process is as follows: The master clock node sends a synchronization message to the slave clock node. In one-step mode, the synchronization message contains the timestamp t1 of the sending time. In two-step mode, the master clock node sends a synchronization message and a follow-up message to the slave clock node. The follow-up message contains the sending time t1. The slave clock node records the timestamp t2 of the received synchronization message and obtains the timestamp t1 from the synchronization / follow-up message. After receiving the synchronization message, the slave clock node sends a delay request message (Delay_req) to the master clock node and records the sending time t3 of the delay request message. After receiving the delay request message, the master clock node records the receiving time t4 of the delay request message and sends a delay response message (Delay_Resp) carrying time t4 to the slave clock node. The slave clock node obtains the time t4 from the delay response message. The slave clock node calculates the time offset between the master clock node and the slave clock node based on t1, t2, t3, and t4: Offse = [(t2-t1)+(t3-t4)] / 2. The slave clock node then uses the time offset to achieve time synchronization between the master clock node and the slave clock node.

[0096] Please refer to Figure 1 This application provides a time synchronization device applied to a master clock node in a Precision Time Protocol (PTP) domain. The PTP domain also includes slave clock nodes. The device includes an FPGA (Field Programmable Gate Array) 11 and a processor 12. The FPGA 11 includes a time counter 111, a PTP transmission module 112, a timestamp processing module 113, a PCS (Physical Coding Sublayer) receiving module 114, and a PTP receiving module 115.

[0097] Time counter 111 generates a timestamp in real time to output the local time. The time counter includes a second counter and a nanosecond counter. For example, time counter 111 uses a 250MHz reference clock to generate a local timestamp conforming to the IEEE 1588 protocol format. The timestamp is 80 bits, with the high 48 bits representing the second count value cnt1588_s and the low 32 bits representing the nanosecond count value cnt1588_ns. The timestamp generation process is as follows: Upon system reset, the second counter and nanosecond counter are cleared to zero. The nanosecond count value cnt1588_ns is incremented by 4 in each clock cycle. When cnt1588_ns is greater than or equal to 1 second, the second count value cnt1588_s is incremented by 1, and the nanosecond count value cnt1588_ns is reset to 4, thus generating the timestamp.

[0098] In response to receiving the first Ethernet frame output by the processor 12, the PTP transmission module 112 outputs a first transmit data packet start identifier (SOP) signal sop_tx and sends it to the timestamp processing module 113. In response to parsing the synchronization message from the first Ethernet frame, it outputs a first transmit signal event_tx and sends it to the timestamp processing module 113. In response to the first transmit SOP signal sop_tx, the timestamp processing module 113 assigns the first current timestamp obtained from the time counter 111 to the first transmit time latch signal tx_time_latch, and in response to the first transmit signal, assigns the first transmit time latch signal to the timestamp t1 register. The timestamp processing module 113 includes a timestamp t1 register and a timestamp t4 register. The processor 12 reads the first transmit time latch signal from the timestamp t1 register as timestamp t1, timestamps the synchronization message / follower message with timestamp t1, and outputs the first Ethernet frame to the slave clock node via the FPGA 11, realizing the transmission of timestamp t1 between the master clock node and the slave clock node.

[0099] PCS receiving module 114, in response to receiving the second Ethernet frame output from the clock node, outputs a first received data packet start identifier (SOP) signal sop_rx and sends it to timestamp processing module 113. PTP receiving module 115, in response to parsing the delay request message in the second Ethernet frame, outputs a first received signal event_rx. Timestamp processing module 11, in response to the first received SOP signal sop_rx, assigns the second current timestamp obtained from time counter 111 to the first received time latch signal rx_time_latch, and in response to the first received signal event_rx, assigns the first received time latch signal to the timestamp t4 register. The processor reads the first received time latch signal from the timestamp t4 register as timestamp t4, timestamps the delay response message with timestamp t4, and outputs the third Ethernet frame carrying the delay response message to the slave clock node through FPGA 11, realizing the transmission of timestamp t4 between the master clock node and the slave clock node.

[0100] In this embodiment, the timestamp of the PTP message is locked at multiple levels by FPGA11, high-precision timestamp is extracted and sent, and fixed-point capture of hardware timestamp is achieved by using high-speed clock and register chain, avoiding uncertainty across clock domains and ensuring the stability and accuracy of time.

[0101] The following describes the data interaction between the master clock node and the slave clock node. For example... Figure 2As shown in one embodiment of this application, FPGA 11 includes an RGMII receiving and processing module 116, a MAC (Media Access Control) transmitting module 117, a PCS transmitting module 118, and a serial transmitting module 119. The processor 12 and FPGA 11 communicate via an RGMII interface. The processor 12 outputs data txd[3:0] to the RGMII receiving and processing module 116, which uses a 125MHz clock. The RGMII receiving and processing module 116 converts the received data and clock, unifies the data and clock, and outputs 8-bit wide data data[7:0] and a 156MHz system clock signal sysclk to the MAC transmitting module 117. The MAC transmitting module 117 is mainly responsible for data packet management and addressing, ensuring that data is correctly packaged, addressed, and undergoes preliminary error checking. It encapsulates the data data[7:0] into a first Ethernet frame, adding a frame header (source MAC address, destination MAC address, type, etc.) and a frame trailer (CRC checksum). The MAC sending module 117 uses asynchronous RAM. The MAC sending module 117 outputs data[7:0] to the PTP sending module 112, using a clock of 125MHz. The PTP sending module 112 parses the PTP message of the received first Ethernet frame, extracts the synchronization message, outputs the first transmit SOP signal sop_tx and the first transmit signal event_tx to the timestamp processing module 113, and obtains the first current timestamp tx_time_sample from the timestamp processing module 113 to timestamp t1 on the synchronization message, and sends the first Ethernet frame to the PCS sending module 118, using a clock of 125MHz. The PCS sending module 118 performs encoding processing on the first Ethernet frame, using a clock of 125MHz, and converts the parallel data data[19:0] into a high-speed serial bit stream through the serial-to-parallel conversion module 119, and outputs it to an external port (such as an optical port) for further transmission to the slave clock node.

[0102] like Figure 3As shown in one embodiment of this application, FPGA 11 includes a serial receiving module 11A, a MAC receiving module 11B, and an RGMII transmitting processing module 11C. The master clock node receives the second Ethernet frame sent from the clock node through an external port (such as an optical port), and the serial receiving module 11A converts the serial data into parallel data data[19:0], which uses a 125MHz clock. The PCS receiving module 114 performs data encoding / decoding and rate matching functions, outputs 8-bit wide data data[7:0] and a 156MHz system clock signal sysclk to the MAC receiving module 11B, and outputs a first receive SOP signal sop_rx to the timestamp processing module 113. The MAC receiving module 11B performs parsing of the second Ethernet frame, parses out the payload data, and outputs 8-bit wide data data[7:0] and a 156MHz system clock signal sysclk to the PTP receiving module 115. The PTP receiving module 115 parses the PTP (Delay Request) message of the second Ethernet frame and outputs 8-bit wide data data[7:0] and a 156MHz system clock signal sysclk to the RGMII transmitting processing module 11C. During the parsing of the delay request message, the first received signal event_rx, the first received timestamp signal rx_time_sample, the MsgType field value msgtype_rx, the timestamp field ptp_timestamp_rx, and the received data packet end identifier EOP signal eop_rx are output to the timestamp processing module 113. The RGMII transmitting processing module 11C performs interface conversion, etc., and outputs 8-bit wide data data[7:0] and a 125MHz system clock signal sysclk to the processor 12 so that the processor 12 can process the delay request message.

[0103] Processor 12 acquires timestamp t4, adds timestamp t4 to the delayed response message, and outputs the third Ethernet frame carrying the delayed response message to the slave clock node via the FPGA. This implementation is similar to the above embodiment and will not be described again here.

[0104] The entire parsing process of the PTP message described above only used two 156MHz system clock cycles, thus achieving extremely low latency in message processing and timestamp processing.

[0105] Processor 12 can be configured via registers of FPGA 11 to support single-step and double-step modes of PTP. Timestamp processing module 113 includes a timestamp t1 pulse register and a timestamp t1 register.

[0106] In one embodiment of this application, when the processor 12 is configured to support single-step mode, the timestamp processing module 113 uses a 250MHz clock for signal processing. The time counter 111 uses a 250MHz reference clock to generate a real-time changing timestamp. The PTP sending module 112 receives the first Ethernet frame sent by the MAC sending module 117, parses it, and extracts the synchronization message. When the SOP identifier of the data packet in the first Ethernet frame is parsed, the first transmit SOP signal sop_tx is output and set to high. In response to the rising edge of the first transmit SOP signal, the timestamp processing module 113 obtains the first current timestamp ts_1588_time from the time counter 11 and assigns the first current timestamp ts_1588_time to the first transmit time latch signal tx_time_latch to pre-lock the first current timestamp at that clock cycle. PTP sending module 112 continues to parse the synchronization message. Responding to the MsgType field value being 0 in the synchronization message, it outputs the first sending signal event_tx and sets event_tx high. Timestamp processing module 113, responding to the rising edge of the first sending signal event_tx, assigns the first sending time latch signal tx_time_latch to the first sending time stamp signal tx_time_sample1 and sends tx_time_sample1 to PTP sending module 112. In single-step mode, the master clock node needs to carry t1 in the sent synchronization message. If processor 12 sends the synchronization message to FPGA 11 for timestamp processing, then reads the FPGA 11's registers to obtain the timestamp t1, and finally adds the timestamp t1 to the synchronization message, this process increases the line delay time. Therefore, in this embodiment, the FPGA 11 directly timestamps the synchronization message. The PTP transmission module 112 uses byte counting to obtain the byte position of the OriginTimestamp field (timestamp field) in the synchronization message, adds the timestamp t1 represented by the first transmitted timestamp signal tx_time_sample to this byte position, and gradually replaces the timestamp t1 (i.e., the first current timestamp) from high to low bits by clocking, so that the synchronization message carries the timestamp t1. Through the above data interaction method, the FPGA 11 outputs the first Ethernet frame carrying the synchronization message to the slave clock node.

[0107] In one embodiment of this application, when the processor 12 is configured in two-step mode, the timestamp processing module 113 uses a 250MHz clock for signal processing. The time counter 111 uses a 250MHz reference clock to generate real-time changing timestamps. The PTP transmission module 112 receives the first Ethernet frame sent by the MAC transmission module 117, parses it, and extracts the synchronization message. When it parses the start of SOP (Start of Public Operation) identifier of the data packet in the first Ethernet frame, it outputs the first transmit SOP signal sop_tx1 and sets sop_tx1 high. In response to the rising edge of the first transmit SOP signal, the timestamp processing module 113 obtains the first current timestamp ts_1588_time from the time counter 11 and assigns the first current timestamp ts_1588_time to the first transmit time latch signal tx_time_latch to pre-lock the first current timestamp at that clock cycle. PTP sending module 112 continues parsing the synchronization message. Responding to the MsgType field value of 0 in the synchronization message, it outputs the first transmission signal event_tx and sets event_tx high. Timestamp processing module 113, responding to the rising edge of the first transmission signal event_tx, assigns the first transmission time latch signal tx_time_latch to the first transmission time stamp signal tx_time_sample, sends tx_time_sample to PTP sending module 112, and outputs the first Ethernet frame to the slave clock node. After sending the synchronization message, processor 12 performs a read / write operation to refresh the timestamp t1 pulse register, setting the timestamp t1 pulse signal in the timestamp t1 pulse register to 1. It is set to 1 in the current clock cycle and automatically cleared in the next clock cycle. Timestamp processing module 113, responding to the rising edge of the timestamp t1 pulse signal, triggers the latching and refreshing of the first transmission time stamp signal tx_time_sample to the timestamp t1 register. Processor 12 reads the timestamp t1 register, uses the first transmission timestamp signal (i.e., the first current timestamp ts_1588_time) as timestamp t1, adds timestamp t1 to the generated follow-up message, and outputs the fourth Ethernet frame carrying the follow-up message to the slave clock node through PTP transmission module 112. Since the management interface between FPGA11 and processor 12 uses a 100MHz clock and a 16-bit data width, its processing speed is faster than the external SPI serial interface. The hardware interface between FPGA11 and processor 12 uses the SPI serial interface. Therefore, processor 12 reads the timestamp t1 pulse register first and then the timestamp t1 register, which ensures that the read timestamp t1 is the timestamp after the current round of synchronization message refresh.

[0108] In one embodiment of this application, the timestamp processing module 113 includes a timestamp t4 pulse register and a timestamp t4 register. A delay request message sent by the master clock node is received from the clock node; this delay request message is encapsulated in a second Ethernet frame. When the PCS receiving module 114 parses the SOP identifier in the second Ethernet frame, it outputs a first receive data packet start identifier SOP signal sop_rx and sets sop_rx high. In response to the rising edge of the first receive SOP signal, the timestamp processing module 113 assigns the second current timestamp ts_1588_time obtained from the time counter 11 to the first receive time latch signal rx_time_latch to pre-lock the second current timestamp at that clock cycle. The PTP receiving module 115 parses the delay request message in the second Ethernet frame; in response to the MsgType field value being 0x01 in the delay request message, it outputs a first receive signal event_rx, sets event_rx high, and sends the delay request message to the processor 12. In response to the rising edge of the first received signal event_rx, the timestamp processing module 113 assigns the first received time latch signal rx_time_latch1 to the first received time stamp signal rx_time_sample. After receiving the delay request message, the processor 12 performs a read / write operation to refresh the timestamp t4 pulse register, setting the timestamp t4 pulse signal in the timestamp t4 pulse register to 1. In response to the rising edge of the timestamp t4 pulse signal, the timestamp processing module 113 triggers the latching and refreshing of the first received time stamp signal rx_time_sample to the timestamp t4 register. The processor 12 reads the timestamp t4 register, uses the read first received time stamp signal as the timestamp t4 (i.e., the second current timestamp ts_1588_time2), timestamps the delay response message with timestamp t4, and outputs it to the slave clock node through the PTP transmission module 112 carrying the delay response message in a third Ethernet frame.

[0109] This application also provides a time synchronization device applied to a slave clock node in a Precision Time Protocol (PTP) domain. The PTP domain also includes a master clock node. The device includes an FPGA 11 and a processor 12. The FPGA 11 includes a time counter 111, a PCS receiving module 114, a PTP receiving module 115, a PTP transmitting module 112, and a timestamp processing module 113.

[0110] Time counter 111 generates timestamps in real time. The time counter includes a second counter and a nanosecond counter. For example, time counter 111 uses a 250MHz reference clock to generate a local timestamp t conforming to the IEEE 1588 protocol format. The timestamp is 80 bits, with the high 48 bits representing the second count value cnt1588_s and the low 32 bits representing the nanosecond count value cnt1588_ns. The timestamp generation process is as follows: Upon system reset, the second counter and nanosecond counter are cleared to zero. The nanosecond count value cnt1588_ns is incremented by 4 in each clock cycle. When cnt1588_ns is greater than or equal to 1 second, the second count value cnt1588_s is incremented by 1, and the nanosecond count value cnt1588_ns is reset to 4, thus generating the timestamp.

[0111] The master clock node sends a fifth Ethernet frame to the slave clock node. In response to the fifth Ethernet frame, the PCS receiving module 114 outputs a second receive data packet start identifier (SOP) signal, sop_rx, to the timestamp processing module 113. It also outputs the fifth Ethernet frame to the MAC receiving module 11B for parsing, extracting the PTP packet, and outputting the parsed PTP packet to the PTP receiving module 115. In response to the second receive SOP signal, sop_rx, the timestamp processing module 113 assigns the third current timestamp obtained from the time counter 111 to the second receive time latch signal, rx_time_latch. The PTP receiving module 115 continues parsing the PTP packet. When it extracts a synchronization packet carrying a timestamp t1, it outputs a second receive signal, event_rx, to the timestamp processing module 113. In response to the second received signal event_rx, the timestamp processing module 113 assigns the second received time latch signal rx_time_latch to the second received time stamp signal rx_time_sample, and assigns the second received time stamp signal rx_time_sample as the timestamp t2 of the current round, along with the timestamp t1 of the current round, to the timestamp t12 register, thereby capturing the timestamps t1 and t2 of the current round. The timestamp t1 is obtained based on the synchronization message or the received follow-up message.

[0112] Processor 12 generates a delay request message and, through processing by RGMII receiving module 116 and MAC sending module 11, encapsulates the delay request message in a sixth Ethernet frame and sends it to PTP sending module 112. PTP sending module 112 parses the sixth Ethernet frame and, in response to the sixth Ethernet frame, outputs a second transmit data packet start identifier (SOP) signal, sop_tx, to timestamp processing module 113. In response to the second transmit SOP signal, event_tx, timestamp processing module 113 assigns the fourth current timestamp obtained from time counter 111 to the second transmit time latch signal, tx_time_latch. PTP sending module 112 continues parsing the message; when a delay request message is parsed, it outputs a second transmit signal, event_tx, to timestamp processing module 113. In response to the second transmit signal, event_tx, timestamp processing module 113 assigns the second transmit time latch signal, tx_time_latch, to the second transmit time stamp signal, tx_time_sample. The sixth Ethernet frame is output to the master clock node via PCS transmission module 118 and serial transmission module 119.

[0113] The master clock node sends a seventh Ethernet frame to the slave clock node, which carries a delay response message. The slave clock node receives the seventh Ethernet frame through an optical port. After processing by the conversion receiving module 11A, PCS receiving module 114, and MAC receiving module 11B, the delay response message parsed from the seventh Ethernet frame is output to the PTP receiving module 115. The PTP receiving module 115 parses the timestamp t4 carried in the delay response message. The timestamp processing module 113 assigns the second transmission time stamp signal as the timestamp t3 of this round, along with the timestamp t4 of this round, to the timestamp t34 register, thereby realizing the capture of the timestamps t3 and t4 of this round.

[0114] Processor 12 reads timestamps t1, t2, t3, and t4 from timestamp registers t12 and t34, and calculates the time offset. Time counter 111 performs time synchronization based on the time offset.

[0115] In this embodiment, an internal time feedback loop is constructed based on the PTP message interaction between the slave clock node and the master clock node to extract and send high-precision timestamps, forming a closed-loop feedback control loop. This dynamically adjusts the time deviation of the local clock, enabling the local clock to gradually converge and synchronize with the time of the master clock node, achieving high-precision time synchronization with an accuracy of up to 4ns. The optimized and concise time correction algorithm effectively suppresses the impact of network jitter, maintaining rapid convergence and stable synchronization.

[0116] The data interaction process between the clock node and the master clock node is similar to the above. Figure 2 and Figure 3 The interaction process is similar and will not be described in detail here.

[0117] Processor 12 can be configured via registers of FPGA 11 to support single-step and double-step modes of PTP. Timestamp processing module 113 includes a timestamp t12 latch register, a timestamp t12 register, a timestamp t34 latch register, and a timestamp t34 register. In the initial state, the timestamp t12 latch enable signal t12_latch_en and the timestamp t34 latch enable signal t34_latch_en are set to 1. The timestamp t12 latch enable signal is used to indicate the latch enable of the timestamp t12 latch register, and the timestamp t34 latch enable signal is used to indicate the latch enable of the timestamp t34 latch register. Using the timestamp t12 latch enable signal as the latch switch of the timestamp t12 latch register and the timestamp t34 latch enable signal as the latch switch of the timestamp t34 latch register can ensure that timestamps t1 and t2 are interlocked in pairs and timestamps t3 and t4 are interlocked in pairs during the PTP message exchange between the slave clock node and the master clock node in the same round, so as to avoid timestamp misalignment.

[0118] In one embodiment of this application, when the processor 12 is configured to support single-step mode, the timestamp processing module 113 uses a 250MHz clock for signal processing. The time counter 111 uses a 250MHz reference clock to generate a real-time changing timestamp. The PCS receiving module 114 parses the fifth Ethernet frame. When it parses the SOP identifier in the fifth Ethernet frame, it sets the second receive data packet start identifier SOP signal sop_rx high and outputs it to the timestamp processing module 113. In response to the rising edge of the second receive SOP signal sop_rx, the timestamp processing module 113 assigns the third current timestamp ts_1588_time obtained from the time counter 111 to the second receive time latch signal rx_time_latch. The PTP receiving module 114 continues to parse the synchronization message in the fifth Ethernet frame. In response to the MsgType field value being 0 in the synchronization message, it outputs the second receive signal event_rx to the timestamp processing module 113 and sets event_rx high. In response to the rising edge of the second received signal event_rx, the timestamp processing module 113 assigns the second received time latch signal rx_time_latch to the second received time stamp signal rx_time_sample. The second received time stamp signal is the timestamp t2 of this round. The PTP receiving module 114 continues to parse the synchronization message and obtain the timestamp t1 in the synchronization message. The timestamp t1 is located in bytes 35-44 of the synchronization message (OriginTimestamp field). When the end-of-packet identifier EOP is parsed, the eop signal is the last data of the valid packet data, used to indicate the end of the frame. The received packet end identifier EOP signal eop_rx is set high and output to the timestamp processing module 113. In response to the timestamp t12 latch enable signal being 1, the MsgType field value being 0 (indicating a synchronization message), and the receive EOP signal being 1, the timestamp processing module 113 assigns the second receive time stamp signal rx_time_sample as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 latch register, and sets the timestamp t12 latch enable signal to zero to ensure that the timestamp t12 latch register remains unchanged before the processor 12 reads the timestamp t12 register. After receiving the synchronization message, the processor 12 performs a read / write operation, sets the timestamp t12 latch enable signal t12_latch_en to 1, refreshes the timestamps t1 and t2 in the timestamp t12 latch register to the timestamp t12 register, reads the timestamps t1 and t2 in the timestamp t12 register to obtain the timestamps t1 and t2 of the current round of interaction, and sets the timestamp t12 latch enable signal t12_latch_en to 1 to latch the timestamps t1 and t2 of the next round of interaction.

[0119] In one embodiment of this application, when the processor 12 is configured to support two-step mode, the timestamp processing module 113 uses a 250MHz clock for signal processing. The time counter 111 uses a 250MHz reference clock to generate a real-time changing timestamp. The PCS receiving module 114 parses the fifth Ethernet frame. When it parses the SOP identifier in the fifth Ethernet frame, it sets the second receive data packet start identifier SOP signal sop_rx high and outputs it to the timestamp processing module 113. In response to the rising edge of the second receive SOP signal sop_rx, the timestamp processing module 113 assigns the third current timestamp ts_1588_time obtained from the time counter 111 to the second receive time latch signal rx_time_latch. The PTP receiving module 114 continues to parse the synchronization message in the fifth Ethernet frame. In response to the MsgType field value being 0 in the synchronization message, it outputs the second receive signal event_rx to the timestamp processing module 113 and sets event_rx high. In response to the rising edge of the second received signal event_rx, the timestamp processing module 113 assigns the second received time latch signal rx_time_latch to the second received time stamp signal rx_time_sample, which is the timestamp t2 of this round. The PTP receiving module 114 sends the synchronization message to the processor 12 for processing. The master clock node sends the eighth Ethernet frame to the slave clock node, which carries a follow-up message. The PTP receiving module 114 parses the follow-up message. When the MsgType field value in the message is 8, it indicates that the message is a follow-up message. The timestamp t1 is obtained through the OriginTimestamp field in the message. When the end-of-packet identifier EOP is parsed, the received end-of-packet identifier EOP signal eop_rx is set to 1 and output to the timestamp processing module 113. In response to the timestamp t12 latch enable signal being 1, the MsgType field value being 8, and the received EOP signal being 1, the timestamp processing module 113 assigns the second received time stamp signal rx_time_sample as the timestamp t2 of the current round, along with the timestamp t1 of the current round, to the timestamp t12 latch register, and sets the timestamp t12 latch enable signal to zero. After receiving the synchronization message, the processor 12 performs a register read / write refresh operation, sets the timestamp t12 latch enable signal t12_latch_en to 1, refreshes the timestamps t1 and t2 in the timestamp t12 latch register to the timestamp t12 register, reads the timestamps t1 and t2 in the timestamp t12 register to obtain the timestamps t1 and t2 of the current round of interaction, and sets the timestamp t12 latch enable signal t12_latch_en to 1 to latch the timestamps t1 and t2 of the next round of interaction.

[0120] In one embodiment of this application, the processor 12 generates a delay request message and, through processing by the RGMII receiving processing module 116 and the MAC sending module 11, encapsulates the delay request message in a sixth Ethernet frame and sends it to the PTP sending module 112. The PTP sending module 112 parses the sixth Ethernet frame. When it parses an SOP identifier in the sixth Ethernet frame, it sets the second transmit data packet start identifier SOP signal sop_tx high and outputs it to the timestamp processing module 113. In response to the rising edge of the second transmit SOP signal, the timestamp processing module 113 assigns the fourth current timestamp obtained from the time counter 111 to the second transmit time latch signal tx_time_latch. The PTP sending module 112 continues parsing the delay request message in the sixth Ethernet frame. In response to the MsgType field value being 0x01 in the delay request message, it sets the second transmit signal event_tx high, outputs it to the timestamp processing module 113, and outputs the sixth Ethernet frame to the master clock node. In response to the rising edge of the second transmission signal event_tx, the timestamp processing module 113 assigns the second transmission time latch signal to the second transmission time stamp signal tx_time_sample, which is the timestamp t3 of this round. The PTP receiving module 114 parses the MsgType field value of the delayed response message in the seventh Ethernet frame sent by the master clock node as 9, obtains the timestamp t4 in the follow-up message, and outputs the receive data packet end identifier EOP signal eop_rx when parsing the data packet end identifier EOP, with eop_rx being high. In response to the timestamp t34 latch enable signal being 1, the MsgType field value being 9, and the receive EOP signal being 1, the timestamp processing module 113 assigns the second transmission time stamp signal tx_time_sample as the timestamp t3 of this round, along with the timestamp t4 of this round, to the timestamp t34 latch register, and sets the timestamp t34 latch enable signal to zero. After receiving the delayed response message, the processor 12 sets the timestamp t34 latch enable signal to 1, and refreshes the timestamps t3 and t4 in the timestamp t34 latch register to the timestamp t34 register, that is, obtains the timestamps t3 and t4 of the current round of interaction. At the same time, it sets the timestamp t34_latch_en enable signal to 1 to latch the timestamps t3 and t4 of the next round of interaction.

[0121] In one embodiment of this application, the time counter 111 includes a second counter, a nanosecond counter, a second offset register, and a nanosecond offset register. The nanosecond counter generates the current nanosecond value, and the second counter generates the current current second value. The current nanosecond value and the current current second value constitute the current timestamp. The time offset calculated above includes a second offset value and a nanosecond offset value. The processor 12 writes the second offset value into the second offset register and the nanosecond offset value into the nanosecond offset register. The highest bit of the nanosecond offset register is the sign bit. Both the nanosecond offset value and the nanosecond offset register are 32 bits, with the highest bit being the sign bit, where 0 represents a positive offset and 1 represents a negative offset. The lowest two bits are invalid values. Therefore, the nanosecond offset value is an integer multiple of 4ns, one period of a 250MHz clock, thus achieving a clock synchronization accuracy of 4ns. The temporary nanosecond adjustment value is calculated based on the sign bit of the nanosecond offset register, as follows:

[0122] If the sign bit indicates a positive offset, calculate the temporary nanosecond adjustment value: Temporary nanosecond adjustment value = Current nanosecond value + Nanosecond offset value (right-shifted by 2 bits) + 8. If the sign bit indicates a negative offset, calculate the temporary nanosecond adjustment value: Temporary nanosecond adjustment value = Current nanosecond value + (1 - Nanosecond offset value) + 8. The temporary nanosecond adjustment value needs to be processed by a 2-cycle 3D 250MHz clock before it can be updated to the nanosecond count. Therefore, the above calculation formula needs to be compensated for 2 clock cycles, i.e., 8ns.

[0123] Based on whether the offset is positive or negative, and whether the temporary nanosecond adjustment value exceeds 1 second, a carry or borrow is determined to adjust the second counter. When there is a positive offset, if the temporary nanosecond adjustment value exceeds 1 second, a carry is generated; when there is a negative offset, if the temporary nanosecond adjustment value does not exceed 1 second, a borrow is generated. The adjustment process is as follows:

[0124] When the sign bit indicates a positive offset, if the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value = temporary nanosecond adjustment value - 1, and the adjusted second value = current second value + second offset value + 1; if the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value = current second value + second offset value.

[0125] When the sign bit indicates a negative offset, if the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value = temporary nanosecond adjustment value - 1, and the adjusted second value = current second value - second offset value; if the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value = current second value - second offset value - 1.

[0126] The nanosecond counter performs nanosecond synchronization based on the adjusted nanosecond value, and the second counter performs second synchronization based on the adjusted second value, thereby achieving time synchronization from the clock node.

[0127] In one embodiment of this application, clock frequency synchronization is performed before time synchronization, and this frequency is achieved via synchronous Ethernet. The implementation of the master clock is similar and will not be repeated here, taking the slave clock node as an example. The slave clock node receives multiple synchronous Ethernet packets through a multi-channel optical port. The FPGA 11 performs clock recovery processing on these packets, extracting multiple line recovery clocks (e.g., a 125MHz clock) and dividing them to obtain multiple clock sources at 8kHz. These multiple clock sources, along with the local clock, are input to the clock chip as reference clock sources for processing. The processor 12 selects the clock quality based on the information carried in the synchronous Ethernet packets and configures the priority of the reference clock source for the clock chip via an interface, determining which reference clock source the slave clock node's clock should synchronize to. The clock chip outputs a synchronized 125MHz clock to the FPGA 11. The FPGA 11 uses phase-locked loop (PLL) frequency multiplication to generate a synchronized 250MHz high-frequency clock. The 250MHz high-frequency clock is used as the clock input for the time counter 111, thus ensuring that the speed of the time counter 111 is consistent with the selected clock source, thereby achieving clock frequency synchronization.

[0128] This application provides a communication device including the time synchronization apparatus as described above. The communication device can function as a Boundary Clock (BC) node. For example, the communication device supports multiple optical ports as PTP interfaces, synchronizing time from an upstream clock node through one of the PTP interfaces and distributing time to downstream clock nodes through the remaining PTP interfaces. When a clock node acts as a clock source, it can distribute time to downstream clock nodes through multiple PTP interfaces. In this embodiment, the communication device can be flexibly configured as a master clock, slave clock, boundary clock, and transparent clock, supporting various operating modes.

[0129] Although preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present application as disclosed in the appended claims.

Claims

1. A time synchronization device, characterized in that, A master clock node is used in a Precision Time Protocol (PTP) domain, which also includes slave clock nodes. The device includes a processor and an FPGA, wherein the FPGA includes: A time counter used to generate timestamps in real time; The PTP transmission module is configured to output a first transmit data packet start identifier (SOP) signal in response to receiving a first Ethernet frame output by the processor, and to output a first transmit signal in response to parsing the synchronization message in the first Ethernet frame. The timestamp processing module includes a timestamp t1 pulse register and a timestamp t1 register, which are used to assign a first current timestamp obtained from the time counter to a first transmission time latch signal in response to a first transmission SOP signal, and to assign the first transmission time latch signal to the timestamp t1 register in response to the first transmission signal. The processor is configured to read the first transmission time latch signal from the timestamp t1 register as timestamp t1, timestamp t1 on the synchronization message / follower message, and output the first Ethernet frame to the slave clock node through the FPGA; The FPGA also includes: The PCS receiving module is configured to output a first receive data packet start identifier (SOP) signal in response to receiving the second Ethernet frame output from the clock node; The PTP receiving module is used to output a first receiving signal in response to parsing the delay request message in the second Ethernet frame; The timestamp processing module is used to assign a second current timestamp obtained from the time counter to a first receive time latch signal in response to a first receive SOP signal, and to assign the first receive time latch signal to the timestamp t4 register in response to the first receive signal. The processor is configured to read the first receive time latch signal from the timestamp t4 register as timestamp t4, stamp the delayed response message with the timestamp t4, and output the third Ethernet frame carrying the delayed response message to the slave clock node through the FPGA; The processor configuration supports two-step mode; When the PTP transmitting module parses the SOP identifier of the first Ethernet frame, it outputs the first transmit SOP signal; The timestamp processing module responds to the rising edge of the first transmit SOP signal by obtaining the first current timestamp from the time counter and assigning the first current timestamp to the first transmit time latch signal. The PTP sending module continues to parse the synchronization message in the first Ethernet frame. In response to the MsgType field value being 0 in the synchronization message, it outputs a first sending signal and sends the first Ethernet frame to the slave clock node. The timestamp processing module responds to the rising edge of the first transmission signal by assigning the first transmission time latch signal to the first transmission time marker signal; After the processor sends the synchronization message, it sets the timestamp t1 pulse signal in the timestamp t1 pulse register to 1; The timestamp processing module responds to the rising edge of the timestamp t1 pulse signal by triggering the latching of the first transmission time stamp signal into the timestamp t1 register; The processor reads the timestamp t1 register, uses the first transmission time stamp signal as timestamp t1, stamps the follow-up message with the timestamp t1, and outputs the fourth Ethernet frame carrying the follow-up message to the slave clock node through the PTP transmission module.

2. The time synchronization device according to claim 1, characterized in that, The processor configuration supports single-step mode. When the PTP transmitting module parses the SOP identifier of the first Ethernet frame, it outputs the first transmit SOP signal. The timestamp processing module responds to the rising edge of the first transmit SOP signal by obtaining the first current timestamp from the time counter and assigning the first current timestamp to the first transmit time latch signal. The PTP sending module continues to parse the synchronization message in the first Ethernet frame, and outputs the first sending signal in response to the MsgType field value being 0 in the synchronization message. The timestamp processing module responds to the rising edge of the first transmission signal by assigning the first transmission time latch signal to the first transmission time marker signal and sending it to the PTP transmission module. The PTP sending module uses byte counting to obtain the byte position of the OriginTimestamp field in the synchronization message, adds the timestamp t1 represented by the first transmission time stamp signal to the byte position, and outputs the first Ethernet frame carrying the synchronization message to the slave clock node.

3. The time synchronization device according to claim 1, characterized in that, The timestamp processing module includes a timestamp t4 pulse register and a timestamp t4 register. When the PCS receiving module parses the SOP identifier in the second Ethernet frame, it outputs the first receive data packet start identifier SOP signal. In response to the rising edge of the first receive SOP signal, the timestamp processing module assigns the second current timestamp obtained from the time counter to the first receive time latch signal. When the MsgType field value in the delay request message of the second Ethernet frame is 0x01, the PTP receiving module outputs a first receiving signal and sends the delay request message to the processor. The timestamp processing module responds to the rising edge of the first received signal by assigning the first received time latch signal to the first received time marker signal. After receiving the delay request message, the processor sets the timestamp t4 pulse signal in the timestamp t4 pulse register to 1; The timestamp processing module responds to the rising edge of the timestamp t4 pulse signal by triggering the latching of the first received time stamp signal into the timestamp t4 register; The processor reads the timestamp t4 register, uses the read first received time stamp signal as timestamp t4, stamps the delayed response message with the timestamp t4, and outputs the delayed response message to the slave clock node through the PTP sending module via a third Ethernet frame.

4. A time synchronization device, characterized in that, The device is used as a slave clock node in a Precision Time Protocol (PTP) domain, which also includes a master clock node. The device comprises a processor and an FPGA. The FPGA includes a time counter, a PCS receiving module, a PTP receiving module, a PTP transmitting module, and a timestamp processing module. A time counter used to generate timestamps in real time; The PCS receiving module is used to output a second receive data packet start identifier (SOP) signal in response to receiving the fifth Ethernet frame sent by the master clock node. The PTP receiving module is used to output a second receiving signal when parsing the synchronization message in the fifth Ethernet frame; A timestamp processing module, comprising a timestamp t12 latch register and a timestamp t12 register, is used to, in response to a second receive SOP signal, assign a third current timestamp obtained from the time counter to a second receive time latch signal, and in response to the second receive signal, assign the second receive time latch signal to a second receive time marker signal, and assign the second receive time marker signal as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 register, wherein the timestamp t1 is obtained based on the synchronization message or the received follow message; The processor is used to generate the sixth Ethernet frame carrying a delay request message; The PTP transmission module is used to output a second transmit data packet start identifier (SOP) signal in response to the sixth Ethernet frame, and to output a second transmit signal when the delay request message is parsed, and to output the sixth Ethernet frame to the master clock node; The timestamp processing module is used to assign the fourth current timestamp obtained from the time counter to the second transmission time latch signal in response to the second transmission SOP signal, and to assign the second transmission time latch signal to the second transmission time mark signal in response to the second transmission signal. The PTP receiving module is used to parse out the timestamp t4 carried in the delayed response message in the seventh Ethernet frame sent by the master clock node; The timestamp processing module is used to assign the second transmission time stamp signal as the timestamp t3 of this round, and the timestamp t4 of this round together to the timestamp t34 register; The processor is configured to read timestamps t1, t2, t3, and t4 from the timestamp t12 register and the timestamp t34 register, and calculate the time offset; A time counter performs time synchronization based on the time offset; The processor configuration supports two-step mode. When the PCS receiving module parses the SOP identifier in the fifth Ethernet frame, it outputs a second receive data packet start identifier SOP signal. In response to the rising edge of the second receive SOP signal, the timestamp processing module assigns the third current timestamp obtained from the time counter to the second receive time latch signal. The PTP receiving module continues to parse the synchronization message in the fifth Ethernet frame, and outputs a second receiving signal in response to the MsgType field value being 0 in the synchronization message. The timestamp processing module responds to the rising edge of the second received signal by assigning the second received time latch signal to the second received time marker signal; The PTP receiving module parses the MsgType field value of the follow-up message in the eighth Ethernet frame sent by the master clock node as 8, obtains the timestamp t1 in the follow-up message, and outputs the receive data packet end identifier EOP signal when it parses the data packet end identifier EOP. In response to the timestamp t12 latch enable signal being 1, the MsgType field value being 8, and the received EOP signal being 1, the timestamp processing module assigns the second received time stamp signal as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 latch register, and sets the timestamp t12 latch enable signal to zero. The timestamp t12 latch enable signal is used to indicate the latch enable of the timestamp t12 latch register. After receiving the synchronization message, the processor sets the timestamp t12 latch enable signal to 1, and refreshes the timestamps t1 and t2 in the timestamp t12 latch register to the timestamp t12 register.

5. The time synchronization device according to claim 4, characterized in that, The processor configuration supports single-step mode. When the PCS receiving module parses the SOP identifier in the fifth Ethernet frame, it outputs a second receive data packet start identifier SOP signal. In response to the rising edge of the second receive SOP signal, the timestamp processing module assigns the third current timestamp obtained from the time counter to the second receive time latch signal. The PTP receiving module continues to parse the synchronization message in the fifth Ethernet frame, and outputs a second receiving signal in response to the MsgType field value being 0 in the synchronization message. The timestamp processing module responds to the rising edge of the second received signal by assigning the second received time latch signal to the second received time marker signal; The PTP receiving module continues to parse the synchronization message, obtain the timestamp t1 in the synchronization message, and output the receive data packet end identifier EOP signal when it parses the data packet end identifier EOP; In response to the timestamp t12 latch enable signal being 1, the MsgType field value being 0, and the received EOP signal being 1, the timestamp processing module assigns the second received time stamp signal as the timestamp t2 of the current round, together with the timestamp t1 of the current round, to the timestamp t12 latch register, and sets the timestamp t12 latch enable signal to zero. The timestamp t12 latch enable signal is used to indicate the latch enable of the timestamp t12 latch register. After receiving the synchronization message, the processor sets the timestamp t12 latch enable signal to 1, and refreshes the timestamps t1 and t2 in the timestamp t12 latch register to the timestamp t12 register.

6. The time synchronization device according to claim 5, characterized in that, The timestamp processing module includes a timestamp t34 latch register and a timestamp t34 register. The PTP transmitting module is used to output a second data packet start identifier SOP signal when it parses the SOP identifier in the sixth Ethernet frame. The timestamp processing module is used to assign the fourth current timestamp obtained from the time counter to the second transmission time latch signal in response to the rising edge of the second transmission SOP signal. The PTP sending module continues to parse the delay request message in the sixth Ethernet frame, and in response to the MsgType field value of 0x01 in the synchronization message, outputs a second sending signal and outputs the sixth Ethernet frame to the master clock node; The timestamp processing module responds to the rising edge of the second transmission signal by assigning the second transmission time latch signal to the second transmission time marker signal; The PTP receiving module parses the MsgType field value of the delayed response message in the seventh Ethernet frame sent by the master clock node as 9, obtains the timestamp t4 in the follow message, and outputs the receive data packet end identifier EOP signal when it parses the data packet end identifier EOP. In response to the timestamp t34 latch enable signal being 1, the MsgType field value being 9, and the receive EOP signal being 1, the timestamp processing module assigns the second transmit time stamp signal as the timestamp t3 of the current round, together with the timestamp t4 of the current round, to the timestamp t34 latch register, and sets the timestamp t34 latch enable signal to zero. The timestamp t34 latch enable signal is used to indicate the latch enable of the timestamp t34 latch register. After receiving the delayed response message, the processor sets the timestamp t34 latch enable signal to 1, and refreshes the timestamps t3 and t4 in the timestamp t34 latch register to the timestamp t34 register.

7. The time synchronization device according to claim 6, characterized in that, The time counter includes a second counter, a nanosecond counter, a second offset register, and a nanosecond offset register, wherein, The nanosecond counter outputs the current nanosecond value; The second counter outputs the current second value; The processor writes the second offset value in the time offset into the second offset register, and writes the nanosecond offset value in the time offset into the nanosecond offset register, wherein the highest bit of the nanosecond offset register is the sign bit; If the sign bit indicates a positive offset, calculate the temporary nanosecond adjustment value, where the temporary nanosecond adjustment value = current nanosecond value + nanosecond offset value + 8, and... If the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value = temporary nanosecond adjustment value - 1, and the adjusted second value = current second value + second offset value + 1; If the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value = the current second value + the second offset value; If the sign bit indicates a negative offset, calculate the temporary nanosecond adjustment value, where the temporary nanosecond adjustment value = current nanosecond value + (1 - nanosecond offset value) + 8, where... If the temporary nanosecond adjustment value exceeds 1 second, the adjusted nanosecond value = temporary nanosecond adjustment value - 1, and the adjusted second value = current second value - second offset value; If the temporary nanosecond adjustment value does not exceed 1 second, the adjusted nanosecond value is the temporary nanosecond adjustment value, and the adjusted second value = current second value - second offset value - 1; The nanosecond counter performs nanosecond synchronization based on the adjusted nanosecond value, and the second counter performs second synchronization based on the adjusted second value.

8. A communication device, characterized in that, It includes the time synchronization device as described in claims 1-3 and the time synchronization device as described in claims 4-7.

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