A method and apparatus for calibrating UART baud rate

Abstract

This invention provides a method and apparatus for calibrating the UART baud rate, belonging to the field of communication technology. The receiver chip uses a counter to count the system clock during the start bit data and check data periods, and determines whether the received check data is a preset value. If so, a rounding algorithm is used to calculate the frequency division value based on the preset data bit width and the stored count value, and this value is updated in the baud rate register. The calibration completion flag is set to valid, and the enable signal is set to invalid. Otherwise, calibration fails, the calibration error flag and calibration completion flag are set to valid, and the enable signal is set to invalid. Subsequently, the receiver communicates with the transmitter using the baud rate calculated based on the frequency division value. This solution enables more accurate calibration even when the chip has a low-precision built-in OSC, meeting both the UART's clock accuracy requirements and the need for low chip cost, and is easy to use.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and apparatus for calibrating UART baud rate. Background Technology

[0002] With the rapid development of IoT (Internet of Things) technology, it is playing an increasingly important role in various fields such as smart homes, intelligent transportation, and industrial automation.

[0003] UART (Universal Asynchronous Receiver / Transmitter) is widely used in IoT chips due to its low power consumption, high stability, and lack of strict clock synchronization. However, as an asynchronous interface, UART has high requirements for clock accuracy, and even small clock deviations can affect data communication.

[0004] The OSC (oscillator) is the "heart" of a chip, providing a stable clock signal for all modules within the chip. Existing chips are divided into built-in OSC chips and external OSC chips. Built-in OSC chips integrate the oscillator inside the chip, reducing the use of external components and lowering material and assembly costs. However, built-in OSC chips have relatively lower clock accuracy, and the clock signal they generate may have some fluctuations and deviations.

[0005] To reduce costs, electronic device manufacturers typically use built-in OSC chips. However, when UART is used with a built-in OSC chip, sampling errors and communication failures are prone to occur during data transmission and reception due to the internal OSC clock accuracy issues. Therefore, baud rate calibration is necessary. Traditional baud rate calibration schemes use 1-bit data sampling and integer division for calibration. This method is not accurate enough when sampling clocks are limited, resulting in significant calculation errors. In practical applications, this inaccurate calibration may cause data errors during UART communication, affecting the normal operation of the device. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and apparatus for calibrating UART baud rate.

[0007] In a first aspect, embodiments of the present invention provide a method for calibrating the UART baud rate, comprising:

[0008] Step 101: When the device in the receiver chip detects that the enable signal is valid, it starts to detect the falling edge of the start bit on the signal line. When the falling edge of the start bit is detected, the device starts to receive the start bit data sent by the sender and controls the counter to start counting.

[0009] Step 102: When the device detects the rising edge of the start bit, the start bit data reception is completed and the device starts receiving the verification data sent by the sender, and controls the counter to continue counting;

[0010] Step 103: When the device detects a falling edge of a data bit, it controls the counter to continue counting;

[0011] Step 104: When the device detects the rising edge of the data bit, the verification data reception is complete, the counter is controlled to stop counting, and the count value is saved;

[0012] Step 105: The device determines whether the received verification data is a preset value. If yes, it executes step 106; otherwise, the calibration fails, the calibration error flag and calibration completion flag are set to valid, and the enable signal is set to invalid.

[0013] Step 106: The device uses a rounding algorithm to calculate the frequency division value based on the preset data bit width and the stored count value, updates the baud rate register, sets the calibration completion flag to valid, and sets the enable signal to invalid.

[0014] The device employs a rounding algorithm to calculate the frequency division value based on a preset data bit width and a stored count value. The calculation includes: the device uses a divider to calculate 0.5 times the preset data bit width to obtain a first intermediate value; uses an adder to calculate the first intermediate value and the count value to obtain a second intermediate value; uses a divider to calculate the second intermediate value as the dividend and the preset data bit width as the divisor; and outputs the calculated quotient as the frequency division value.

[0015] Secondly, embodiments of the present invention provide an apparatus for calibrating the UART baud rate, comprising: a counter, a detection control module, a first judgment module, a first setting module, a calculation update module, a second setting module, and a baud rate register;

[0016] The detection and control module is used to detect the falling edge of the start bit on the signal line when the enable signal is valid, and to start receiving the start bit data sent by the sender and control the counter to start when the falling edge of the start bit is detected. The counter starts counting the system clock.

[0017] The detection and control module is also used to control the counter to continue counting when the rising edge of the start bit is detected, after the start bit data reception is completed and the verification data sent by the sender is started.

[0018] The detection control module is also used to control the counter to continue counting when a falling edge of a data bit is detected;

[0019] The detection control module is also used to control the counter to stop counting and save the count value when the rising edge of the data bit is detected, after the verification data reception is completed.

[0020] The first judgment module is used to determine whether the verification data received by the detection control module is a preset value. If it is, the calculation update module is triggered; otherwise, the calibration fails and the first setting module is triggered.

[0021] The first setting module is used to set the calibration error flag and calibration completion flag to be valid, and to set the enable signal to be invalid;

[0022] The calculation and update module is used to calculate the frequency division value based on the preset data bit width and the count value stored by the detection and control module using a rounding algorithm, and update it to the baud rate register, thereby triggering the second setting module;

[0023] The second setting module is used to set the calibration completion flag to valid and the enable signal to invalid.

[0024] The calculation and update module includes: a first divider, an adder, and a second divider.

[0025] The first divider is used to calculate 0.5 times the preset data bit width to obtain a first intermediate value and output it to the adder;

[0026] The adder is used to calculate a second intermediate value from the first intermediate value and the count value and output the result to the second divider;

[0027] The second divider is used to calculate the second intermediate value as the dividend and the preset data bit width as the divisor, output the calculated quotient and update the baud rate register as the frequency division value, thereby triggering the second setting module.

[0028] Thirdly, embodiments of the present invention provide a chip that includes the aforementioned device, oscillator, and CPU. The oscillator provides a system clock, and the CPU is equipped with a driver program. The device and the CPU work together to implement the aforementioned method.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] The baud rate calibration scheme provided in this application embodiment can achieve more accurate calibration even when the chip has a built-in OSC with low precision, meeting the UART's clock accuracy requirements. It solves the problem that UART cannot communicate normally when it is applied to a built-in OSC chip due to the poor clock accuracy of the internal OSC, improves the usability of the built-in OSC chip, and helps electronic device manufacturers control costs. Attached Figure Description

[0031] Figure 1 A flowchart illustrating a method for calibrating the UART baud rate according to Embodiment 1 of the present invention;

[0032] Figure 2 A timing diagram of the receiver receiving start bit data and check data provided in Embodiment 1 of the present invention;

[0033] Figure 3 The circuit diagram for calculating the frequency division value provided in Embodiment 1 of the present invention;

[0034] Figure 4 This is a block diagram of an apparatus for calibrating UART baud rate according to Embodiment 2 of the present invention;

[0035] Figure 5 This is a schematic diagram of a chip containing a device for calibrating the UART baud rate, provided in Embodiment 2 of the present invention.

[0036] Figure 6 This is a schematic diagram illustrating a usage scenario of a chip that includes a device for calibrating the UART baud rate, as provided in Embodiment 2 of the present invention. Detailed Implementation

[0037] This application proposes a method and apparatus for calibrating UART baud rate. The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. Examples of the embodiments are shown in the drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0038] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0039] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Example 1

[0040] Embodiment 1 of the present invention provides a method for calibrating the UART baud rate, implemented through hardware circuitry (i.e., a device) arranged in a chip. This method is performed before the receiving chip receives communication data. Figure 1 As shown, the method in this embodiment includes:

[0041] Step 101: When the device in the receiver chip detects that the enable signal is valid, it starts to detect the falling edge of the start bit on the signal line. When the falling edge of the start bit is detected, the device starts to receive the start bit data sent by the sender and controls the counter to start counting.

[0042] In this embodiment, the data transmission signal line is high level by default; the device controls the counter to start, specifically: the device outputs a first control signal to the counter, and the counter starts after receiving the first control signal; preferably, the first control signal is a high level signal;

[0043] Before step 101, the following steps are also included: the receiver driver sets the enable signal to be valid, specifically: the receiver driver sets the enable signal bit in the UART control register to 1;

[0044] In this embodiment, the device in the receiver chip detects that the enable signal bit in the UART control register is 1, thus indicating that the enable signal is valid.

[0045] Step 102: When the device detects the rising edge of the start bit, the start bit data reception is complete and the device begins to receive the verification data sent by the sender, and controls the counter to continue counting;

[0046] Specifically, in this embodiment, the start bit data is 0;

[0047] In this embodiment, controlling the counter to continue counting specifically involves the device continuously outputting a first control signal to the counter;

[0048] Step 103: When the device detects a falling edge of a data bit, it controls the counter to continue counting;

[0049] Step 104: When the device detects the rising edge of the data bit, the verification data reception is completed, the control counter stops counting, and the count value is saved;

[0050] In this embodiment, the device receives the check data sent by the sender sequentially from the least significant bit to the most significant bit, and uses the start bit data and check data to calibrate the baud rate. The reception timing diagram is shown below. Figure 2 As shown;

[0051] To stop the counter from counting, the device outputs a second control signal to the counter, and the counter stops counting upon receiving the second control signal; preferably, the second control signal is a low-level signal.

[0052] Step 105: The device determines whether the received verification data is a preset value. If yes, proceed to step 106; otherwise, the calibration fails. Set the calibration error flag and calibration completion flag to valid and the enable signal to invalid.

[0053] Specifically, the preset value in this embodiment is 7F;

[0054] Optionally, the calibration error flag and calibration completion flag can be enabled by setting both the calibration error flag and calibration completion flag bits in the status register to 1; the enable signal can be disabled by setting the enable signal bit in the UART control register to 0.

[0055] Step 106: The device uses a rounding algorithm to calculate the frequency division value based on the preset data bit width and the saved count value, updates it to the baud rate register, sets the calibration completion flag to valid, and sets the enable signal to invalid.

[0056] Specifically, the preset data bit width in this embodiment is 9;

[0057] The process of calculating the frequency division value in step 106 uses a rounding algorithm (that is, adding 0.5 times the dividend to the divisor before performing the division operation), which can further reduce the error rate. The specific implementation circuit is as follows: Figure 3 As shown, the implementation process includes: using a divider to calculate 0.5 times the preset data bit width to obtain a first intermediate value; using an adder to calculate the first intermediate value and the count value to obtain a second intermediate value; using a divider to calculate the second intermediate value as the dividend and the preset data bit width as the divisor; outputting the calculated quotient and using it as the frequency division value.

[0058] The method in this embodiment also includes: the receiver's driver monitors the calibration completion flag in real time, and when the calibration completion flag is detected to be valid, it determines whether the calibration is successful. If it is, it returns a calibration success response to the sender. The receiver calculates the baud rate according to the value in the baud rate register and uses the baud rate to start data communication with the sender. Otherwise, the calibration fails and ends.

[0059] Specifically, determining whether the calibration was successful involves checking if the calibration error flag in the status register is 1. If it is, the calibration failed; otherwise, the calibration was successful.

[0060] Optionally, in this embodiment, after determining that the calibration has failed, the method further includes: updating the calibration failure count, determining whether the current calibration failure count has reached a preset number, and if so, ending the process; otherwise, setting the calibration completion flag and error flag to invalid, setting the enable signal to valid, and returning to step 101.

[0061] In step 101, the calibration operation is restarted. If the sender does not receive a calibration success response from the receiver, the start bit and verification data are sent again to restart the calibration operation. Preferably, if the sender does not receive a calibration success response from the receiver within a preset time, the start bit and verification data are sent again.

[0062] In this embodiment, after the frequency division value in the baud rate register is updated, the baud rate calculated based on the frequency division value also changes accordingly. The baud rate is calculated based on the value in the baud rate register by dividing the system clock frequency by the value in the baud rate register (i.e., the frequency division value) to obtain the baud rate.

[0063] The baud rate calibration scheme provided in this embodiment can achieve more accurate calibration even when the chip has a built-in OSC with low precision. It not only meets the clock accuracy requirements of UART, but also solves the problem that UART cannot communicate normally due to the poor clock accuracy of the internal OSC when it is used in a chip with a built-in OSC. This improves the usability of the built-in OSC chip and helps electronic device manufacturers control costs.

[0064] The following example illustrates this, taking a theoretical system clock of 20MHz at the receiver and a UART communication baud rate of 4MHz. It assumes the OSC clock accuracy is poor, with a preset range of 5%, and considers the impact of cross-clock domains:

[0065] In existing technology, calibration is performed using a 1-bit start bit. Integer division is used, and the counter only records the system clock integer. Communication is based on the count value, which may be 4 or 5 times the actual start bit, which may be 4.8, 5.1, or 5.8 system clock cycles. Assuming the start bit is 4.8 clock cycles and the counter only records 4 clock cycles, the error is (4.8-4) / 4 = 20%. If the error exceeds 5%, a communication error will occur. Assuming the start bit is 5.1 clock cycles and the counter records 5 clock cycles, the error is (5.1-5) / 5 = 2%, and normal communication is possible. Assuming the start bit is 5.8 clock cycles and the counter records 5 clock cycles, the error is (5.8-5) / 5 = 16%, and if the error exceeds 5%, a communication error will occur.

[0066] The technical solution of this application adopts a 9-bit calibration scheme (i.e., the preset data bit width is 9). Assuming 1 bit is 4.8 clock cycles, the counter records 43 system clock cycles (4.8 * 9 rounded down). The frequency division value is calculated to be 5 using a rounding algorithm (i.e., ...). Figure 3 The circuit calculation (43+9 / 2) / 9 results in 5), so the error is (5-4.8) / 5=4%. The error does not exceed 5%, and the sender and receiver can communicate normally. Assuming 1 bit is 5.1 clock cycles, the counter records 45 system clock cycles (5.1*9 rounded down). Using the rounding algorithm, the frequency division value is calculated to be 5 (i.e., Figure 3 The circuit calculation (45+9 / 2) / 9 results in 5), so the error is (5.1-5) / 5=2%. The error does not exceed 5%, and the sender and receiver can communicate normally. Assuming 1 bit is 5.8 clock cycles, the counter records 52 system clock cycles (5.8*9 rounded down). Using rounding, the frequency division value is calculated to be 5 (i.e., Figure 3 The circuit calculation (52+9 / 2) / 9 results in 6), so the error is (6-5.8) / 6=3%. The error does not exceed 5%, and the sender and receiver can communicate normally.

[0067] As can be seen from the above specific examples, the method of this embodiment is more accurate in calibration and more convenient to use. Example 2

[0068] Embodiment 2 of the present invention provides a device for calibrating the UART baud rate. This device is disposed in the chip of the receiver and operates before the receiver receives communication data, such as... Figure 4 As shown, it includes a counter, a detection control module, a first judgment module, a first setting module, a calculation and update module, a second setting module, and a baud rate register;

[0069] The detection and control module is used to detect the falling edge of the start bit on the signal line when the enable signal is valid. When the falling edge of the start bit is detected, it starts to receive the start bit data sent by the sender and controls the counter to start. The counter starts counting against the system clock.

[0070] In this embodiment, the data transmission signal line is high level by default; the detection control module is specifically used to detect the falling edge of the start bit on the signal line when the enable signal is valid, and to start receiving the start bit data sent by the sender when the falling edge of the start bit is detected, and output the first control signal to the counter. After receiving the first control signal, the counter starts and starts counting the system clock; preferably, the first control signal is a high level signal.

[0071] In this embodiment, the system clock is provided by the OSC;

[0072] The detection and control module is also used to control the counter to continue counting when the rising edge of the start bit is detected, indicating that the start bit data reception is complete and the sender begins to receive the verification data sent by the sender.

[0073] For example, in this embodiment, the start bit data is 0;

[0074] In this embodiment, the detection control module is further configured to detect that the start bit data reception is complete when the rising edge of the start bit is detected, and to start receiving the verification data sent by the sender, and to continuously output the first control signal to the counter.

[0075] The detection control module is also used to control the counter to continue counting when a falling edge of a data bit is detected;

[0076] In this embodiment, the detection control module is further configured to continuously output a first control signal to the counter when a falling edge of a data bit is detected;

[0077] The detection and control module is also used to verify that data reception is complete when a rising edge of a data bit is detected, control the counter to stop counting, and save the count value.

[0078] In this embodiment, the detection control module receives the verification data sent by the sender sequentially from the least significant bit to the most significant bit. The verification data and the start bit data are used to calibrate the baud rate.

[0079] Specifically, the detection control module is also used to verify that the data reception is complete when the rising edge of the data bit is detected, and output a second control signal to the counter. After receiving the second control signal, the counter stops counting and saves the counter's count value; preferably, the second control signal is a low-level signal.

[0080] The first judgment module is used to determine whether the received verification data is a preset value. If it is, the calculation and update module is triggered; otherwise, the calibration fails and the first setting module is triggered.

[0081] Specifically, the preset value in this embodiment is 7F;

[0082] The first setting module is used to enable the calibration error flag and the calibration completion flag, and disable the enable signal;

[0083] The calculation and update module is used to calculate the frequency division value based on the preset data bit width and the saved count value using a rounding algorithm and update it to the baud rate register, triggering the second setting module;

[0084] Specifically, the preset data bit width in this embodiment is 9;

[0085] In this embodiment, the calculation update module includes a first divider, an adder, and a second divider. The first divider is used to calculate 0.5 times the preset data bit width to obtain a first intermediate value and output it to the adder. The adder is used to calculate the first intermediate value and the count value to obtain a second intermediate value and output it to the second divider. The second divider is used to calculate the second intermediate value as the dividend and the preset data bit width as the divisor, output the calculated quotient, and update the baud rate register as the frequency division value, triggering the second setting module.

[0086] The second setting module is used to set the calibration completion flag to valid and the enable signal to invalid.

[0087] Optionally, the device may also include a UART control register and a status register;

[0088] The enable signal is valid when the value of the enable signal bit in the UART control register is set to 1 by the receiver's driver.

[0089] The first setting module is specifically used to set both the calibration error flag and calibration completion flag in the status register to 1, and to modify the value of the enable signal bit in the UART control register to 0;

[0090] The second setting module is specifically used to set the calibration completion flag in the status register to 1 and modify the value of the enable signal bit in the UART control register to 0.

[0091] The implementation device of this embodiment can be arranged in a chip, such as Figure 5 As shown, the chip includes the device, OSC and CPU of this embodiment. The OSC provides a system clock for the counter and a register module including a UART control register, a status register and a baud rate register. The detection control module controls the counter to count the system clock provided by the OSC during the period of start bit data and check data.

[0092] The CPU has a driver program that monitors the calibration completion flag in real time. When the calibration completion flag is detected to be valid, it determines whether the calibration is successful. If so, it returns a calibration success response to the sender. The baud rate is calculated based on the value in the baud rate register, and the receiver uses this baud rate to start data communication with the sender.

[0093] Specifically, the driver on the CPU is used to monitor the calibration completion flag in the status register in real time. If the value of the calibration completion flag is 1, it checks whether the value of the calibration error flag in the status register is 1. If it is, the calibration fails; otherwise, it returns a calibration success response to the sender. The baud rate is calculated based on the value in the baud rate register, and the sender uses this baud rate to start data communication with the receiver.

[0094] In this embodiment, the driver on the CPU is also used to enable the enable signal, specifically by setting the value of the enable signal bit in the UART control register to 1.

[0095] Optionally, the driver on the CPU is also used to update the number of calibration failures when a calibration failure is detected, and to determine whether the current number of calibration failures has reached the preset number. If so, the process ends; otherwise, the calibration completion flag and error flag are set to invalid, the enable signal is set to valid, and the calibration device is triggered to re-perform the calibration operation.

[0096] If the sender does not receive a calibration success response from the receiver, it will resend the start bit and verification data, and the calibration device will restart the calibration operation. Preferably, if the sender does not receive a calibration success response from the receiver within a preset time, it will resend the start bit and verification data.

[0097] For example, in this embodiment, the implementation device is arranged in a serial port WIFI chip. The serial port WIFI chip is suitable for IoT applications requiring serial port transparent transmission, such as smart power strips, smart lighting control, industrial wireless control, smart buildings, sensor networks, home automation, smart factories, etc., providing data transmission and intelligent control applications for IoT, smart lighting, smart factories, smart healthcare, and other fields. Figure 6 As shown, the main controller (MCU) inside the sweeping robot communicates with the serial WIFI chip via UART. Before communication, the MCU sends start bit data 0 and check data 7F to the serial WIFI chip. The implementation device in the serial WIFI chip calibrates the communication baud rate by receiving start bit 0 and check data 7F. After successful calibration, the serial WIFI chip communicates with the MCU using the baud rate calculated by the driver module on the CPU.

[0098] This invention provides a solution for calibrating the UART baud rate using a built-in OSC chip. It employs a more precise and effective calibration process, which can improve the stability and reliability of UART communication, meet the communication needs of IoT devices in complex scenarios, and is very convenient to use.

[0099] Optionally, embodiments of this application also provide an electronic device, which includes at least one processor, a memory, and instructions stored in the memory and executable by the at least one processor. The at least one processor executes the instructions to implement the method for calibrating the UART baud rate in the above embodiments. When the electronic device is a chip system, it can be composed of chips or may include chips and other discrete devices; embodiments of this application do not specifically limit this. The chip is coupled to the memory and is used to execute the computer program stored in the memory to perform the method for calibrating the UART baud rate disclosed in the above embodiments.

[0100] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be entirely or partially in the form of a computer program product. This computer program product includes one or more computer programs. When the computer program is loaded and executed on an electronic device, all or part of the processes or functions described in the embodiments of this application are generated. The computer program can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one base station, electronic device, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to the electronic device or a data storage device including one or more servers, data centers, etc., that can be integrated using media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)). In the embodiments of this application, the electronic device may include the aforementioned apparatus.

[0101] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other module can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0102] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A method for calibrating UART baud rate, characterized in that, The method includes: Step 101: When the device in the receiver chip detects that the enable signal is valid, it starts to detect the falling edge of the start bit on the signal line. When the falling edge of the start bit is detected, the device starts to receive the start bit data sent by the sender and controls the counter to start counting. Step 102: When the device detects the rising edge of the start bit, the start bit data reception is completed and the device starts receiving the verification data sent by the sender, and controls the counter to continue counting; Step 103: When the device detects a falling edge of a data bit, it controls the counter to continue counting; Step 104: When the device detects the rising edge of the data bit, the verification data reception is complete, the counter is controlled to stop counting, and the count value is saved; Step 105: The device determines whether the received verification data is a preset value. If yes, it executes step 106; otherwise, the calibration fails, the calibration error flag and calibration completion flag are set to valid, and the enable signal is set to invalid. Step 106: The device uses a rounding algorithm to calculate the frequency division value based on the preset data bit width and the stored count value, updates the baud rate register, sets the calibration completion flag to valid, and sets the enable signal to invalid. The device employs a rounding algorithm to calculate the frequency division value based on a preset data bit width and a stored count value. The calculation includes: the device uses a divider to calculate 0.5 times the preset data bit width to obtain a first intermediate value; uses an adder to calculate the first intermediate value and the count value to obtain a second intermediate value; uses a divider to calculate the second intermediate value as the dividend and the preset data bit width as the divisor; and outputs the calculated quotient as the frequency division value.

2. The method as described in claim 1, characterized in that, The device controls the counter to start, specifically by: the device outputting a first control signal to the counter, and the counter starting after receiving the first control signal; Specifically, controlling the counter to continue counting involves the device continuously outputting the first control signal to the counter. The control of the counter to stop counting specifically involves the device outputting a second control signal to the counter, and the counter stopping counting upon receiving the second control signal.

3. The method as described in claim 1, characterized in that, Before step 101, the method further includes: the receiver's driver setting the enable signal to be valid.

4. The method as described in claim 1, characterized in that, The device in the receiver chip detects that the enable signal is valid, specifically: the device in the receiver chip detects that the value of the enable signal bit in the UART control register is 1; The step of setting the calibration error flag and calibration completion flag to be valid specifically involves setting both the calibration error flag bit and the calibration completion flag bit in the status register to 1. Setting the enable signal to invalid specifically involves modifying the value of the enable signal bit in the UART control register to 0.

5. The method as described in claim 1, characterized in that, The method further includes: the receiver's driver monitors the calibration completion flag in real time; when the calibration completion flag is detected to be valid, it determines whether the calibration is successful; if so, it returns a calibration success response to the sender; the receiver calculates the baud rate based on the value in the baud rate register and uses the baud rate to start data communication with the sender; otherwise, the calibration fails and ends.

6. The method as described in claim 5, characterized in that, The determination of whether the calibration is successful is specifically as follows: determine whether the value of the calibration error flag bit in the status register is 1. If it is, the calibration fails; otherwise, the calibration is successful.

7. The method as described in claim 5, characterized in that, After determining that the calibration has failed, the process further includes: updating the calibration failure count, determining whether the current calibration failure count has reached the preset number, and if so, ending the process; otherwise, setting the calibration completion flag and the error flag to invalid, setting the enable signal to valid, and returning to step 101.

8. A device for calibrating UART baud rate, characterized in that, include: The system includes a counter, a detection and control module, a first judgment module, a first setting module, a calculation and update module, a second setting module, and a baud rate register. The detection and control module is used to detect the falling edge of the start bit on the signal line when the enable signal is valid, and to start receiving the start bit data sent by the sender and control the counter to start when the falling edge of the start bit is detected. The counter starts counting the system clock. The detection and control module is also used to control the counter to continue counting when the rising edge of the start bit is detected, after the start bit data reception is completed and the verification data sent by the sender is started. The detection control module is also used to control the counter to continue counting when a falling edge of a data bit is detected; The detection control module is also used to control the counter to stop counting and save the count value when the rising edge of the data bit is detected, after the verification data reception is completed. The first judgment module is used to determine whether the verification data received by the detection control module is a preset value. If it is, the calculation update module is triggered; otherwise, the calibration fails and the first setting module is triggered. The first setting module is used to set the calibration error flag and calibration completion flag to be valid, and to set the enable signal to be invalid; The calculation and update module is used to calculate the frequency division value based on the preset data bit width and the count value stored by the detection and control module using a rounding algorithm, and update it to the baud rate register, thereby triggering the second setting module; The second setting module is used to set the calibration completion flag to valid and the enable signal to invalid. The calculation and update module includes: a first divider, an adder, and a second divider. The first divider is used to calculate 0.5 times the preset data bit width to obtain a first intermediate value and output it to the adder; The adder is used to calculate a second intermediate value from the first intermediate value and the count value and output the result to the second divider; The second divider is used to calculate the second intermediate value as the dividend and the preset data bit width as the divisor, output the calculated quotient and update the baud rate register as the frequency division value, thereby triggering the second setting module.

9. The apparatus as claimed in claim 8, characterized in that, The detection and control module is specifically used to detect the falling edge of the start bit on the signal line when the enable signal is valid, and to start receiving the start bit data sent by the sender when the falling edge of the start bit is detected, and to output a first control signal to the counter. The counter starts after receiving the first control signal and starts counting the system clock. The detection and control module is further configured to start receiving the verification data sent by the sender when the rising edge of the start bit is detected, and to continuously output the first control signal to the counter. The detection and control module is further configured to continuously output a first control signal to the counter when a falling edge of a data bit is detected; The detection control module is further configured to complete the reception of the verification data when the rising edge of the data bit is detected, output a second control signal to the counter, and stop counting after receiving the second control signal and save the counter's count value.

10. The apparatus as claimed in claim 8, characterized in that, The device also includes a UART control register and a status register; The enable signal is valid when the value of the enable signal bit in the UART control register is set to 1 by the receiver's driver. The first setting module is specifically used to set both the calibration error flag and the calibration completion flag in the status register to 1, and to modify the value of the enable signal bit in the UART control register to 0; The second setting module is specifically used to set the calibration completion flag bit in the status register to 1 and modify the value of the enable signal bit in the UART control register to 0.

11. A chip, characterized in that, The device includes the apparatus, oscillator, and CPU as described in any one of claims 8-10, wherein the oscillator provides a system clock, a counter in the device counts the system clock, and a driver is provided on the CPU, and the device and the CPU work together.

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