A High-Precision Time-Frequency Synchronization Optimization Method for Distributed Wireless Network Communication

Abstract

This invention belongs to the field of wireless ad hoc network communication technology, specifically relating to a high-precision time-frequency synchronization optimization method for distributed wireless network communication. The specific process is as follows: Counter setting: A time-stamp correction counter is set in each node of the distributed system of the wireless network, and the hardware timestamp counter is periodically adjusted according to the frequency error estimate; Coarse synchronization: Time synchronization is performed N times according to the PTP time synchronization algorithm; Fine synchronization: Starting from the (N+1)th synchronization, each m synchronizations are recorded as a cycle; when the synchronization of this cycle is completed, m sets of time synchronization errors and time synchronization intervals are obtained. Kalman filtering is applied to these m time synchronization errors, and the filtered time synchronization error value of the mth time is used to adjust the hardware timestamp counter.

Description

Technical Field

[0001] This invention belongs to the field of wireless ad hoc network communication technology, specifically relating to a high-precision time-frequency synchronization optimization method for distributed wireless network communication. Background Technology

[0002] With the rapid development of wireless communication technology, distributed systems based on wireless networking have been widely used in military communications, wireless sensor networks, vehicle-to-everything (V2X) networks, industrial IoT, and 5G / 6G distributed base stations. Wireless networking, through self-organization and multi-hop forwarding mechanisms between nodes, can form flexible communication networks without relying on fixed infrastructure, offering advantages such as rapid deployment, wide coverage, and strong robustness. However, these networks often consist of a large number of nodes, which need to maintain strict time-frequency consistency to achieve functions such as collaborative communication, joint signal processing, and distributed measurement and control. Therefore, high-precision time and frequency synchronization is fundamental to the stable operation of wireless networking communication systems.

[0003] Traditional network time synchronization methods, such as NTP (Network Time Protocol), can only achieve millisecond-level synchronization accuracy, which cannot meet the needs of high-precision distributed systems. While satellite-based time synchronization methods like GPS / BeiDou offer higher accuracy, they are difficult to apply stably in indoor or complex electromagnetic environments, and are limited by equipment cost and interference resistance. Against this backdrop, the IEEE 1588 Precision Time Protocol (PTP) was proposed and widely adopted. PTP achieves sub-microsecond or even nanosecond-level clock synchronization in Ethernet environments through timestamp exchange and delay measurement.

[0004] The traditional Precision Time Protocol (PTP) was first applied in wired Ethernet environments, relying on the periodic exchange of messages and recording timestamps between master and slave nodes to estimate link delay and clock skew, thereby achieving nanosecond-level time synchronization. However, PTP faces many challenges when directly applied in wireless networking: First, wireless channels suffer from multipath propagation, fading, and random access mechanisms, resulting in significant link delay jitter and asymmetric uplink and downlink delays, violating PTP's fundamental assumption of symmetrical delay. Second, distributed wireless nodes are typically equipped with only low-cost crystal oscillators, leading to significant clock drift and making it more difficult to maintain high-precision synchronization over long periods. Furthermore, limited wireless network bandwidth and node energy make it difficult to support high-frequency message exchange, thus affecting synchronization accuracy and efficiency. To address these challenges, recent research has proposed a series of adaptive improvement methods, including implementing hardware timestamps at the physical or MAC layer to reduce delay uncertainty, introducing channel delay estimation and compensation mechanisms, combining digital phase-locked loops (DPLLs) and voltage-controlled crystal oscillators (VCXOs) for frequency synchronization, and employing boundary clocks, transparent clocks, or regression correction algorithms to suppress error accumulation in multi-hop networking scenarios. Currently, in scenarios such as 5G / 6G distributed base stations, wireless sensor networks, vehicle-to-everything (V2X) and industrial IoT, PTP, combined with methods such as Synchronous Ethernet (SyncE), satellite timing, and Reference Broadcast Synchronization (RBS), has gradually formed a high-precision time-frequency synchronization solution for wireless networking communication, providing fundamental support for the stable operation and high-performance collaboration of large-scale wireless networks.

[0005] PTP time-frequency synchronization principle:

[0006] Precision Time Protocol (PTP) is a high-precision network time synchronization protocol based on Ethernet. This protocol features low cost, high synchronization accuracy, and low resource consumption, and is widely researched and applied in the field of distributed data acquisition. The PTP protocol works by exchanging message data and recording timestamps between master and slave nodes. The slave node obtains four timestamps (t1, t2, t3, and t4) to calculate the average delay of the master-slave link and the clock deviation between the master and slave nodes. A synchronization algorithm then completes the time synchronization between the slave and master nodes.

[0007] The master and slave nodes employ a transmit-receive-based bidirectional synchronization model for time synchronization error measurement. Node A is the time synchronization reference node, and node B is the node to be synchronized. The transmit-receive-based bidirectional synchronization model is as follows: Figure 1 As shown.

[0008] During the i-th time synchronization, reference node A sends a synchronization message to node B at time T1(i). Node B receives the synchronization message at time T2(i) and sends a reply message to reference node A at time T3(i). Subsequently, reference node A receives the message at time T4(i). After processing, the time synchronization error value between the two parties is obtained. Reference node A sends a message to notify node B to correct the time, thus completing one time synchronization process. The relationship between T1(i), T2(i), T3(i), and T4(i) during the i-th time synchronization process can be obtained from the model as follows:

[0009]

[0010] Where, α i Let T1(i) be the difference between the clock frequency of node B and the clock frequency of the reference node A, and let ΔT1(i) and ΔT3(i) be the differences between T1(i) and T3(i) from the last time synchronization adjustment, respectively.

[0011] When the clock frequencies of node B and reference node A are equal, it can be simplified to:

[0012]

[0013] Without considering the relative motion between nodes, the time synchronization error between nodes can be calculated as follows:

[0014]

[0015] The transmission delay between nodes can be calculated along with the time synchronization error:

[0016]

[0017] Based on the above principle, it is possible to measure time error, thereby compensating for the time error of the hardware timestamp counter and achieving time synchronization.

[0018] Clock frequency refers to a series of reference pulse signals generated by a local crystal oscillator on a hardware platform for synchronizing the operation of components in digital circuits. Nominal frequency is the target frequency specified during the design of a device or system; it is the "nominal value" marked by the manufacturer at the time of shipment. It represents the frequency that the clock source should theoretically output, but due to factors such as manufacturing process, temperature, power supply, and circuit noise, the actual frequency may deviate to some extent.

[0019] If the clock frequencies of two nodes are the same, they can remain synchronized after one time synchronization. However, in reality, the clock frequencies between nodes will always differ, and the clock frequency will not be stable at a fixed value. This will cause time errors in the counter due to clock frequency errors even after time synchronization. Ignoring the influence of factors such as motion, this time error can be considered to be caused by the accumulation of clock frequency errors. Therefore, the clock frequency error can be calculated based on the interval between two time synchronizations and the next time error measurement value, and thus frequency synchronization can be achieved.

[0020] like Figure 2 As shown, similar to equation (2), the relationship between T1, T2, T3, and T4 in the bidirectional synchronization model with clock frequency offset can be listed:

[0021]

[0022] Where α is the error coefficient between the clocks of node B and the reference node A, and t d The difference between the physical clocks T2 and T3 can be obtained by measurement. d delay is the path delay between the two nodes, and offset is the clock offset between the nodes.

[0023] The clock offset and path delay can be calculated using equation (5):

[0024]

[0025] After completing one time synchronization, under the premise of path symmetry, the synchronization error generated by the next time synchronization mainly comes from the deviation of clock frequencies between nodes. According to equation (6), the error caused by clock frequency can be obtained as follows:

[0026]

[0027] The clock frequency deviation between the two nodes can be roughly calculated using equation (8):

[0028]

[0029] After obtaining the clock frequency deviation, frequency synchronization can be achieved by using a phase-locked loop (PLL) to generate and lock a fixed-frequency disciplined clock that matches the reference frequency.

[0030] IV. Disadvantages of the prior art and the technical problem to be solved by the present invention

[0031] The above method can achieve a rough time-frequency synchronization, but in actual engineering implementation, the accuracy of time-frequency synchronization is related to factors such as acquisition accuracy, transmission delay, clock frequency and relative movement of nodes.

[0032] In the time synchronization process described above, there is often an error between the timestamp of signal acquisition and the actual arrival time of the signal. This error is due to the time error caused by the acquisition precision. The magnitude of this error is related to the sampling rate of the receiver, the number of bits for signal quantization, and the timestamp precision, plus the resolution of the timestamp itself. That is, the timestamps involved in the time error calculation themselves contain time errors. Part of the calculated time synchronization error is caused by the error generated by the acquisition precision. Directly using this time error to compensate for the timestamp counter often results in over-correction or under-correction.

[0033] The aforementioned synchronization algorithm cannot directly modify the clock frequency using the calculated clock frequency error. It requires adding a digital phase-locked loop or software adjustment. For large-scale embedded projects, frequently changing the hardware platform's clock frequency carries significant risks, potentially causing timing errors and affecting program operation. Therefore, some complex embedded projects are not suitable for achieving frequency synchronization by directly changing the clock frequency.

[0034] In practical engineering, in addition to the frequency deviation between the actual center frequency generated by the node clock and the nominal frequency, the node clock also experiences frequency drift during operation. Furthermore, communication interference and errors may occur during communication. The frequency deviation calculated solely based on the time deviation generated between two time synchronization intervals is prone to significant errors, leading to over-correction or under-correction.

[0035] Furthermore, as time-frequency synchronization progresses, the clock frequency synchronization accuracy will tend to a certain value and cannot be further improved. This is because after the clock frequency is synchronized to a certain accuracy range, the clock frequency error is small and cannot accumulate a significant time synchronization error, thus making it impossible to obtain a more accurate estimate. Summary of the Invention

[0036] In view of this, the present invention proposes a high-precision time-frequency synchronization optimization method for distributed wireless network communication, which achieves high-precision time-frequency synchronization without relying on digital phase-locked loops to change the clock frequency.

[0037] The technical solution for implementing the present invention is as follows:

[0038] A high-precision time-frequency synchronization optimization method for distributed wireless network communication, the specific process of which is as follows:

[0039] Counter settings: Set a time-scale correction counter in each node of the wireless network distributed system;

[0040] Coarse synchronization: Perform time synchronization N times according to the PTP time synchronization algorithm;

[0041] Fine synchronization: Starting from the (N+1)th synchronization, let every m synchronizations be denoted as one cycle;

[0042] First cycle: The hardware timestamp counter is periodically adjusted using the period value of the time stamp correction counter calculated by coarse synchronization; the time synchronization error is calculated and timestamp counter error compensation is performed after each time synchronization; after the time synchronization of this cycle is completed, Kalman filtering is performed on m groups of time synchronization errors, and least squares estimation fitting is performed using the filtered time synchronization error and the time interval between each two adjacent time synchronizations; the period value of the time stamp correction counter is calculated based on the fitted clock frequency error.

[0043] The second cycle begins: the timestamp counter is periodically adjusted using the period value of the time stamp correction counter calculated in the previous cycle; the time synchronization error is calculated after each time synchronization, and Kalman filtering is performed on the time synchronization error in combination with the data from the previous cycle. The filtered time error value is then used to compensate the hardware timestamp counter; after the time synchronization of this cycle is completed, Kalman filtering is performed on m groups of time synchronization errors, and least squares estimation fitting is performed using the filtered time synchronization error and the time interval between each two adjacent time synchronizations. The period value of the time stamp correction counter is then calculated based on the fitted clock frequency error.

[0044] Optionally, the present invention sets two standard deviation thresholds for clock frequency errors: α1*f and α2*f; where α1 and α2 are threshold coefficients, and f is the nominal frequency of the slave node;

[0045] If the standard deviation of the clock frequency error obtained M times consecutively is lower than the threshold value α1*f, the time synchronization interval is increased and the fine synchronization process continues; if the standard deviation of the clock frequency error obtained M times consecutively exceeds α2*f, the time synchronization interval is decreased and the time-frequency synchronization process continues.

[0046] Optionally, the period value of the time-scale correction counter is calculated based on the fitted clock frequency error as described in this invention by converting the estimated clock frequency error Δf and the nominal frequency f into the period value T of the time-scale correction counter using the following formula;

[0047]

[0048] Optionally, during coarse synchronization, the present invention performs single clock frequency error estimation fitting during the 2nd to Nth time synchronizations, and uses the fitted clock frequency error to calculate the period value of the timestamp correction counter, which is used to adjust the period value of the timestamp counter.

[0049] Optionally, the specific process of clock frequency error fitting described in this invention is as follows:

[0050] The time synchronization error Δy is obtained after Kalman filtering. i and the time interval Δx between two consecutive times i Convert to x i and y i Then proceed, x i It is the reference value at each time synchronization, two adjacent x values. i The difference is the time interval between two consecutive time synchronizations, y i It is the cumulative sum of the time error in each round and the previous time error, with two adjacent y's. i The difference is the time synchronization error of a single time synchronization process, and the slope obtained by fitting is the estimated value of the clock frequency error.

[0051] After m rounds of two-way information exchange, the node to be synchronized receives a total of m sets of time information;

[0052] There are m sets of sample data: (x1, y1), (x2, y2), (x3, y3), ..., (x m ,y m The linear function to be fitted is y(x,ω)=ω1x+ω2, which can be expressed in matrix form as:

[0053] Y = XΩ T

[0054] in, Ω=[ω1,ω2], according to the above formula, the cumulative relative time deviation of the nodes to be synchronized is calculated as follows:

[0055] y i =(α-1)x i +β

[0056] Establish a linear model:

[0057]

[0058] Where ε is the Gaussian noise matrix, ω1 and ω2 are unknowns in the model assumptions, ω1 = α-1, ω2 = β, and the minimum residual sum of squares estimator of Ω is calculated as follows:

[0059] Ω=[α-1,β]=(X T X) -1 X T Y

[0060] Wherein, the frequency deviation α⁻¹ is a dimensionless number representing the ratio of the relative frequency deviation between the node to be synchronized and the reference node to the clock frequency of the reference node:

[0061]

[0062] Where Δf represents the clock frequency error.

[0063] Beneficial effects:

[0064] This invention, under the premise of achieving time-frequency synchronization between nodes, calculates the clock frequency error based on the time synchronization error sequence value obtained by the PTP time synchronization algorithm, and achieves high-precision time-frequency synchronization without the need for clock frequency changes using a digital phase-locked loop. The specific content can be divided into the following three parts:

[0065] First, Kalman filtering is used to process the obtained time synchronization error sequence value. The filtered time error value is used to compensate the hardware timestamp counter. Least squares estimation is used to fit the time synchronization error sequence value to obtain the clock frequency error, thereby achieving high-precision and stable time-frequency synchronization.

[0066] Second, two threshold values ​​are designed to determine whether the frequency synchronization is stable and to dynamically adjust the time synchronization interval. By increasing the cumulative duration of frequency offset, the clock frequency error is made more obvious, thereby achieving more stable and higher-precision time-frequency synchronization.

[0067] Third, a time stamp correction counter was designed. The period value of the time stamp correction counter was calculated based on the clock frequency error, and the hardware timestamp counter was periodically adjusted. This not only improved the accuracy of the hardware timestamp, but also achieved frequency synchronization at the hardware timestamp counter level without changing the clock frequency itself. This improved the accuracy of time-frequency synchronization, saved resources, and ensured the stability and reliability of program operation. Attached Figure Description

[0068] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 It is a bidirectional synchronization model based on sending and receiving;

[0070] Figure 2 This is a two-way synchronization model with a frequency difference.

[0071] Figure 3 This is a flowchart of the method of the present invention;

[0072] Figure 4 This is a rough synchronization flowchart;

[0073] Figure 5 For precise synchronization flowchart;

[0074] Figure 6This is a schematic diagram of clock frequency error fitting;

[0075] Figure 7 This is a diagram illustrating multiple time synchronizations. Detailed Implementation

[0076] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0077] It should be noted that, in the absence of conflict, the following embodiments and features can be combined with each other; and, based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0078] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0079] To improve the accuracy of time-frequency synchronization, this application provides an optimization method for high-precision time-frequency synchronization in distributed wireless network communication, such as... Figure 3 As shown, the method includes two steps: setting the time scale correction counter and coarse synchronization, as well as fine synchronization.

[0080] Time-scale correction counter settings: Set a time-scale correction counter in each node of the wireless network distributed system;

[0081] Coarse synchronization: Perform time synchronization N times according to the PTP time synchronization algorithm. During the 2nd to Nth time synchronization, perform single clock frequency error estimation and fitting, and use the fitted clock frequency error to calculate the period value of the timestamp correction counter, which is used to adjust the period value of the timestamp counter.

[0082] like Figure 4As shown, in the actual communication process of the ad hoc network, time synchronization and frequency synchronization need to be completed as soon as possible after the communication link is established. The frequency deviation value obtained from the first few time synchronizations is extremely large. Therefore, using too much time information to calculate the frequency deviation at the beginning will not only produce a large delay, but also the estimated value of the frequency deviation will not be accurate enough. The initial time synchronization is coarse synchronization. In this embodiment, the first three time synchronizations are coarse synchronizations, which are performed only according to the PTP time synchronization algorithm. The second and third time synchronizations are performed by estimating the single clock frequency error (according to formulas (8)-(9)). Based on the fitted clock frequency error, the period value of the corresponding time stamp correction counter is calculated, and the hardware timestamp counter of the node to be synchronized is periodically adjusted (that is, the time stamp correction counter is cleared and recounted after each full count, and the hardware timestamp counter is adjusted by one unit).

[0083] Fine synchronization: Starting from the (N+1)th synchronization, let every m synchronizations be denoted as one cycle;

[0084] First cycle: The hardware timestamp counter is periodically adjusted using the period value of the time stamp correction counter calculated by coarse synchronization; the time synchronization error is calculated and timestamp counter error compensation is performed after each time synchronization; after the time synchronization of this cycle is completed, Kalman filtering is performed on m groups of time synchronization errors, and least squares estimation fitting is performed using the filtered time synchronization error and the time interval between each two adjacent time synchronizations; the period value of the time stamp correction counter is calculated based on the fitted clock frequency error.

[0085] The second cycle begins: the timestamp counter is periodically adjusted using the period value of the time stamp correction counter calculated in the previous cycle; the time synchronization error is calculated after each time synchronization, and Kalman filtering is performed on the time synchronization error in combination with the data from the previous cycle. The filtered time error value is then used to compensate the hardware timestamp counter; after the time synchronization of this cycle is completed, Kalman filtering is performed on m groups of time synchronization errors, and least squares estimation fitting is performed using the filtered time synchronization error and the time interval between each two adjacent time synchronizations. The period value of the time stamp correction counter is then calculated based on the fitted clock frequency error.

[0086] like Figure 5 As shown, in this embodiment, starting from the 4th time synchronization, the fine synchronization stage begins, and the main process is as follows:

[0087] Starting from the 4th time synchronization, each m synchronizations constitute a cycle (m is 20 in this example). Within a cycle, the time synchronization error values ​​obtained from the PTP time synchronization algorithm for m consecutive times and the time interval between each adjacent time synchronization are recorded. Each time, the hardware timestamp counter of the node to be synchronized is compensated according to the calculated time synchronization error, but the clock frequency error estimation is updated, i.e., synchronization is only performed using the previously obtained clock frequency error. When the synchronization of this cycle is completed and m sets of time synchronization errors and time synchronization intervals are obtained, Kalman filtering is performed on these m time synchronization errors. The filtered time synchronization error value of the mth time is used to adjust the hardware timestamp counter. At the same time, least squares estimation is performed using the filtered data and time intervals to obtain the frequency error estimate, and the time scale correction counter cycle value is updated. The adjustment of the hardware timestamp counter mentioned above corresponds to time synchronization, and the adjustment of the time scale correction counter cycle value corresponds to frequency synchronization. The purpose of this process is to minimize the error impact caused by the acquisition accuracy and prevent over-correction or under-correction.

[0088] Starting from the second cycle, each subsequent time synchronization error undergoes Kalman filtering (the first m cycles are for raw data accumulation). The hardware timestamp counter is then compensated based on the Kalman-filtered time synchronization error value. Simultaneously, fine frequency synchronization is enabled. Least squares estimation is performed using the m sets of Kalman-filtered time synchronization errors to fit the clock frequency error. The period value of the time stamp correction counter is then calculated, and the hardware timestamp counter is periodically adjusted. This completes one cycle. The m recorded time synchronization error values ​​are retained as the raw data for Kalman filtering and used for filtering subsequent time synchronization errors. Frequency synchronization is performed only after every m recorded time synchronization results, and within each cycle, frequency synchronization is performed based on the clock frequency error obtained in the previous cycle.

[0089] The difference between the first cycle and subsequent cycles is as follows: In the first cycle, because not enough data (m times) have been accumulated, Kalman filtering of the time error value is only performed on the mth time, and the filtered value is then used to adjust the hardware timestamp counter. However, in subsequent cycles, because previous data has been retained, the time synchronization error obtained from each time synchronization can be Kalman filtered, and the filtered value is used to adjust the hardware timestamp counter. At the end of each subsequent cycle, a frequency estimation is performed, and the time stamp correction counter cycle value is updated after estimating the frequency error value.

[0090] Set two standard deviation thresholds for clock frequency errors: α1*f and α2*f; where α1 and α2 are threshold coefficients, and f is the nominal frequency of the slave node.

[0091] If the standard deviation of the clock frequency error obtained five times in a row is lower than the threshold value α1*f, the clock frequency synchronization is considered to be stable. In order to further improve the frequency synchronization accuracy, the time synchronization interval needs to be increased and the above fine synchronization process continues. If the standard deviation of the clock frequency error obtained five times in a row exceeds α2*f after increasing the time interval, the frequency synchronization is considered to be unstable. The time synchronization interval needs to be reduced and the above time-frequency synchronization process continues.

[0092] The specific implementation process of clock frequency error estimation is as follows:

[0093] In the initial stage of time synchronization, the reference node and the node to be synchronized perform m bidirectional information exchanges, with each exchange generating T. 1,i T 2,i T 3,i T 4,i Four timestamp information, such as Figure 6 As shown. Where, T 1,i and T 4,i Generated by the reference node, T 2,i and T 3,i The timestamps are generated by the node to be synchronized. The reference node then sends two timestamps T generated by the reference node to the node to be synchronized. 1,i and T 4,i After the synchronization node receives the two timestamps sent by the reference node, it calculates the transmission delay and relative time offset according to equations (3) and (4), and then performs Kalman filtering to obtain the time synchronization error Δy. i and the time interval Δx between two consecutive times i This is used to compensate the local hardware timestamp counters of different nodes, so that the local hardware timestamp counters of the nodes to be synchronized are the same as those of the reference nodes.

[0094] The frequency error is calculated as the ratio of the time synchronization error to the time interval. However, to use least squares estimation, these time synchronization errors and time intervals need to be accumulated separately and then fitted to the slope, i.e., converted to x. i and y i Then proceed, x i It is the reference value at each time synchronization, two adjacent x values. i The difference is the time interval between two adjacent time synchronizations. For ease of model building, the arithmetic mean of the two timestamps is used directly as the time. i It is the cumulative sum of the time error in each round and the previous time error, with two adjacent y's. i The difference is the time synchronization error of a single time synchronization process, such as... Figure 7 As shown.

[0095] After m rounds of bidirectional information exchange, the node to be synchronized receives a total of m sets of time information. Let xi y is the arithmetic mean of the two timestamps generated by the reference node during the i-th round of interaction. i It is the cumulative relative time deviation generated by the i-th round of interaction, calculated according to the PTP time synchronization algorithm, i.e.

[0096]

[0097] The local clock frequency and local reference time of the reference node are used as the time and frequency synchronization references for the communication system.

[0098] Suppose there are m sets of sample data: (x1, y1), (x2, y2), (x3, y3), ..., (x m ,y m The linear function to be fitted is y(x,ω)=ω1x+ω2, which can be expressed in matrix form as follows:

[0099] Y = XΩ T (12)

[0100] in

[0101]

[0102] Based on the above formula, the relative time deviation of the node to be synchronized can be calculated as follows:

[0103] y i =(α-1)x i +β (14)

[0104] A linear model can be established.

[0105]

[0106] Where ε is the Gaussian noise matrix, ω1 and ω2 are unknowns in the model assumptions, and ω1 = α-1, ω2 = β. According to equation (15), the minimum residual sum of squares estimator of Ω can be calculated as follows:

[0107] Ω=[α-1,β]=(X T X) -1 X T Y (16)

[0108] The frequency deviation α⁻¹ calculated according to equation (14) is a dimensionless number, representing the ratio of the relative frequency deviation between the node to be synchronized and the reference node to the clock frequency of the reference node.

[0109]

[0110] However, in practical applications, it is difficult to directly measure the clock frequency of communication nodes. This is because most devices do not have a dedicated clock output pin in order to maintain the stability of the clock output. Even if a chip for measuring the clock frequency is added to the node, the chip itself has errors, and high-precision frequency measurement oscilloscopes or spectrum analyzers cannot be used in real-time communication.

[0111] To overcome this difficulty, this application uses the nominal frequency f of the node to approximate the frequency deviation Δf by replacing the clock frequency of the reference node. The nominal frequency is the operating frequency of the device under ideal conditions and is a stable value. Although using the nominal frequency introduces some error, this error is acceptable in this application and can greatly simplify the calculation process and improve the accuracy of time synchronization. During multiple frequency synchronization processes, the relative frequency deviation Δf between the reference node and the node to be synchronized is continuously reduced. The lower the relative frequency deviation Δf, the smaller the error of using the nominal frequency to replace the clock frequency of the reference node, and the higher the accuracy of frequency synchronization.

[0112] Regarding the time-calibration counter:

[0113] According to the above records, if the calculated clock frequency error is directly used to change the main reference clock frequency of the hardware platform, it will affect the stability of the program operation and, in severe cases, cause the program's timing logic to be disordered. Considering that the main function of time-frequency synchronization is to serve time synchronization and help improve the accuracy of time synchronization, time-frequency synchronization at the hardware timestamp counter level can be achieved by compensating for the time error caused by the clock frequency error of the hardware timestamp. This invention designs a "time-stamp correction counter". A new counter is added to the hardware platform. The period value T of the time-stamp correction counter is calculated by converting the estimated clock frequency error value and the nominal frequency using formula (18). Every time the time-stamp correction counter completes its cycle, the hardware timestamp counter is adjusted by one counting unit. Time-frequency synchronization is achieved by periodically adjusting the hardware timestamp counter using this method.

[0114] Simultaneously, while reading the hardware timestamp count, the value of the timescale correction counter is read synchronously to improve the timestamp's accuracy, thereby further improving the accuracy of time-frequency synchronization. For example, if the hardware platform's clock frequency is 125MHz, the clock period is 8ns, meaning the timestamp counts once every 8ns. Adding a timescale correction counter can further read the stepping within less than 8ns, effectively increasing the resolution of the timestamp's decimal part and improving timestamp accuracy.

[0115]

[0116] Where T is the period of the time-stamp correction counter, f is the nominal frequency of the hardware platform, and Δf is the estimated clock frequency error. (For example, if the nominal frequency of the hardware platform is 128MHz and the estimated clock frequency error is 200Hz, then the period of the time-stamp correction counter is 128000000 / 200 = 640000, meaning the time-stamp correction counter resets to zero and restarts counting after 640000, and the hardware timestamp counter is adjusted by one counting unit.)

[0117] Based on the obtained clock frequency error estimate, combined with the nominal frequency of the hardware platform, the frequency word can be calculated and handed over to the DDS module to realize the disciplined clock of the corresponding frequency, thereby realizing frequency synchronization verification between nodes.

[0118] This embodiment optimizes existing time-frequency synchronization methods. Based on the PTP time synchronization algorithm, it utilizes a Kalman filter to process time synchronization errors, reducing the impact of acquisition accuracy errors on time synchronization. It uses the time error from multiple time synchronization calculations to fit the clock frequency error using least-squares estimation, improving the accuracy of clock frequency error estimation. When the clock frequency error is below a threshold, a dynamic sequence calculation method is used to increase the time synchronization interval, further enhancing the estimation accuracy of the clock frequency error. Simultaneously, a "time-stamp correction counter" is designed to periodically adjust the hardware timestamp counter using the obtained clock frequency error as a time-stamp correction counter. This further improves timestamp accuracy and achieves high-precision time-frequency synchronization without directly modifying the hardware clock.

[0119] In summary, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-precision time-frequency synchronization optimization method for distributed wireless network communication, characterized in that, The specific process is as follows: Counter settings: Set a time-scale correction counter in each node of the wireless network distributed system; Coarse synchronization: Perform time synchronization N times according to the PTP time synchronization algorithm; Fine synchronization: Starting from the (N+1)th synchronization, let every m synchronizations be denoted as one cycle; First cycle: The hardware timestamp counter is periodically adjusted using the period value of the time stamp correction counter calculated by coarse synchronization; the time synchronization error is calculated and timestamp counter error compensation is performed after each time synchronization; after the time synchronization of this cycle is completed, Kalman filtering is performed on m groups of time synchronization errors, and least squares estimation fitting is performed using the filtered time synchronization error and the time interval between each two adjacent time synchronizations; the period value of the time stamp correction counter is calculated based on the fitted clock frequency error. The second cycle begins: the timestamp counter is periodically adjusted using the period value of the time stamp correction counter calculated in the previous cycle; the time synchronization error is calculated after each time synchronization, and the time synchronization error is Kalman filtered in combination with the data from the previous cycle, and the filtered time error value is used to compensate the hardware timestamp counter. After the time synchronization of this cycle is completed, Kalman filtering is performed on the m groups of time synchronization errors, and least squares estimation fitting is performed using the filtered time synchronization error and the time interval between each two adjacent time synchronizations. The period value of the time scale correction counter is calculated based on the fitted clock frequency error. Set two standard deviation thresholds for clock frequency errors: and ;in, and The threshold coefficient, The nominal frequency of the slave node; If the standard deviation of the clock frequency error obtained in M ​​consecutive tests is lower than the threshold value Increase the time synchronization interval and continue the fine synchronization process; If the standard deviation of the clock frequency error for M consecutive cycles exceeds If the time synchronization interval is reduced, the fine synchronization process continues.

2. The high-precision time-frequency synchronization optimization method for distributed wireless network communication according to claim 1, characterized in that, The number of times M is 5.

3. The high-precision time-frequency synchronization optimization method for distributed wireless network communication according to claim 1, characterized in that, The period value of the time-calibration counter, calculated based on the fitted clock frequency error, is: obtained from the estimated clock frequency error value. With the nominal frequency of the slave node The period value of the time-calibration counter can be calculated using the following formula. ; 。 4. The high-precision time-frequency synchronization optimization method for distributed wireless network communication according to claim 1, characterized in that, During coarse synchronization, a single clock frequency error estimation and fitting is performed during the 2nd to Nth time synchronizations, and the fitted clock frequency error is used to calculate the period value of the timestamp correction counter, which is then used to adjust the period value of the timestamp counter.

5. The high-precision time-frequency synchronization optimization method for distributed wireless networking communication according to claim 4, characterized in that, The number of iterations N is 3.

6. The high-precision time-frequency synchronization optimization method for distributed wireless network communication according to claim 1, characterized in that, The specific process of clock frequency error fitting is as follows: The time synchronization error is obtained after Kalman filtering. and the time interval between two consecutive times Converted to and Then proceed, These are reference values ​​for each time synchronization, two adjacent values. The difference is the time interval between two consecutive time synchronizations. It is the sum of the time error in each round and the previous time error, with two adjacent rounds... The difference is the time synchronization error of a single time synchronization process; After m rounds of two-way information exchange, the node to be synchronized receives a total of m sets of time information; There are m sets of sample data: The univariate linear function to be fitted is Represented in matrix form as: in, , , ; Based on the univariate linear function and its matrix form, the relative time deviation of the nodes to be synchronized is calculated as follows: Establish a linear model: in, It is a Gaussian noise matrix. and These are the unknowns in the model assumptions. = , = Calculate The minimum residual sum of squares estimator is: Among them, frequency deviation It is a dimensionless number representing the ratio of the relative frequency deviation between the node to be synchronized and the reference node to the clock frequency of the reference node: in, This indicates clock frequency error.

7. The high-precision time-frequency synchronization optimization method for distributed wireless network communication according to claim 6, characterized in that, The value of m is 20.

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