Power supply test circuit and power supply test method

Abstract

This application relates to the field of power electronics technology, specifically to a power supply testing circuit and method, including a current and voltage sampling circuit, a main control chip, a sampling calibration circuit, and a drive control circuit. The sampling calibration circuit includes a reference voltage circuit, a DAC calibration circuit, and an amplification control circuit. After acquiring first sampling information, the current and voltage sampling circuit generates a DAC control code, sends the DAC control code to the DAC calibration circuit, outputs an analog reference voltage, generates a reference voltage control signal, controls the output power, acquires second sampling information, generates a second measurement result, and uploads the information to a host computer when the second measurement result matches the theoretical reference value. This ensures that the information is sent to the host computer only after successful calibration, solving the problem of inaccurate measurement and large errors caused by directly sending the measurement value converted from a single ADC to the host computer.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a power supply test circuit and a power supply test method. Background Technology

[0002] With the increasing popularity of various power supply devices such as adapters and batteries, the requirements for power density, output accuracy and dynamic performance of power supplies are increasing, which in turn places higher demands on the measurement accuracy of power supply testing equipment.

[0003] In existing power supply testing equipment, the channel current is led to IN+1 from the drain side of the MOS transistor in the structure for monitoring the power supply current. Specifically, refer to Chinese invention patent CN120370208B, which describes in paragraph 0212: "In the power control circuit, terminal 101-1 is connected to the gate of the switching transistor MOS101 through resistor R148, and the gate of the switching transistor MOS101 is connected to GND1 through resistor R149; the drain of MOS101 is connected to terminal IN+1 through resistors R132, R131, R130, R129, and R128 connected in sequence, and terminal IN+1 is used for sampling." It can be seen that the drain of MOS101 is connected to IN+1 only after passing through a resistor branch composed of resistors R132, R131, R130, R129, and R128. In addition, as described in the manual 0213-0214, terminal IN+1 is connected to terminal IN-1 through a branch of resistors R156 and R157 connected in series and another branch of resistors R158 and R159 connected in series. Terminal IN-1 is then connected to GND1, and the two resistor branches form a parallel current sampling network.

[0004] As can be seen, the current sampling path from IN+1 to IN-1 involves two series resistor branches. The current sampling is conducted through a distributed equivalent resistance consisting of multiple resistors, relay RY101 contacts, terminal connections, and PCB copper foil. The equivalent resistance being sampled is determined by multiple discrete resistors and traces, and is significantly affected by layout, wiring, soldering processes, and contact aging. The cumulative resistance errors make it impossible to calculate accurately, resulting in the difficulty in precisely defining and maintaining the stability of the actual resistance value. This introduces systematic proportional errors and temperature drift, leading to low sampling accuracy.

[0005] Furthermore, in signal processing, traditional signal acquisition and processing schemes are typically based on a one-way information processing structure of analog signal conditioning, ADC sampling, and digital processing and uploading. This one-way information processing structure can also be seen in the description of Chinese invention patent CN120370208B. This signal processing method has drawbacks. Because the measured value converted by the ADC is directly sent to the host computer, there is a lack of verification of the measurement results, which leads to inaccurate measurements and large errors. Summary of the Invention

[0006] Therefore, it is necessary to provide a power supply test circuit and power supply test method that can solve the problem of inaccurate measurement and large error caused by sending the measured value calculated by the ADC to the host computer in one go and lacking result verification.

[0007] The technical solution of this invention is as follows:

[0008] A power supply testing circuit includes a current and voltage sampling circuit, a main control chip, a sampling calibration circuit, and a drive control circuit. The current and voltage sampling circuit is connected to the main control chip and is used to send first sampling information to the main control chip.

[0009] The main control chip generates a first measurement result based on the first sampling information, generates a DAC control code based on the first measurement result and the target set value, and sends the DAC control code to the sampling calibration circuit.

[0010] The sampling calibration circuit includes a reference voltage circuit, a DAC calibration circuit, and an amplification control circuit, wherein:

[0011] The reference voltage circuit is connected to the DAC calibration circuit and is used to provide a reference voltage to the DAC calibration circuit.

[0012] The DAC calibration circuit is connected to the main control chip and is used to output an analog reference voltage that is proportional to the DAC control code under the constraint of the reference voltage.

[0013] The amplification control circuit is used to generate a reference voltage control signal based on the received analog reference voltage, and send the reference voltage control signal to the drive control circuit so that the drive control circuit controls the output power.

[0014] The current and voltage sampling circuit acquires the second sampling information and sends it to the main control chip, so that the main control chip generates a second measurement result based on the second sampling information;

[0015] When the main control chip determines that the second measurement result matches the theoretical reference value, it uploads the information to the host computer. The theoretical reference value is calculated and generated by the main control chip based on the DAC control code and the reference voltage.

[0016] Optionally, the DAC calibration circuit includes a DAC processing chip and a capacitor C116. The DAC processing chip is connected to the main control chip U104, the reference voltage circuit, and the amplification control circuit. The capacitor C116 is connected to the second pin of the DAC processing chip.

[0017] Optionally, the reference voltage circuit includes a reference voltage source chip, capacitors C113, C114, and C115. The sixth pin of the reference voltage source chip is connected to the third pin of the DAC processing chip. One end of capacitors C113, C114, and C115 is connected to the second, fifth, and sixth pins of the reference voltage source chip, respectively. The other ends of capacitors C113, C114, and C115 are all grounded.

[0018] Optionally, the amplification control circuit includes an amplification control chip, the ninth pin of which is connected to the first pin of the DAC processing chip, and the first and third pins of the amplification control chip are connected to the drive control circuit.

[0019] Optionally, the current and voltage sampling circuit includes a power supply circuit, a first sampling resistor, a second sampling resistor, and a sampling chip;

[0020] The power input terminal of the power supply access circuit is connected to the power supply under test. The two ends of the first sampling resistor and the second sampling resistor are respectively connected to the positive sampling point and the negative sampling point. The positive sampling point is also connected to the power supply access circuit.

[0021] The positive sampling point and the negative sampling point are respectively connected to the sampling chip, so that the sampling chip sends the sampling information to the main control chip.

[0022] Optionally, the power supply circuit includes a relay, a MOSFET driver circuit, a first shunt resistor, and a second shunt resistor. The fourth pin of the relay is connected to the power input terminal, the MOSFET driver circuit is connected to the relay, and both the first shunt resistor and the second shunt resistor are connected to the MOSFET driver circuit.

[0023] Optionally, the MOS transistor driving circuit includes a first MOS transistor and a second MOS transistor, the drains of the first MOS transistor and the second MOS transistor are both connected to the fifth pin of the relay, the source of the first MOS transistor is connected to the first shunt resistor, and the source of the second MOS transistor is connected to the second shunt resistor.

[0024] Both the first shunt resistor and the second shunt resistor are connected to the tenth pin of the sampling chip.

[0025] The technical effects of the above-mentioned power supply test circuit are as follows:

[0026] 1. By setting up a reference voltage circuit, a DAC calibration circuit, and an amplification control circuit, after the current and voltage sampling circuit obtains the first sampling information and sends it to the main control chip, it does not directly send it to the host computer. Instead, it generates a DAC control code based on the first measurement result and the target set value, and sends the DAC control code to the sampling calibration circuit. Under the constraint of the reference voltage provided by the reference voltage circuit, the DAC calibration circuit outputs an analog reference voltage proportional to the DAC control code. Based on the amplification control circuit, it generates a reference voltage control signal. After the drive control circuit controls the output power based on the reference voltage control signal, the current and voltage sampling circuit obtains the second sampling information and sends it to the main control chip. The main control chip then generates a second measurement result based on the second sampling information. The main control chip then uploads the information to the host computer only when it determines that the second measurement result matches the theoretical reference value. This achieves the goal of sending the information to the host computer only after passing the second calibration, solving the problem of inaccurate measurement and large errors caused by directly sending the measurement value converted by the ADC to the host computer without verification of the measurement result.

[0027] 2. By setting a first sampling resistor and a second sampling resistor, and connecting the two ends of the first sampling resistor and the second sampling resistor to the positive sampling point and the negative sampling point respectively, and then connecting them to the sampling chip, the shunt resistor formed by the independent first sampling resistor and the second sampling resistor in parallel participates in the main voltage drop. The upstream MOSFET, relay, copper foil, etc. are all located before the positive sampling point, no longer between the positive and negative sampling points, thus avoiding the introduction of systematic proportional errors and temperature drift. This solves the problem that multiple resistance errors accumulate and cannot be accurately calculated, resulting in difficulty in accurately defining the actual resistance value and low sampling accuracy.

[0028] A power supply testing method is also provided, the testing method comprising:

[0029] Step S100: The current and voltage sampling circuit sends the acquired first sampling information to the main control chip. The main control chip generates a first measurement result based on the first sampling information and generates a DAC control code.

[0030] Step S200: The DAC calibration circuit receives the DAC control code and outputs an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage;

[0031] Step S300: The amplification control circuit generates a reference voltage control signal based on the received analog reference voltage and sends it to the drive control circuit;

[0032] Step S400: The current and voltage sampling circuit sends the acquired second sampling information to the main control chip, and the main control chip generates a second measurement result based on the second sampling information;

[0033] Step S500: When the main control chip determines that the second measurement result matches the theoretical reference value, it uploads the information to the host computer.

[0034] The technical effects achieved by the above power supply testing method are as follows:

[0035] The aforementioned power supply testing method is based on the aforementioned power supply testing circuit, therefore, the power supply testing method also possesses the technical effects of the power supply testing circuit. Specifically, after acquiring the first sampling information through the current and voltage sampling circuit and sending it to the main control chip U104, it does not directly send it to the host computer. Instead, it generates a DAC control code based on the first measurement result and the target set value, and sends the DAC control code to the sampling calibration circuit. This causes the DAC calibration circuit to output an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage provided by the reference voltage circuit. The amplification control circuit then generates a signal based on the analog reference voltage. Reference voltage control signal: After the drive control circuit controls the output power based on the reference voltage control signal, the current and voltage sampling circuit acquires the second sampling information and sends it to the main control chip U104, so that the main control chip U104 generates a second measurement result based on the second sampling information. Then, the main control chip U104 uploads the information to the host computer only when it determines that the second measurement result matches the theoretical reference value. This realizes that the information is sent to the host computer only after passing the second calibration, which solves the problem of directly sending the measurement value converted by the ADC to the host computer without the verification of the measurement result, thus leading to inaccurate measurement and large error. Attached Figure Description

[0036] Figure 1 This is a circuit schematic of the main control chip in the power supply test circuit of one embodiment;

[0037] Figure 2 This is a circuit schematic of the DAC calibration circuit in one embodiment;

[0038] Figure 3 This is a circuit schematic of a reference voltage circuit in one embodiment;

[0039] Figure 4 This is a circuit diagram of the amplification control circuit in one embodiment;

[0040] Figure 5 This is a circuit schematic diagram of the signal processing circuit in one embodiment;

[0041] Figure 6 This is a circuit diagram of a first-stage amplifier circuit in one embodiment;

[0042] Figure 7 This is a circuit schematic of a MOS transistor driving circuit in one embodiment;

[0043] Figure 8 This is a schematic diagram of a combined circuit of the first sampling resistor and the second sampling resistor in one embodiment;

[0044] Figure 9 This is a circuit schematic diagram with a sampling chip as the core in one embodiment;

[0045] Figure 10 This is a circuit schematic diagram with a relay as the core in one embodiment;

[0046] Figure 11 This is a flowchart of a power supply testing method in one embodiment. Detailed Implementation

[0047] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0048] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0049] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0050] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0051] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0052] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0053] In one embodiment, such as Figure 1 As shown, a power supply test circuit is provided, including a current and voltage sampling circuit, a main control chip U104, a sampling calibration circuit, and a drive control circuit. The current and voltage sampling circuit is connected to the main control chip U104 and is used to send the first sampling information to the main control chip U104.

[0054] The main control chip U104 generates a first measurement result based on the first sampling information, and generates a DAC control code based on the first measurement result and the target set value, and sends the DAC control code to the sampling calibration circuit. The current and voltage sampling circuit is used to sample the power supply under test. After sampling, it calculates and obtains the first sampling information, which includes the original voltage and current code values. The main control chip U104 calculates the current output power, voltage error, current error, and other physical quantities based on the original voltage and current code values, combined with the calibrated resistance values ​​and voltage division ratios of the first sampling resistor R179 and the second sampling resistor R180 (described below) in the current and voltage sampling circuit, thus generating the first measurement result. The calculation of the first measurement result is implemented based on the internal firmware of the main control chip U104, which is an STM32G431RBT6.

[0055] The target setpoints are preset and include, but are not limited to, target constant voltage, constant current, and power curves. Based on the first measurement result and the target setpoints, the corresponding control quantity is calculated and encoded into a digital code for the DAC, i.e., the DAC control code. The DAC control code is sent to the sampling calibration circuit, specifically to the DAC calibration circuit within the sampling calibration circuit.

[0056] The sampling calibration circuit includes a reference voltage circuit, a DAC calibration circuit, and an amplification control circuit. The reference voltage circuit is connected to the DAC calibration circuit and is used to provide a reference voltage to the DAC calibration circuit.

[0057] The DAC calibration circuit is connected to the main control chip and is used to output an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage. After receiving the DAC control code, the DAC calibration circuit stores the DAC control code in an internal register and uses it as a control quantity to cause the DAC calibration circuit to output an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage.

[0058] The amplification control circuit is used to generate a reference voltage control signal based on the received analog reference voltage, and send the reference voltage control signal to the drive control circuit so that the drive control circuit controls the output power.

[0059] When the output channel reaches a stable state, the current and voltage sampling circuit acquires second sampling information and sends it to the main control chip U104, so that the main control chip U104 generates a second measurement result based on the second sampling information. In this step, after the drive control circuit adjusts the output based on the reference voltage control signal, the main control chip U104 can determine that the output channel has reached a stable state by detecting whether the change in output voltage / current within a preset time window is less than a stability threshold; after determining that the output is stable, the current and voltage sampling circuit is triggered to acquire the second sampling information. The stability threshold and the preset time window are preset by those skilled in the art.

[0060] When the main control chip U104 determines that the second measurement result matches the theoretical reference value, it uploads the information to the host computer. The theoretical reference value is calculated by the main control chip U104 based on the DAC control code and the reference voltage. After the output channel stabilizes, the current and voltage sampling circuit samples and acquires second sampling information. The main control chip U104 generates the second measurement result based on this second sampling information. The main control chip U104 calculates the theoretical reference value based on the DAC control code written to the DAC calibration circuit and the reference voltage. It then compares the theoretical reference value with the second measurement result. Only when the difference between the two does not exceed a preset threshold is the second measurement result considered to match the theoretical reference value, and only then is the second measurement result uploaded to the host computer. The preset threshold is set by those skilled in the art and is not limited in this application.

[0061] The main control chip U104 has recorded the DAC control code when writing it into the DAC calibration circuit. At the same time, the main control chip U104 also knows the nominal value and calibration coefficient of the reference voltage. Therefore, the theoretical reference value can be estimated through the transfer function corresponding to the DAC calibration circuit.

[0062] In this application, the theoretical reference value is used to characterize the theoretical target physical quantity at the output terminal under the current control mode. Specifically, when the control mode is constant voltage mode, the theoretical reference value is the theoretical output voltage; when the control mode is constant current mode, the theoretical reference value is the theoretical output current; when the control mode is constant power mode, the theoretical reference value can be the converted theoretical output power or the corresponding theoretical output voltage or current.

[0063] In this application, by setting up a reference voltage circuit, a DAC calibration circuit, and an amplification control circuit, after acquiring the first sampling information through the current and voltage sampling circuit and sending it to the main control chip U104, it does not directly send it to the host computer. Instead, it generates a DAC control code based on the first measurement result and the target set value, and sends the DAC control code to the sampling calibration circuit. This causes the DAC calibration circuit to output an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage provided by the reference voltage circuit. Based on the analog reference voltage, the amplification control circuit generates a reference voltage control signal. After the drive control circuit controls the output power based on the reference voltage control signal, the current and voltage sampling circuit acquires the second sampling information and sends it to the main control chip U104, so that the main control chip U104 generates a second measurement result based on the second sampling information. Then, the main control chip U104 uploads the information to the host computer only when it determines that the second measurement result matches the theoretical reference value. This realizes that the information is sent to the host computer only after passing the second calibration, which solves the problem of sending the measurement value converted by the ADC directly to the host computer without the verification of the measurement result, thus leading to inaccurate measurement and large error.

[0064] In one embodiment, such as Figure 2 As shown, the DAC calibration circuit includes a DAC processing chip U110 and a capacitor C116. The DAC processing chip U110 is connected to the main control chip U104, the reference voltage circuit and the amplification control circuit. The capacitor C116 is connected to the second pin of the DAC processing chip U110.

[0065] The fifth pin of the DAC processing chip U110 is connected to the thirty-fifth pin of the main control chip U104, the sixth pin of the DAC processing chip U110 is connected to the thirty-seventh pin of the main control chip U104, and the fourth pin of the DAC processing chip U110 is connected to the thirty-sixth pin of the main control chip U104. The DAC processing chip U110 and the main control chip U104 perform mutual data transmission and calculation based on their connected pins.

[0066] In one embodiment, such as Figure 3As shown, the reference voltage circuit includes a reference voltage source chip U109, capacitors C113, C114, and C115. The sixth pin of the reference voltage source chip U109 is connected to the third pin of the DAC processing chip U110. One end of each capacitor (C113, C114, and C115) is connected to the second, fifth, and sixth pins of the reference voltage source chip U109, respectively. The other ends of each capacitor (C113, C114, and C115) are grounded. Capacitors C114 and C115 act as a filter circuit to ensure the stability of the output reference voltage. The reference voltage is output from the sixth pin of the reference voltage source chip U109 to the third pin of the DAC processing chip U110. This reference voltage is a fixed voltage that is as stable as possible, highly accurate, and with minimal temperature drift. By providing this reference voltage, the DAC processing chip U110 no longer uses the power supply as a reference. Even if the power supply fluctuates with load, temperature, and ripple, it will not be affected, filtering out instability caused by slight power supply jitter.

[0067] The reference voltage is used both to constrain the analog reference voltage output by the DAC processing chip U110, serving as the reference voltage for the DAC and determining the proportional relationship of its output voltage, and to be used by the main control chip U104 to calculate the theoretical reference value. Therefore, the main control chip U104 can calculate the current theoretical reference value based solely on the DAC control code and the calibration parameters of the reference voltage, without relying on external measurements.

[0068] After the output voltage is regulated and stabilized by the drive control circuit, the current and voltage sampling circuit acquires the second measurement result again. The main control chip U104 compares the second measurement result with the theoretical reference value calculated based on the DAC control code and the reference voltage. The information is uploaded to the host computer only when the deviation between the two is within the preset consistency threshold.

[0069] Therefore, the setting of the reference voltage not only improves the accuracy of digital-to-analog conversion and analog reference voltage generation, but also serves as the physical benchmark for self-verification of measurement results in this application. This enables the power supply test circuit to automatically identify and suppress erroneous measurement results caused by sampling link drift and drive link abnormalities before data upload, thereby significantly improving the reliability of the output measurement data.

[0070] In one embodiment, such as Figure 4As shown, the amplification control circuit includes an amplification control chip U108. The ninth pin of the amplification control chip U108 is connected to the first pin of the DAC processing chip U110. The first and third pins of the amplification control chip U108 are connected to the drive control circuit. The seventh pin of the amplification control chip U108 is connected to the thirty-fourth pin of the main control chip U104; the sixth pin of the amplification control chip U108 is connected to the thirty-third pin of the main control chip U104. The DAC processing chip U110 controls the amplification control chip U108 by connecting to its ninth pin, ensuring that the amplification control chip U108 outputs a correct reference voltage control signal, which is then used to control the drive control circuit.

[0071] like Figure 5 As shown, the drive control circuit includes a signal processing circuit. The third pin of the amplifier chip U113A in the signal processing circuit is connected to the first pin of the amplifier control chip U108. The fifth pin of the amplifier chip U113B in the signal processing circuit is connected to the third pin of the amplifier control chip U108. It should be noted that the amplifier chips U113A, U113B, and U114 in the signal processing circuit described in this application are the same as the chips U103B, U103A, and U104 in the signal processing circuit of Chinese Invention Patent Publication No. CN120370208B. Those skilled in the art should understand their working principle; therefore, this application will not elaborate further.

[0072] like Figure 6 As shown, the output terminal CH1_PROG_CELL of the signal processing circuit described in this application is connected to amplifier chips U117A and U117B in the first-stage amplifier circuit. Specifically, the output terminal CH1_PROG_CELL is connected to the third pin of amplifier chip U117A and the fifth pin of amplifier chip U117B, and is connected to the first pin of amplifier chip U117A via the output terminal CH1_Q101A_EN, and the seventh pin of amplifier chip U117B via the output terminal CH1_Q101B_EN.

[0073] It should be noted that the drive control circuit and the signal processing circuit are not the focus of this application and are existing technologies. Therefore, those skilled in the art should know and master the principles. Hence, this application adopts an abbreviated form and does not elaborate in detail.

[0074] like Figure 7As shown, the connection terminals CH1_Q101A_EN and CH1_Q101B_EN are used to drive the first MOS transistor Q101A and the second MOS transistor Q101B in the MOS transistor drive circuit (described below).

[0075] In one embodiment, such as Figures 7-10 As shown, the current and voltage sampling circuit includes a power supply circuit, a first sampling resistor R179, a second sampling resistor R180, and a sampling chip U105.

[0076] like Figures 8-10 As shown, the power input terminal CH1_VIN of the power supply access circuit is connected to the power supply under test. The two ends of the first sampling resistor R179 and the second sampling resistor R180 are respectively connected to the positive sampling point CH1_IN+ and the negative sampling point CH1_IN-. The positive sampling point CH1_IN+ is also connected to the power supply access circuit.

[0077] The positive sampling point CH1_IN+ and the negative sampling point CH1_IN- are respectively connected to the sampling chip U105, so that the sampling chip U105 sends the sampling information to the main control chip U104.

[0078] In this embodiment, by setting a first sampling resistor R179 and a second sampling resistor R180, and connecting the two ends of the first sampling resistor R179 and the second sampling resistor R180 to the positive sampling point CH1_IN+ and the negative sampling point CH1_IN- respectively, and then connecting them to the tenth and ninth pins of the sampling chip U105, the current is measured. The shunt resistor formed by the independent first sampling resistor R179 and the second sampling resistor R180 in parallel participates in the main voltage drop. The upstream MOSFET, relay, copper foil, etc. are all located before the positive sampling point CH1_IN+, and are no longer between the positive sampling point CH1_IN+ and the negative sampling point CH1_IN-. This avoids the introduction of systematic proportional error and temperature drift, and solves the problem that multiple resistance errors accumulate and cannot be accurately calculated, resulting in difficulty in accurately defining the actual resistance value and low sampling accuracy.

[0079] like Figure 9 As shown, the power input terminal CH1_VIN is connected to the eighth pin of the sampling chip U105 via resistors R108, R107, and R106 for voltage measurement.

[0080] Furthermore, the resistance values ​​of both the first sampling resistor R179 and the second sampling resistor R180 are 10 milliohms. By setting an exact resistance of 10 milliohms for calculation, the accuracy of current sampling is improved.

[0081] In one embodiment, such as Figure 10 As shown, the power input circuit includes a relay RL101, a MOSFET driver circuit, a first shunt resistor R172, and a second shunt resistor R174. The fourth pin of the relay RL101 is connected to the power input terminal CH1_VIN. The MOSFET driver circuit is connected to the relay RL101. Both the first shunt resistor R172 and the second shunt resistor R174 are connected to the MOSFET driver circuit.

[0082] In one embodiment, such as Figure 7 As shown, the MOSFET driving circuit includes a first MOSFET Q101A and a second MOSFET Q101B. The drains of both the first MOSFET Q101A and the second MOSFET Q101B are connected to the fifth pin of the relay RL101. The source of the first MOSFET Q101A is connected to the first shunt resistor R172, and the source of the second MOSFET Q101B is connected to the second shunt resistor R174.

[0083] The first shunt resistor R172 and the second shunt resistor R174 are both connected to the tenth pin of the sampling chip U105.

[0084] The first shunt resistor R172 and the second shunt resistor R174 serve as source-dissipative current sampling resistors for the first MOSFET Q101A and the second MOSFET Q101B.

[0085] Specifically, the first shunt resistor R172 and the second shunt resistor R174 both have a resistance of 10 milliohms. That is, the first shunt resistor R172 and the second shunt resistor R174 are set with small resistance values ​​in the milliohm range, so their voltage drop and power consumption are still limited even under large current. On the other hand, the voltage drop of the source resistor is distributed in the source circuit of the MOSFET and is not concentrated in a single device, so the impact on the total channel voltage drop and efficiency is controllable.

[0086] In existing multi-MOS parallel structures, the discrete parameters of each MOS transistor lead to uneven current distribution, which can easily cause current grabbing and thermal runaway. This embodiment addresses this issue by introducing local current negative feedback in the source circuit based on the first shunt resistor R172 and the second shunt resistor R174. This causes the source potential of the MOS transistor with excessive current to rise and the gate-source voltage to fall, thus automatically suppressing its current; conversely, the opposite occurs with the MOS transistor with insufficient current. Automatic current sharing among multiple power MOS transistors can be achieved at the device level without complex digital control, improving the overall thermal stability and reliability of the channel.

[0087] By setting milliohm-level first shunt resistor R172 and second shunt resistor R174 in the source circuit of the parallel MOSFETs, local current negative feedback is introduced, which enables the current between each MOSFET to be automatically balanced, suppresses current snatching and thermal runaway caused by parameter dispersion, and further improves the thermal stability and reliability of multi-channel output.

[0088] In summary, the first sampling resistor R179 and the second sampling resistor R180 serve as the main sampling resistors for the measurement channel, used to generate a voltage drop proportional to the total channel current, which is then accurately measured by the differential input pin of the sampling chip U105.

[0089] The first shunt resistor R172 and the second shunt resistor R174 are mainly used as current sharing resistors for the source circuit of the parallel MOS transistor, which are used to introduce local current negative feedback to suppress current grabbing. Their voltage drop can be selected as an auxiliary quantity for branch current monitoring.

[0090] In one embodiment, such as Figure 11 As shown, a power supply testing method is also provided, including:

[0091] Step S100: The current and voltage sampling circuit sends the acquired first sampling information to the main control chip U104. The main control chip U104 generates a first measurement result based on the first sampling information and generates a DAC control code. Specifically, the DAC control code is generated based on the first measurement result and the target set value.

[0092] Step S200: The DAC calibration circuit receives the DAC control code and outputs an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage;

[0093] Step S300: The amplification control circuit generates a reference voltage control signal based on the received analog reference voltage and sends it to the drive control circuit;

[0094] Step S400: When the output channel reaches a stable state, the current and voltage sampling circuit will send the second sampling information acquired again to the main control chip U104, and the main control chip U104 will generate a second measurement result based on the second sampling information.

[0095] In this step, after the drive control circuit adjusts the output based on the reference voltage control signal, the main control chip U104 can determine that the output channel has reached a stable state by detecting whether the change in output voltage / current within a preset time window is less than a stability threshold. After determining that the output is stable, the current and voltage sampling circuit is triggered to collect second sampling information. The stability threshold and the preset time window are preset by those skilled in the art.

[0096] Step S500: When the main control chip U104 determines that the second measurement result matches the theoretical reference value, it uploads the information to the host computer.

[0097] In this embodiment, after the first sampling information is obtained through the current and voltage sampling circuit and sent to the main control chip U104, it is not directly sent to the host computer. Instead, a DAC control code is generated based on the first measurement result and the target setting value, and the DAC control code is sent to the sampling calibration circuit. Under the constraint of the reference voltage provided by the reference voltage circuit, the DAC calibration circuit outputs an analog reference voltage proportional to the DAC control code. Based on the amplification control circuit, a reference voltage control signal is generated according to the analog reference voltage. After the drive control circuit controls the output power based on the reference voltage control signal, the current and voltage sampling circuit obtains the second sampling information and sends it to the main control chip U104. The main control chip U104 generates a second measurement result based on the second sampling information. Then, the main control chip U104 uploads the information to the host computer only when it determines that the second measurement result matches the theoretical reference value. This achieves the goal of sending the information to the host computer only after passing the second calibration, solving the problem of sending the measurement value converted by the ADC directly to the host computer without verification of the measurement result, which leads to inaccurate measurement and large error.

[0098] In one embodiment, the power supply testing method further includes:

[0099] Step S600: When it is determined that the difference between the second measurement result and the theoretical reference value is less than a preset threshold, the main control chip U104 calculates the correction coefficient of the current test channel based on the theoretical reference value and the second measurement result, and stores the correction coefficient after establishing a correspondence between the current test channel's identifier and output level.

[0100] In one embodiment, the correction coefficient is obtained by calculating the ratio of the theoretical reference value to the second measurement result, specifically by dividing the theoretical reference value by the second measurement result.

[0101] Step S700: When the same test channel executes steps S100-S500 again under the same output level, after generating the first measurement result based on the first sampling information, the main control chip obtains the correction coefficient corresponding to the test channel and output level, and uses the correction coefficient to compensate the first measurement result to obtain the compensated measurement result, and sends the compensated measurement result as the final test result of the power supply under test to the host computer.

[0102] Specifically, the compensated measurement result is obtained by multiplying the correction coefficient by the first measurement result.

[0103] In this embodiment, the deviation between the theoretical reference value obtained during the self-calibration process and the second measurement result is converted into a correction coefficient, thereby correcting the subsequent first measurement result obtained under the same test channel and the same output level, achieving automatic calibration of the test channel. Without changing the original self-calibration process, the systematic error of the tested power supply output is further reduced, and the accuracy of the measurement results is improved.

[0104] In another embodiment, the power supply testing method further includes: based on the calculation of the correction coefficient, triggering a recalculation of the correction coefficient in response to a large temperature change or a high number of times the correction coefficient is used.

[0105] Specifically, when calculating the correction coefficient, the main control chip U104 records the temperature value of the onboard temperature sensor at that time, associates and stores the temperature value with the correction coefficient, and initializes the usage count of the correction coefficient to zero. The onboard temperature sensor is pre-configured so that when the same test channel executes steps S100-S700 multiple times at the same output level, each time the main control chip U104 calls the correction coefficient to compensate for the first measurement result, the usage count is incremented, and the current temperature value of the onboard temperature sensor is read synchronously.

[0106] When the difference between the current temperature and the temperature value recorded when the correction coefficient was generated is greater than the temperature change threshold, and / or when the number of times the correction coefficient was used is greater than the number of times it was used, the main control chip U104 triggers the re-execution of steps S200-S700 to obtain a new correction coefficient for the current test channel and output level, and replaces the original correction coefficient with the new correction coefficient, thereby ensuring that the correction effect remains effective under temperature changes and long-term operating conditions.

[0107] The temperature change threshold is generally set between 5℃ and 20℃, such as 10℃. The usage frequency threshold is preset, generally between 100 and 1000 times, such as 500 times.

[0108] It should be noted that the information interaction and execution process between the above modules are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0110] This application also provides a network device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above method embodiments.

[0111] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0112] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the above-described method embodiments.

[0113] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above-described embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographic device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0115] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0116] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0118] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

[0119] One embodiment of this application also provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above-described methods.

[0120] The computer device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that the above description is an example of a computer device and does not constitute a limitation on the computer device. It may include more or fewer components than described above, or a combination of certain components, or different components, such as input / output devices, network access devices, etc.

[0121] The processor referred to can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0122] In some embodiments, the memory may be an internal storage unit of the computer device, such as a hard drive or RAM. In other embodiments, the memory may be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory may include both internal and external storage units of the computer device. The memory is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0124] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A power supply testing circuit, comprising a current and voltage sampling circuit, a main control chip, a sampling calibration circuit, and a drive control circuit, wherein the current and voltage sampling circuit is connected to the main control chip and is used to send first sampling information to the main control chip; characterized in that, The main control chip generates a first measurement result based on the first sampling information, generates a DAC control code based on the first measurement result and the target set value, and sends the DAC control code to the sampling calibration circuit. The sampling calibration circuit includes a reference voltage circuit, a DAC calibration circuit, and an amplification control circuit, wherein: The reference voltage circuit is connected to the DAC calibration circuit and is used to provide a reference voltage to the DAC calibration circuit. The DAC calibration circuit is connected to the main control chip and is used to output an analog reference voltage that is proportional to the DAC control code under the constraint of the reference voltage. The amplification control circuit is used to generate a reference voltage control signal based on the received analog reference voltage, and send the reference voltage control signal to the drive control circuit so that the drive control circuit controls the output power; The current and voltage sampling circuit acquires the second sampling information and sends it to the main control chip, so that the main control chip generates a second measurement result based on the second sampling information; When the main control chip determines that the second measurement result matches the theoretical reference value, it uploads the information to the host computer. The theoretical reference value is calculated and generated by the main control chip based on the DAC control code and the reference voltage.

2. The power supply test circuit according to claim 1, characterized in that, The DAC calibration circuit includes a DAC processing chip and a capacitor C116. The DAC processing chip is connected to the main control chip U104, the reference voltage circuit, and the amplification control circuit. The capacitor C116 is connected to the second pin of the DAC processing chip.

3. The power supply test circuit according to claim 2, characterized in that, The reference voltage circuit includes a reference voltage source chip, capacitors C113, C114, and C115. The sixth pin of the reference voltage source chip is connected to the third pin of the DAC processing chip. One end of capacitors C113, C114, and C115 is connected to the second, fifth, and sixth pins of the reference voltage source chip, respectively. The other ends of capacitors C113, C114, and C115 are all grounded.

4. The power supply test circuit according to claim 3, characterized in that, The amplification control circuit includes an amplification control chip, the ninth pin of which is connected to the first pin of the DAC processing chip, and the first and third pins of the amplification control chip are connected to the drive control circuit.

5. The power supply test circuit according to claim 1, characterized in that, The current and voltage sampling circuit includes a power supply circuit, a first sampling resistor, a second sampling resistor, and a sampling chip. The power input terminal of the power supply access circuit is connected to the power supply under test. The two ends of the first sampling resistor and the second sampling resistor are respectively connected to the positive sampling point and the negative sampling point. The positive sampling point is also connected to the power supply access circuit. The positive sampling point and the negative sampling point are respectively connected to the sampling chip, so that the sampling chip sends the sampling information to the main control chip.

6. The power supply test circuit according to claim 5, characterized in that, The power input circuit includes a relay, a MOSFET driver circuit, a first shunt resistor, and a second shunt resistor. The fourth pin of the relay is connected to the power input terminal. The MOSFET driver circuit is connected to the relay. Both the first shunt resistor and the second shunt resistor are connected to the MOSFET driver circuit.

7. The power supply test circuit according to claim 6, characterized in that, The MOS transistor driving circuit includes a first MOS transistor and a second MOS transistor. The drains of both the first MOS transistor and the second MOS transistor are connected to the fifth pin of the relay. The source of the first MOS transistor is connected to the first shunt resistor, and the source of the second MOS transistor is connected to the second shunt resistor. Both the first shunt resistor and the second shunt resistor are connected to the tenth pin of the sampling chip.

8. A power supply testing method, characterized in that, The test method, applied to the power supply test circuit as described in any one of claims 1-7, comprises: Step S100: The current and voltage sampling circuit sends the acquired first sampling information to the main control chip. The main control chip generates a first measurement result based on the first sampling information and generates a DAC control code based on the first measurement result and the target set value. Step S200: The DAC calibration circuit receives the DAC control code and outputs an analog reference voltage proportional to the DAC control code under the constraint of the reference voltage; Step S300: The amplification control circuit generates a reference voltage control signal based on the received analog reference voltage and sends it to the drive control circuit; Step S400: The current and voltage sampling circuit sends the acquired second sampling information to the main control chip, and the main control chip generates a second measurement result based on the second sampling information; Step S500: When the main control chip determines that the second measurement result matches the theoretical reference value, it uploads the information to the host computer.

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