A method and system for optimizing anti-interference data of communication arrays

Abstract

This application relates to the field of communication array anti-interference technology, and discloses a communication array anti-interference data optimization method and system, including real-time monitoring of the resource occupancy rate of at least one digital signal processing task in the communication array, as well as the real-time performance of the communication link; determining whether the digital signal processing task is in a low-performance state based on the resource occupancy rate and real-time performance; when it is determined that at least one digital signal processing task is in a low-performance state, dynamically lowering the execution priority of the digital signal processing task, and reallocating computing resources based on the principle of prioritizing the execution of key processing tasks related to correcting internal nonlinear errors of the system and / or ensuring the transmission of desired signals, thereby prioritizing the execution of key tasks and avoiding system overload and performance degradation caused by invalid computation.

Description

Technical Field

[0001] This application relates to the field of communication array anti-interference technology, and more specifically, to a communication array anti-interference data optimization method and system. Background Technology

[0002] In modern communications, communication array systems play a crucial role in complex and ever-changing electromagnetic environments, improving signal reception quality and interference resistance through multi-antenna collaborative operation. However, in practical deployments, these systems often face challenges from various interference sources, leading to a deterioration in received signal quality and consequently affecting data transmission reliability. Traditional interference suppression methods typically rely on adjusting preset fixed parameters, making them ineffective against rapidly changing or statistically unstable interference. Furthermore, as array size increases and data processing demands rise, traditional methods often suffer from low computational efficiency when processing large-scale spatial spectrum data, failing to meet the requirements of real-time communication. Especially in long-term deployments and harsh environmental conditions, the physical degradation of internal system components, such as the performance drift of analog-to-digital converters (ADCs), further exacerbates these problems, introducing imperceptible errors into the signal processing chain from the source, severely impacting the effectiveness of interference suppression strategies.

[0003] In long-term deployments of communication arrays and when analog-to-digital converters exhibit nonlinear reference voltage drift, existing automated calibration programs, due to their linear correction models, cannot accurately identify and correct such nonlinear errors. Instead, they solidify erroneous calibration coefficients, leading to continuous misjudgments and ineffective suppression of low-power intermittent interference close to the main signal direction. This results in overload and frequency reduction of the digital signal processing chip, ultimately causing a severe deterioration in the real-time performance of large-scale spatial spectrum data processing and occasional data loss. This ineffective computational burden, when processing large-scale spatial spectrum data, causes the load on the digital signal processing chip to continuously increase, pushing the heatsink temperature beyond its design range. To protect the chip from overheating, the internal temperature monitoring mechanism of the processing unit triggers frequency reduction protection, i.e., reducing the chip's operating frequency. This frequency reduction mechanism directly leads to a severe deterioration in the real-time performance of data processing, preventing the system from completing the processing of received data within the specified time and potentially causing occasional packet loss of critical data in the processing link, further deteriorating communication quality and system stability. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides a communication array anti-interference data optimization method and system. It aims to solve the problems of low efficiency of traditional anti-interference methods in complex electromagnetic environments when facing rapidly changing or statistically unstable interference, and the introduction of errors into the signal processing chain due to the degradation of internal system components during long-term deployment, which in turn causes digital signal processing chip overload and frequency reduction, ultimately resulting in a serious decrease in the real-time performance of large-scale spatial spectrum data processing and occasional data loss.

[0005] In a first aspect, this application provides a method for optimizing anti-interference data of a communication array, including:

[0006] Real-time monitoring of the resource utilization of at least one digital signal processing task in the communication array, as well as the real-time performance of the communication link;

[0007] Based on resource utilization and real-time performance, determine whether the digital signal processing task is in a state of low efficiency;

[0008] When at least one digital signal processing task is determined to be in a state of low performance, the execution priority of the digital signal processing task is dynamically reduced, and computing resources are reallocated based on the principle of prioritizing the execution of critical processing tasks related to correcting internal nonlinear errors of the system and / or ensuring the transmission of desired signals.

[0009] This application can dynamically identify and optimize low-performance digital signal processing tasks in communication arrays. By adjusting priorities and reallocating resources, it effectively solves the limitations of traditional anti-interference methods in complex and ever-changing environments, improves the system's adaptability and processing efficiency when facing interference, and especially when there are internal nonlinear errors in the system, it can prioritize the execution of critical tasks, thereby avoiding system overload and performance degradation caused by invalid calculations.

[0010] Furthermore, this application proposes that the digital signal processing task includes at least calculating the signal covariance matrix, performing spatial spectrum estimation to determine the direction of interference, and calculating the beamforming weight vector.

[0011] Furthermore, this application also proposes that the real-time performance of the communication link includes at least the instantaneous error rate of data transmission and the actual suppression depth of specific interference signals.

[0012] Furthermore, this application proposes a step for determining whether a digital signal processing task is in a state of low performance based on resource utilization and real-time performance, including:

[0013] When the resource utilization rate of the digital signal processing task is higher than the first preset threshold and the improvement of the real-time performance of the communication link is lower than the second preset threshold, the digital signal processing task is judged to be in a state of low efficiency.

[0014] When the resource utilization rate of the digital signal processing task is lower than or equal to the first preset threshold or the improvement of the real-time performance of the communication link is higher than or equal to the second preset threshold, if the digital signal processing task frequently updates the interference source and the signal strength of the interference source is consistently higher than the preset communication quality threshold, the digital signal processing task is judged to be in a state of low efficiency.

[0015] Furthermore, this application also proposes that the steps for reallocating computing resources include:

[0016] By using a scheduler or hardware scheduling logic, the time slice allocation or computing core usage of digital signal processing tasks that are judged to be in a low-performance state in the processor is reduced, and the freed computing resources are reallocated.

[0017] Furthermore, this application also proposes that the released computing resources include processor computing power and memory bandwidth.

[0018] Furthermore, this application also proposes that the key processing tasks related to correcting internal nonlinear errors of the system include at least the task of analyzing the internal diagnostic data of the analog-to-digital converter, and / or the task of determining the consistency of the received signal with multiple dimensions.

[0019] Furthermore, this application also proposes that the execution process for analyzing the internal diagnostic data of the analog-to-digital converter includes:

[0020] Read the internal diagnostic registers of the analog-to-digital converter to obtain real-time operating status data;

[0021] Input real-time operating status data into a preset error model to estimate the nonlinear drift characteristics of the analog-to-digital converter.

[0022] Furthermore, this application also proposes that the execution process of the task of determining the consistency of multi-dimensional features of the received signal includes:

[0023] Calculate the relative time delay difference between the received signal and multiple antenna channels in the communication array;

[0024] If the relative time delay difference is an integer multiple of the system sampling clock period of the communication array, or is consistent with the pre-stored inherent processing delay data, then the received signal is determined to be false interference.

[0025] Secondly, this application provides a communication array anti-interference data optimization system, the system comprising:

[0026] The task monitoring module is used to monitor the resource utilization of at least one digital signal processing task in the communication array in real time, as well as the real-time performance of the communication link.

[0027] The status judgment module is used to determine whether the digital signal processing task is in a low-performance state based on resource utilization and real-time performance.

[0028] The resource adjustment module is used to dynamically reduce the execution priority of digital signal processing tasks when it is determined that at least one digital signal processing task is in a low-performance state, and reallocate computing resources based on the principle of prioritizing the execution of key processing tasks related to correcting internal nonlinear errors of the system and / or ensuring the transmission of desired signals.

[0029] In summary, this application provides a communication array anti-interference data optimization method and system. The method dynamically determines whether a digital signal processing task is in a low-performance state by real-time monitoring of the resource utilization rate of the digital signal processing task and the real-time performance of the communication link. When a low-performance task is identified, its execution priority is dynamically lowered, and computational resources are reallocated based on the principle of prioritizing the execution of key processing tasks related to correcting internal nonlinear errors and / or ensuring the transmission of desired signals. This application avoids unnecessary computational burdens through intelligent task priority adjustment and computational resource reallocation, thereby preventing the digital signal processing chip from triggering frequency reduction protection due to overload, effectively ensuring the real-time performance of data processing and system stability. Especially in the case of nonlinear reference voltage drift in the analog-to-digital converter, this application can prioritize the execution of key processing tasks related to correcting internal nonlinear errors, thus solving the error problem at its source. This avoids the drawback of traditional linear correction models failing to accurately identify and correct such nonlinear errors, significantly improving the anti-interference capability and data transmission reliability of the communication array in complex electromagnetic environments. This application can effectively overcome the problems of digital signal processing chip overload, frequency reduction and data loss caused by ineffective suppression in the prior art, and achieve a significant improvement in the anti-interference performance of the communication array. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating a communication array anti-interference data optimization method provided in an embodiment of this application.

[0031] Figure 2 This is a schematic diagram of the structure of a communication array anti-interference data optimization system provided in an embodiment of this application.

[0032] Labeling Explanation: 210, Task Monitoring Module; 220, Status Judgment Module; 230, Resource Adjustment Module. Detailed Implementation

[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] In modern communications, communication array systems play a crucial role in complex and ever-changing electromagnetic environments, improving signal reception quality and anti-interference capabilities through multi-antenna collaborative operation. However, in practical deployments, these systems often face challenges from various interference sources, leading to a deterioration in received signal quality and consequently affecting data transmission reliability. Traditional anti-interference methods typically rely on adjusting preset fixed parameters, making them ineffective against rapidly changing or statistically unstable interference. Furthermore, as array size increases and data processing demands rise, traditional methods often suffer from low computational efficiency when processing large-scale spatial spectrum data, failing to meet the requirements of real-time communication. Especially in long-term deployments and harsh environmental conditions, the physical degradation of internal system components, such as performance drift of analog-to-digital converters (ADCs), further exacerbates these problems, introducing imperceptible errors into the signal processing chain from the source, severely impacting the effectiveness of anti-interference strategies.

[0036] Firstly, please see Figure 1 This application proposes a method for optimizing anti-interference data in communication arrays, including:

[0037] S1. Monitor the resource utilization rate of at least one digital signal processing task in the communication array in real time, as well as the real-time performance of the communication link.

[0038] S2. Based on resource utilization and real-time performance, determine whether the digital signal processing task is in a state of low efficiency;

[0039] S3. When it is determined that at least one digital signal processing task is in a low-performance state, the execution priority of the digital signal processing task is dynamically reduced, and computing resources are reallocated based on the principle of prioritizing the execution of key processing tasks related to correcting internal nonlinear errors of the system and / or ensuring the transmission of the desired signal.

[0040] This application introduces dynamic monitoring, intelligent judgment, and priority adjustment mechanisms to effectively identify and mitigate the performance degradation of digital signal processing tasks under complex electromagnetic environments and internal system degradation conditions, thereby optimizing the allocation of computing resources and improving the anti-interference performance and real-time data processing of communication arrays.

[0041] The term "communication array" as used in this application generally refers to a system composed of multiple antenna elements that work together to achieve functions such as signal reception, transmission, or beamforming. Digital signal processing tasks refer to the various computational tasks performed on the received signals within the communication array, such as signal filtering, modulation / demodulation, channel estimation, and interference suppression. Resource utilization refers to the degree to which digital signal processing tasks consume system computing resources (such as processor time, memory, and bandwidth) during execution. The real-time performance of the communication link reflects the quality and efficiency of data transmission, such as data transmission rate, bit error rate, and signal-to-noise ratio. Inefficient performance refers to a situation where, despite consuming certain resources, the digital signal processing task fails to achieve the expected performance improvement or efficiency level, and may even negatively impact the overall system performance.

[0042] In one embodiment of the anti-interference data optimization method for communication arrays, it is first necessary to monitor in real time the resource utilization rate of at least one digital signal processing task in the communication array, as well as the real-time performance of the communication link.

[0043] Specifically, resource utilization monitoring can be achieved in several ways. For example, dedicated hardware sensors or software agents can be deployed to periodically read processor core utilization, memory allocation and deallocation, and data bus throughput. This data can be aggregated and stored in a central monitoring unit for subsequent analysis. Alternatively, operating system APIs can be used to obtain information such as CPU time slice consumption and memory page table access frequency for each digital signal processing task, thereby indirectly assessing its resource utilization.

[0044] Meanwhile, monitoring the real-time performance of the communication link is also crucial. For example, performance probes can be set up at key nodes in the data transmission path to measure packet loss rate, end-to-end latency, and bit error rate in real time. These performance indicators reflect the health and interference resistance of the communication link. Alternatively, the actual performance of the communication link in the current environment can be evaluated by analyzing the signal-to-noise ratio (SNR) or signal-to-interference-noise ratio (SINR) of the received signal. This monitoring data will be continuously collected to provide a basis for subsequent performance assessments.

[0045] Furthermore, based on the monitored resource utilization and real-time performance, it is necessary to determine whether the digital signal processing task is in a state of low efficiency.

[0046] For example, a series of preset thresholds and rules can be set. When the resource utilization of a digital signal processing task consistently exceeds a preset upper limit, but the real-time performance of the communication link (e.g., bit error rate) does not improve significantly, or even deteriorates, it can be preliminarily determined that the task may be in an inefficient state. As another approach, a machine learning model can be used for this judgment. By collecting a large amount of historical data, including the resource utilization of different digital signal processing tasks, communication link performance, and corresponding system engineer judgments, a classifier can be trained. This classifier can automatically determine whether a digital signal processing task is in an inefficient state based on real-time monitoring data. This method can adapt to more complex scenarios and improve the accuracy of the judgment.

[0047] When at least one digital signal processing task is determined to be in a state of low performance, the execution priority of the digital signal processing task needs to be dynamically reduced, and computing resources should be reallocated based on the principle of prioritizing the execution of critical processing tasks related to correcting internal nonlinear errors of the system and / or ensuring the transmission of desired signals.

[0048] For example, the priority of digital signal processing tasks deemed inefficient can be dynamically adjusted through the task scheduler of the operating system or real-time operating system. Specifically, their priority can be moved from the high-priority queue to the medium-priority or low-priority queue, thereby reducing their chances of acquiring processor time slices. Simultaneously, the freed-up computing resources (such as processor power and memory bandwidth) will be reallocated to other more critical tasks. As another implementation method, this can be achieved through hardware scheduling logic. In some high-performance communication array systems, there may be dedicated hardware accelerators or programmable gate arrays (FPGAs) that integrate task scheduling and resource management functions. When a digital signal processing task is deemed inefficient, the hardware scheduling logic can directly reduce the computing units or memory access bandwidth allocated to that task and dynamically allocate these resources to critical processing tasks related to correcting internal nonlinear errors or ensuring the transmission of desired signals. This hardware-level adjustment enables faster and more precise resource management.

[0049] The communication array anti-interference data optimization method of this application can dynamically identify tasks in a low-performance state by real-time monitoring of the resource utilization of digital signal processing tasks and the real-time performance of the communication link. Once identified, the system intelligently lowers the execution priority of these tasks and allocates the freed-up computing resources to key processing tasks related to correcting internal nonlinear errors or ensuring the transmission of desired signals. This mechanism effectively avoids the waste of ineffective computing resources and ensures the stable operation of core functions. Especially in complex scenarios such as nonlinear drift in analog-to-digital converters (ADCs), it can effectively prevent digital signal processing chips from overloading and reducing their frequency, thereby significantly improving the real-time performance of large-scale spatial spectrum data processing and the reliability of data transmission.

[0050] Compared to traditional anti-interference methods that rely on preset fixed parameters or linear correction models, the solution presented in this application has significant advantages. Traditional methods often fail to effectively cope with rapidly changing or statistically unstable interference, as well as internal nonlinear errors, and may even exacerbate problems due to incorrect calibration. This application, by introducing dynamic monitoring and intelligent judgment mechanisms, can perceive changes in system status and environment in real time and adjust resource allocation strategies accordingly, thereby avoiding unnecessary computational burden. For example, in the case of nonlinear drift in the analog-to-digital converter (ADC), this application can prioritize critical tasks related to nonlinear error correction, ensuring that the signal processing chain is optimized from the source, avoiding beamforming misjudgments and ineffective suppression caused by the inability to identify nonlinear errors in traditional methods. Furthermore, by dynamically reducing the priority of inefficient tasks and reallocating computational resources, this application effectively solves the problems of digital signal processing chip overload, frequency reduction, and occasional data loss, significantly improving the anti-interference performance of the communication array and the real-time performance of data processing, providing strong technical support for reliable communication in complex electromagnetic environments.

[0051] Specifically, in the above-mentioned communication array anti-interference data optimization method, the digital signal processing task can include a variety of specific operations to achieve effective suppression of interference and optimization of communication performance.

[0052] In the above-mentioned communication array anti-interference data optimization method, the digital signal processing tasks include at least calculating the signal covariance matrix, performing spatial spectrum estimation to determine the direction of interference, and calculating the beamforming weight vector.

[0053] Specifically, calculating the signal covariance matrix involves constructing a matrix reflecting the signal correlation between different antenna elements through statistical analysis of signal samples received by the communication array. This matrix contains spatial information and interference characteristics of the signal source and forms the basis for subsequent spatial processing. Its purpose is to provide necessary data support for interference suppression and desired signal extraction.

[0054] In this context, spatial spectrum estimation to determine the direction of interference can be understood as using the calculated signal covariance matrix and spatial spectrum estimation algorithms such as MUSIC (Multiple Signal Classification) or ESPRIT (Rotation Invariant Technique for Estimating Signal Parameters) to identify and locate the direction of interference sources in the communication environment. The aim is to accurately grasp the spatial distribution of interference, providing a basis for targeted interference suppression.

[0055] This application's solution, by clearly defining the specific content of digital signal processing tasks, enables a more refined assessment of the operational status of these core tasks when monitoring resource utilization and communication link performance in real time. When these critical digital signal processing tasks, such as calculating the signal covariance matrix, performing spatial spectrum estimation, and calculating beamforming weight vectors, are determined to be in a low-performance state, their execution priority is dynamically reduced and computing resources are reallocated. This ensures that the system prioritizes the allocation of limited computing resources to more urgent or critical tasks. For example, if the spatial spectrum estimation task cannot update the interference direction in time due to insufficient resources, it may cause the beamforming weight vector to become invalid, thus failing to effectively suppress interference. By adjusting the priority of these specific tasks, ineffective consumption of computing resources can be avoided, and resources can be transferred to critical processing tasks that can more effectively improve the overall anti-interference capability of the system, thereby optimizing the overall performance of the communication array.

[0056] In some embodiments described above, the resource utilization rate of at least one digital signal processing task in the communication array and the real-time performance of the communication link are monitored in real time, and the performance of the digital signal processing task is determined based on this information. However, in practical applications, the method of measuring the real-time performance of the communication link directly affects the accuracy and comprehensiveness of the judgment on the low performance of the task. If the performance indicators of the communication link are not properly selected or are not comprehensive enough, it may lead to misjudgment of task performance, thereby affecting the subsequent resource optimization effect.

[0057] In this regard, this application further proposes that the real-time performance of the aforementioned communication link should include at least the instantaneous error rate of data transmission and the actual suppression depth of specific interference signals.

[0058] The instantaneous error rate (IRR) of data transmission refers to the proportion of data packets or bit streams transmitted in a communication link within a specific time window. This metric directly reflects the reliability and data integrity of the communication link; a higher IRR usually indicates poorer communication quality and may indicate severe interference or channel fading. In practical applications, the IRR can be calculated in real time by monitoring the number of data checksum failures, retransmission requests, or bit error rate (BER) at the receiving end.

[0059] Furthermore, the actual suppression depth for a specific interference signal refers to the communication array's ability to attenuate the power of that interference signal in the presence of a specific interference source. This metric quantifies the actual effectiveness of the anti-interference algorithm and reflects the system's ability to maintain communication performance in complex electromagnetic environments. The actual suppression depth can be obtained by comparing the strength of the interference signal before entering the communication array with its residual strength after array processing, for example, by measuring the improvement in the signal-to-noise ratio (SNR) or the interference rejection ratio (INR) of the interference signal.

[0060] This application's solution introduces the instantaneous error rate of data transmission and the actual suppression depth of specific interference signals as metrics for the real-time performance of the communication link, enabling a more comprehensive and detailed assessment of the actual operating status of the communication link. When the resource utilization of a digital signal processing task is high, but the instantaneous error rate of the communication link remains high or the suppression depth of specific interference signals is insufficient, this indicates that even with a large investment of computing resources, the task has failed to effectively improve communication quality or combat interference. Therefore, it can be accurately determined that the digital signal processing task may be in a state of low efficiency, providing a reliable basis for subsequent priority adjustments and reallocation of computing resources.

[0061] Specifically, the steps mentioned above for determining whether a digital signal processing task is in a state of low efficiency based on resource utilization and real-time performance can be performed in the following ways.

[0062] When the resource utilization rate of the digital signal processing task is higher than the first preset threshold and the improvement of the real-time performance of the communication link is lower than the second preset threshold, the digital signal processing task is judged to be in a state of low efficiency.

[0063] When the resource utilization rate of the digital signal processing task is lower than or equal to the first preset threshold or the improvement of the real-time performance of the communication link is higher than or equal to the second preset threshold, if the digital signal processing task frequently updates the interference source and the signal strength of the interference source is consistently higher than the preset communication quality threshold, the digital signal processing task is judged to be in a state of low efficiency.

[0064] The first and second preset thresholds are configurable system parameters, whose values ​​can be dynamically adjusted or preset based on the specific communication environment, system design requirements, and historical operating data. Resource utilization can specifically refer to indicators such as processor (CPU) utilization, memory usage, and I / O bandwidth usage. The degree of improvement in the real-time performance of the communication link refers to the change in key performance indicators of the communication link (such as the instantaneous error rate of data transmission, signal-to-noise ratio, bit error rate, or actual suppression depth of specific interference signals) before and after the execution of the digital signal processing task. When a task consumes a large amount of resources but does not significantly improve communication performance, it is considered to be in a state of low efficiency. In addition, even if the resource utilization of the task is not high or the performance appears to be improved, if it continuously processes frequently changing interference sources and the interference signal strength is always higher than the preset communication quality threshold, it indicates that the task may be trapped in ineffective loop processing or unable to effectively cope with the current complex interference environment, and should also be judged as inefficient.

[0065] This application's solution, by introducing multi-dimensional, hierarchical judgment logic, can more accurately identify the inefficient state of digital signal processing tasks. The first judgment criterion focuses on a direct comparison between resource input and performance output; when a task invests a large amount of computing resources but fails to bring the expected improvement in communication performance, it is considered inefficient. The second judgment criterion targets more subtle inefficiencies, where the task may not excessively consume resources, and may even show some improvement in local performance, but due to the dynamic and complex nature of the interference environment, the task's continued processing fails to fundamentally solve the communication quality problem and may instead consume unnecessary computation cycles due to frequent updates. Through the combination of these two mechanisms, the system can comprehensively evaluate the actual contribution of digital signal processing tasks, avoiding misjudgments caused by the one-sidedness of a single indicator.

[0066] In some of the embodiments described above in this application, a scheme is proposed to dynamically reduce the execution priority of digital signal processing tasks and reallocate computing resources. However, in its implementation, the lack of a specific scheduling mechanism may lead to insufficiently fine-grained resource allocation or the introduction of additional system overhead during dynamic adjustment, thereby affecting the overall real-time performance and efficiency.

[0067] In response, this application further proposes steps for reallocating computing resources, including:

[0068] By using a scheduler or hardware scheduling logic, the time slice allocation or computing core usage of digital signal processing tasks that are judged to be in a low-performance state in the processor is reduced, and the freed computing resources are reallocated.

[0069] Specifically, a "scheduler or hardware scheduling logic" refers to a software module or dedicated hardware circuit responsible for managing and allocating system computing resources. The scheduler is typically part of the operating system kernel, responsible for allocating processor time slices among multiple tasks; hardware scheduling logic can be circuitry integrated into the processor or dedicated accelerator, used for lower-level and faster management of computing core usage. Its purpose is to provide a controllable and efficient mechanism to dynamically adjust the execution priority of digital signal processing tasks and reallocate computing resources. "Reducing the time slice allocation or computing core usage of digital signal processing tasks judged to be inefficient" can be understood as follows: when a digital signal processing task is identified as inefficient, the scheduler reduces the time share of that task running on the processor, or the hardware scheduling logic reduces its exclusive or shared time on specific computing cores. The aim is to limit the consumption of valuable computing resources by inefficient tasks, thereby freeing up resources for more critical tasks. In practical applications, "reallocating freed computing resources" specifically refers to allocating processor time, computing cores, or other related computing power saved by reducing the time slice allocation or core usage of inefficient tasks to other high-priority or more important tasks, according to a preset strategy (e.g., prioritizing critical processing tasks related to correcting internal nonlinear errors and / or ensuring the transmission of desired signals). The aim is to ensure optimal overall system performance, especially in resource-constrained or interference-prone environments.

[0070] This application's solution provides a concrete and controllable mechanism for dynamically reducing the execution priority of digital signal processing tasks and reallocating computing resources by introducing a scheduler or hardware scheduling logic. When a digital signal processing task is judged to be inefficient, the scheduler or hardware scheduling logic can precisely intervene, directly limiting its consumption of system resources by reducing the task's time slice allocation or computational core usage. It is precisely this refined resource management capability that enables the system to effectively reclaim computing resources occupied by inefficient tasks and reallocate these resources to more critical processing tasks according to preset priority principles, thereby avoiding resource waste and system performance degradation that might result from a lack of a specific scheduling mechanism.

[0071] Specifically, during the process of dynamically lowering the execution priority of digital signal processing tasks and reallocating computing resources, the released computing resources can be explicitly defined.

[0072] The aforementioned released computing resources include processor computing power and memory bandwidth. Processor computing power refers to the processing capability provided by computing units such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), or Dedicated Digital Signal Processors (DSPs), typically measured in floating-point operations per second (FLOPS) or instruction cycles. Memory bandwidth refers to the rate at which data is transferred between the processor and memory, determining the efficiency and speed of data access. In digital signal processing tasks within communication arrays, large amounts of data require rapid access and processing; therefore, memory bandwidth is one of the key factors affecting system performance.

[0073] This application's solution explicitly defines the released computing resources as processor computing power and memory bandwidth, enabling the resource scheduler or hardware scheduling logic to more accurately identify and manage available computing and data transfer capabilities when reallocating resources. When a digital signal processing task is determined to be inefficient and demoted in priority, its previously occupied processor time slices, computing cores, and memory access permissions are partially or completely released. This released processor computing power and memory bandwidth can then be reallocated to critical processing tasks related to correcting internal nonlinear errors and / or ensuring the transmission of desired signals, thereby ensuring that the system can prioritize the execution of its most essential functions even in complex interference environments.

[0074] In some embodiments of this application, key processing tasks related to correcting internal nonlinear errors of the system include at least the task of analyzing the internal diagnostic data of the analog-to-digital converter and / or the task of determining the consistency of the received signal with multiple dimensions.

[0075] The task of analyzing the internal diagnostic data of the analog-to-digital converter (ADC) involves reading internal diagnostic information such as its operating status, temperature, and power supply voltage to assess performance drift or potential faults, thereby identifying and quantifying the nonlinear errors introduced by the ADC. The aim is to ensure that the ADC can stably and accurately convert analog signals into digital signals in complex electromagnetic environments, avoiding distortion in subsequent digital signal processing due to its internal errors.

[0076] Furthermore, the task of determining the consistency of received signals across multiple dimensions involves analyzing the characteristics of the received signal in different dimensions (e.g., time, frequency, space, etc.) and comparing them with expected or known signal characteristics to determine the authenticity of the signal or whether any anomalies exist. For example, the consistency of signal arrival time, phase, amplitude, and other characteristics can be checked across different antenna channels to identify abnormal signals caused by internal nonlinear effects or spurious interference. The aim is to distinguish the true desired signal from spurious signals or interference generated by internal nonlinear effects, ensuring the accurate transmission of the desired signal.

[0077] This application's solution defines the tasks of analyzing the internal diagnostic data of the analog-to-digital converter (ADC) and / or determining the multi-dimensional characteristic consistency of the received signal as key processing tasks related to correcting internal nonlinear errors in the system. This ensures that these tasks are prioritized during the reallocation of computing resources. When digital signal processing tasks in the communication array are inefficient due to resource constraints, the system dynamically lowers their execution priority and allocates the freed-up computing resources to these key tasks. By analyzing the ADC's internal diagnostic data, potential nonlinear drift can be detected and corrected in a timely manner, thereby reducing the generation of internal nonlinear errors in the system at the source. Simultaneously, by determining the multi-dimensional characteristic consistency of the received signal, abnormal signals caused by internal nonlinear effects or spurious interference can be effectively identified and eliminated, ensuring the accuracy of subsequent signal processing. This priority setting and resource allocation mechanism ensures that the system can effectively maintain its internal stability and signal processing accuracy even under resource constraints, thereby improving overall anti-interference performance.

[0078] In some of the embodiments described above in this application, key processing tasks related to correcting internal nonlinear errors of the system are proposed, among which the task of analyzing the internal diagnostic data of the analog-to-digital converter is an important aspect. Specifically, the execution process of the task of analyzing the internal diagnostic data of the analog-to-digital converter can be further refined into the following steps.

[0079] The process of analyzing the internal diagnostic data of an analog-to-digital converter includes:

[0080] Read the internal diagnostic registers of the analog-to-digital converter to obtain real-time operating status data;

[0081] Input real-time operating status data into a preset error model to estimate the nonlinear drift characteristics of the analog-to-digital converter.

[0082] Specifically, the analog-to-digital converter (ADC) is a key component in a communication array that converts analog signals into digital signals, and its performance directly affects the accuracy of subsequent digital signal processing. Internal diagnostic registers are typically integrated within the ADC to store various real-time operating status parameters during operation, such as temperature, supply voltage, clock frequency deviation, and internal reference voltage drift. By reading these registers, real-time operating status data reflecting the ADC's current health and performance can be obtained. This real-time operating status data can be understood as a series of quantitative indicators reflecting the ADC's internal physical or electrical state.

[0083] Furthermore, the pre-defined error model can be a mathematical function model, a lookup table, or a model trained based on machine learning. This model is designed to describe the relationship between the nonlinear characteristics of the analog-to-digital converter (ADC) and its internal operating parameters. By inputting the acquired real-time operating data into this error model, the current nonlinear drift characteristics of the ADC can be calculated or predicted. Nonlinear drift characteristics refer to the degree and direction to which the input-output relationship of the ADC deviates from the ideal linear relationship under different operating conditions or over time; examples include gain error, offset error, and harmonic distortion.

[0084] The proposed solution obtains real-time operating status data by reading the internal diagnostic registers of the analog-to-digital converter (ADC) and inputs this data into a preset error model to estimate nonlinear drift characteristics. This allows for real-time and accurate monitoring of the ADC's operating status. Because the ADC's nonlinear drift can be detected and quantified promptly, the system can perform targeted compensation or calibration, effectively preventing signal distortion and error accumulation caused by ADC performance degradation. This proactive diagnostic and estimation mechanism ensures that subsequent digital signal processing tasks can be performed based on higher-quality data, thereby improving the data processing accuracy and anti-interference capability of the entire communication array in complex interference environments.

[0085] Specifically, the execution process of the above-mentioned task of determining the consistency of received signals through multi-dimensional features includes:

[0086] Calculate the relative time delay difference between the received signal and multiple antenna channels in the communication array;

[0087] If the relative time delay difference is an integer multiple of the system sampling clock period of the communication array, or is consistent with the pre-stored inherent processing delay data, then the received signal is determined to be false interference.

[0088] Calculating the relative time delay difference between the received signal and multiple antenna channels in the communication array can be understood as performing time synchronization analysis on the signals received by different antenna channels. This can be achieved by using cross-correlation functions, generalized cross-correlation functions (GCC), or other time delay estimation algorithms to determine the time differences in signal arrival at each channel. The purpose is to identify any abnormal time delay patterns during signal propagation in space or transmission within the system. This helps distinguish between genuine external signals and internally generated or specific types of spurious signals.

[0089] Furthermore, if the calculated relative delay difference is an integer multiple of the system sampling clock period of the communication array, or is consistent with the pre-stored inherent processing delay data, the received signal is determined to be spurious interference. Specifically, an integer multiple of the system sampling clock period may indicate that the signal is caused by internal clock synchronization errors or digital processing artifacts, rather than a genuine external interference source. Consistency with the pre-stored inherent processing delay data means that the signal's delay characteristics match the known, normal internal signal transmission path or the delay characteristics of a specific calibration signal in the system design, and therefore should not be considered an external threat requiring anti-interference processing. In this way, signals generated internally or with specific known characteristics can be avoided from being misjudged as external interference, thereby improving the accuracy of interference identification.

[0090] The proposed solution effectively identifies and distinguishes between real external interference and spurious interference by performing multi-dimensional feature consistency determination on the received signal. Specifically, by calculating the relative time delay difference between different antenna channels in the communication array and comparing it with the system sampling clock cycle or pre-stored inherent processing delay data, the source characteristics of the signal can be revealed. When the signal's time delay characteristics match the system's internal clock or a known internal path, it indicates that the signal is not from a real external interference source, but rather an artifact or specific calibration signal generated within the system. Therefore, the system can avoid wasting limited computing resources on processing these spurious interferences, thus allocating resources more effectively to critical processing tasks related to correcting internal nonlinear errors and / or ensuring the transmission of desired signals, thereby optimizing the anti-interference capability of the communication array.

[0091] Through the above technical solution, this application can accurately identify false interference, avoiding the erroneous allocation of system resources to suppressing non-real interference. This not only improves the response efficiency and processing capability of the communication array to real external interference, but also optimizes the allocation of computing resources, enabling critical processing tasks, such as correcting internal nonlinear errors or ensuring the transmission of desired signals, to receive more sufficient computational support. Ultimately, this solution significantly improves the overall anti-interference performance of the communication array and the stability of system operation, reduces the false alarm rate, and ensures the reliability of communication in complex electromagnetic environments.

[0092] Secondly, see Figure 2 The specific embodiments of this application also disclose a communication array anti-interference data optimization system, the system comprising:

[0093] The task monitoring module 210 is used to monitor the resource utilization rate of at least one digital signal processing task in the communication array and the real-time performance of the communication link in real time.

[0094] The status judgment module 220 is used to determine whether the digital signal processing task is in a low-performance state based on the resource utilization rate and real-time performance.

[0095] The resource adjustment module 230 is used to dynamically reduce the execution priority of digital signal processing tasks when it is determined that at least one digital signal processing task is in a low-performance state, and reallocate computing resources based on the principle of prioritizing the execution of key processing tasks related to correcting internal nonlinear errors of the system and / or ensuring the transmission of desired signals.

[0096] This system, through its modular design, enables intelligent management and optimization of digital signal processing tasks within the communication array. The task monitoring module 210 continuously collects key system operation data, providing a basis for subsequent decision-making. Based on this data, the status judgment module 220 accurately identifies tasks that fail to effectively utilize resources or contribute insufficiently to system performance. Once an inefficient task is identified, the resource adjustment module 230 intervenes, dynamically adjusting task priorities and reallocating computing resources to ensure the priority execution of critical tasks, especially those related to internal nonlinear error correction and expected signal transmission assurance. This effectively improves the overall anti-interference capability and data processing efficiency of the communication array.

[0097] The above embodiments have already described specific methods for real-time monitoring of resource utilization and real-time performance of communication links in digital signal processing tasks, determining whether digital signal processing tasks are in a low-performance state, and dynamically lowering the execution priority of digital signal processing tasks and reallocating computing resources, which will not be repeated here. It should be emphasized that the communication array anti-interference data optimization system of this application implements the above methods by introducing specific functional modules.

[0098] This application constructs a dynamic and adaptive optimization system by introducing a task monitoring module 210, a status judgment module 220, and a resource adjustment module 230. The task monitoring module 210 can perceive the system's operating status and communication link performance in real time and comprehensively, providing data support for intelligent decision-making. The status judgment module 220 can accurately identify inefficient digital signal processing tasks based on this real-time data, avoiding resource waste caused by misjudgment or delayed judgment in traditional methods. More importantly, the resource adjustment module 230 can dynamically reduce the execution priority of inefficient tasks and prioritize the allocation of freed computing resources to key processing tasks related to correcting internal nonlinear errors and / or ensuring the transmission of desired signals. This mechanism effectively avoids problems such as overload, frequency reduction, and occasional data loss in digital signal processing chips, especially in complex scenarios such as nonlinear drift in analog-to-digital converters, ensuring the stable operation of core functions and the real-time performance of data processing.

[0099] Through the above system design, this application realizes intelligent optimization and efficient utilization of computing resources, significantly improves the anti-interference performance of the communication array in complex electromagnetic environments and the reliability of data transmission, and overcomes the limitations of existing technologies in processing large-scale spatial spectrum data, such as low efficiency and insufficient ability to correct nonlinear errors.

[0100] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A communication array anti-jamming data optimization method, characterized in that, The system comprises: monitoring resource occupancy of at least one digital signal processing task in a communication array and real-time performance of a communication link; judging whether the digital signal processing task is in a low-efficiency state according to the resource occupancy and the real-time performance; when at least one digital signal processing task is judged to be in a low-efficiency state, dynamically adjusting execution priority of the digital signal processing task and reallocating computing resources based on the principle of prioritizing execution of key processing tasks related to correction of internal nonlinear errors of the system and guaranteeing expected signal transmission; the real-time performance of the communication link at least includes instantaneous error rate of data transmission and actual suppression depth of a specific interference signal; the key processing tasks related to correction of internal nonlinear errors of the system at least include a task of analyzing internal diagnostic data of an analog-to-digital converter and / or a task of judging multi-dimensional feature consistency of a received signal; the execution process of the task of analyzing internal diagnostic data of the analog-to-digital converter comprises: reading internal diagnostic registers of the analog-to-digital converter to obtain real-time working state data; inputting the real-time working state data into a preset error model to estimate nonlinear drift characteristics of the analog-to-digital converter; the execution process of the task of judging multi-dimensional feature consistency of the received signal comprises: calculating relative time delay difference between the received signal and multiple antenna channels in the communication array; if the relative time delay difference is an integer multiple of a system sampling clock period of the communication array or consistent with pre-stored inherent processing delay data, it is judged that the received signal is a false interference.

2. The communication array anti-jamming data optimization method of claim 1, wherein, the digital signal processing task at least includes calculating a signal covariance matrix, performing spatial spectrum estimation to judge an interference direction, and calculating a beamforming weight vector.

3. The communication array anti-jamming data optimization method of claim 1, wherein, the step of judging whether the digital signal processing task is in a low-efficiency state according to the resource occupancy and the real-time performance comprises: when resource occupancy of the digital signal processing task is higher than a first preset threshold and improvement degree of the real-time performance of the communication link is lower than a second preset threshold, it is judged that the digital signal processing task is in a low-efficiency state; when resource occupancy of the digital signal processing task is lower than or equal to the first preset threshold or improvement degree of the real-time performance of the communication link is higher than or equal to the second preset threshold, if the digital signal processing task frequently updates an interference source and signal strength of the interference source continuously is higher than a preset communication quality threshold, it is judged that the digital signal processing task is in a low-efficiency state.

4. The communication array anti-jamming data optimization method of claim 1, wherein, the step of dynamically adjusting execution priority of the digital signal processing task and reallocating computing resources comprises: through a scheduler or hardware scheduling logic, reducing time slice allocation or computing core occupancy of the digital signal processing task judged to be in a low-efficiency state in a processor and reallocating released computing resources.

5. The communication array anti-jamming data optimization method of claim 4, wherein, the released computing resources include processor computing power and memory bandwidth.

6. A communication array anti-jamming data optimization system for performing the communication array anti-jamming data optimization method of any one of claims 1 to 5, characterized in that, the system comprises: A task monitoring module is configured to monitor resource occupancy of at least one digital signal processing task in a communication array and real-time performance of a communication link; A state judging module is configured to judge whether the digital signal processing task is in a low-efficiency state according to the resource occupancy and the real-time performance; A resource adjusting module is configured to dynamically lower execution priority of the digital signal processing task when it is determined that at least one digital signal processing task is in a low-efficiency state, and to reallocate computing resources based on a principle that priority is given to execution of key processing tasks related to correction of internal nonlinear errors of a system and guarantee of expected signal transmission; The real-time performance of the communication link at least includes instantaneous error rate of data transmission and actual suppression depth of a specific interference signal; The key processing tasks related to correction of internal nonlinear errors of a system at least include a task of analyzing internal diagnostic data of an analog-to-digital converter and / or a task of making multi-dimensional feature consistency judgment on a received signal; The execution process of the task of analyzing internal diagnostic data of an analog-to-digital converter includes: reading internal diagnostic registers of the analog-to-digital converter to obtain real-time working state data; inputting the real-time working state data into a preset error model to estimate nonlinear drift characteristics of the analog-to-digital converter; The execution process of the task of making multi-dimensional feature consistency judgment on a received signal includes: calculating relative time delay difference between the received signal and multiple antenna channels in the communication array; if the relative time delay difference is in an integer multiple relationship with a system sampling clock period of the communication array or is consistent with pre-stored inherent processing delay data, it is determined that the received signal is a false interference.

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