Quality of service (QoS) level-based service for requests of shared resources

Abstract

Systems and methods relate to managing access to shared memory. Requests received at a memory controller from one of one or more customers configured to access the shared memory for access to the shared memory are placed in at least one queue in the memory controller. A series of one or more timeout values is assigned to the request based at least in part on a priority associated with the customer generating the request. The priority may be fixed or based on a Quality of Service (QoS) level of the customer. A timer is incremented while the request is still in the first queue. A criticality level of the request is incremented as the timer traverses each of the one or more timeout values in the series. Requests with higher criticality levels may be prioritized to serve better than requests with lower criticality levels.

Description

[0001] This application is a divisional application of Chinese invention patent application 201780021153.6 (PCT / US2017 / 023185), entitled "QoS-based service for requests for shared resources," filed on March 20, 2017. Technical Field

[0002] The disclosed aspects relate to resource allocation in a processing system. More specifically, exemplary aspects relate to services that prioritize requests for shared resources (e.g., shared storage) based on quality of service (QoS) metrics. Background Technology

[0003] Some processing systems may contain shared resources (e.g., shared memory) shared among various consumers (e.g., processing elements). With technological advancements, there is a growing trend towards an increasing number of consumers or "clients" integrated into processing systems. However, this trend also increases competition and conflict for shared resources. For example, it is difficult to allocate memory bandwidth for shared memory among various consumers while simultaneously ensuring the expected Quality of Service (QoS) or other performance metrics for all consumers.

[0004] In some processing systems, a memory controller may be employed to manage the allocation of memory bandwidth to various clients. In situations where there is competition among multiple clients, the average service time for serving client requests for shared memory increases. In conventional implementations, the service time for each client may be increased equally or similarly, regardless of the concept of priority among the clients. However, in such implementations, while increased service time may be acceptable for some clients, it may be unacceptable for some high-priority clients. Accordingly, improved allocation of available memory bandwidth is needed in this field. Summary of the Invention

[0005] An exemplary aspect of the present invention relates to a system and method for managing access to shared memory. A request for access to shared memory from one of one or more clients configured to access the shared memory, received at a memory controller, is placed in at least one queue in the memory controller. A series of one or more timeout values ​​is assigned to the request, at least in part based on a priority associated with the client generating the request. The priority may be fixed or based on the client's Quality of Service (QoS) level. A timer increments while the request is still in a first queue. As the timer iterates through each of the series of one or more timeout values, the criticality level of the request increases. Requests with higher criticality levels can be prioritized and served over requests with lower criticality levels.

[0006] For example, an exemplary aspect relates to a method for managing access to shared memory. The method includes receiving, at a memory controller, a first request for access to the shared memory from a first customer configured to access the shared memory from one or more customers, and placing the first request in at least a first queue of the memory controller. A series of one or more timeout values ​​is assigned to the first request based at least in part on a priority associated with the first customer. A timer increments while the first request is still in the first queue, and the criticality level of the first request increases as the timer iterates through each of the one or more timeout values ​​in the series.

[0007] Another exemplary aspect relates to a device including a memory controller configured to receive a first request for access to shared memory from a first customer of one or more customers configured to access shared memory. The memory controller includes: at least a first queue configured to suspend the first request; and logic configured to assign a series of one or more timeout values ​​to the first request at least in part based on a priority associated with the first customer, increment a timer while the first request is still in the first queue, and increment the criticality level of the first request as the timer iterates through each of the one or more timeout values ​​in the series.

[0008] Another exemplary aspect relates to an apparatus comprising: means for queuing a first request for access to shared memory received from a first customer configured to access shared memory from one or more customers; means for assigning a series of one or more timeout values ​​to the first request at least in part based on a priority associated with the first customer; means for incrementing a time value while the first request is still in the first queue; and means for incrementing a criticality level of the first request as the time value traverses each of the series of one or more timeout values.

[0009] Another exemplary aspect relates to a non-transitory computer-readable storage medium comprising code that, when executed by a processor, causes the processor to perform operations for managing access to shared memory. The non-transitory computer-readable storage medium includes: code for receiving at a memory controller a first request for access to the shared memory from one or more clients configured to access the shared memory; code for placing the first request in a first queue at least on the memory controller; code for assigning a series of one or more timeout values ​​to the first request, at least partially based on a priority associated with the first client; code for incrementing a timer while the first request is still in the first queue; and code for incrementing a criticality level of the first request as the timer iterates through each of the one or more timeout values ​​in the series. Attached Figure Description

[0010] The accompanying drawings are provided to aid in the description of aspects of the invention, and are provided merely for illustrative purposes and not for limiting the scope of the invention.

[0011] Figure 1 A block diagram of a processor system configured according to aspects of the present invention is depicted.

[0012] Figure 2 An exemplary method for serving a request for shared memory according to an aspect of the present invention is described.

[0013] Figure 3 An exemplary computing device in which aspects of the invention can be advantageously employed is described. Detailed Implementation

[0014] Aspects of the invention are disclosed in the following description and related drawings relating to specific aspects of the invention. Alternative aspects may be devised without departing from the scope of the invention. Furthermore, well-known elements of the invention will not be described in detail or will be omitted to avoid obscuring the relevant details of the invention.

[0015] The word “exemplary” is used herein to mean “serving as an example, illustration, or description.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. Similarly, the term “aspects of the invention” does not require that all aspects of the invention encompass the features, advantages, or modes of operation discussed.

[0016] The terminology used herein is for descriptive purposes only and is not intended to limit the scope of the invention. As used herein, the singular forms “a” and “described” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] Furthermore, many aspects are described with regard to the sequence of actions performed by elements of a computing device, for example. It will be appreciated that the various actions described herein can be performed by specific circuitry (e.g., an application-specific integrated circuit (ASIC)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, the sequence of actions described herein can be considered entirely embodied in any form of computer-readable storage medium storing a corresponding set of computer instructions that, when executed, will cause the associated processor to perform the functionality described herein. Therefore, various aspects of the invention can be embodied in many different forms, and all forms are contemplated within the scope of the claimed subject matter. Furthermore, for each of the aspects described herein, a corresponding form of any such aspect may be described herein as, for example, "logic" "configured to" perform the described actions.

[0018] In this invention, a shared resource allocation technique is provided that can improve service time for some customers (e.g., high-priority customers). In cases of competition for shared resources, this improvement may also result in a degrading of service time for some other customers (e.g., lower-priority customers).

[0019] In a processing system with multiple clients, each client is assigned a priority, which can be a fixed priority or a dynamic priority that can be dynamically modified. In one aspect, the dynamic priority may be based on a proportional sharing parameter (referred to as a proportional sharing weight) associated with the client, where the proportional sharing parameter provides a measure of the proportional allocation of priority among clients in the processing system based on resources within the system. In some cases, the proportional sharing parameter may be based on the Quality of Service (QoS) class to which the client belongs, where each QoS class may represent one or more clients in the processing system.

[0020] When a request from a client is received at a shared resource manager (e.g., a memory controller for shared memory (more precisely, the front end of a memory controller that includes a queue of received read / write requests to the shared memory)), the request is assigned one or more timeout values, which can be a function of the priority associated with the client. As each of the one or more timeout values ​​is exceeded, the criticality of the request increases. Among other factors that can be considered, more critical requests are processed with higher priority and can be serviced before less critical requests. A similar concept of priority-based service can also be followed at the back end of the memory controller, where, in addition to the priority associated with the request received from the front end, the state of the shared memory can also be considered.

[0021] Now for reference Figure 1The diagram illustrates a processing system 100 configured according to exemplary aspects. The processing system 100 may include one or more processors (or more precisely, processor cores), typically shown as processors 102a-b, each processor having one or more possible tiers of cache memory, specifically illustrated, where L1 cache memory 104a-b corresponds to processor 102a-b. Processors 102a-b (in conjunction with one or more cache memories, such as L1 cache memory 104a-b) are referred to as clients. Accordingly, multiple clients can make requests to access shared memory, illustrated as memory 110, where access to memory 110 can be managed by memory controller 108. In some aspects, memory 110 may be, for example, main memory implemented using dynamic random access memory (DRAM) technology, and more precisely, may be dual data rate (DDR) memory, and in such cases, memory controller 108 may also be correspondingly referred to as a DRAM controller / scheduler or a DDR controller / scheduler, etc.

[0022] According to the various processes discussed herein, the memory controller 108 may receive and serve requests from processors 102a-b. In this regard, the memory controller 108 may include a front end indicated by reference numeral 108a and a back end indicated by reference numeral 108b. The front end 108a may include one or more queues for receiving read and write requests from various clients, such as processors 102a-b. In the illustrated figures, a combined read / write queue 112 is shown as an example, wherein read and write requests may be stored as they are received. Thus, the read / write queue 112 may be a buffer, for example, a first-in, first-out (FIFO). The queue management block 113 includes logic configured to manage the read / write queue 112 and substantially perform functions associated with assigning priorities to requests in the read / write queue 112, wherein requests for access to memory 110 may be served at least in part based on these priorities. Accordingly, in one aspect, queue management block 113 may be configured to assign priorities to requests received at memory controller 108 and placed in read / write queue 112, or to associate priorities with said requests. The assigned priorities may be based at least in part on the client that generated the request, wherein the priorities may be pre-specified fixed priorities for the client or dynamically modifiable priorities based on, for example, the QoS class to which the client belongs.

[0023] In some respects, requests ready for service can be passed from read / write queue 112 to backend 108b of memory controller 108, for example, in cases where memory controller 108 is configured with separate frontend and backend processing (remember that in some cases the frontend and backend processing functionality described above can be combined, and in those cases, a single queue may exist to hold requests until they are pulled from the queue to be permitted access to memory 110). In this regard, backend 108b may also contain several queues; for example, another combination of read / write queues, 116, is shown. Accepted requests for service from frontend 108a are passed to read / write queue 116 at backend 108b. Correspondingly, queue management block 117 is shown, which includes logic to manage service requests placed in read / write queue 116. Backend 108b may also include additional buffers, such as response blocks (not shown separately), which can be used to temporarily store read data returned from memory 110 and / or status messages relating to access to memory 110.

[0024] Of the various possible access requests to memory 110, read requests (or load requests) are considered in more detail with reference to timing-critical requests. This is because write requests (or storage requests) involve data to be written, and therefore once the data has been sent, the client may not have subsequent computations dependent on the write, and thus may not need to wait for the write operation to complete. However, in the case of read requests, once a request is made to memory controller 108 from various clients, the request is queued to be granted access to memory 110, and the corresponding data is then returned to the requesting client according to the various aspects of service discussed below. Therefore, once a read request has been issued, the requesting client waits for the result or data corresponding to the read request. The amount of time between when a read request is sent and when the data is returned from memory 110 is generally referred to as latency. While some clients (or more precisely, some requests from some clients) can tolerate long latency, some clients or specific requests from some clients may be timing-critical, and therefore long latency may be unacceptable.

[0025] In the effort to serve time-critical requests prior to non-time-critical requests, memory controller 108 may implement a priority ordering scheme at various stages of the request. An example implementation of different types of queue management at the front-end and back-end will now be discussed, when the following aspects apply to both the front-end and back-end. Thus, in one example, at the read / write queue 112 of front-end 108a, the priority ordering scheme may consider the priority associated with the client generating the request (e.g., fixed priority or a shared dynamic priority proportional to the client's QoS level). Alternatively, in one example, at the read / write queue 116 at back-end 108b, the priority ordering scheme may also consider characteristics or states associated with memory 110, such as precharge banks, open line buffers, first-ready requests, etc., which will now be explained in further detail.

[0026] Considering memory 110 in more detail, memory 110 may have multiple libraries (e.g., DRAM or DDR libraries, not specifically described), where each library comprises a memory block or array. Each read request can be serviced by accessing a particular library. For efficiency (e.g., in terms of latency, power consumption, etc.), if the library involved in the request has been precharged (e.g., to serve different requests), then it is desirable to serve the request. The priority ordering of serving requests that are ready to be served first (e.g., those involving precharged libraries) is referred to in this invention as serving the first-ready request. This can sometimes mean that requests are served out of order. Because memory 110 is shared among multiple customers, it is also possible that requests from different customers may involve the same library, and this leads to possible contention. Resolving contention can sometimes benefit the reception of later requests.

[0027] There is also the concept of row buffers associated with various libraries. In short, a row buffer holds data read from a specific row of a library before it is returned to the requesting client through various interconnects or channels. Row buffers are typically designed to be larger than the size of a cache row, allowing them to be filled with data to serve multiple cache rows before being transferred to the interconnect, which improves the efficiency of data transfers from memory 110. Therefore, if a row buffer is open, it is desirable to prioritize and serve any requests that may be able to access the row corresponding to the row buffer. Such requests relating to rows where the row buffer is open are referred to as "row hits" in this invention. In aspects of the invention, requests that will result in row hits can be assigned higher priority in the read / write queue 116 at backend 108b.

[0028] In an exemplary aspect, a criticality level can be assigned to a request in either or both of the read / write queues 112, 116, and requests can be prioritized based on criticality levels for serving / accessing memory 110, taking into account other factors such as the state of memory 110 (e.g., row hit, precharge, or first-ready library).

[0029] For example, when a first request is received at memory controller 108 (e.g., at front-end 108a) from a first customer (e.g., processors 102a-b or L1 cache 104a-b), the corresponding priority for the first customer is obtained, for example, via queue management block 113. The priority can be a fixed priority or a dynamic priority based on the first customer's Quality of Service (QoS) level, where a group of one or more customers can be classified into QoS levels depending on each customer's QoS requirements. The first request itself may have an indication of the associated priority or level of the first customer from which the priority can be derived. In some instances, queue management block 113 at front-end 108a of memory controller 108 may have a database or table (not shown) for priorities or QoS levels associated with various customers, and the priority of the first request can be obtained from such a database.

[0030] When a first request is received at memory controller 108, memory controller 108 may place the request in read / write queue 112 at front end 108a. Correspondingly, the logic of, for example, queue management block 113 may be configured to assign a series of one or more timeout values ​​to the first request in read / write queue 108, at least in part based on the priority of the first client. Queue management block 113 may also include a timer or other means for incrementing time values ​​(wherein, it should be understood that "incrementing" can be in a positive or negative direction without affecting the scope of the invention). For example, the timer may increment while the first request remains in read / write queue 108. As the timer iterates through each of the series of one or more timeout values, the criticality level of the first request may increment (wherein, the same criticality level can increment in a positive or negative direction without affecting the scope of the invention).

[0031] For example, when the first request is placed in read / write queue 112, the timer can start from a reset value of zero. The timer can increment in each clock cycle, for example, keeping the request in read / write queue 112 (e.g., without being passed to read / write queue 116 or serviced for access to memory 110). When the timer reaches a first timeout value in a series of one or more timeout values, the criticality level of the request increases, for example, to a first criticality level. In one embodiment that iterates through the series of timeout values, when the timer reaches the first timeout value, the timer can be reset and incremented again until the timer reaches a second timeout value, and so on. If the request is still held in read / write queue 112 when the timer iterates through the second timeout value, then the criticality level increases to a second criticality level, and so on. The longer a request remains in a queue, such as read / write queue 112, the more timeout values ​​are traversed and the higher the criticality level of the request.

[0032] In some cases, subsequent, later timeout values ​​can be smaller or have a shorter duration compared to earlier or prior timeout values ​​(e.g., a second timeout value can be shorter than the first timeout value). This can speed up the process of increasing the criticality of a request (remember that in some cases it's possible to immediately increase the criticality level of a request for a timeout value that will be zero). For example, a later timeout value can be exponentially smaller than the immediately preceding earlier timeout value, which can cause the criticality level to increase exponentially while the first request remains in the queue unserviced. Similarly, it's possible for later timeout values ​​in a series to be greater than earlier timeout values; in this case, the criticality level of the request can increase at a shorter rate as the timer iterates through more timeout values.

[0033] Accordingly, in some respects, queue management block 113 may be configured, for example, to prioritize requests so that if a first request has a higher level of criticality than a second request, then the first request is allowed to access memory 110 in read / write queue 112 before the second request.

[0034] As mentioned above, the series of one or more timeout values ​​used for the first request can be a function of the priority of the first customer. In the case of dynamically modifiable priorities, the priority can be at least partially based on the Quality of Service (QoS) level associated with the first customer, denoted as QoS level C. The series of one or more timeout values ​​can also depend on the occupancy of read / write queue 112, for example, and more precisely, in some cases, the number of requests from queues of the same QoS level (denoted as occupancy_c for QoS level C).

[0035] In one aspect, α cIndicates a programmable constant associated with a specific QoS level C. In some cases, α c It can also be called the "span" and can be inversely proportional to the shared parameters associated with the same level C. A series of instance timeout values ​​associated with a request can be represented as t = M * α. c *occupancy_c, where M can be a programmable scaling factor. In some cases, M can be different for each of one or more timeout values. In some cases, there may be only one timeout value, where criticality can be a binary function such that when a timeout value expires, the associated request is promoted to critical and otherwise the request remains non-critical. In some cases, the request or the QoS level of the request can be indexed into a table (not shown) in queue management block 113, for example, to determine α. c The value is used to calculate the corresponding timeout value.

[0036] The multiplier M can be a function of the expected latency in the memory controller 108, which can be based, for example, on a specific implementation or memory configuration. In one instance, after an associated timeout expires in a lightly loaded system (e.g., the memory controller 108 does not have a relatively large number of requests queued for service), the multiplier M can be selected to have α. c A priority level of 1 (where "1" represents the highest possible priority) becomes critical or has an increased criticality level. It will be observed that under this scheme, all requests will eventually become critical or reach the highest level of criticality, but timeout values ​​can be set for low-priority requests so that their criticality level is lower (or slower to be implemented) compared to requests from higher priority levels.

[0037] A similar priority sorting scheme can be implemented in the backend 108b of the memory controller 108. More specifically, the queue management block 117 can be configured to assign a series of one or more timeout values ​​to requests in the read / write request queue 116, at least in part, based on priority. A criticality level can be similarly generated by a timer configured to increment and increase the criticality level as the timer iterates through each of the one or more timeout values ​​in the series. In addition to the criticality level obtained based on one or more timeout values ​​(which can be a function of factors such as associated QoS levels, occupancy, etc.), the state of the memory 110 (e.g., precharge library, first-ready row buffer, etc.) can also be considered at the backend 108b in the read / write queue 116. While various options are possible, an example of integrating the criticality level with the state of the memory 110 for serving requests in the read / write queue 116 is discussed below.

[0038] Again, requests with higher criticality levels can be generally prioritized for service over requests with lower criticality levels. Accordingly, because requests with higher criticality levels can be served before those with lower criticality levels, the service time for requests with higher criticality levels can be improved (this could, in some cases, mean that the service time for requests with lower criticality levels can be degraded compared to an exemplary concept where some requests are not included in the priority or criticality level elevation). When considering the state of memory 110, an instance order in which requests in read / write queue 116 can be served may follow the order in which row hits (if any) are served first (where if there are row hits for two requests, one with a higher criticality level than the other, then the request with the higher criticality level of the two requests with row hits will be served first). However, in some aspects, even within a scheme where row hits are prioritized in this way, limitations can still be imposed on the number of consecutive row hits that are served; for example, requests that may not have row hits can be considered after a pre-specified number of row hits.

[0039] After a line hit, the first ready request involving the precharged library of memory 110 can be considered in an exemplary priority sorting scheme (again, by consideration of criticality level, for example, if there are two first ready requests, i.e., involving the memory library of the precharged memory 110, and one request has a higher criticality level than the other, then the first ready request with the higher criticality level will be served first).

[0040] In this manner, an exemplary aspect of the invention may include a priority ordering scheme for serving requests for shared memory based at least in part on a priority associated with a customer (the priority may be further based on proportional sharing, which is assigned to the customer based on a QoS level associated with the customer), wherein the priority ordering scheme may further take into account the characteristics or state of the shared memory, such as row hits, first-ready precharged libraries, etc.

[0041] Accordingly, it will be understood that the exemplary aspects include various methods for performing the processes, functions, and / or algorithms disclosed herein. For example, Figure 2 This describes the method for managing access to shared memory 200.

[0042] In block 202, method 200 includes receiving at a memory controller (e.g., memory controller 108) a first request for access to shared memory (e.g., memory 110) from a first client of one or more clients configured to access shared memory (e.g., processors 102a-b, L1 caches 104a-b, etc.).

[0043] In block 204, the first request may be placed in at least a first queue in the memory controller (e.g., one of read / write queues 112, 116, depending on the specific implementation of the front-end / back-end management in the memory controller 108).

[0044] In block 206, a series of one or more timeout values ​​may be assigned to the first request at least in part based on a priority associated with the first customer (e.g., queue management 113, 117 may assign one or more series of timeout values ​​based on a fixed priority or a dynamically modifiable priority, the dynamically modifiable priority being based on a proportional sharing associated with the QoS level of the first customer).

[0045] In block 208, the timer is incremented while the first request is still in the first queue (e.g., in queue management 113, 117).

[0046] In block 210, the criticality level of the first request increases as the timer iterates through each of one or more timeout values ​​in the series. Therefore, method 200 may involve priority ordering in some cases to allow the first request to access memory 110 in the first queue if it has a higher criticality level than the second request. In various cases, prioritizing requests in the first queue may be based on other factors, such as the occupancy rate of the first queue, one or more states of the shared memory, etc.

[0047] Now refer to Figure 3 The discussion can utilize example devices of exemplary aspects of the present invention. Figure 3 A block diagram of a computing device 300 is shown. The computing device 300 may correspond to... Figure 1 The illustrated implementation of the processing system 100 is configured to perform... Figure 2 Method 200. In Figure 3 In the description, computing device 300 is shown as including processor 102a, L1 cache memory 104a, memory controller 108 (shown as front-end 108a with read / write queue 112 and queue management block 113 and back-end 108b with read / write queue 116 and queue management block 117), and Figure 1 The memory 110. Various other configurations are also possible, and for clarity... Figure 3 References may have been omitted. Figure 1 Some details of the components discussed. Figure 3 In this embodiment, processor 102a is exemplarily shown as coupled to memory 110 via a single-level cache memory (L1 cache memory 104a), but it should be understood that computing device 300 may also support other memory configurations known in the art.

[0048] Figure 3 A display controller 326 coupled to the processor 102a and to the display 328 is also shown. In some cases, the computing device 300 can be used for wireless communication and Figure 3 Optional blocks are also shown in dashed lines, such as a decoder / decoder (codec) 334 (e.g., an audio and / or voice codec) coupled to processor 102a, and a speaker 336 and a microphone 338 may be coupled to codec 334; and a wireless antenna 342 coupled to wireless controller 340, which is coupled to processor 102a. With the presence of one or more of these optional blocks, in certain aspects, processor 102a, display controller 326, memory 110, and wireless controller 340 are included in an in-package system or on-chip system device 322.

[0049] Accordingly, in certain aspects, input device 330 and power supply 344 are coupled to on-chip system device 322. Furthermore, in certain aspects, such as Figure 3 As illustrated, with one or more optional blocks present, the display 328, input device 330, speaker 336, microphone 338, wireless antenna 342, and power supply 344 are external to the system-on-chip 322. However, each of the display 328, input device 330, speaker 336, microphone 338, wireless antenna 342, and power supply 344 can be coupled to components of the system-on-chip 322, such as an interface or controller.

[0050] It should be noted that although Figure 3 The device is generally depicted as a computing device, processor 102a, and memory 110, but they can also be integrated into set-top boxes, servers, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed-location data units, computers, laptop computers, tablet computers, communication devices, mobile phones, or other similar devices.

[0051] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0052] Furthermore, those skilled in the art will appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0053] The methods, sequences, and / or algorithms described in connection with the aspects disclosed herein can be embodied directly in hardware, as software modules executed by a processor, or as a combination of hardware and software modules. The software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage media known in the art. Exemplary storage media are coupled to the processor, enabling the processor to read information from and write information to the storage media. Alternatively, the storage media can be integrated into the processor.

[0054] Accordingly, aspects of the invention may include computer-readable media embodying methods for managing access to shared memory. Accordingly, the invention is not limited to the illustrated examples, and any means for performing the functionality described herein are included in aspects of the invention.

[0055] While the foregoing disclosure illustrates illustrative aspects of the invention, it should be noted that various changes and modifications may be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps, and / or actions of the method claims according to aspects of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural form is also covered unless expressly stated to be limited to the singular.

Claims

1. A method for managing access to shared memory, the method comprising: The memory controller receives a first request for access to the shared memory from a first of one or more clients configured to access the shared memory. The first request is placed in a first queue in at least the memory controller; Based on a priority associated with the first customer, a series of at least two timeout values ​​is assigned to the first request, wherein the priority associated with the first customer is a dynamically modifiable priority based at least in part on a Quality of Service (QoS) class associated with the first customer, wherein one or more other customers belong to the same QoS class as the first customer, and wherein the series of timeout values ​​is determined according to the QoS class associated with the customer, and is further based on the occupancy of the first queue, wherein the occupancy of the first queue includes the number of requests from the same QoS class as the first request. Furthermore, each of the timeout values ​​associated with the request is a function of the expected waiting time of the first request in the memory controller, a constant associated with the QoS level, and the occupancy rate of the first queue, and wherein the later timeout value in the series is one of the following: the later timeout value is less than the earlier timeout value, such that the criticality level of the first request increases at a faster rate as the timer iterates through more timeout values; or the later timeout value is greater than the earlier timeout value, such that the criticality level of the first request increases at a slower rate as the timer iterates through more timeout values. Increment the timer while the first request is still in the first queue; As the timer iterates through each of the timeout values ​​in the series, the criticality level of the first request is incremented; as well as Priority sorting is used to allow the first request to access the shared memory in the first queue if the first request has a higher level of criticality than the second request.

2. The method of claim 1, wherein the first client is a processor or a cache memory.

3. The method of claim 1, wherein the first queue is at the front end of the memory controller that interfaces with the one or more clients.

4. The method of claim 1, wherein the first queue is at the back end of the memory controller that interfaces with the shared memory.

5. A device for managing access to shared memory based on priorities related to quality of service metrics, comprising: A memory controller configured to receive a first request for access to shared memory from a first customer of one or more customers configured to access shared memory, wherein the memory controller includes: At least a first queue, which is configured to suspend the first request; and Logic, configured to implement the method according to any one of claims 1 to 4.

6. The device according to claim 5, which is integrated into a device selected from the following: a set-top box, a server, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop computer, a tablet computer, a communication device, and a mobile phone.

7. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for managing access to a shared memory according to any one of claims 1 to 4.

Images