Low-delay interface control module priority arbitration method for chip

Abstract

The invention relates to the technical field of intelligent chips, in particular to a low-delay interface control module priority arbitration method for a chip, which comprises the following steps of: receiving a plurality of access requests, associating static priorities, QoS (Quality of Service) levels and timestamps, and generating dynamic sorting counts; and the dynamic sorting count is decreased progressively through a QoS differential aging mechanism, an updated sorting count is generated, conflict arbitration is performed by using a secondary arbitration strategy, and the access type of the optimal request is determined. Grouping the access requests based on the access type of the optimal request, calculating a sorting counting difference value, and generating a quantization difference value; and constructing a load decision model, determining a corresponding dynamic switching threshold value, comparing and judging the quantization difference value through the dynamic switching threshold value, and generating a switching enable signal. And calculating an authorization signal of the optimal arbitration request through the flattened logic structure, and outputting bus authorization information. By constructing the flattening arbitration method, the balance among high throughput, low delay and high hardware efficiency is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of intelligent chip, in particular to a low-delay interface control module priority arbitration method for chip. BACKGROUND

[0002] In the technical field of intelligent chip, especially in the high-performance system-on-chip and inter-chip interconnection environment, multiple bus masters (such as CPU, DMA engine, etc.) compete for access to shared bus resources. In these high-concurrency competition scenarios, an efficient bus arbitration method is needed to handle bus master priority issues. The existing bus arbitration method enforces fairness by introducing a dynamic degradation mechanism. The specific workflow is as follows: the arbitrator first grants bus ownership to the high-priority agent. After the agent is authorized or completes the first transaction, its priority is immediately temporarily reduced. The arbitrator then temporarily reduces the priority of the authorized agent and raises the priority of the original low-priority agent to a level higher than that of the degraded agent. This means that in the next arbitration cycle, the original low-priority agent can have priority to obtain bus ownership. After the original low-priority agent completes its data transaction, the degraded agent will restore to the original state of the high-priority agent.

[0003] However, the dynamic degradation mechanism is essentially a reactive "post-punishment" fairness strategy. It requires the high-priority agent to give up the bus after each successful access, regardless of whether the high-priority agent still has a large number of time-critical continuous requests to handle. This forced priority conversion and rotation inevitably introduces additional delay jitter for high-priority traffic under high load conditions. This method sacrifices the delay predictability of high-priority services, which is a serious performance defect for delay-sensitive devices such as real-time video or network adapters. At the same time, for any complex arbitration algorithm, if a multi-level logic structure (such as a tree comparator) is used, the arbitration decision itself will have a delay that increases with the number of functional modules, eventually exceeding the strict limit on arbitration switching time for high-frequency SoC, thus failing to achieve low-delay interfaces. In summary, the existing arbitration method still cannot achieve a good balance between high throughput, predictable low delay, and high hardware efficiency in the face of intelligent chip system scenarios with strict delay requirements.

[0004] Therefore, a low-delay interface control module priority arbitration method for chip is proposed. SUMMARY

[0005] The present application aims to provide a low-delay interface control module priority arbitration method for chip, which is used to realize low-delay interface in intelligent chip system scenarios with strict delay requirements.

[0006] To achieve the above object, the present application provides the following technical solutions: A low-latency interface control module priority arbitration method for a chip, comprising: Receiving access requests of a plurality of bus agents of an intelligent chip, and associating static priorities, QoS levels and time stamps to generate dynamic ordering counts; Decrementing the dynamic ordering counts in each arbitration cycle through a QoS differentiated aging mechanism, the QoS differentiated aging mechanism setting different decrement rates for the access requests based on the QoS levels to generate updated ordering counts, and using a secondary arbitration strategy to conflict-arbitrate the requests whose updated ordering counts simultaneously reach a minimum value to determine an access type of an optimal request; Grouping the access requests based on the access type of the optimal request, and calculating a difference value of the ordering counts between optimal requests of the same type and optimal requests of different types to generate a quantized difference value; Based on monitoring of a bus load, constructing a load decision model that maps bus load levels to switching thresholds and determines corresponding dynamic switching thresholds, comparing the quantized difference value through the dynamic switching thresholds to generate a switching enable signal; Based on the switching enable signal, calculating an authorization signal of the optimal arbitration request through a flattened two-level logic structure to output bus authorization information and complete access control of internal data channels of the intelligent chip.

[0007] Preferably, the dynamic ordering count is generated through weighted calculation of the static priority, the QoS level and a waiting time calculated from the time stamp, the weights of the weighted calculation being preset and the calculation result satisfying that the higher the priority, the smaller the initial count; the static priority being a preset N-bit binary number obtained by a register according to a MasterID of the request; the QoS level being an M-bit value in a protocol field obtained by signal line extraction on the bus request; the time stamp being a system counter value obtained when the request arrives; and the waiting time being obtained by a subtracter through subtraction of the current system time and the time stamp.

[0008] Preferably, the QoS differentiated aging mechanism is specifically implemented as follows: The current ordering count of the access request and the QoS level are taken as inputs of the QoS differentiated aging mechanism, the current ordering count being the dynamic ordering count of a new request and the updated ordering count of an ungranted request in the last cycle; based on the QoS level of the request, a corresponding decrement rate is found for the access request through QoS-to-rate mapping logic, the decrement rate being stored through a lookup table, the decrement rate corresponding to a high QoS level being greater than the decrement rate corresponding to a low QoS level, and the current ordering count and the decrement rate being calculated in parallel through a subtracter array to generate the updated ordering count for the next round of arbitration.

[0009] Preferably, the secondary arbitration strategy occurs after the primary ordering count comparison, only for access requests whose counts reach the minimum value, and is implemented based on a flattened combinational logic, including: Comparing the current updated ordering count with the minimum value through a parallel comparator array, generating a set of binary signals, and performing secondary arbitration on access requests with binary signals of 1; in the secondary arbitration, the request with the highest static priority is used as the winner; if the static priority still conflicts, a minimum selector is used to find and output the winner request identification with the minimum timestamp, and determine the access type of the winner request.

[0010] Preferably, the monitored parameters of the bus load include the depth of the request queue to be processed, the effective utilization rate of the bus, and the number of authorized but incomplete transactions; the monitored parameters of the bus load are weighted to generate a comprehensive load score, and the load score is converted into a discrete load level through a multi-stage comparator chain as the input of the load decision model, so that the intelligent chip can accurately perceive the busy degree of its internal data flow.

[0011] Preferably, the load decision model is constructed based on a lookup table, including: The lookup table is composed of a multiplexer array, used to store the mapping relationship between the load level and the basic switching threshold, divide the bus load into K levels, and preset K basic switching thresholds; according to the load level, the lookup table structure is used to select and output the pre-stored dynamic switching threshold in a combinational logic manner, and the entire lookup process is an address-to-data mapping process, which is completed within a single clock cycle, meeting the low delay requirement of the intelligent chip.

[0012] Preferably, the specific generation process of the switching enable signal includes: Comparing the quantized difference value with the dynamic switching threshold through a comparator to generate the switching enable signal, wherein the comparator is a parallel comparator; the generation logic of the switching enable signal is that if the quantized difference value is greater than the dynamic switching threshold, the switching enable signal is 1, otherwise, the switching enable signal is 0.

[0013] Preferably, the flattened two-level logic structure adopts a parallel computing topology, and its core is constructed by an AND gate array and an OR gate array; the combinational logic array receives all input signals in parallel and simultaneously calculates the winning state of all authorized requests, and performs a logical OR operation on the respective winning states to output the final authorization signal, thereby guaranteeing a low-delay arbitration decision; the specific implementation manner is: The input signal is converted into parallel Boolean signals, which include validity signal, tie trigger signal, global decision signal, same type optimal signal, different type optimal signal and secondary arbitration result signal; the validity signal is generated based on the storage state of the request queue; the same type optimal signal and the different type optimal signal are generated based on the minimum selection logic of the update ordering count of each group of requests; the tie trigger signal is generated based on the comparison result of the minimum update ordering count; the global decision signal is the switching enable signal; the secondary arbitration result signal is generated by the secondary arbitration decision strategy logic; based on the Boolean signals, a first level logic AND gate array calculates all possible 'winning states' for each request to be authorized in parallel, wherein each winning state corresponds to an independent AND gate, and the final AND gate outputs an intermediate Boolean result; a second level logic OR gate array performs a logical OR operation on all winning states of the request to be authorized, and finally generates the authorization signal of the request.

[0014] Compared with the prior art, the method has the following beneficial effects: 1. The method combines the QoS differentiated aging mechanism and the secondary arbitration strategy to map the QoS level of the request to a higher decreasing rate; the method enables the high QoS request to reduce its ordering count faster, dynamically maintains the high priority of the request, and thus guarantees the response real-time performance of the time-critical task, and realizes the predictability and stable low latency of the arbitration method.

[0015] 2. The method introduces the dynamic ordering count, integrates the decision model of the quantized difference value and the dynamic switching threshold, dynamically improves the priority of the request, and adaptively adjusts according to the bus load, and thus realizes the time-driven arbitration; the method can accurately perceive the real-time urgency of the request, effectively avoids the expiration of the delay-sensitive request due to the arbitrariness of arbitration, and thus realizes the maximization of the bus throughput and bandwidth utilization, and guarantees the balance of the arbitration method in terms of throughput and latency requirement.

[0016] 3. The method specially adopts a flattened two-level logic structure to realize the generation of the final authorization signal; the flattened structure is a pure combinational logic (AND-OR array), which can minimize the physical delay on the critical path of the authorization signal generation stage, and thus minimizes the total delay of the entire arbitration decision process, and supports a higher system working frequency. BRIEF DESCRIPTION OF DRAWINGS

[0017] Fig. 1 The flow chart of the low-latency interface control module priority arbitration method for a chip according to the present application; Fig. 2 The load decision model structure diagram according to the present application; Fig. 3 The flattened two-level structure flow chart according to the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0019] Please refer to Figs. 1 to 3 The present application provides a low-latency interface control module priority arbitration method for a chip, and the technical solutions are as follows: A low-latency interface control module priority arbitration method for a chip, please refer to Fig. 1 The specific implementation steps of the method provided by the present application include: S1, receiving access requests of a plurality of bus agents, and associating static priorities, QoS levels and time stamps to generate dynamic ordering counts; S2, decrementing the dynamic ordering counts in each arbitration cycle through a QoS differentiated aging mechanism, the QoS differentiated aging mechanism setting different decrement rates for the access requests based on the QoS levels to generate updated ordering counts, and using a secondary arbitration strategy to perform conflict arbitration on the requests whose updated ordering counts simultaneously reach the minimum value to determine the access type of the optimal request; S3, grouping the access requests based on the access type of the optimal request, and calculating the ordering count difference between the optimal requests of the same type and the optimal requests of different types to generate quantized difference values; S4, constructing a load decision model based on the monitoring of the bus load, the load decision model mapping the bus load level with a switching threshold and determining a corresponding dynamic switching threshold, comparing the quantized difference values through the dynamic switching threshold to generate a switching enable signal; S5, based on the switching enable signal, calculating the authorization signal of the optimal arbitration request through a flattened two-level logic structure, outputting bus authorization information, and completing the access control of the internal data channel of the intelligent chip.

[0020] Embodiment one: The embodiment provides a low-latency interface control module priority arbitration method for a chip, and the use scenario is an intelligent chip system scenario with strict delay requirements.

[0021] Further, the access requests of a plurality of bus agents are received, and static priorities, QoS levels and time stamps are associated to generate dynamic ordering counts; corresponding to the above step S1, the specific process is: When multiple bus masters compete for access to a shared bus resource, the system receives access requests from multiple bus agents and obtains a static priority of the request in parallel , a QoS level (Q), and a latency (W) calculated by a subtractor. The static priority of the request is obtained by reading a hard-coded lookup logic associated with a MasterID of the requesting master, and a preset N-bit static priority value is obtained. The principle of determining the static priority value is that the most critical module (such as a CPU core or a security module) of the system is assigned the highest static priority, the most delay-sensitive module (such as a real-time video engine or a network interface) is assigned a higher priority, and the module closest to the shared resource (such as a memory controller) may be given a structural advantage, which is reflected as a higher priority. The QoS level is obtained by signal line extraction logic of a bus interface, and an M-bit QoS value in a protocol field is obtained. The static priority and the QoS level should implement the design principle of "the smaller the count, the higher the priority". If the static priority value and the protocol QoS value are directly proportional to the priority, an inverter needs to be used for conversion, so that they show a negative contribution or a smaller value in the weighted calculation. If the static priority value and the QoS protocol value are inversely proportional to the priority, they can be directly used. The latency is obtained by latching the system clock counter value when the access request arrives, and calculating (current system time - system clock counter value) in the current period by a subtractor to obtain the latency in real time.

[0022] Three multiplication operations are completely performed in parallel by a multiplier array: latency (W) multiplied by a weight , static priority multiplied by a weight , and QoS level (Q) multiplied by a weight , to generate results of the three parallel multiplications 、 、 wherein is a subtraction item 、 is an addition item, and the weight is a preset hard-coded constant, wherein The value is relatively large, and it must be ensured that the weighted value generated by the minimum increment of W is sufficient to cover the sum of the maximum weighted contributions of the static priority and the QoS level. The value is medium, and is used to distinguish the inherent importance of the functional modules. The influence weight should be lower than the latency but higher than the QoS level; and the The relative minimum is mainly used to adjust the contribution of the QoS level to the initial value of the dynamic ordering count and as a secondary ordering factor; for example, in a specific implementation, the static priority and the QoS level are both defined as 4-bit unsigned integers (numerical range [0, 15]), and the latency is a 16-bit unsigned integer. To meet the "domination" principle, the weight , , is set according to the following rules: wherein . Assuming that (left shift by 1 bit), (no shift). The sum of the maximum static contributions is: Therefore, must be greater than 45. To achieve efficient implementation in hardware, the power of 2 closest to and greater than 45 is selected as , i.e. (corresponding to logical left shift by 6 bits). Finally, in a specific implementation, the following settings are made: (corresponding to logical left shift by 6 bits), (corresponding to logical left shift by 1 bit), (no shift), which not only ensures that the weight of the latency is significantly higher than that of the static priority and the QoS level, but also reflects the basic influence of the static priority being higher than the QoS level, while achieving efficient hardware implementation. Those skilled in the art should understand that these weight values are only illustrative and can be adjusted according to the bus protocol and performance requirements (such as sensitivity to delay) of a specific chip. The multiplier array is implemented using optimized shift-add logic to minimize critical path delay and uses a tree adder structure. Convert to its complement, the complement representation of is the negative of , , The results of the three parallel multiplications are sent to the second-stage tree adder structure for fast summation to generate the final dynamic ordering count; the tree adder structure uses a carry-lookahead adder and performs summation in parallel through a tree topology of two CLA series, thereby significantly reducing the calculation delay of the dynamic ordering count to adapt to the high-frequency operation requirements of the target chip. The final bit width of the dynamic ordering count is designed to be able to accommodate the maximum value of the weighted calculation result, and this value should be at least greater than the bit width of the product of the maximum value that the latency W can reach and to ensure that the decrement operation within the arbitration period does not cause negative overflow.

[0023] As a preferred embodiment, the weights can also be adjusted by a dynamic weight adjustment mechanism of real-time system working mode, which can adaptively adjust the weights of latency and QoS level according to different system running situations and , so as to dynamically balance between power consumption and performance, which is specifically implemented as: Receiving binary "system working mode" signals (low power mode, real-time critical task flow mode, real-time congestion burst mode) from the system power management unit (PMU), which are predefined and represent different emphasis requirements of the system on delay and power consumption. A hard-coded lookup table (LUT) is constructed, whose input is "system working mode" and output is a set of pre-calibrated dynamic weights: The lookup table must be designed as a flattened logic structure to ensure that weight switching is completed within a single clock cycle. When the system is in low power mode, the lookup table outputs a set of lower and values. Reducing the weight of can slow down the decrease of the sorting count (aging speed), so that the arbiter does not rush to raise its priority when requests are queued, reducing unnecessary arbiter activity or power consumption. When the system detects "real-time critical task flow" or "congestion burst", the lookup table outputs a set of higher and values, and higher temporarily amplifies the contribution of latency, so that the dynamic sorting count of time-sensitive requests decreases rapidly, thereby forcibly raising the priority of urgent requests when congestion occurs, ensuring their real-time performance. In each arbitration period, the multiplier array receives dynamic weights from the lookup table in parallel and replaces the preset static weights, and the final dynamic sorting count is completely generated in parallel in the multiplier array and tree adder structure.

[0024] Compared with static weights, the dynamic weight adjustment mechanism enables the arbitration method to better adapt to changing system load and performance requirements, providing a more robust arbitration decision-making capability.

[0025] By introducing dynamic sorting count, the static priority of the request and the latency calculated by the timestamp are combined, which can effectively and accurately perceive the real-time urgency of the request and effectively avoid the expiration of delay-sensitive requests due to arbitration blindness.

[0026] Further, the dynamic ordering count is decremented in each arbitration cycle by a QoS differentiated aging mechanism that sets different decrement rates for access requests based on QoS levels, generates updated ordering counts, and uses a secondary arbitration strategy to conflict-arbitrate requests whose updated ordering counts reach a minimum value simultaneously, to determine the access type of the optimal request; corresponding to the above step S2, the specific process is as follows: The QoS-to-rate mapping logic of the QoS differentiated aging mechanism is implemented by a combinational logic lookup table, which is hard-coded by a multiplexer array; the combinational logic lookup table stores the mapping relationship between the M possible QoS levels and the preset decrement rates The values of the decrement rates are pre-calibrated hard-coded constants according to system latency requirements and service priorities, and the pre-calibration of the decrement rates needs to follow the following principles: a maximum allowable latency period and an ordering count are set. For the highest QoS level (e.g., QoS0), its corresponding decrement rate should at least satisfy , where is the maximum possible value of the new request dynamic ordering count. The values of the decrement rates of different QoS levels should be decreased in steps according to their corresponding latency sensitivity requirements. For example, the decrement rate corresponding to QoS level 0 (the highest priority), the decrement rate corresponding to QoS level 7, and the decrement rate corresponding to QoS level 15 (the lowest priority). In the subtraction operation, when the result of subtracting the decrement rate from the current ordering count is less than the minimum value of the ordering count (e.g., 0), the updated ordering count will be saturated and kept at the minimum value to avoid negative overflow and ensure the logical correctness of the counter. The decrement rate corresponding to a high QoS level is greater than the decrement rate corresponding to a low QoS level, ensuring that the ordering count of a high QoS request decreases faster, thereby accelerating its priority promotion. The current dynamic ordering count of the access request and the QoS level are taken as inputs of the QoS differentiated aging mechanism, and the corresponding decrement rate ​The current dynamic ordering count is subtracted from the decrement rate by a subtractor array to generate an updated ordering count; the subtractor array is equipped with an independent subtraction unit for each request slot in the queue, and each subtraction unit uses a carry lookahead adder (CLA) structure to implement subtraction. The subtractor array processes all requests simultaneously, ensuring that all value update ordering counts are stably output within a single clock cycle. In each arbitration period, the "updated ordering count" will be used for arbitration comparison in the current period. At the same time, for all unauthorized access requests, the "updated ordering count" will be latched and fed back as input to the subtractor array in the next clock cycle, and subtraction is performed again with the corresponding decrement rate, thereby realizing the arbitration period decrement of the ordering count. The newly arrived access request uses the "dynamic ordering count" generated by S1 as the input for the first decrement.

[0027] The generation of the updated ordering count by the QoS differentiated aging mechanism realizes dynamic accelerated aging, which directly links the priority promotion speed of the request to its business demand, providing real-time and accurate updated ordering count for subsequent core decision logic.

[0028] When comparing the updated ordering counts of all access requests in the queue through a minimization selector tree, the minimization selector tree uses a parallel tree topology to compare two updated ordering counts in a multi-stage comparator, output the smaller value of each, and continue to compare the smaller values until the root of the tree outputs the global minimum value. The depth of the minimization selector tree is stage, ensuring that the global minimum value is stably output within a very short combinational logic delay. By comparing all access request updated ordering counts with the global minimum value through a parallel comparator array, a set of binary signals T is generated based on the comparison result. If the updated ordering count and the global minimum value are equal, T outputs 1; otherwise, T outputs 0. Requests with T=1 are defined as tie requests, and the parallel comparator array contains N independent equality comparators. The arbitration logic confirms the occurrence of a tie by checking whether there are two or more binary signals equal to 1 in the T vector, and triggers the subsequent secondary arbitration strategy.

[0029] The secondary arbitration first breaks the tie using the inherent importance of the request, inputs the generated binary signal T into a priority encoder, which receives the static priority values corresponding to all the tie requests at the same time, and selects the request with the highest static priority (i.e. the smallest static priority value) as the winner among all the tie requests, outputs an initial winner identifier, and checks whether there are multiple requests still having the same highest static priority, if there are multiple requests still having the same highest static priority, uses the request latency as the final decision criterion, defines the multiple requests having the same highest static priority as conflict requests, inputs the record timestamps of the conflict requests into a minimization selector, and the minimization selector compares the timestamps in parallel and selects the timestamp with the smallest value. Finally, a unique winning request is determined, and the arbitration logic finally outputs a unique winning request identifier, which is a L-bit binary vector, i.e. a One-Hot vector, pointing to the slot in the queue where the winning request identifier is located. The winning request identifier is used as a selection signal of a multiplexer, and the multiplexer uses the selection signal as an address to select and output the access type of the winning request from all the access type fields in a combinational logic manner. The extracted access type information of the winning request is the access type of the optimal request determined by the arbitration in this cycle .

[0030] As a preferred embodiment, the secondary arbitration strategy can introduce a "history hunger degree" factor as a third-level arbitration, track the time when each bus agent is continuously deprived of the bus ownership by maintaining a counter, and ensure that requests with lower static priority or lower level do not suffer from permanent hunger under extreme competition conditions. The specific implementation is as follows: Each bus agent in the system is equipped with an independent "last authorized cycle counter" In each arbitration cycle, for all agents that do not obtain bus authorization, the corresponding counter is incremented by one, and once a certain agent obtains bus authorization, the counter is immediately reset to 0. Only when the second-level decision still cannot break the conflict (i.e. multiple conflict requests have the same minimum update count, the same highest static priority, and the same minimum timestamp), the third-level decision is triggered, the minimization selector compares the values of all the remaining conflict requests in parallel, and the request with the maximum value (i.e. the request that has not been authorized for the longest time) is granted the bus ownership. This ensures that the most "hunger" request is served.

[0031] In the case of design defects or extreme pathological loads, the historical starvation factor as the final bottom-up logic can avoid the system from entering a deadlock or livelock state, significantly improving the system robustness and reliability of the arbiter.

[0032] The secondary arbitration strategy provides a hierarchical and fast conflict resolution mechanism by combining static priority and timestamp, ensuring that the bus grant mechanism can operate stably and reliably even under extreme competition conditions; successfully integrating a complex conflict resolution mechanism into a low-latency arbitration architecture.

[0033] Further, based on the access type of the optimal request, the access requests are grouped, and the ordering count difference between the optimal requests of the same type and the optimal requests of different types is calculated to generate a quantized difference value; corresponding to the above step S3, the specific process is: By comparing the access type of each access request in the queue with the access type of the optimal request Parallel execution comparison, if , the access request is marked as a same-type request and divided into a same-type group , if , the access request is marked as a different-type request and divided into a different-type group , the two parallel minimum selector trees find the optimal requests in the respective groups, the first minimum selector tree is only valid for requests, and all same-type requests are compared in parallel to output the minimum count in the group , at the same time, the comparator tree or additional encoding logic outputs the optimal request identifier corresponding to the minimum count , if multiple same-type requests have the same minimum count, the secondary arbitration strategy is used to determine the unique optimal request identifier , the second minimum selector tree performs the same operation on requests, and outputs the minimum count in the group and the optimal request identifier , the two minimum values are received by a subtractor and a subtraction operation is performed: , generating the original difference value . Subsequently, the original difference value is quantized by a quantization table to map it to an N-bit binary quantized difference value . The quantization rules of the quantization table convert continuous ordering count difference values into discrete decision values that can be used for hardware comparison. For example, the quantization table can be pre-configured as follows: 1. When is in the negative value range (e.g. ), the quantized difference value Set to 0; 2. When Within a small range of differences (e.g.) ), quantification difference Set it to a small value (e.g., 10); 3. When Within a large positive range (e.g.) ), quantification difference Set it to a relatively high positive value (e.g., 50).

[0034] Since a smaller sort count indicates a higher priority, ... The more negative the value, the greater the priority advantage of different types of requests, and the higher the switching benefit. Therefore, the quantified difference... Set to a non-negative value, representing the potential benefit of switching access types. The quantization table is pre-calibrated based on the hardware overhead of bus switching latency and the latency requirements of different QoS levels, ensuring... This can represent the true benefits of the switch. The quantification logic will divide the data into several discrete intervals, each corresponding to a discrete... Value. If It is a large positive value (i.e.) much smaller This means that the urgency of different types of optimal requests is far higher than that of the optimal requests of the same type, and the benefits of the system switching access types are extremely high; if If the value is a small positive value or zero, it means that the urgency of different types of requests is not much different or is lower than that of requests of the same type. In this case, it is advisable to keep the current access type to avoid switching overhead.

[0035] The bus load is monitored by three parameters: queue depth (D), bus utilization (U), and number of pending transactions. The depth of the pending request queue is tracked by a queue depth counter. Whenever a new bus proxy request is confirmed as valid by the arbitrator and written into the pending request queue, the counter is incremented by one, driven by the request arrival logic. Whenever the arbitrator grants bus ownership to a request and the request is removed from the queue, the counter is decremented by one, driven by the bus authorization logic. The bus utilization rate is measured within a fixed periodic window. Within, is the number of effective bus cycles. With total number of cycles The ratio. To meet the hardware design goals of low latency and high efficiency, a fixed period window is used. Must be set to One clock cycle. For example, set One clock cycle (i.e., p=10). Bus utilization is tracked by a cycle counter and an effective counter. The cycle counter increments in each arbitration cycle, and when it reaches... The time is reset to zero. The valid counter is at... During a cycle, the count increments only when the bus is in active use. When the cycle counter resets to zero, the currently accumulated number of active cycles is incremented. This represents the total number of valid buses within the window. At this point, the formula for calculating the bus utilization rate U becomes: Therefore, the calculation of bus utilization rate U is done by... The value is achieved by P-bit logical right shift. This right-shift-based approximate division avoids the use of high-latency dividers, thus ensuring real-time, low-latency calculation of bus utilization and meeting the immediacy requirements of the load decision model for input data. The number of incomplete transactions is tracked by an incomplete transaction counter. When the arbitrator issues an authorization signal to a request, the counter increments by one synchronously. When the bus interface logic receives the completion signal corresponding to the authorized transaction, the counter decrements by one synchronously. The completion signal includes a read response or a write response.

[0036] Furthermore, a load decision model is constructed based on the monitoring of bus load. This model maps bus load levels to switching thresholds and determines corresponding dynamic switching thresholds. The quantization difference is compared and judged using these dynamic switching thresholds to generate a switching enable signal. Corresponding to step S4 above, the specific process is as follows: The three load monitoring parameters are fed into a weighted combinational logic circuit, where queue depth and number of incomplete transactions are updated in real time, and bus utilization is updated periodically, to generate a comprehensive load score. ,Right now The weight , and These are parameters that can be configured by the main controller. As the highest weighting factor, real-time congestion pressure is used as the monitoring indicator to ensure that changes in D have a decisive impact on the overall load score and quickly reflect instantaneous congestion. As a medium-to-high weight, it uses long-term bandwidth pressure as a monitoring indicator to smooth short-term fluctuations and increase the total load score when the bandwidth is close to saturation. As a lower-weighted indicator, resource lock-in risk is used as a monitoring indicator and as a supplementary indicator. When the value is too high, it puts pressure on the total load score, causing the arbiter to become more conservative. For example, in a specific implementation, also to facilitate hardware shift-addition implementation, it can be set to... This setup emphasizes queue depth (D) as the primary indicator of instantaneous congestion pressure, with a weight twice that of bus utilization (U) and four times that of the number of pending transactions, ensuring... Fast response to queue backlog. The actual values of the weights are determined by the following procedure: based on the timing and delay characteristics of the bus protocol, a theoretical contribution model of the three parameters is established, in the FPGA or RTL simulation environment, run multiple load test cases, gradually adjust the weight value, when the system appears the expected congestion (for example, the delay starts to exceed the target threshold), to achieve higher discrete load levels, the weight constant value (usually in the form of or , which is directly hard-coded into the RTL code as part of the pure combinational logic) is verified and solidified. In a preferred embodiment, these weights can be dynamically loaded and adjusted according to the dynamic weight adjustment mechanism of the real-time system operation mode described above. For example, when the system is running in the "power optimization mode", the weight of bus utilization) can be reduced; while in the "performance priority mode", and the weights are raised, so that more sensitive to reflect the congestion of high delay and deep queue, to achieve adaptive response to bus load.

[0037] The comprehensive load score is compared with K-1 preset load thresholds by a multi-stage comparator chain to generate discrete load levels , specifically, if , (lowest load level); if , (highest load level). The load decision model takes as input, looks up and outputs the pre-stored basic switching threshold . The dynamic switching threshold is equal to the basic switching threshold . The determination of the K-1 preset load thresholds is based on the sensitivity of the system to bus switching tolerance and performance goals. In actual engineering, the value of K is usually set to 4 to 8 levels, which only requires 2 or 3 bits of encoding, which can effectively balance accuracy and delay; for example, assuming K=4 (i.e. ), combined with the weight examples of the foregoing , The theoretical range of may be 0 to hundreds. At this time, three layers of load thresholds can be preset: , . The comparison logic is as follows: if , (low load); if , (low load); if then (medium load); if then (high load). The load threshold is determined by the following iterative process: according to the maximum range of the weight and parameter in the calculation formula, estimate the approximate interval of the load threshold, in the RTL simulation environment, run a series of high-competitive load, accurately record the real-time trajectory and the change of key delay indicators (such as 99% delay), associate the load threshold with the corresponding dynamic switching threshold, and hard code it into the lookup table, after multiple iterations and verifications, the final load threshold value is hard coded into the multi-comparator chain of the arbiter logic as an immutable constant to divide the interval.

[0038] Through the monitoring of bus load, the arbiter obtains real-time perception of the health status of the bus. It can provide a basis for the subsequent load decision model to dynamically adjust its switching tolerance according to the actual pressure level, so that the arbitration strategy has adaptability and system robustness.

[0039] The load decision model is based on a lookup table, which is composed of a multiplexer array, in which K preset basic switching thresholds are hard coded, each threshold corresponding to a load level The preset basic switching threshold is a hard-coded constant determined by a complex system simulation and calibration process based on the quantification of bus switching overhead and the tolerance of the system to load pressure. The determination process is as follows: through bus protocol simulation, accurately quantify the actual clock cycles X required for a type of access switching, and calculate the basic penalty count by multiplying the system's baseline aging rate with the clock cycles X, and establish a strategy mapping. The baseline aging rate is the minimum non-zero decreasing rate in the QoS differentiated aging mechanism; the minimum threshold is usually set to 1 / 4 or less of the basic penalty count, and the maximum threshold is usually set to 2 or 3 times the basic penalty count, or a large enough value to ensure that the arbiter will not switch in 99% of cases when congested. In the RTL simulation environment, run multiple load scenarios and monitor the average transaction delay and bus utilization in real time. According to the system performance indicators, fine-tune the threshold , for example, if is found to be too low, resulting in too much switching at high load and a decrease in bus utilization, then is increased to ensure that each load level corresponds to All of these allow the bus to achieve the optimal latency / throughput tradeoff under the current load conditions. The verified K threshold values ​​are hard-coded into the memory cells of a lookup table (LUT), becoming part of a pure combinational logic multiplexer array. For example, corresponding to the aforementioned load level of K=4... Assuming the base penalty count is 100, the lookup table can be hardcoded to store the following mapping: when When, output (Encourage switching); when When, output (Neutral); when When, output (Suppress switching); when When, output (Strongly suppress switching). K thresholds arrive It must be positively correlated with K load levels, minimum threshold Representing low load, this encourages the arbitrator to switch freely based on minor differences in the urgency of requests, prioritizing the next most urgent request; maximum threshold. The first threshold represents high load, which strongly suppresses all switching and forces the arbitrator to prioritize batch processing of requests of the same type in order to quickly clear the queue and alleviate congestion. The remaining thresholds represent medium load, which allow switching only when the urgency of different types of requests is significantly higher than the base penalty count.

[0040] Discrete load levels As a selection signal, the selection signal is input to the control logic of a K-to-1 multiplexer array. The multiplexer array then selects the signal based on the discrete load level. The value is mapped from address to data, and then one of the input data lines is activated through gate logic. At the output, the multiplexer array outputs the selected value. That is, dynamic switching threshold When under low load, When set to a smaller value, the arbitrator has a high tolerance for switching overhead. The quantization difference only needs to be slightly greater than this small threshold to trigger an access type switch, prioritizing more urgent requests. Under high load conditions... When set to a large value, the arbitrator will try its best to suppress switching, and will only allow access type switching when the urgency of the different types of optimal requests is far greater than the switching cost.

[0041] As an enhancement to the aforementioned load decision model, the load decision model can be improved by incorporating the short-term rate of change of the load fraction. As an additional input dimension, the arbitrator not only perceives the current congestion state. Furthermore, it can predict short-term trends in bus load. This allows the arbitrator to pre-adjust the dynamic switching threshold before congestion occurs, specifically implemented as follows: Introduce a small register or circular buffer to store the combined load score of the first X arbitration cycles (X is typically set to 4). Historical values ​​are calculated using a subtractor in each period. Compared with the previous sampling period The difference, that is: By comparison With two preset thresholds The trend is divided into discrete trend levels. ; ; The preset threshold The calibration method is as follows: First, determine the overall load fraction. The complete range of values ​​is used to run a long-term benchmark test under stable, continuous load conditions (e.g., medium load, no sudden changes or mode switching). Record the values ​​at this point. Change value within a continuous period The statistical distribution of these variations is considered as "system noise" or "normal fluctuations." Based on the statistical results, a rate of change that is much larger than the average noise fluctuation but smaller than the rate at which actual congestion begins is selected as the statistical distribution. Initial value. For example, if the normal fluctuation range is within ±5 units, then... Set to 10 or 15, Substitute the data into the predictive model and conduct actual load tests. If... If the threshold is too small, the model becomes overly sensitive to noise, leading to misjudgments (frequent and unnecessary threshold adjustments). If... If the load is too large, the model will be slow to react and unable to capture the trend of increasing load in time, leading to prediction failure. Through iterative adjustments, the optimal balance between maximizing bus throughput and minimizing latency jitter under various typical workloads can be found. The original load decision model's single-input lookup table is expanded to be based on two dimensions (discrete load level). Short-term trend level The lookup table (PLDM-LUT) is used to determine the dynamic switching threshold. Its internal mapping logic adjusts the base threshold based on the trend level: (Medium) + (UP): Output a higher value (Above the threshold under a stable trend), preemptively suppress switching; (High load) + (DOWN): Outputs a lower value. Pre-emptively relax the switch if the quantized difference is below the threshold of the steady trend.

[0042] By introducing the short-term change rate of the load fraction, the load decision model can more smoothly adapt to the load changes, reduce the oscillation and instability of the arbitrator at the load peak and valley, and help to achieve more predictable low latency.

[0043] By generating dynamic switching thresholds through the load decision model, the complex, load-based adaptive strategy is flattened into a one-layer logic lookup operation, ensuring that the generation of dynamic switching thresholds will not become a critical path delay bottleneck in the entire arbitration decision-making process. Thus, it ensures that the bus always runs at the best "delay-throughput" efficiency point under the current load condition.

[0044] By comparing the quantized difference and the dynamic switching threshold through a parallel comparator, output a 1-bit switch enable signal (Enable), the generation logic of which is: if , then Enable=1, otherwise Enable=0. When Enable=1, it means that the urgency of different types of optimal requests is significantly higher than and the gap is greater than the switching cost under the current load , at this time, the switching type is worth it. When Enable=0, it means that the urgency gap is not enough to make up for the switching overhead, and the current access type should be maintained.

[0045] By comparing the quantized difference with the dynamic switching threshold, and by quantizing the urgency benefit and dynamically adapting the switching cost, the arbitrator can make the optimal authorization decision that takes into account both latency and throughput under any bus load condition.

[0046] Further, based on the switching enable signal, the optimal arbitration request authorization signal is calculated through a flattened two-level logic structure to output the bus authorization information, completing the access control of the internal data channel of the intelligent chip; corresponding to the above step S5, the specific process is: Convert the minimum update order count, same type minimum count, different type minimum count, quantized difference, and switching enable signal into parallel Boolean signals, which include: validity signal , tie trigger signal , global decision signal G, same type optimal signal , different type optimal signal , and secondary arbitration result signal The validity signal represents the signal is logic high (1) if the request still resides in the arbiter's pending queue, otherwise 0; only the request with validity signal 1 can be granted bus ownership. The tie trigger signal is generated by the minimum update order count, the tie trigger signal is 1 representing the initial order count of this request reaches the minimum absolute value among all requests; only when this signal is 1, the AND array needs to consider its subsequent secondary arbitration results such as static priority and timestamp. The global decision signal is determined by the switch enable signal, 1 representing the arbiter decides to switch access type after load adaptive decision, in the AND array as a global control signal, used to select the winning path of the optimal request of the same type or the optimal request of different types. The same type optimal signal is generated by the same type minimum count, representing whether the request is the minimum count among all requests of the same access type. The different type optimal signal is generated by the different type minimum count, representing whether the request is the minimum count among all requests of different access types. The secondary arbitration result signal is generated by the secondary arbitration strategy logic, representing whether the request has the highest static priority among the tie requests or whether the request has the minimum timestamp, used to further determine whether the request is the final winner based on the static priority or timestamp rule when there is an average initial count. The Boolean signals are combined into a multi-dimensional input vector of the AND-OR array.

[0047] The flattened two-level logic structure is constructed based on the AND-OR array, a multi-bit input vector is input into the AND-OR array, the first level is a high fan-in AND gate array, the AND gate array is composed of AND gates, wherein is the number of bus requests, and is the number of potential winning paths or conditions preset for each request, for each access request in the queue , the winning state of the request is the logical disjunction of all possible winning conditions. For example, its logic can be simplified as the logical disjunction (OR) of the following main cases: 1. the type optimal authorization item that is must be a valid request, the global decision tends not to switch, and is the optimal request among the same type requests, and there is no order count tie; 2. the switch type optimal authorization item that is must be a valid request, the global decision tends to switch, and is the optimal request among the different type requests, and there is no order count tie; 3. the extreme tie bottom path item that wins only through the secondary arbitration strategy when a tie occurs These parallel-generated path terms include, but are not limited to, these three types. The AND gate array computes all these possible winning conditions in parallel. When the winning condition of a path is met, the intermediate Boolean result is output as 1; otherwise, the output is 0. The intermediate Boolean results are then integrated. .

[0048] The second level is a high-fan-in OR gate array, the array consisting of... Composed of one or more gates ( (This refers to the number of bus requests). Each OR gate is dedicated to one access request and is responsible for aggregating all conditions that could make that request succeed. Each OR gate receives... inputs (i.e., all intermediate Boolean results accessed) arrive The request's dedicated OR gate performs a logical OR operation on all winning path items of the input, thereby controlling the logical latency to a single OR gate delay and outputting their respective grant signals. The logical meaning of the OR gate array is: if a request satisfies any of the preset winning paths (i.e., receives a logic 1 output on any winning path), then it should be granted bus authorization. This ensures that the request is correctly identified and authorized, whether through dynamic load adaptive decision-making or through a secondary arbitration fallback mechanism. Finally, at the end of each clock cycle, the bus arbitrator outputs the authorization status in parallel to all N request agents. Since all winning paths are designed to be mutually exclusive, and each path produces an output of value 1 for at most one request, the final output set of the OR array is... In this system, only one signal is 1, thus achieving the uniqueness and determinism of bus authorization.

[0049] By constructing a two-level logic structure based on a two-level logic AND-OR array, the entire signal path passes through only one AND gate delay and one OR gate delay, thereby minimizing the physical delay on the critical path and achieving a balance between high throughput, extremely low arbitration delay, and high hardware efficiency.

[0050] This invention achieves real-time response for time-critical tasks through a QoS-differentiated aging mechanism and a secondary arbitration strategy. It also implements time-driven arbitration by introducing a decision model that integrates dynamic sorting and counting with quantization difference and dynamic switching threshold. Ultimately, it constructs an arbitration method with extremely low and flat logical latency, which effectively guarantees the high throughput, predictability, and low latency of the arbitration method, thereby achieving a good balance of performance when facing intelligent chip system scenarios with strict latency requirements.

[0051] Example 2: This application embodiment uses the AI ​​matrix calculation core request in an artificial intelligence acceleration chip. and system control unit request In the queue, the specific scene is competed for by the QoS differentiation aging mechanism, in The priority of the is quickly pushed to the highest in the case of slightly lower initial count.

[0052] When and two requests enter the queue at the same time, the arbitrator calculates their dynamic ordering counts based on preset weights: The dynamic ordering count of the is 400, The initial priority of the is slightly better; the QoS-to-rate mapping logic (implemented by a combination of logic lookup tables, ensuring single-cycle output) receives the QoS levels of the two requests in parallel, mapping the highest QoS level (Q7) to the largest decreasing rate , and the lowest QoS level (Q1) to the smallest decreasing rate . Subsequently, the subtractor array calculates and generates the updated ordering counts in parallel: at cycle time, the updated ordering count of the is 400-16=384, while the updated ordering count of the is 350-2=348, at this time is still the current optimal request, and at cycle time, since the count has decreased by a total of 400, its updated ordering count drops to 0 (reaching the lowest priority), while only decreases by 50, and its updated ordering count is still 300,

[0053] has already passed through the fast aging mechanism, and its priority promotion speed far exceeds , becoming the global optimal request.

[0054] Embodiment Three: Fig. 2 The bus current authorization type is read in the embodiment of the application, there is a high urgency write request in the queue as a different type optimal request, and a slightly poor read request competes for a specific scene, and the load decision model adaptively decides whether to pay the read-write switching overhead according to the real-time load condition, refer to for the load decision model structure diagram.

[0055] Bus load monitoring module monitors bus status in parallel: queue depth D=40 (far above normal value) and real-time bus utilization U=95% (extremely high). These real-time data are sent to the weighted calculation unit, and the load level is calculated after comprehensive calculation (the highest load). Subsequently, the load decision model receives , and logically outputs the corresponding dynamic switching threshold 250, which is preset to a value much higher than the basic switching penalty (such as T=100). The arbiter enters the core judgment of the optimal arbitration request generation: there is a high-emergency write request (different types of optimal, ) and a currently authorized type of read request (same type of optimal, ) in competition. The subtracter calculates the quantization difference = 500-300 = 200. The quantization difference 200 represents the priority gain that can be obtained after switching types. The parallel comparator then performs the core judgment logic: compare the quantization difference 200 with the switching cost dynamic switching threshold 250, and the comparator outputs the switching enable signal = 0. This means that in the current high-load environment, the priority gain obtained by switching types (from read to write) is not enough to offset the high switching penalty brought by it.

[0056] Through the load decision model, the arbiter can prioritize the batch processing of same-type requests when the bus resources are highly congested, avoiding the invalid cycles introduced by type switching, thereby ensuring the bus throughput and bandwidth utilization under high load.

[0057] Embodiment Four: The embodiment of the application is in a multi-core processor, the request of three different cores Because of long waiting time or priority decrement, the update ordering count of each core reaches the global minimum value at the same time. For specific scenarios, the secondary arbitration strategy determines the unique winner based on static priority and timestamp.

[0058] First, the parallel comparator array compares the update ordering counts of all requests, and detects that , The count of each core is 128, which matches the global minimum value. This immediately generates a tie trigger signal = 1, which activates the secondary arbitration logic; then the first-level decision is made: the static priority is compared, and the priority encoder compares , , The result shows that (highest priority), while and ​​​(lower priority), the priority encoder immediately decides The highest priority among all tie requests, and generates a secondary arbitration result signal = 1. At this time, the decision ends, The winner has been determined to be unique. Assume , The are all 1, at this time the decision enters the second level: timestamp comparison, the minimizer only compares , The timestamps of The timestamp of is the smallest, the decision wins. Regardless of which level the decision is made, the secondary arbitration logic must ensure that only one unique winner is output. This decision result is then converted into a Boolean signal.

[0059] Through the secondary arbitration strategy, the arbitration is guaranteed to be deterministic under extreme competition conditions, avoiding deadlock or bus errors caused by the arbiter being unable to decide.

[0060] Embodiment five: After completing the priority and switching decisions of S1 to S3, the application embodiment quickly outputs the bus grant signal for specific scenarios through the flattened two-level logic structure. Through this structure, the minimum physical delay of the grant decision is ensured. Referring to Fig. 3 , it is a flattened two-level structure flowchart: Assume that in the current arbitration cycle, the S3 decision logic has completed the calculation and output the following control signals: 1. Switching enable signal: 1, indicating that the current switching access type is the optimal choice allowed and the benefit is greater than the cost. 2. Same type optimal request identification: pointing to request . 3. Different type optimal request identification: pointing to request In the flattened two-level logic structure, all possible grant paths are connected in parallel, mainly including "maintain type optimal grant item" and "switching type optimal grant item". The structure takes the output control signal as input and directly calculates the final grant signal. First, the switching enable signal Enable signal output by S3 is taken as a global decision signal and input into the AND-OR array of S4. Since the global decision signal = 1, all calculation paths of "maintain type optimal grant item" (which require Enable = 0) will be immediately shielded to 0 by the AND gate array. At the same time, all calculation paths of "switching type optimal grant item" (which require Enable = 1) will be activated. In the activated "switching type optimal grant item" path, since S3 outputs , only the AND gate output of the corresponding request is 1, representing are activated. Finally, all requested grant terms (including hold and switch) are finally integrated by an OR gate array, since only the requested grant terms are 1, the flattened logic structure finally outputs , completing the bus grant.

[0061] By flattening the two-level structure, the physical delay of the entire grant decision chain is precisely limited to one AND gate delay and one OR gate delay, ensuring that the bus grant signal can be stably output within a single clock cycle, thus achieving the single-cycle completion goal of the low-latency arbitration method.

[0062] While embodiments of the present application have been shown and described, it is to be understood that the embodiments described are merely divergences of the principles and spirit of the present application and that numerous modifications, changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the present application as defined by the appended claims and their equivalents.

Claims

1. A priority arbitration method for a low-latency interface control module of a chip, characterized in that, The application relates to an access control method and device for an intelligent chip. The application comprises the following steps: receiving access requests of a plurality of bus agents, associating static priorities, QoS levels and time stamps, generating dynamic ranking counts; reducing the dynamic ranking counts in each arbitration cycle through a QoS differentiated aging mechanism, the QoS differentiated aging mechanism sets different reduction rates for the access requests based on the QoS levels, generates updated ranking counts, and uses a secondary arbitration strategy to perform conflict arbitration on the requests whose updated ranking counts simultaneously reach a minimum value, determines an access type of an optimal request; grouping the access requests based on the access type of the optimal request, and calculating a ranking count difference value between optimal requests of the same type and optimal requests of different types, generating a quantitative difference value; constructing a load decision model based on monitoring of a bus load, the load decision model maps bus load levels and switching thresholds and determines corresponding dynamic switching thresholds, compares the quantitative difference value through the dynamic switching thresholds, and generates a switching enable signal; based on the switching enable signal, calculating an authorization signal of the optimal arbitration request through a flattened two-level logic structure, outputting bus authorization information, and completing access control on an internal data channel of the intelligent chip. The dynamic ranking count is generated through weighted calculation of the static priority, the QoS level and a waiting time calculated from the time stamp, the weights of the weighted calculation are preset, and the calculation result satisfies that the higher the priority, the smaller the initial count; the static priority is a preset N-bit binary number, which is obtained by a register according to a MasterID of the request; the QoS level is an M-bit value in a protocol field, which is obtained by signal line extraction on the bus request; the time stamp is a system counter value obtained when the request arrives; and the waiting time is obtained by a subtracter through subtraction of a current intelligent chip system time and the time stamp. The QoS differentiated aging mechanism specifically comprises the following steps: The current ranking count of the access request and the QoS level are taken as inputs of the QoS differentiated aging mechanism, the current ranking count is the dynamic ranking count of a new request and the updated ranking count of an unauthorized request in the last cycle; based on the QoS level of the request, a corresponding reduction rate is found for the access request through QoS-to-rate mapping logic, the reduction rate is stored through a lookup table, the reduction rate corresponding to a high QoS level is greater than the reduction rate corresponding to a low QoS level, and the current ranking count and the reduction rate are calculated in parallel through a subtracter array to generate updated ranking counts for the next round of arbitration. The secondary arbitration strategy occurs after the main ranking count comparison, is only used for the access requests whose counts reach the minimum value, and is realized based on flattened combination logic, and the specific implementation comprises the following steps:

2. The method of claim 1, wherein the low-latency interface control module priority arbitration method for a chip is characterized by, A parallel comparator array is used to compare the current updated ranking count with the minimum value, a group of binary signals are generated, the access requests with the binary signals being 1 are subjected to secondary arbitration; in the secondary arbitration, the request with the highest static priority is used as the winner; if the static priorities still conflict, a minimum selector is used to find and output a winner request identifier with the minimum time stamp, and the access type of the winner request is determined.

3. The method of claim 1, wherein the low-latency interface control module priority arbitration method for a chip is characterized by, ​ ​ 4. The method of claim 1, wherein the low-latency interface control module priority arbitration method for a chip is characterized by, ​ ​ 5. The method of claim 1, wherein the low-latency interface control module priority arbitration method for a chip is characterized by, The bus load monitoring parameters include: the depth of the request queue to be processed, the bus effective utilization rate and the number of authorized but incomplete transactions; the bus load monitoring parameters are weighted to generate a comprehensive load score, and the load score is converted into a discrete load level through a multi-stage comparator chain as the input of the load decision model, so that the intelligent chip can accurately perceive the busy degree of its internal data flow.

6. The method of claim 1, wherein, The load decision model is constructed based on a lookup table, and the specific implementation includes: The lookup table is composed of a multiplexer array, which is used to store the mapping relationship between the load level and the basic switching threshold, divide the bus load into K levels, and preset K basic switching thresholds; according to the load level, the lookup table structure combines logically selects and outputs the pre-stored dynamic switching threshold, the entire lookup process is an address-to-data mapping process, which is completed within a single clock cycle, meeting the low delay requirement of the intelligent chip.

7. The method of claim 1, wherein the low-latency interface control module priority arbitration method for a chip is characterized by, The specific generation process of the switching enable signal includes: The comparator compares the quantized difference value with the dynamic switching threshold to generate the switching enable signal, and the comparator is a parallel comparator; the generation logic of the switching enable signal is: if the quantized difference value is greater than the dynamic switching threshold, the switching enable signal is 1, otherwise the switching enable signal is 0.

8. The method of claim 1, wherein the low-latency interface control module priority arbitration method for a chip is characterized by, The flattened two-level logic structure adopts a parallel computing topology, and its core is constructed by an AND gate array and an OR gate array; the combined logic array receives all input signals in parallel and simultaneously calculates the winning state of all authorized requests, and logically ORs the respective winning states to output the final authorization signal, thereby ensuring low-delay arbitration decision; the specific implementation mode is: The input signals are converted into parallel Boolean signals, including: validity signal, tie trigger signal, global decision signal, same type optimal signal, different type optimal signal and secondary arbitration result signal; the validity signal is generated based on the storage state of the request queue; the same type optimal signal and the different type optimal signal are generated based on the minimum selection logic of the updated ordering count of each group of requests; the tie trigger signal is generated based on the comparison result of the minimum updated ordering count; the global decision signal is the switching enable signal; The secondary arbitration result signal is generated by the secondary arbitration strategy logic; based on the Boolean signal, the first-level logic AND gate array calculates all the "winning states" of each authorized request in parallel, wherein each winning state corresponds to an independent AND gate, and the final AND gate outputs the intermediate Boolean result at the same time; the second-level logic OR gate array logically ORs all the winning states of the authorized requests to generate the authorization signal of the request.

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