A method for back-end loopback testing of solid-state memory

Abstract

This invention relates to the field of solid-state storage, specifically a back-end loopback testing method for solid-state storage. This method separates the implementation of the loopback testing interface from the main upper-layer business logic. This allows switching from normal firmware operation mode to loopback testing mode by only appropriately modifying the initialization steps and replacing the callback functions for related flash controller register operations, while retaining the back-end processing architecture. This improves code reusability and compatibility, and reduces the difficulty and cost of code maintenance during subsequent firmware development. A software-implemented circular queue and bitmap mapping table serve as containers to simulate the idle, triggering, and completion register behaviors of the flash controller. The time for calling these operation interfaces is fixed and predictable, allowing for the estimation of the upper limit of CPU computing power in the SSD controller chip. This provides strong guidance for the analysis and improvement of performance indicators such as 4K random read command IOPS.

Description

Technical Field

[0001] This invention relates to the field of solid-state storage, specifically a back-end loopback testing method for solid-state storage. Background Technology

[0002] Solid-state drives (SSDs) and other storage devices that use NAND flash memory chips as their medium typically consist of three main components based on their functionalities: front-end (FE), algorithm (FTL), and back-end (BE). The front-end receives read / write commands and data from the host via a communication link such as PCIe and reports the command completion status. The algorithm translates the logical address (LBA) in the front-end command context into a physical address (PBA) to determine which location in the flash memory to write to or read from. The back-end performs erase, write, and read operations on the specified storage block in the flash memory chip based on the command type and physical address, and reports the command completion result (whether there are errors, etc.) back to the algorithm. The complete firmware execution process in the SSD controller chip generally requires the division of labor and cooperation among the front-end, algorithm, and back-end components. However, in some cases, it may be desirable for the firmware back-end to operate independently of the actual flash memory device to eliminate the impact and interference of the flash memory itself on the overall system. For example, in the early stages of SSD controller hardware and software product development, the backend drivers for flash memory chips may be incomplete or lack physical hardware support; or errors or faults may be found during system integration testing that cannot accurately locate specific functional modules, requiring investigation to determine if they are flash memory related issues; in addition, when testing the 4K random read IOPS performance of SSDs, it is often necessary to first assess whether the software code execution time and processor computing power are the bottleneck factors limiting performance, which also requires conducting the test without operating the actual flash memory hardware.

[0003] SSD Backend Loopback Mode is a special firmware operation mode proposed to address the aforementioned needs. In normal firmware operation mode, after the algorithm layer sends a command message, the backend first parses the command parameters in the message and configures the relevant hardware registers of the NAND Flash Controller accordingly. Then, it starts the flash controller to execute the command, sending it to the flash memory chip through the flash physical interface (PHY). After the command execution is complete, the firmware obtains the command completion status and error information from the flash controller and returns a message to the algorithm layer. In loopback mode, the backend still parses and processes the message according to the normal process, but it does not actually send the command to the flash memory chip for execution. Instead, it directly returns a message indicating that the command is complete and the status is correct to the algorithm layer. This maintains the integrity of the command and data path from the SSD frontend to the backend while bypassing flash read / write operations.

[0004] Existing backend loopback testing methods typically involve the backend immediately returning a completion message after receiving a command message from the algorithm. Its main drawback is that it cannot cover the software code along the complete path of "message parsing -> command configuration -> execution -> waiting for completion." This makes it difficult to detect logical errors or bugs (not hardware-dependent) in the backend firmware path in a timely manner. Furthermore, it doesn't consider the necessary software time for command issuance / completion waiting functions when evaluating I / O performance limits, leading to a larger error between the measured results and actual conditions. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a back-end loopback testing method for solid-state storage. While retaining the overall firmware process architecture, some low-level operation interfaces have been replaced, resulting in advantages such as high code reusability and ease of maintenance.

[0006] To solve the aforementioned technical problem, the technical solution adopted by the present invention is: a back-end loopback test method for solid-state memory, which constructs two circular queues: an idle sequence number queue and an occupied sequence number queue. The two circular queues store unused and used command slot sequence numbers respectively in a first-in-first-out order, which is used to simulate the flash memory controller's management algorithm for command slots.

[0007] During loopback testing, the read idle and complete register operation interfaces and write trigger register operation interfaces are replaced with software-simulated circular queue operations, thereby achieving complete loopback testing functionality.

[0008] Circular queue operations include:

[0009] A. When calling the operation interface to read the free register, first check if the free sequence number queue is empty. If it is empty, return an invalid value. Otherwise, take the first element in the free sequence number queue as the starting sequence number, and search for the number of consecutive sequence numbers in the remaining elements of the free sequence number queue as the result and return it.

[0010] B. When the operation interface for writing the trigger register is called, perform the following operations:

[0011] B1. Determine whether the conditions of the free sequence number queue being non-empty and the occupied sequence number queue being non-full are met. If they are met, execute B2; otherwise, execute B4.

[0012] B2. Take the first element from the idle sequence number queue, check the status of the command slot number corresponding to the first element of the idle sequence number queue. If the status is idle, execute B3; otherwise, execute B4.

[0013] B3. Change the status of the command slot number corresponding to the first element of the idle sequence number queue to occupied, and then add the command slot number to the end of the occupied sequence number queue.

[0014] B4. The program throws an exception and enters the assertion state, indicating that there may be a design flaw in the firmware that the trigger register is not operating according to the correct procedure, and debugging is required.

[0015] C. When the operation interface function for reading the register is called, the output is initialized to an invalid value beforehand, and then the element transfer operation between the occupied / free sequence number queues is repeatedly executed.

[0016] Furthermore, the element transfer operation between the occupied / free sequence number queues is as follows:

[0017] C1. Determine if the queue of occupied sequence numbers is not empty. If it is, execute C2; ​​otherwise, execute C5.

[0018] C2. Retrieve the first element of the occupied sequence number queue, check the status of the command slot number corresponding to the first element of the occupied sequence number queue. If the status is occupied and the free sequence number queue is not full, then execute C3; otherwise, execute C4.

[0019] C3. Modify the status of the command slot number corresponding to the first element of the occupied sequence number queue to free, and add the command slot number to the end of the free sequence number queue and the output result;

[0020] C4. The program throws an exception and enters the assertion state;

[0021] C5. Return the output to the upper-level interface caller.

[0022] Furthermore, the free sequence number queue and the occupied sequence number queue are equipped with write pointers and read pointers, which are the indexes of elements in the queue. When a command slot number is added to the free sequence number queue or the occupied sequence number queue, the write pointer increments cyclically. When a command slot number is taken from the free sequence number queue or the occupied sequence number queue, the read pointer increments cyclically. After the read pointer or write pointer reaches the boundary position of the queue, it returns to the beginning.

[0023] Furthermore, the free queue and the occupied queue are equipped with operation type labels. The operation type label is used to indicate the type of the most recent operation. The empty or full status of the free queue or the occupied queue is determined by combining the pointer position and the operation type label. When the read pointer and the write pointer are at the same position, if the last operation type is write, it is considered full. When the read pointer and the write pointer are at the same position, if the last operation type is read, it is considered empty. When the read pointer and the write pointer are at different positions, it is neither empty nor full.

[0024] Furthermore, the status of the command slot number is recorded through a bitmap mapping table. The bitmap mapping table has multiple bits, and each bit represents the status of a command slot number. True indicates that it is occupied, and false indicates that it is idle.

[0025] Furthermore, the command slot numbers are stored in a slot number storage array. The length of the slot number storage array is the sum of the widths of all command slot numbers, and the array element type is the same as the width of a single command slot number.

[0026] Furthermore, during the firmware power-on initialization in the backend loopback test mode, the idle sequence number queue is filled and the occupied sequence number queue is cleared in an order that starts from 0 and increments sequentially, and the allocation status of all command slot sequence numbers is set to a fully idle state.

[0027] Furthermore, the maximum number of consecutive serial numbers that can be searched in the remaining elements of the free serial number queue is 4.

[0028] Furthermore, when the idle sequence number queue is empty, the returned invalid value sequence number is 0xFF, and the quantity is 0.

[0029] Furthermore, the element transfer operation between occupied / free sequence number queues can be performed a maximum of 4 times.

[0030] The beneficial effects of this invention: The method for implementing the back-end loopback test mode of solid-state memory described in this invention has the greatest advantage of adopting a highly cohesive and loosely coupled modular and encapsulated design structure, which separates the implementation of the loopback test interface from the main upper-layer business logic. This allows the switch from normal firmware operation mode to loopback test mode to retain the back-end processing architecture, by only appropriately modifying the initialization steps and replacing the callback functions of the flash controller's related register operations. This improves code reusability and compatibility, and reduces the difficulty and cost of code maintenance in subsequent firmware development.

[0031] Furthermore, the circular queue and bitmap mapping table implemented in software serve as containers to simulate the idle, triggering, and completion register behaviors of the flash controller. The time complexity of element access is O(1), meaning that the time to call these operation interfaces is fixed and predictable, and is usually significantly lower than the actual time to access the corresponding hardware registers. Therefore, it can be used to estimate the upper limit of CPU computing power in SSD controller chips, thus providing strong guidance for the analysis and improvement of performance indicators such as 4K random read command IOPS. Attached Figure Description

[0032] Figure 1 A flowchart illustrating the operation of reading the Available register in software simulation;

[0033] Figure 2 A flowchart illustrating the operation of writing to the trigger register in software.

[0034] Figure 3 This is a software simulation of the Slot Done register operation process. Detailed Implementation

[0035] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] This embodiment discloses a loopback test method for solid-state memory backend. This method simulates the behavior of the Available, Trigger, and Slot Done registers in the flash memory controller module in a software manner. Based on reusing most of the backend process code architecture in the firmware, the loopback test mode function is realized.

[0038] First, the behavior of the Available, Trigger, and SlotDone registers in the existing flash controller module is introduced: The flash controller internally consists of several key interactive interface components, including the Command Slot Pool, Status Slot Pool, Available Register, Trigger Register, and SlotDone Register. The Command Slot Pool is an SRAM memory space used to cache a certain number of flash read / write command configuration information (each channel of the flash controller typically has no more than 128 command slots), which are allocated and recycled sequentially from front to back. The Status Slot Pool is similar to the Command Slot Pool, also an SRAM memory space of the same size, used to store the command completion status at the corresponding sequence number in the Command Slot Pool. The Available Register is a read-only register indicating the next available command slot number and the number of available consecutive slots (maximum 4). If all command slots are in use, an invalid value (sequence number 0xFF, quantity 0) is returned instead. The trigger register acts as an activation switch. When enabled, it sends the command for the next available slot shown in the free register to the flash memory chip for execution. Each time this register is configured, one flash memory command is executed. The completion register is also read-only. When the flash memory controller receives a command execution completion signal from the flash memory chip, it fills the sequence number of that command in the slot pool into the completion register. The value of the completion register is 32 bits, while the command slot sequence number is only 8 bits, so it can hold 4 slot sequence numbers. That is, each time the completion register is read, a maximum of 4 slot sequence numbers can be retrieved simultaneously. The output of the completion register is one-time. That is, after retrieving a slot sequence number from it, repeated readings will not return the previous result, but will return the newly completed command slot sequence number (if no new command is completed in between, an invalid value 0xFF is output). An allocated and triggered slot sequence number will not reappear in the free register until it is removed from the completion register and reclaimed. (Note: Unlike the completion register, the output of the free register is not a one-time event; its value will remain unchanged until the command slot sequence number is triggered.)

[0039] In the normal execution flow of the backend, upon receiving a command message from the algorithm layer, the firmware first queries the free registers of the flash memory controller. If an available sequence number is found, the message is parsed and configuration information is filled into the corresponding command slot. Then, the trigger register is enabled to execute the command. If no available slot sequence number is found, the command execution attempt is skipped, and the firmware will re-evaluate the situation during the next polling of the free registers. The firmware periodically checks the completion register. When one or more valid slot sequence numbers are found, the firmware sequentially reads the completion status information of the corresponding sequence number command from the status slot pool and returns the result to the algorithm layer in the form of a message based on status information such as whether there are any errors. Overall, the main business process of the backend firmware can be summarized as alternating between the actions of "checking command messages and the free registers of the flash memory controller" and "checking the completion register and replying with status messages".

[0040] Based on the above hardware operating characteristics and backend firmware process, the relevant API callback interfaces for operating the flash controller's idle, trigger, and complete registers in the firmware program are overridden. The original direct access to the hardware register address is replaced with software logic, and the same register behavior model is established, thereby achieving the effect of loopback testing.

[0041] The core of this method is to construct two circular queue objects: an idle sequence number queue and an occupied sequence number queue. These queues store unused and in-use command slot numbers in a first-in, first-out (FIFO) order, simulating the flash memory controller's management algorithm for command slots. The data structure includes write / read pointers (element index subscripts), read / write tags (recent operation type), and an array of length sufficient to hold all slot numbers (element type has the same bit width as the slot number, i.e., 8 bits). When a slot number is added to (or removed from) a slot, the write pointer (or read pointer) increments cyclically (backtracking after reaching the boundary). The read / write tags are used to determine the container's full / empty state to prevent access overflow (when the read and write pointers are at the same position, if the last operation type was write, it is considered full; otherwise, it is considered empty; if the read and write pointer positions are different, it is neither empty nor full).

[0042] In addition, a bitmap mapping table is needed as an auxiliary to record and detect the allocation status of slot numbers (each bit represents the status of a slot number, true indicates occupied, false indicates idle) to prevent the error of duplicate numbers in the queue.

[0043] During firmware power-on initialization in backend loopback test mode, the idle sequence number queues of each channel are filled in sequentially increasing order starting from 0, the occupied sequence number queues are cleared, and the bitmap mapping table is also set to a fully idle state.

[0044] like Figure 1As shown, when the operation interface function for reading the free register is called, if the free sequence number queue is found to be empty, an invalid value (sequence number is 0xFF, quantity is 0) is returned; otherwise, the first element in the free sequence number queue is used as the starting sequence number (the element is not deleted), and the number of consecutive sequence numbers in the remaining elements is searched and returned as the result (up to 4 are checked).

[0045] like Figure 2 As shown, when the operation interface function for writing the trigger register is called, the status of the two circular queues is first checked. If the free sequence number queue is not empty and the occupied sequence number queue is not full, the first element in the free sequence number queue is taken out, and its status in the bitmap mapping table is checked (it should be in an unused state, i.e., the flag is false). Its status is then changed to used (the flag is true), and then it is moved to the end of the occupied sequence number queue and inserted. If an illegal condition that does not match the expected result occurs (the free sequence number queue is empty, the occupied sequence number queue is full, or there are duplicate elements in the queue, etc.), the program throws an exception and enters the assertion (ASSERT) state, indicating that there may be a design flaw in the firmware that does not operate the trigger register according to the correct process, and debugging is required.

[0046] like Figure 3 As shown, when the operation interface function for reading the completion register is called, the output is initially initialized to an invalid value (i.e., four invalid slot numbers 0xFF). Then, the element transfer operation between the occupied / free slot queues is repeatedly executed (up to four times, because the completion register can return a maximum of four slot numbers at a time). The specific steps are as follows: The filling status of the occupied slot queue is checked. If it is not empty, the first element is retrieved and its occupied status in the bitmap mapping table is checked (it should be in use, marked as true). Then, its status is changed to released (marked as false), and it is filled into the tail of the free slot queue. The slot number is added to the return result in order. At the same time, the slot information corresponding to the slot number in the status slot pool is modified in software to show that the execution was successful and error-free. If the occupied slot queue is detected to be empty in the loop, the loop ends early and the output result is returned. If an unexpected situation occurs during operation (duplicate elements in the occupied slot queue, the free slot queue is full, etc.), an exception is thrown and the system enters the assertion state.

[0047] By replacing the read idle and complete register and write trigger register callback interfaces with corresponding queue operation functions simulated by software, a complete loopback test function can be achieved.

[0048] The above description is merely the basic principle and preferred embodiment of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. A method for back-end loopback testing of solid-state memory, characterized in that: Construct two circular queues: an idle sequence number queue and an occupied sequence number queue. The two circular queues store the sequence numbers of unused and used command slots respectively in a first-in-first-out order, which is used to simulate the flash memory controller's management algorithm for command slots. During loopback testing, the read free register operation interface, read complete register operation interface, and write trigger register operation interface are replaced with software-simulated circular queue operations to achieve complete loopback testing functionality. Circular queue operations include: A. When calling the operation interface to read the free register, first check if the free sequence number queue is empty. If it is empty, return an invalid value. Otherwise, take the first element in the free sequence number queue as the starting sequence number, and search for the number of consecutive sequence numbers in the remaining elements of the free sequence number queue as the result and return it. B. When the operation interface for writing the trigger register is called, perform the following operations: B1. Determine whether the conditions of the free sequence number queue being non-empty and the occupied sequence number queue being non-full are met. If they are met, execute B2; otherwise, execute B4. B2. Take the first element from the idle sequence number queue, check the status of the command slot number corresponding to the first element of the idle sequence number queue. If the status is idle, execute B3; otherwise, execute B4. B3. Change the status of the command slot number corresponding to the first element of the idle sequence number queue to occupied, and then add the command slot number to the end of the occupied sequence number queue. B4. When the program throws an exception and enters the assertion state, it indicates that there may be a design flaw in the firmware and the trigger register is not being operated according to the correct procedure, requiring debugging. C. When the operation interface of reading the register is called, the output is initialized to an invalid value beforehand, and then the element transfer operation between the occupied / free sequence number queue is repeatedly executed.

2. The solid-state memory back-end loopback test method according to claim 1, characterized in that: The element transfer operation between occupied / free sequence number queues is as follows: C1. Determine if the queue of occupied sequence numbers is not empty. If it is, execute C2; ​​otherwise, execute C5. C2. Retrieve the first element of the occupied sequence number queue, check the status of the command slot number corresponding to the first element of the occupied sequence number queue. If the status is occupied and the free sequence number queue is not full, then execute C3; otherwise, execute C4. C3. Modify the status of the command slot number corresponding to the first element of the occupied sequence number queue to free, and add the command slot number to the end of the free sequence number queue and the output result; C4. The program throws an exception and enters the assertion state; C5. Return the output to the upper-level interface caller.

3. The solid-state memory back-end loopback test method according to claim 1 or 2, characterized in that: There are write pointers and read pointers used as indexes of elements in the free sequence number queue and the occupied sequence number queue, respectively. When a command slot number is added to the free sequence number queue or the occupied sequence number queue, the write pointer increments cyclically. When a command slot number is removed from the free sequence number queue or the occupied sequence number queue, the read pointer increments cyclically. After the read pointer or write pointer reaches the boundary position of the queue, it returns to the beginning.

4. The solid-state memory back-end loopback test method according to claim 3, characterized in that: The free queue and the occupied queue are labeled with operation type. The operation type label indicates the type of the most recent operation. The empty or full status of the free queue or the occupied queue is determined by combining the pointer position and the operation type label. When the read pointer and the write pointer are at the same position, if the last operation type was write, it is considered full. When the read pointer and the write pointer are at the same position, if the last operation type was read, it is considered empty. When the read pointer and the write pointer are at different positions, it is neither empty nor full.

5. The solid-state memory back-end loopback test method according to claim 1, characterized in that: The status of the command slot number is recorded through a bitmap mapping table. The bitmap mapping table has multiple bits, and each bit represents the status of a command slot number. True indicates that it is occupied, and false indicates that it is idle.

6. The solid-state memory back-end loopback test method according to claim 1, characterized in that: The command slot numbers are stored in an array. The length of the array is the sum of the widths of all command slot numbers, and the length of a single element in the array is the same as the width of a single command slot number.

7. The solid-state memory back-end loopback test method according to claim 1, characterized in that: When the firmware in the backend loopback test mode is powered on and initialized, the idle sequence number queue is filled and the occupied sequence number queue is cleared in ascending order starting from 0, and the allocation status of all command slot sequence numbers is set to a fully idle state.

8. The solid-state memory back-end loopback test method according to claim 1, characterized in that: The maximum number of consecutive numbers that can be searched in the remaining elements of the free sequence queue is 4.

9. The solid-state memory back-end loopback test method according to claim 1, characterized in that: When the idle sequence number queue is empty, the returned invalid value sequence number is 0xFF and the quantity is 0.

10. The solid-state memory back-end loopback test method according to claim 1, characterized in that: The element transfer operation between occupied and free sequence number queues can be performed a maximum of 4 times.

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