Solid state storage I / O scheduling system, method, solid state drive and electronic device

Abstract

This application applies to the field of integrated circuit technology, providing a solid-state storage I / O scheduling system, method, solid-state drive (SSD), and electronic device. The system includes an SSD and a processor. The SSD integrates a main control chip and a neural network processing unit, which are vertically interconnected. The processor is installed in the electronic device, and the SSD is connected to or installed inside the electronic device. The processor is configured to: extract feature data of read / write requests when generating read / write requests for the SSD; the neural network processing unit is configured to: read the feature data; read the memory state of the SSD from the main control chip; run a neural network learning model based on the memory state and feature data to obtain scheduling information for read / write requests; and the processor is configured to: read the scheduling information and schedule read / write requests based on the scheduling information. This system can improve the I / O performance of the SSD.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to a solid-state storage I / O scheduling system, method, solid-state drive and electronic device. Background Technology

[0002] I / O scheduling refers to the scheduling of read and write operation requests to improve overall system efficiency and resource utilization. Current operating systems perform I / O scheduling based solely on logical block address contiguousness or request size, without being aware of the internal physical state of the solid-state drive (SSD). However, the internal physical state of the SSD affects its data read and write efficiency. For example, the garbage collection process can impact data write efficiency. Summary of the Invention

[0003] In view of this, embodiments of this application provide a solid-state storage I / O scheduling system, method, solid-state drive, and electronic device to improve the I / O performance of solid-state drives.

[0004] A first aspect of this application provides a solid-state storage I / O scheduling system, including a solid-state drive (SSD) and a processor. The SSD integrates a main control chip and a neural network processing unit, which are vertically interconnected. The processor is installed in an electronic device, and the SSD is connected to or installed inside the electronic device.

[0005] The processor is configured to: extract feature data of the read / write request when generating the read / write request for the solid-state drive; The neural network processing unit is configured as follows: Read the feature data; Read the memory status of the solid-state drive from the main control chip; Based on the memory state and the feature data, a neural network learning model is run to obtain the scheduling information for the read / write requests. The processor is configured to: read the scheduling information and schedule the read / write requests based on the scheduling information.

[0006] In one possible implementation, the main control chip and the neural network processing unit are vertically stacked through through-silicon vias (TSVs). The neural network processing unit is used to read the flash memory conversion layer mapping table and the memory cell busy / idle status from the flash memory conversion layer status register of the main control chip through the TSVs. The mapping table and the memory cell busy / idle status are used to characterize the memory status.

[0007] In one possible implementation, the main control chip and the neural network processor have a shared memory space, which is mapped in a base address register, and the processor reads and writes to the shared memory space through memory mapping.

[0008] In one possible implementation, the processor is configured to: write the feature data into the shared memory space; and read the scheduling information from the shared memory space; The neural network processing unit is configured to: read the feature data from the shared storage space; and write the scheduling information into the shared storage space.

[0009] In one possible implementation, the scheduling information includes a hardware queue for the read / write request and an injection latency, and the processor is configured to: Based on the injection delay time, the order of the read and write requests in the hardware queue is determined; The read / write requests are inserted into the hardware queue according to the specified order.

[0010] In one possible implementation, the processor is further configured to: determine a reward value corresponding to the read / write request after the read / write request is executed, wherein the reward value is used to characterize the read / write efficiency of the read / write request; The neural network processing unit is configured as follows: Based on the reward value, the neural network weights in the neural network learning model are fine-tuned.

[0011] In one possible implementation, the processor is configured as follows: Determine the response time for the read / write request; If the response time is less than or equal to a preset dynamic latency threshold, the reward value is determined to be a positive reward value. The dynamic latency threshold is determined based on the average response time of multiple read and write requests. If the response time is greater than a preset dynamic delay threshold, then the reward value is determined to be a negative reward value.

[0012] A second aspect of this application provides a solid-state storage I / O scheduling method, including: When generating read / write requests for the solid-state drive, extract the feature data of the read / write requests; Obtain the memory status of the solid-state drive; Based on the memory state and the feature data, a neural network learning model is run to obtain the scheduling information for the read / write request; The read / write requests are scheduled according to the scheduling information.

[0013] A third aspect of this application provides a solid-state drive (SSD), characterized in that it includes a neural network processing unit. The SSD integrates a main control chip and the neural network processing unit, which are vertically interconnected. An electronic device performs I / O scheduling on the SSD using the method described in the second aspect above.

[0014] A fourth aspect of this application provides an electronic device including the solid-state storage I / O scheduling system described in any of the first aspects above.

[0015] A fifth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to perform the method described in the second aspect above.

[0016] Compared with the prior art, the embodiments of this application have at least the following advantages: This application can simultaneously schedule read and write requests based on the physical state of the solid-state drive (SSD) and the feature data of the read / write requests, thereby improving the I / O performance of the SSD. In the SSD I / O scheduling system of this application embodiment, the SSD integrates a main control chip and a neural network processing unit. The main control chip and the neural network processing unit are vertically interconnected, allowing the neural network processing unit to read the memory state from the main control chip. When generating read / write requests, the processor in the electronic device can extract the feature data of the read / write requests. The neural network processing unit has a neural network learning model, which uses the feature data and memory state as input to obtain the scheduling information for read / write requests. The scheduling information for read / write requests is obtained based on the memory state and feature data. Therefore, when scheduling read / write requests, the processor can consider both the physical state of the memory itself, thus avoiding read / write latency caused by the internal physical state of the memory, and the characteristics of the read / write requests themselves, meeting the needs of the read / write requests. The system in this application embodiment can optimize the scheduling of read / write requests, thereby improving the I / O performance of the SSD. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0018] Figure 1 This application provides a solid-state storage I / O scheduling system. Figure 2 This is a schematic diagram of a solid-state storage I / O scheduling method provided in an embodiment of this application; Figure 3 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] Existing operating system (OS)-level I / O (input / output) schedulers only schedule based on logical block address (LBA) contiguousness or request size, and cannot perceive the internal physical state of solid-state drives (SSDs). For example, the Linux operating system's I / O scheduler mq-deadline and BFQ scheduler cannot perceive the internal physical state of SSDs, such as garbage collection (GC) processes, wear leveling operations, and die / plane conflicts.

[0021] The internal physical state of a solid-state drive (SSD) affects data read / write efficiency. Each plane in an SSD contains a complete array of blocks, which can independently cache data. Planes perform programming / erase operations through the shared control logic of dies, leading to die / plane conflicts. Die / plane conflicts reduce parallelism, thus decreasing SSD read / write efficiency. The execution of the SSD's garbage collection process inevitably consumes hardware and software resources, competing with read / write requests and negatively impacting read / write efficiency, particularly data write efficiency. The wear and tear on the SSD affects the time taken to write data, thus affecting data read / write efficiency.

[0022] Existing I / O scheduling methods cannot perceive the internal physical state of the solid-state drive (SSD) during scheduling, which means they cannot take the internal physical state of the SSD into account during I / O scheduling, easily leading to low I / O efficiency.

[0023] Based on this, embodiments of this application provide a solid-state storage I / O scheduling system and method that can consider the internal physical state of the solid-state drive when performing I / O scheduling, thereby improving I / O efficiency.

[0024] The technical solution of this application will be described below through specific embodiments.

[0025] This application provides a solid-state storage I / O scheduling system, including a solid-state drive and a processor. The solid-state drive integrates a main control chip and a neural network processing unit (NPU). The main control chip and the neural network processing unit (NPU) are vertically interconnected. The processor is installed in an electronic device. The solid-state drive is connected to the electronic device or installed inside the electronic device.

[0026] Figure 1 This is a schematic diagram of a solid-state storage I / O scheduling system provided in an embodiment of this application, as shown below. Figure 1 As shown, the solid-state storage I / O scheduling system includes a solid-state drive 10 and a processor 20. The solid-state drive 10 may include a controller chip 101 and a neural network processing unit 102, wherein the controller chip 101 and the neural network processing unit 102 are vertically interconnected. In one possible implementation, a low-power neural network processing unit can be vertically integrated above the controller chip of the solid-state drive using 3D advanced packaging technology. The controller chip 101 and the neural network processing unit 102 can be vertically stacked using TSV (Through Silicon Via) or Hybrid Bonding technology. The controller chip die is responsible for flash memory control, error checking and correction (ECC), etc., while the neural network processing unit die is responsible for inference.

[0027] The aforementioned electronic devices may be mobile phones, tablets, wearable devices, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), etc. This application does not impose any restrictions on the specific type of electronic device.

[0028] The processor in an electronic device can generate read / write requests during execution. The processor can be divided into multiple processes, each of which can read data from or write data to the solid-state drive (SSD) during execution. When a process reads or writes data to the SSD, it can generate a read / write request.

[0029] The processor is configured to extract feature data of read / write requests when generating read / write requests for the solid-state drive.

[0030] The aforementioned neural network unit can be configured to: read feature data; read the memory state of the solid-state drive from the main control chip; and, based on the memory state and feature data, run a neural network learning model to obtain scheduling information for read and write requests.

[0031] The processor can also be configured to read scheduling information and schedule read / write requests based on the scheduling information.

[0032] For example, the aforementioned feature data may include the logical block address, size, operation type, process ID, queue depth, and / or current I / O arrival rate of the read / write request. The logical block address uniquely identifies the data block targeted by the read / write request; the size can be the data size to be read or written; the operation type can be read or write; the process ID can be the unique identifier of the process initiating the read / write request; the queue depth can include the upper limit of the number of incomplete read / write requests that each request queue can simultaneously handle; and the current I / O arrival rate can be the number of newly submitted read / write requests to the storage system's I / O request queue per unit time, used to quantify the frequency of I / O operations initiated by upper-layer applications or processes.

[0033] The feature data extracted by the processor can be stored in a pre-agreed storage location, so that the neural network processing unit can read the feature data from the pre-agreed storage location.

[0034] The aforementioned memory states can be used to characterize the internal physical state of the solid-state drive. The neural network processing unit is connected to the main controller chip, thus enabling it to read the memory states from the main controller chip. In one possible implementation, the main controller chip and the neural network processing unit are vertically stacked via through-silicon vias (TSVs). The neural network processing unit is used to read the Flash Translation Layer Mapping Table (FTL Mapping Table) and the busy / idle status of the memory cells from the flash translation layer status register of the main controller chip through the TSVs. The mapping table and the busy / idle status of the memory cells are used to characterize the memory states.

[0035] The Flash Translation Layer (FTL) mapping table is a core metadata structure maintained by the FTL in a solid-state chip. It records the dynamic mapping relationship between logical addresses and physical addresses, enabling address translation. The FTL mapping table can include garbage collection processes, wear leveling operations, and die / plane collisions. For example, it can include wear level fields that characterize the lifespan of physical blocks. These wear level fields can include Erase Count (EC) and Wear Level Marker fields. Based on these fields, the wear level of the corresponding data block can be determined.

[0036] In one possible implementation, the main control chip and the neural network processor share a common memory space, which is mapped in the base address register. The processor reads and writes to this shared memory space via memory mapping. The processor can be configured to write feature data to the shared memory space. When writing feature data to the solid-state drive (SSD), the processor can bypass the Non-Volatile Memory Express (NVMe) protocol, thereby reducing the cost and improving the efficiency of feature data writing to the SSD. After the feature data extracted by the processor is written to the shared memory space via memory mapping, the neural network processing unit can directly read the feature data from the shared memory space, improving the data reading efficiency of the neural network processing unit.

[0037] Based on this, neural network units can directly read data from memory when reading feature data and memory states, resulting in high data reading efficiency and thus improving the execution efficiency of neural network units.

[0038] The neural network processing unit can be deployed with a neural network model, which can be a pre-trained scheduling optimization model. The neural network processing unit inputs feature data and reads the memory state into the neural network model to obtain scheduling information, which is then written to the shared memory space. The processor can be configured to read scheduling information from the shared memory space. The processor can read scheduling information through memory mapping, thereby improving the efficiency of reading scheduling information.

[0039] In one possible implementation, the scheduling information includes the hardware queue of read / write requests and the injection latency, and the processor can be configured as follows: The order of read and write requests in the hardware queue is determined based on the injection delay time; Read and write requests are inserted into the hardware queue in sequence.

[0040] The scheduling information of the neural network processing unit can include hardware queue identifiers and delay times. The processor can distribute read / write requests to specific NVMe hardware queues (Submission Queues) or adjust the insertion order within the queues based on the scheduling information generated by the neural network processing unit. For example, if the neural network processing unit predicts that a certain read / write request will trigger long-tail garbage collection, it can postpone processing that read / write request, prioritizing smaller read / write requests to improve read / write efficiency and avoid the accumulation of read / write requests caused by long-tail garbage collection processes. For instance, the scheduling information could be: Assign to Queue #3, Delay 5us. Based on this scheduling information, the processor can allocate read / write requests to hardware queue #3, determine the order of read / write requests in the queue based on the 5us delay, and insert the read / write request into the corresponding position in hardware queue #3.

[0041] In one possible implementation, the processor is further configured to: determine the reward value corresponding to the read / write request after the read / write request is executed, the reward value being used to characterize the read / write efficiency of the read / write request; The neural network processing unit is configured as follows: Based on the reward value, fine-tune the neural network weights in the neural network learning model.

[0042] The neural network learning model of the neural network processing unit can be updated online. After a batch of read and write requests are completed, the neural network weights in the neural network learning model can be adjusted based on whether the scheduling information of the requesting network processing unit improves the efficiency of the read and write requests, thereby improving the scheduling optimization performance of the neural network learning model.

[0043] In one possible implementation, the processor is configured as follows: Determine the response time for read and write requests; If the response time is less than or equal to the preset dynamic latency threshold, the reward value is determined to be a positive reward value. The dynamic latency threshold is determined based on the average response time of multiple read and write requests. If the response time exceeds the preset dynamic delay threshold, the reward value is determined to be a negative reward value.

[0044] Specifically, the processor can include a driver program that can track the latency of read / write requests, which can be the response time mentioned above. After determining the corresponding reward value based on the response time, the driver program can write the reward value back to the neural network processing unit via an out-of-band channel or a dedicated NVMe Vendor Command. The neural network processing unit can then utilize the gradient engine in the upper SRAM to fine-tune the neural network weights based on the reward value, thereby updating the neural network learning model and improving model performance.

[0045] In this embodiment, a low-power neural network processing unit is vertically integrated above the main controller chip of the solid-state drive using advanced 3D packaging technology. Through the vertical stacking of the main controller chip and the neural network processing unit, extremely high-bandwidth, extremely low-latency inter-chip communication can be achieved between the neural network processing unit and the active chip. The neural network processing unit can directly read the extremely high-bandwidth, extremely low-latency inter-chip communication within the main controller chip. It can also directly read the FTL mapping table and die busy / idle status within the main controller chip as model input, without needing to go through Dynamic Random Access Memory (DRAM), thereby improving the efficiency of reading internal state data.

[0046] In this embodiment, a shared storage space is established between the main control chip and the neural network processing unit. The processor reads and writes in the shared storage space through memory mapping, so that the processor can quickly write the feature data of the read / write request into the shared storage space, and the neural network processing unit can quickly read the feature data from the shared storage space.

[0047] Based on feature data and internal state data, the neural network processing unit generates scheduling information. The scheduling information generated by the neural network generation unit can simultaneously take into account the read / write request itself and the internal physical state of the solid-state drive (SSD). Therefore, it schedules read / write requests based on the scheduling information, which is equivalent to taking the internal state of the SSD into account in the read / write request, thereby optimizing the scheduling of read / write requests and improving read / write efficiency.

[0048] Furthermore, in this embodiment, the model in the neural network unit can be optimized based on the execution status of read and write requests, thereby further improving model performance, enhancing the scheduling and optimization capabilities of the neural network unit, and thus improving read and write efficiency.

[0049] Reference Figure 2 This illustration shows a flowchart of another solid-state storage I / O scheduling method provided in an embodiment of this application, which may specifically include the following steps: S201, when generating a read / write request for the solid-state drive, extract the feature data of the read / write request.

[0050] The method in this embodiment can be applied to electronic devices, which may include processors. Solid-state drives (SSDs) may be built into or external to the electronic devices, and the electronic devices may read and write data to the SSDs.

[0051] The read / write requests mentioned above can include data read requests and data write requests. Data read requests are used to read data from the solid-state drive (SSD), and data write requests are used to write data to the SSD.

[0052] The aforementioned characteristic data may include logical block address, size, operation type, process ID, queue depth, and current I / O arrival rate. Specifically, the logical block address uniquely identifies the data block targeted by the read / write request; the size can be the data size to be read or written; the operation type can be read or write; the process ID is the unique identifier of the process initiating the read / write request; the queue depth can include the upper limit of the number of incomplete read / write requests that each request queue can simultaneously handle; and the current I / O arrival rate is the number of newly submitted read / write requests to the storage system's I / O request queue per unit time, used to quantify the frequency of I / O operations initiated by upper-layer applications or processes.

[0053] In one possible implementation, the electronic device can intercept block I / O at the block layer. (BIO) requests, and extract the characteristic data of read and write requests from block I / O requests.

[0054] S202, Obtain the memory status of the solid-state drive.

[0055] The aforementioned memory states can be used to characterize the internal physical state of the solid-state drive (SSD). The neural network processing unit is connected to the main controller chip, allowing it to read the memory states from the main controller chip. In one possible implementation, the main controller chip and the neural network processing unit are vertically stacked via through-silicon vias (TSVs). The neural network processing unit reads the flash memory translation layer mapping table and the memory cell busy / idle status from the flash memory translation layer status register of the main controller chip through the TSVs. The mapping table and the memory cell busy / idle status are used to characterize the memory states.

[0056] The flash translation layer mapping table is a core metadata structure maintained by the flash translation layer in a solid-state chip. It records the dynamic mapping relationship between logical addresses and physical addresses, enabling address translation. The flash translation layer mapping table can include garbage collection processes, wear leveling operations, and die / plane conflicts. For example, it can include wear level fields, which characterize the lifespan of physical blocks. These wear level fields can include erase count fields and wear level marker fields. Based on these fields, the wear level of the corresponding data block can be determined.

[0057] S203, based on the memory state and the feature data, run a neural network learning model to obtain the scheduling information of the read / write request.

[0058] The neural network processing unit can contain a neural network learning model, which can be a trained scheduling optimization model. The model input consists of feature data and memory state. The neural network processing unit reads the memory state from the main control chip and the feature data from the shared memory space, and then inputs the feature data and memory state into the model. Based on the input data, the model can perform inference to obtain the scheduling information for the read / write request.

[0059] The processor can write feature data sources to the inference input area of ​​the PCIe BAR space. The neural network processing unit performs inference in conjunction with the internal state of the solid-state drive and writes the results (such as the suggested hardware queue ID and the suggested latency in microseconds) to the inference output area.

[0060] S204, The read / write request is scheduled according to the scheduling information.

[0061] The scheduling information may include the hardware queue of read and write requests and the injection delay time. The processor can determine the order of read and write requests in the hardware queue based on the injection delay time, and insert the read and write requests into the hardware queue according to the order.

[0062] In this embodiment, the method described in this application can be executed in the electronic device through a self-developed driver. The driver can establish a high-speed channel with the neural network processing unit through PCIe BAR space mapping or NVMe CMB (Controller Memory Buffer). The driver can send the feature data of read / write requests to the neural network processing unit, which predicts the optimal processing queue or latency strategy for the read / write request under the current device state based on a reinforcement learning (RL) model. The driver rearranges the read / write requests according to the output of the neural network processing unit, and sends the actual latency back to the neural network processing unit as a feedback signal after the read / write request is completed, thereby realizing the online evolution of the model. This embodiment can use a polling or doorbell mechanism to achieve microsecond-level interaction.

[0063] In this embodiment, the neural network processing unit does not participate in data storage, but is used to coordinate the scheduling of read and write requests. Existing compute-grade storage (such as Samsung Smart SSDs) is mainly used for processing data within the SSD (such as accelerating database queries). This application utilizes the computing power within the SSD to optimize host-side scheduling, which is a reverse control flow and represents an architectural innovation.

[0064] Compared to existing intelligent FTL (Framework Timer) within SSDs, which only queues read / write requests after they arrive at the SSD and cannot change the timing and queue distribution of read / write requests issued by the host, this application intervenes before read / write requests are issued (Predispatch Optimization), offering greater optimization potential.

[0065] The embodiments of this application achieve high-bandwidth, low-latency inter-chip communication through 3D packaging, which can meet the real-time requirement (microsecond level) that each read and write request must infer.

[0066] Furthermore, embodiments of this application can also perform model updates based on a closed-loop feedback mechanism. Embodiments of this application construct a reinforcement learning closed loop across the PCIe link: the host perceives the execution result of read / write requests, and updates the model of the neural network processing unit based on this execution result, solving the problems of difficult acquisition of training data and poor scene adaptability in traditional models. Here, the host refers to the aforementioned electronic device.

[0067] It should be noted that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0068] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 3As shown, the electronic device 4 in this embodiment includes: at least one processor 3032 ( Figure 3 (Only one is shown in the diagram) a processor, a solid-state memory 3031, and a computer program 303 stored in the solid-state memory 3031 and executable on the at least one processor 3032, wherein the processor 3032 executes the computer program 303 to implement the steps in any of the above method embodiments.

[0069] The electronic device 4 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud-based electronic device. This electronic device may include, but is not limited to, a processor 3032 and a solid-state memory 3031. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 4 and does not constitute a limitation on electronic device 4. It may include more or fewer components than shown, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0070] The processor 3032 may be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0071] In some embodiments, the solid-state memory 3031 can be an internal storage unit of the electronic device 4, such as a hard disk or memory of the electronic device 4. In other embodiments, the solid-state memory 3031 can also be an external storage device of the electronic device 4, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 4. Furthermore, the solid-state memory 3031 can include both internal and external storage units of the electronic device 4. The solid-state memory 3031 is used to store operating systems, applications, bootloaders, data, and other programs, such as the program code of computer programs. The solid-state memory 3031 can also be used to temporarily store data that has been output or will be output.

[0072] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0073] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0074] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A solid-state storage I / O scheduling system, characterized in that, The device includes a solid-state drive (SSD) and a processor. The SSD integrates a controller chip and a neural network processing unit, which are vertically interconnected. The processor is installed in the electronic device, and the SSD is connected to or installed inside the electronic device. The processor is configured to: extract feature data of the read / write request when generating the read / write request for the solid-state drive; The neural network processing unit is configured as follows: Read the feature data; Read the memory status of the solid-state drive from the main control chip; Based on the memory state and the feature data, a neural network learning model is run to obtain the scheduling information for the read / write requests. The processor is configured to: read the scheduling information and schedule the read / write requests based on the scheduling information.

2. The system as described in claim 1, characterized in that, The main control chip and the neural network processing unit are vertically stacked through through-silicon vias. The neural network processing unit is used to read the flash memory conversion layer mapping table and the memory unit busy / idle status from the flash memory conversion layer status register of the main control chip through the through-silicon via. The mapping table and the memory unit busy / idle status are used to characterize the memory status.

3. The system as described in claim 1 or 2, characterized in that, The main control chip and the neural network processor share a common memory space, which is mapped in the base address register. The processor reads and writes to the common memory space through memory mapping.

4. The system as described in claim 3, characterized in that, The processor is configured to: write the feature data into the shared storage space; and read the scheduling information from the shared storage space; The neural network processing unit is configured to: read the feature data from the shared storage space; and write the scheduling information into the shared storage space.

5. The system as described in claim 1, characterized in that, The scheduling information includes the hardware queue and injection latency of the read / write requests, and the processor is configured to: Based on the injection delay time, the order of the read and write requests in the hardware queue is determined; The read / write requests are inserted into the hardware queue according to the specified order.

6. The system according to any one of claims 1-2 or 4-5, characterized in that, The processor is further configured to: after the read / write request is executed, determine a reward value corresponding to the read / write request, wherein the reward value is used to characterize the read / write efficiency of the read / write request; The neural network processing unit is configured as follows: Based on the reward value, the neural network weights in the neural network learning model are fine-tuned.

7. The system as described in claim 6, characterized in that, The processor is configured to: Determine the response time for the read / write request; If the response time is less than or equal to a preset dynamic latency threshold, the reward value is determined to be a positive reward value. The dynamic latency threshold is determined based on the average response time of multiple read and write requests. If the response time is greater than a preset dynamic delay threshold, then the reward value is determined to be a negative reward value.

8. A solid-state storage I / O scheduling method, characterized in that, include: When generating read / write requests for the solid-state drive, extract the feature data of the read / write requests; Obtain the memory status of the solid-state drive; Based on the memory state and the feature data, a neural network learning model is run to obtain the scheduling information for the read / write request; The read / write requests are scheduled according to the scheduling information.

9. A solid-state drive, characterized in that, The solid-state drive includes a neural network processing unit. The solid-state drive integrates a main control chip and a neural network processing unit. The main control chip and the neural network processing unit are vertically interconnected. The electronic device performs I / O scheduling on the solid-state drive using the method described in claim 8.

10. An electronic device, characterized in that, Includes the solid-state storage I / O scheduling system according to any one of claims 1-7.

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