Distributed wireless terminal signal blanking system and method

Abstract

The application relates to the technical field of wireless communication, in particular to a distributed wireless terminal signal shielding system and method. The system comprises an access unit, at least one expansion unit and multiple covering units, the units are connected through multi-core communication cables for simultaneously transmitting digital communication signals, periodic global clock reference signals and device identification information. The access unit collects source information of surrounding base stations and TDD frame header offset values, and sends the global clock to the expansion unit; the expansion unit forwards the information to the corresponding covering unit; the covering unit generates digital interference signals based on the source information, combines the global clock and the frame offset to accurately determine the TDD downlink time slot for interference emission, and automatically switches to a local synchronization mode when detecting that the global clock is inaccurate, and maintains the interference continuity by listening to the air interface synchronization signal. The system realizes low cost, easy deployment and high synchronization reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a distributed wireless terminal signal shielding system and method. BACKGROUND

[0002] With the increasing demand for high cost performance, easy deployment of distributed mobile phone signal shielding system in scenarios such as examination room and confidential meeting room, it is necessary to significantly reduce the system hardware cost and construction complexity under the premise of ensuring the synchronization accuracy of time division duplex (TDD) system. The existing technology usually adopts a highly centralized architecture with access unit as the core, which completes the multi-band base station signal acquisition, demodulation and interference signal generation by the access unit, and transmits the complete radio frequency interference signal to the expansion unit and coverage unit through coaxial cable and optical fiber respectively.

[0003] This method requires the access unit to be equipped with a large number of high-performance field programmable gate arrays (FPGA), multi-channel analog / digital converters and complex baseband processing modules, and the expansion unit must be configured with wideband optoelectronic conversion devices to support optical fiber transmission of multi-band radio frequency signals, resulting in high system hardware cost; at the same time, the optical fiber link has strict restrictions on wiring technology (such as bending radius, fusion accuracy), which significantly increases the difficulty of engineering deployment and construction cost; in addition, the coverage unit only acts as a passive amplification node and does not have local frame synchronization capability, completely relying on the clock and interference waveform issued by the center node, when the transmission delay or clock jitter exceeds the tolerance threshold, it cannot maintain the precise interference of TDD downlink time slot autonomously, which may cause interference failure or misinterference of uplink.

[0004] Therefore, the system architecture in the prior art is highly centralized, relies on expensive radio frequency level optical fiber transmission, and the coverage end lacks autonomous synchronization capability, resulting in the problems of high overall cost, difficult deployment and insufficient synchronization reliability, which need to be solved urgently. SUMMARY

[0005] The main purpose of the present application is to provide a distributed wireless terminal signal shielding system and method, which aims to solve the technical problems of high overall cost, difficult deployment and insufficient synchronization reliability caused by the highly centralized system architecture, reliance on expensive radio frequency level optical fiber transmission and lack of autonomous synchronization capability of the coverage end in the prior art.

[0006] In order to achieve the above-mentioned application purpose, the first aspect of the present application provides a distributed wireless terminal signal shielding system, which comprises an access unit, at least one expansion unit and a plurality of coverage units; the access unit and the expansion unit are connected through a multi-core communication cable, and the expansion unit and each coverage unit are connected through a multi-core communication cable; the multi-core communication cable is used to simultaneously transmit digital communication signals, periodic global clock reference signals and device identification information;

[0007] The access unit is configured to collect source information of wireless base stations around a target area, the source information including carrier system and corresponding carrier frequency of each communication frequency band, perform air interface synchronization on a time division duplex (TDD) communication system to obtain a frame header offset value, and send the source information, the frame header offset value, and the periodic global clock reference signal to the expansion unit through the multi-core communication cable.

[0008] The expansion unit is configured to receive the source information, the frame header offset value, and the global clock reference signal from the access unit, and forward the source information, the frame header offset value, and the global clock reference signal to a corresponding coverage unit.

[0009] The coverage unit is configured to receive the source information, the frame header offset value, and the global clock reference signal, generate a digital interference signal for each communication frequency band based on the source information, determine a downlink time slot of a TDD communication system based on a periodic reference of the global clock reference signal and the frame header offset value, and transmit the digital interference signal in the determined downlink time slot, monitor timing stability of the global clock reference signal, and switch to a local synchronization mode when it is determined that the global clock reference signal is out of alignment, obtain base station frame structure information by listening to a base station synchronization signal in an air interface, and re-determine a TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signal.

[0010] Further, the multi-core communication cable is a standard Ethernet cable containing at least four pairs of twisted wires; wherein a first pair of twisted wires is used to transmit serial communication data, a second pair of twisted wires is used to transmit the global clock reference signal in differential form, and at least one of the remaining twisted wires is used to transmit a hardware address code of the coverage unit.

[0011] Further, the coverage unit is configured to obtain a measured period by measuring a time interval between adjacent pulses of the global clock reference signal, and calculate a deviation of the measured period from a nominal period; when absolute values of the deviation of X consecutive periods are all greater than a preset threshold ΔT, it is determined that the global clock reference signal is out of alignment.

[0012] Further, ΔT is 5 microseconds and X is 3.

[0013] Further, in the local synchronization mode, the coverage unit is configured to receive an air interface signal through a built-in antenna, extract a primary synchronization signal (PSS) and a secondary synchronization signal (SSS) therefrom, demodulate a starting time of a base station radio frame, and use the starting time of the base station radio frame as a timing reference for local interference transmission.

[0014] Further, the covering unit is configured to automatically switch back to the interference transmission mode controlled by the global clock reference signal when the period deviation of the global clock reference signal is continuously detected to satisfy |deviation|≤ΔT for y consecutive periods.

[0015] Further, the covering unit comprises a programmable logic device and a digital-to-analog converter; the programmable logic device is configured to synthesize digital interference signals of each communication frequency band in real time according to the source information; and the digital-to-analog converter is configured to convert the digital interference signals into analog radio frequency signals and transmit the analog radio frequency signals through a power amplifier.

[0016] Further, the programmable logic device is configured to load a waveform template file from a non-volatile memory, wherein the waveform template file contains pilot interference sequences for different communication systems and corresponding carrier frequencies; and the waveform template file can be updated remotely by the access unit through the multi-core communication cable to realize online upgrading.

[0017] Further, the access unit is configured to transmit the source information and the frame header offset value to the extension unit through a half-duplex serial communication protocol running on a pair of dedicated twisted pairs of the multi-core communication cable.

[0018] The second aspect of the present application further provides a distributed wireless terminal signal shielding method, applied to the covering unit in the system as claimed in any one of the above aspects, comprising the following steps:

[0019] receiving wireless base station source information, TDD frame header offset value and periodic global clock reference signal from the extension unit;

[0020] generating digital interference signals of each communication frequency band based on the source information;

[0021] determining a TDD downlink time slot based on a period reference of the global clock reference signal and the frame header offset value, and transmitting the digital interference signals in the determined downlink time slot;

[0022] monitoring timing stability of the global clock reference signal;

[0023] when it is determined that the global clock reference signal is out of alignment, switching to a local synchronization mode, obtaining base station frame structure information by listening to base station synchronization signals in the air interface, and re-determining a TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signals.

[0024] The third aspect of the present application further comprises a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method as claimed in any one of the above aspects when executing the computer program.

[0025] The fourth aspect of the present application further includes a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any one of the above.

[0026] Advantages

[0027] The present application can effectively solve the problems of high system cost, difficult deployment and insufficient synchronization reliability caused by high centralization of architecture, dependence on radio frequency level optical fiber transmission and lack of autonomous synchronization capability of coverage end in the prior art. By decentralizing the interference signal generation to the coverage unit, the access unit only transmits lightweight source parameters and clock reference signals, without the need for wideband radio frequency transmission, thereby eliminating expensive optical fiber links and optoelectronic conversion modules; using a multi-core communication cable to multiplex transmit data, clock and address information, significantly reducing hardware cost and construction complexity; at the same time, the coverage unit has a global / local dual-mode synchronization mechanism, which can independently listen to the base station synchronization signal and maintain accurate interference when the global clock is inaccurate, ensuring the continuity and accuracy of TDD downlink time slot interference, and fundamentally improving the economy, deployability and synchronization robustness of the system. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A structural schematic block diagram of a distributed wireless terminal signal shielding system according to an embodiment of the present application;

[0029] Figure 2 A flowchart of a distributed wireless terminal signal shielding method according to an embodiment of the present application;

[0030] Figure 3 A structural schematic block diagram of a computer device according to an embodiment of the present application.

[0031] The implementation of the present application, functional features and advantages will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0033] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is further understood that the terms "comprise" and "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, modules, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, modules, components, and / or groups thereof. It is further understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. Furthermore, "connected" or "coupled" as used herein can include wirelessly connected or wirelessly coupled. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. It is further understood that the terms "comprise" and "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, modules, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, modules, components, and / or groups thereof. It is further understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. Furthermore, "connected" or "coupled" as used herein can include wirelessly connected or wirelessly coupled. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Reference Figure 1 The embodiment of the present application provides a kind of distributed wireless terminal signal shielding system, including access unit, at least one extension unit and multiple coverage units;Between the access unit and the extension unit, and between the extension unit and each coverage unit, it is connected by multicore communication cable;The multicore communication cable is used to simultaneously transmit digital communication signal, periodic global clock reference signal and equipment identification information;

[0036] The access unit is used to: collect the source information of the wireless base station around target area, the source information includes the carrier system and corresponding carrier frequency point of each communication frequency band, air interface is synchronized to TDD communication system to obtain frame header offset value, and the source information, the frame header offset value and the periodic global clock reference signal are sent to the extension unit by the multicore communication cable;

[0037] The extension unit is used to: receive the source information, the frame header offset value and the global clock reference signal from the access unit, and forward the source information, the frame header offset value and the global clock reference signal to corresponding coverage unit;

[0038] The covering unit is configured to: receive the source information, the frame header offset value and the global clock reference signal; generate a digital interference signal for each communication frequency band based on the source information; determine a downlink time slot of the TDD communication system based on a period reference of the global clock reference signal and the frame header offset value, and transmit the digital interference signal in the determined downlink time slot; monitor the timing stability of the global clock reference signal, and when it is determined that the global clock reference signal is out of alignment, switch to a local synchronization mode, acquire base station frame structure information by listening to a base station synchronization signal in an air interface, and redetermine a TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signal.

[0039] As described above, the prior art generally adopts a centralized architecture, in which the access unit is connected to the expansion unit through a coaxial cable, and the signal is transmitted to the covering unit through an optical fiber. Specifically, the access unit integrates a high-performance field programmable gate array (FPGA), a multi-channel analog-to-digital / digital-to-analog converter (ADC / DAC), and a complex baseband processing module, which is responsible for collecting source information of base stations around the target area and completing the synthesis and modulation of interference signals for each communication frequency band. The generated wideband radio frequency interference signal is transmitted to the expansion unit through a coaxial cable after power amplification; the expansion unit acts as a relay node to perform optical-to-electrical conversion on the signal and then distribute it to each covering unit through an independent optical fiber link. The covering unit itself only contains an optical-to-electrical converter and a radio frequency power amplifier and does not have the ability to generate local signals, completely relying on the interference waveform and clock synchronization issued by the central node. This architecture has the following technical defects:

[0040] High hardware cost: the access unit needs to be equipped with a large number of high-performance DA chips and complex baseband engines, and the expansion unit needs to be configured with wideband optical-to-electrical conversion devices, significantly increasing the overall cost;

[0041] Large deployment difficulty: optical fiber wiring has strict requirements on bending radius and fusion precision, and is complex to construct and susceptible to environmental influences leading to link interruption;

[0042] Poor synchronization reliability: the covering unit has no independent synchronization capability, and once the optical fiber link has delay fluctuations or clock jitter exceeding the tolerance threshold, it cannot adjust the interference time slot in time, which may result in interference failure or false interference of the uplink.

[0043] This approach requires high-performance hardware components and complex wiring work, resulting in high cost and great deployment difficulty, and has reliability problems in synchronization.

[0044] As Figure 1As shown, the system adopts a three-level cascade topology, including an access unit, at least one expansion unit and multiple coverage units, which are connected in turn through multi-core communication cables to form a tree-shaped deployment network. Unlike traditional centralized architecture, the system decentralizes the interference signal generation and TDD time slot control functions to the coverage units, and the access unit is only responsible for collecting base station source parameters and distributing high-precision global clock reference signals and frame header offset values, which are forwarded to the coverage units via the expansion unit. As a result, the system does not need to transmit wideband radio frequency interference signals, but instead uses ordinary multi-core communication cables to multiplex digital communication, synchronous clock and device address information, uses existing comprehensive wiring infrastructure, does not need professional optical fiber fusion, significantly reduces hardware cost and engineering deployment complexity, and ensures interference reliability through the dual-mode synchronization mechanism of the coverage unit.

[0045] The access unit, as the system master node, is deployed in the weak current room at the edge of the shielded area, and its output is connected to the input of the expansion unit through a multi-core communication cable. This unit contains a wideband frequency sweep receiving module, a baseband processing FPGA and a main controller. In operation, it first performs full-frequency scanning on the 2G / 3G / 4G / 5G frequency bands around the target area, and analyzes the carrier system (such as LTE, NR-TDD) and the corresponding carrier frequency (such as 1880MHz, 2635MHz) used by each communication frequency band. For TDD systems, the access unit detects the phase relationship of the primary synchronization signal (PSS) and the secondary synchronization signal (SSS) in multiple consecutive wireless frames through air interface synchronization algorithm, and calculates the frame header offset value (accuracy ±0.5μs) relative to the local 10ms frame boundary. Then, the source information, frame header offset value and periodic global clock reference pulse generated every 10ms are sent to the expansion unit through the multi-core communication cable. Since only low-speed digital parameters (typical rate <10kbps) are transmitted instead of GHz-level radio frequency signals, the access unit does not need to configure multi-channel high-speed DA converters and complex radio frequency synthesis links, and the hardware cost is significantly reduced.

[0046] The extension unit, as a relay node, has its input end connected to the access unit and its output end connected to each coverage unit through a multi-core communication cable, thereby playing a role of signal distribution hub. The unit contains a serial data receiver, a clock buffer and address decoding logic. It continuously receives data stream and clock pulses from the access unit and performs directional forwarding according to the hardware address code of the coverage unit (hardwired through a reserved wire pair in the cable). Specifically, the extension unit can contain a clock buffer / re-drive circuit for receiving a global clock reference signal, shaping, amplifying and low-jitter distribution; this can be achieved through the hardware components of the extension unit, such as a low-voltage differential signal receiver + fan-out buffer. For example, in a deployment containing 8 coverage units, the extension unit routes information to the target coverage unit according to address bits "0001" to "1000", avoiding broadcast conflicts. This design not only simplifies the wiring topology, but also supports flexible expansion while ensuring that the clock signal jitter received by each coverage unit is controllable (measured < 2us), providing a basis for subsequent accurate interference.

[0047] The coverage unit, as an execution terminal, is directly deployed facing the shielded space, has its input end connected to the extension unit and is internally provided with programmable logic devices (high-speed digital-to-analog converters, power amplifiers and multi-frequency antennas). The unit first receives source information, frame header offset value and global clock reference signal; then, the FPGA loads the corresponding pilot interference sequence template (such as LTE CRS, NR DMRS) of the system from the non-volatile memory, synthesizes digital interference signals of each frequency band in real time; based on the 10ms period reference of the global clock and the frame header offset value, the start and end time of the TDD downlink subframe (such as downlink #1-#6) is accurately calculated, and interference is transmitted within the window. At the same time, the coverage unit continuously monitors the interval between adjacent pulses of the global clock, and when the absolute value of the deviation of 3 consecutive periods is greater than 5 microseconds (which can be adjusted according to the actual application scenario), it is determined that the clock is out of alignment, and automatically switches to the local synchronization mode: through the built-in antenna, the PSS / SSS signal is extracted, the start time of the base station radio frame is demodulated, and the downlink time slot is re-determined based on this as a reference, and interference continues to be transmitted. This dual-mode mechanism effectively solves the synchronization failure problem caused by cable interference or transmission delay, ensuring the continuous and reliable operation of the system in complex electromagnetic environments.

[0048] Unlike the mode of "access unit generating complete radio frequency signal → optical fiber transmission → coverage unit passive amplification" in the prior art, the present application downshifts the interference signal generation function to the coverage unit, and the access unit is only responsible for collecting source parameters and distributing lightweight control information and high-precision global clock reference signals.

[0049] The access unit sends source information, a TDD frame header offset value and a periodic global clock reference signal to the expansion unit through a multi-core communication cable (such as a standard Ethernet cable, referred to as a network cable), without transmitting a wideband radio frequency signal; the expansion unit forwards the above parameters to the coverage unit; after receiving the above parameters, the coverage unit uses a local FPGA to synthesize a digital interference signal in real time, and accurately controls TDD downlink time slot transmission based on the global clock and the frame offset. At the same time, the coverage unit has a dual-mode synchronization capability: when the global clock is inaccurate, it can automatically switch to a local synchronization mode, obtain base station frame structure information by listening to the air interface, and maintain interference continuity.

[0050] Compared with the prior art, the present application has the following advantages:

[0051] Significantly reduce hardware cost: eliminate the multi-channel DA and complex baseband processing module of the access unit, and avoid expensive optical-electric conversion equipment;

[0052] Simplify engineering deployment: use ordinary multi-core communication cables instead of optical fibers and coaxial cables, support plug and play, and construction is convenient;

[0053] Improve synchronization robustness: the coverage unit has local synchronization capability, can operate automatically in the event of central link failure, and ensures the effectiveness of interference.

[0054] In summary, the present application realizes low cost, easy deployment and high reliability through function decentralization and communication multiplexing, effectively overcoming the core defects in the prior art.

[0055] In an embodiment, in the present embodiment, the multi-core communication cable uses an Ethernet cable (such as a Category 5 Enhanced cable (Cat5e) or a Category 6 cable (Cat6)) that meets industry standards, which contains at least four twisted pairs (a total of eight cores) inside, used to build a low-cost, high-reliability physical connection between the access unit, the expansion unit and the coverage unit. Unlike traditional Ethernet, which is only used to transmit network data, the present embodiment redefines the functions of each twisted pair in the cable, enabling parallel multiplexing transmission of three types of key signals: digital communication signals, periodic global clock reference signals and device identification information, in the same cable, thereby avoiding the need to lay additional dedicated clock lines, address lines or optical fibers, significantly simplifying the system structure and reducing deployment costs.

[0056] Specifically, the first pair of twisted-pair wires (e.g. line No. 1 / 2 as defined in the Telecommunications Industry Association / Electronic Industries Alliance 568-B standard (TIA / EIA-568-B)) is configured as a serial communication channel, running a custom half-duplex Universal Asynchronous Receiver / Transmitter (UART) protocol, with a baud rate settable to 115200 bits per second (bps), for transmitting source information generated by the access unit (including the carrier system employed in each communication band, such as Global System for Mobile Communications (GSM), Time Division-Synchronous Code Division Multiple Access, Time Division Duplex Long Term Evolution, New Radio, etc., as well as the corresponding center frequency, such as 900 megahertz (MHz), 1880 MHz, 2635 MHz, and Time Division Duplex (TDD) frame header offset values). This channel adopts a data frame format with parity check, ensuring reliable transmission of control parameters over a distance of hundreds of meters.

[0057] The second pair of twisted-pair wires (e.g. line No. 3 / 6) is dedicated to transmitting a periodic global clock reference signal in differential form. This signal is generated by dividing the frequency of an internal high-stability crystal oscillator in the access unit, with a typical period of 10 milliseconds (corresponding to the TDD radio frame length), and is driven at low-voltage differential signal (LVDS) or Recommended Standard 422 (RS-422) differential level, with the rising edge jitter controlled within ±1 microsecond. Differential transmission effectively suppresses common-mode noise, ensuring timing accuracy over long distances and meeting the technical requirement that the synchronization error does not exceed 5 microseconds under TDD downlink interference.

[0058] At least one of the remaining twisted-pair wires (e.g. line No. 4 / 5 and line No. 7 / 8) is used to transmit the hardware address encoding of the coverage unit. In a typical deployment, if the system contains no more than 4 coverage units, only line No. 4 and line No. 5 can be used: for example, line No. 4 is connected to ground and line No. 5 is connected to the supply voltage (VCC), representing the address "01", corresponding to coverage unit No. 2; both lines are connected to ground, representing "00", corresponding to coverage unit No. 1. In larger-scale systems (such as supporting up to 16 coverage units), line No. 7 and line No. 8 can also be enabled as high-order address bits, forming a 4-bit binary encoding. The address is set through hardware jumpers, fixed pull-up / pull-down resistors, or printed circuit board solder pads, without the need for software configuration, and has the characteristics of plug-and-play and resistance to communication interruption. Although this system uses standard Ethernet cables as the physical medium, it does not use the IEEE 802.3 Ethernet communication protocol stack, but transmits control information based on a custom lightweight half-duplex serial protocol. Therefore, the wire pairs not occupied by data and clock in the cable (such as line No. 4 / 5 / 7 / 8) can be safely used for hardware address encoding, without conflicting with network data.

[0059] The line sequence distribution scheme makes full use of the redundant resources of the standard Ethernet cable, realizes the physical layer integration of the three functions of control, synchronization and addressing without increasing the cost and complexity of the cable, and is an important technical foundation for supporting the system to realize low cost, easy deployment and high synchronization reliability.

[0060] In an embodiment, the covering unit is configured to obtain a measured period by measuring the time interval between adjacent pulses of the global clock reference signal, and calculate the deviation of the measured period from a nominal period; when the absolute values of the deviations of X consecutive periods are all greater than a preset threshold ΔT, it is determined that the global clock reference signal is misaligned.

[0061] In the embodiment, the covering unit is internally provided with a clock monitoring module configured to evaluate the timing stability of the global clock reference signal from the extension unit in real time. The module is implemented by a high-precision Time-to-Digital Converter (TDC) or a microcontroller internal capture unit, which continuously records the time interval between adjacent rising edges of the global clock reference signal as a measured period T meas . The nominal period T0 preset by the system is 10 milliseconds (corresponding to the length of a TDD wireless frame), and the covering unit judges the clock quality by calculating the deviation ΔT n =∣T meas,n -T0∣.

[0062] To avoid misjudgment caused by instantaneous jitter, the covering unit adopts a sliding window mechanism: only when the absolute values of the deviations of X consecutive periods all exceed the preset threshold ΔT, it is determined that the global clock reference signal is misaligned. X is a positive integer, and ΔT is a positive time threshold. For example, in a typical deployment, X is 3 and ΔT is 5 microseconds - that is, if the measured intervals of three consecutive 10ms periods are 10.006ms, 10.007ms and 10.008ms (the deviations are all greater than 5μs), the misalignment determination is triggered. According to the 3GPP TS36.133, the tolerance of the LTE TDD system to the time alignment error is ±5μs, so it is preferred to set ΔT=5μs; it has been measured that in a typical electromagnetic environment of an examination room, instantaneous jitter rarely exceeds 3 consecutive periods, so X=3 can effectively distinguish between faults and noise.

[0063] The logic is executed by a state machine control module in the coverage unit. Once the misalignment is determined, the state machine immediately switches the working mode: turn off the dependence on the global clock, start the local synchronization engine, and then listen to the base station primary synchronization signal (PSS) and secondary synchronization signal (SSS) in the air interface through the built-in radio frequency receiving front end, demodulate the base station radio frame starting time from them, and determine the TDD downlink time slot again based on it to maintain the accurate transmission of the interference signal.

[0064] The mechanism effectively solves the problem of central clock drift caused by electromagnetic interference, loose connection or transmission delay accumulation of multi-core communication cable. Compared with the traditional passive coverage unit scheme which completely depends on central synchronization, the embodiment introduces a robust criterion based on X and ΔT, which not only avoids frequent mis-switching, but also ensures fast response when real failure occurs, significantly improving the operation reliability and interference effectiveness of the system in complex electromagnetic environment.

[0065] In an embodiment, in the local synchronization mode, the coverage unit is configured to receive the air interface signal through the built-in antenna, extract the primary synchronization signal PSS and the secondary synchronization signal SSS from the air interface signal, demodulate the starting time of the base station radio frame, and use the starting time of the base station radio frame as the timing reference for local interference transmission.

[0066] When the coverage unit determines that the global clock reference signal is misaligned, it automatically enters the local synchronization mode. At this time, the coverage unit enables its built-in omnidirectional radio frequency receiving antenna to continuously listen to the air interface downlink signal of the target frequency band (such as 1880MHz, 2635MHz, etc.). The received radio frequency signal is sent to the baseband processing module for down-conversion and sampling after being conditioned by the low-noise amplifier and the band-pass filter. In the local synchronization mode, the coverage unit starts the receiving front end during the period when the device does not transmit interference to listen to the base station downlink synchronization signal; or uses independent receiving and transmitting antennas to be spatially isolated, and cooperates with the band-pass filter to suppress self-interference.

[0067] The baseband processing module is implemented by a programmable logic device (such as a field programmable gate array) or a dedicated digital signal processor (DSP), which is internally configured with a synchronization signal detection engine. The engine performs sliding correlation operation on the sampled data according to the known frame structure of the communication standard (such as time division duplex long term evolution or new radio), to extract the primary synchronization signal PSS and the secondary synchronization signal SSS. PSS is used for coarse timing and cell group identification, and SSS is used for frame boundary detection and cell group identification.

[0068] By jointly resolving the timing relationship between PSS and SSS, the overlay unit can accurately demodulate the starting time of the base station radio frame (i.e. the boundary of radio frame #0) with a time accuracy of within ±1 microsecond. The starting time is locked as the timing reference of the local jamming transmission, and the overlay unit re-calculates the downlink subframe position of the TDD system (e.g. subframes 0, 1, 5, 6 are downlink if the downlink configuration is DSUDD) and starts the digital-to-analog converter (DAC) and power amplifier in the corresponding time slots to transmit the digital jamming signal for the current carrier frequency.

[0069] The local synchronization mechanism does not rely on the clock distribution link of the central node, and is completely based on the autonomous recovery of the frame structure over the air interface, ensuring that the shielding function can still be continuously operated even in the case of interruption of the multi-core communication cable or severe interference. Compared with the defect that the traditional passive overlay solution is invalid once the central synchronization is lost, the embodiment significantly improves the robustness and availability of the system in complex deployment environments, effectively avoids the misentry of interference signals into the base station uplink receiving window, and protects the legal communication from reverse interference.

[0070] In an embodiment, the overlay unit is configured to automatically switch back to the interference transmission mode controlled by the global clock reference signal after re-detecting that the period deviation of the global clock reference signal continuously satisfies |deviation|≤ΔT for y consecutive periods.

[0071] In the embodiment, after switching to the local synchronization mode, the overlay unit does not permanently separate from the global clock control, but continuously monitors the recovery state of the global clock reference signal from the extension unit. Specifically, the clock monitoring module of the overlay unit continues to measure the time interval between adjacent pulses of the signal and calculate the absolute value of the deviation between the measured period and the nominal period (e.g. 10 milliseconds) of each period |ΔTn|.

[0072] The system pre-sets a recovery criterion: when it is detected that the absolute value of the deviation of consecutive y periods all satisfy |ΔTn|≤ΔT (where ΔT is a pre-set threshold, e.g. 5 microseconds), it is determined that the global clock reference signal has recovered and stabilized. Here, y is a positive integer, and its value is used to balance the switching sensitivity and anti-jitter capability. For example, in a typical configuration, y takes a value of 3, i.e. the clock deviation of three consecutive 10ms periods is required to be no more than 5 microseconds before triggering the mode switching back.

[0073] The judgment is performed by the state management logic inside the covering unit. Once the above conditions are met, the state machine automatically switches the timing reference of the jamming transmission from the "local synchronization mode" back to the "global clock control mode": stop relying on the air interface PSS / SSS signal, re-adopt the frame header offset value issued by the access unit and the period reference of the global clock reference signal, accurately align the TDD downlink time slot, and generate and transmit the digital jamming signal on this basis.

[0074] The return mechanism ensures that the system can return to the high-precision, low-delay centralized synchronization architecture in time after the central link failure is recovered, avoiding the cumulative error or system identification deviation that may be introduced by long-term reliance on local synchronization. At the same time, by setting y≥2 (such as y=3), the frequent mode oscillation (Ping-Pong Effect) caused by instantaneous signal improvement is effectively prevented, and the system operation stability is improved. Overall, the design realizes the closed-loop control logic of "fault self-healing + smooth return", making the system have both the precision of centralized architecture and the robustness of distributed architecture, which is significantly better than the traditional single-mode synchronization scheme.

[0075] In an embodiment, the covering unit includes a programmable logic device and a digital-to-analog converter; the programmable logic device is used to synthesize digital jamming signals of each communication frequency band in real time according to the source information; and the digital-to-analog converter is used to convert the digital jamming signals into analog radio frequency signals and then transmit them through a power amplifier.

[0076] In this embodiment, the covering unit includes a programmable logic device and a digital-to-analog converter, which cooperatively complete the local generation and transmission of jamming signals. The FPGA, as the core signal synthesis engine, receives source information from the expansion unit, which contains the carrier system (such as time division duplex long term evolution, new radio, etc.) and the corresponding center frequency (such as 1880MHz, 2635MHz) adopted by the target communication frequency band. The FPGA internally pre-stores pilot jamming sequence templates for different systems (such as cell-specific reference signal CRS in TD-LTE, demodulation reference signal DMRS in NR), and according to the received frequency point parameters, performs frequency shifting through a numerically controlled oscillator (NCO) to synthesize the baseband digital jamming signal of the corresponding frequency band in real time. The sampling rate is usually set to 30.72MSPS or 61.44MSPS to match the bandwidth requirements of mainstream mobile communication systems.

[0077] The synthesized digital jamming signal is outputted in the form of parallel data stream to a high-speed DAC, which converts the digital samples into an analog voltage signal, whose analog output bandwidth covers the range of 700MHz to 6GHz. Subsequently, the analog signal is filtered to remove high-frequency stray components by an anti-aliasing filter and is sent to a radio frequency power amplifier (PA) for gain amplification, and finally radiated to the shielding area through the omnidirectional antenna built-in the coverage unit, forming an effective suppression to the target frequency band.

[0078] The architecture completely decentralizes the generation of jamming signals to the local coverage unit, avoiding the need to transmit the synthesized wideband radio frequency jamming signal from the central node through the optical fiber in the traditional scheme. Thus, not only the expensive optical-electric conversion module and multi-channel high-speed ADC / DAC array are saved, but also the processing load and hardware cost of the access unit are greatly reduced. At the same time, since the jamming signal is generated close to the radiation point, the loss, distortion and time delay uncertainty introduced by long-distance analog transmission are reduced, improving the timing accuracy and spectral purity of the jamming. Overall, this design is the key technical basis for realizing low-cost, high-reliability and precise TDD time slot jamming.

[0079] In an embodiment, the programmable logic device is configured to load a waveform template file from the non-volatile memory, the waveform template file containing pilot jamming sequences for different communication systems and corresponding carrier frequencies; the waveform template file can receive remote update instructions from the access unit through the multi-core communication cable to realize online upgrade.

[0080] In the present embodiment, the programmable logic device in the coverage unit loads a waveform template file from the non-volatile memory (such as serial flash memory or electrically erasable programmable read-only memory) connected thereto during the system power-on initialization stage. The waveform template file is stored in the form of binary data blocks and contains pre-generated pilot jamming sequences for various mobile communication systems (such as Global System for Mobile Communications, Time Division Synchronous Code Division Multiple Access, Time Division Duplex Long Term Evolution, New Radio, etc.) and their corresponding carrier frequencies (such as 900MHz, 1880MHz, 2570MHz, 3400MHz). For example, for the TD-LTE B40 frequency band (2300-2400MHz), the template stores the complex-valued sequence of cell-specific reference signals (CRS) conforming to the 3GPP TS 36.211 standard; for the NR n78 frequency band, it contains the corresponding demodulation reference signal (DMRS) and channel state information reference signal (CSI-RS) jamming waveform.

[0081] To adapt to the evolution of communication standards or the demand for adding shielding frequency bands, the system supports remote online upgrade of waveform templates. Specifically, the access unit sends a remote update instruction to the coverage unit through the multi-core communication cable, which contains the data packet of the new version of the waveform template and the check information (such as the cyclic redundancy check (CRC) code). After receiving the instruction, the communication interface module of the coverage unit temporarily stores it in the internal buffer of the FPGA, and after confirming the integrity, writes the new template to the specified sector of the non-volatile memory, and updates the version identifier. The next time the system restarts or triggers the hot loading mechanism, the FPGA loads the updated waveform template for interference signal synthesis.

[0082] This mechanism avoids the cumbersome operation of on-site disassembly and replacement of firmware or storage chips in traditional solutions, significantly improving the maintainability and adaptability of the system. At the same time, since the waveform template is decoupled from the specific communication parameters, the same hardware platform can support the interference needs of multiple generations of communication standards through software configuration, extending the device life cycle. In addition, template updating is completed through the existing multi-core communication cable, without the need for additional communication links, balancing safety and cost efficiency. Overall, this design realizes the flexible configuration and dynamic evolution capability of interference waveforms, and is an important technical guarantee for the long-term effective operation of the system.

[0083] In an embodiment, the access unit is configured to transmit the source information and the frame header offset value to the expansion unit through a half-duplex serial communication protocol running on a pair of dedicated twisted pairs of the multi-core communication cable.

[0084] In this embodiment, the access unit transmits source information and TDD frame header offset values to the expansion unit through a custom half-duplex serial communication protocol. This protocol runs on a pair of dedicated twisted pairs (such as line 1 / 2 defined according to TIA / EIA-568-B standards) in the multi-core communication cable, and is isolated from other signals (such as global clock reference signals, hardware address encoding) at the physical layer, avoiding mutual interference.

[0085] Specifically, the access unit is equipped with a microcontroller or a dedicated communication interface chip, configured as a universal asynchronous receiver-transmitter mode, using a frame format of 8-bit data bits, no check bits, and 1-bit stop bits (8N1), with a baud rate set to 115200 bits per second (bps). The source information includes the carrier system of each target frequency band (such as LTE, NR) and the corresponding center frequency (such as 1880MHz, 2635MHz), and the frame header offset value is represented by a 32-bit signed integer in units of microseconds. The above parameters are packaged into fixed-length data frames, and the frame structure includes a start identifier (such as 0xAA), a device address field (used to specify the target expansion unit or coverage unit), a payload area, a 16-bit cyclic redundancy check code (CRC-16), and an end symbol.

[0086] Due to the adoption of half-duplex mechanism, only one-way communication is allowed at the same time: in normal working state, the communication direction is access unit→expansion unit; the expansion unit only obtains the bus control right temporarily in special scenarios such as initialization or fault reporting, and requests the reverse transmission right through a preset handshake mechanism (such as pulling down the bus level for 10 ms). This design simplifies the protocol stack complexity, avoids the independent receiving and transmitting lines required by full-duplex, and fully utilizes a pair of twisted pair to realize reliable control information distribution.

[0087] This communication scheme does not rely on the Ethernet MAC / IP protocol stack, reducing the processor resource overhead of the access unit and the expansion unit. At the same time, due to the use of a dedicated line pair, it is not affected by the switching noise of other signals (such as differential clock). By limiting the control communication to a dedicated twisted pair and adopting a lightweight half-duplex protocol, this embodiment effectively supports the overall architecture goal of low cost and easy deployment while ensuring real-time and robustness.

[0088] Reference Figure 2 In an embodiment, the application also proposes a distributed wireless terminal signal shielding method, which applies the covering unit in the system according to any one of the above, characterized in that it comprises the following steps:

[0089] S1, receiving the wireless base station source information, TDD frame header offset value and periodic global clock reference signal from the expansion unit;

[0090] S2, generating digital interference signals of each communication frequency band based on the source information;

[0091] S3, determining the TDD downlink time slot based on the periodic reference of the global clock reference signal and the frame header offset value, and transmitting the digital interference signals in the determined downlink time slot;

[0092] S4, monitoring the timing stability of the global clock reference signal;

[0093] S5, when it is determined that the global clock reference signal is out of alignment, switching to a local synchronization mode, obtaining base station frame structure information by listening to the base station synchronization signal in the air interface, and re-determining the TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signals.

[0094] As described in step S1, the coverage unit receives three types of key information from the expansion unit through a pair of special twisted pair lines (e.g., No. 1 / 2 line) in the multi-core communication cable: wireless base station source information, TDD frame header offset value, and periodic global clock reference signal. Among them, the source information is obtained by the access unit through frequency sweeping in the system initialization stage, including the carrier system (such as TD-LTE B40, NR n78) and center frequency point (such as 1880MHz, 3400MHz) of each communication frequency band in the target area; the frame header offset value is the microsecond-level time offset (e.g., +3.2μs) obtained by the access unit through synchronization calculation on the air interface PSS / SSS signal; and the global clock reference signal is a differential pulse with a period of 10 milliseconds, which is generated by the internal high-stability crystal oscillator of the access unit and transmitted in the form of low-voltage differential signal (LVDS) through the second pair of twisted pair lines (e.g., No. 3 / 6 line). The coverage unit parses the above data and clock edge through the UART interface and clock capture pin respectively, and completes the initialization configuration.

[0095] As described in step S2, the programmable logic device (FPGA) in the coverage unit loads the corresponding pilot interference sequence template (such as TD-LTE CRS or NR DMRS) from the non-volatile memory according to the received source information, and combines the carrier frequency point parameter to perform frequency shifting and modulation through the numerical control oscillator (NCO) to synthesize the baseband digital interference signal of each target frequency band in real time. For example, for the 1880MHz frequency point, the FPGA outputs a complex sample stream with a sampling rate of 30.72MSPS, and the spectral energy is concentrated in the bandwidth corresponding to the TD-LTE downlink subframe, which ensures the effectiveness of the interference while avoiding out-of-band leakage.

[0096] As described in step S3, the coverage unit takes the rising edge of the global clock reference signal as the starting reference of the 10ms wireless frame, superimposes the frame header offset value (e.g., +3.2μs), and accurately calculates the absolute time window of the downlink time slot in the TDD system (e.g., if the downlink configuration is DSUDD, then subframes 0, 1, 5, and 6 are downlink). Before the start of each downlink subframe, the FPGA starts the digital-to-analog converter (DAC) to convert the digital interference signal into an analog radio frequency signal, which is amplified by the power amplifier and transmitted through the antenna, ensuring that the interference only acts on the base station downlink and avoiding misinterference with user uplink communication.

[0097] As described in step S4, the coverage unit continuously monitors the timing stability of the global clock reference signal. The built-in time measurement unit records the interval between adjacent clock pulses and calculates the absolute value of the deviation between the measured period and the nominal period (10ms). This monitoring process is implemented by a hardware counter with a sampling rate of up to nanoseconds, ensuring sensitive capture of jitter.

[0098] As described in step S5, when it is determined that the global clock is misaligned (for example, the deviation of 3 consecutive periods is greater than 5 microseconds), the covering unit automatically switches to the local synchronization mode: the built-in radio frequency receiving front end is enabled, the air interface signal is listened to, the primary synchronization signal (PSS) and the secondary synchronization signal (SSS) are extracted through the sliding correlation algorithm, and the starting time of the base station radio frame is demodulated. As a new reference, the position of the TDD downlink subframe is re-determined, and the digital interference signal continues to be transmitted. This mechanism ensures that even if the central clock link is interrupted, the shielding function can still run continuously, effectively solving the problem of interference interruption caused by single-point failure in traditional solutions.

[0099] Reference Figure 3 In the embodiments of the present application, a computer device is also provided, which can be a server, and the internal structure thereof can be as shown in Figure 3 The computer device includes a processor, a memory, a storage medium (non-volatile storage medium), and a network interface connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes the storage medium (non-volatile storage medium) and the memory. The storage medium (non-volatile storage medium) stores an operating system, a computer program, and a database. The memory provides an environment for the operation of the operating system and the computer program in the storage medium (non-volatile storage medium). The database of the computer device is used to store the use data and the like in the process of the distributed wireless terminal signal shielding method. The network interface of the computer device is used to communicate with the external terminal through network connection. Further, the computer device can be further provided with an input device and a display screen and the like. The computer program is executed by the processor to implement a distributed wireless terminal signal shielding method, which includes the following steps: receiving wireless base station source information, a TDD frame header offset value, and a periodic global clock reference signal from an extension unit; generating a digital interference signal for each communication frequency band based on the source information; determining a TDD downlink time slot based on the periodic reference of the global clock reference signal and the frame header offset value, and transmitting the digital interference signal in the determined downlink time slot; monitoring the timing stability of the global clock reference signal; when it is determined that the global clock reference signal is misaligned, switching to a local synchronization mode, acquiring base station frame structure information by listening to the base station synchronization signal in the air interface, and re-determining the TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signal. Those skilled in the art can understand that Figure 3 The structure shown in the

[0100] An embodiment of the present application further provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement a distributed wireless terminal signal shielding method, comprising the following steps: receiving wireless base station source information, a TDD frame header offset value and a periodic global clock reference signal from an extension unit; generating digital interference signals of each communication frequency band based on the source information; determining a TDD downlink time slot based on a periodic reference of the global clock reference signal and the frame header offset value, and transmitting the digital interference signals in the determined downlink time slot; monitoring timing stability of the global clock reference signal; when it is determined that the global clock reference signal is inaccurate, switching to a local synchronization mode, obtaining base station frame structure information by listening to base station synchronization signals in an air interface, and re-determining a TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signals. It can be understood that the computer readable storage medium in the embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0101] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiments. Any reference to memory, storage, databases, or other media in this application and in embodiments refers to both non-volatile and / or volatile memory. Non-volatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), or external cache memory. As an illustration but not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0102] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a", "comprising", or "comprises" does not, without further restriction, exclude the existence of additional elements of the process, method, article, or apparatus that comprises the element.

[0103] The above only describes the preferred embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A distributed wireless terminal signal shielding system, characterized in that, It includes an access unit, at least one extension unit, and multiple coverage units; the access unit and the extension unit, as well as the extension unit and each of the coverage units, are connected via multi-core communication cables; the multi-core communication cables are used to simultaneously transmit digital communication signals, periodic global clock reference signals, and device identification information; The access unit is used to: collect source information of wireless base stations around the target area, the source information including the carrier system and corresponding carrier frequency of each communication band, perform air interface synchronization of the time division duplex (TDD) communication system to obtain the frame header offset value, and send the source information, the frame header offset value and the periodic global clock reference signal to the extension unit through the multi-core communication cable; The extension unit is configured to: receive the source information, the frame header offset value, and the global clock reference signal from the access unit, and forward the source information, the frame header offset value, and the global clock reference signal to the corresponding coverage unit; The coverage unit is configured to: receive the source information, the frame header offset value, and the global clock reference signal; generate digital interference signals for each communication frequency band based on the source information; determine the downlink time slot of the TDD communication system based on the period reference of the global clock reference signal and the frame header offset value, and transmit the digital interference signal within the determined downlink time slot; monitor the timing stability of the global clock reference signal, and when it is determined that the global clock reference signal is out of sync, switch to local synchronization mode, obtain base station frame structure information by listening to the base station synchronization signal in the air interface, and re-determine the TDD downlink time slot based on the base station frame structure information to continue transmitting the digital interference signal.

2. The distributed wireless terminal signal shielding system according to claim 1, characterized in that, The multi-core communication cable is a standard Ethernet cable containing at least four pairs of twisted pairs; wherein, the first pair of twisted pairs is used to transmit serial communication data, the second pair of twisted pairs is used to transmit the global clock reference signal in differential form, and at least one of the remaining twisted pairs is used to transmit the hardware address code of the coverage unit.

3. The distributed wireless terminal signal shielding system according to claim 1 or 2, characterized in that, The coverage unit is used to obtain the measured period by measuring the time interval between adjacent pulses of the global clock reference signal, and to calculate the deviation between the measured period and the nominal period; when the absolute value of the deviation for X consecutive periods is greater than a preset threshold ΔT, the global clock reference signal is determined to be out of alignment.

4. The distributed wireless terminal signal shielding system according to claim 3, characterized in that, ΔT is 5 microseconds, and X is 3.

5. The distributed wireless terminal signal shielding system according to claim 1, characterized in that, In the local synchronization mode, the coverage unit is used to receive air interface signals through the built-in antenna, extract the primary synchronization signal PSS and the secondary synchronization signal SSS from them, demodulate the start time of the base station radio frame, and use the start time of the base station radio frame as the timing reference for local interference transmission.

6. The distributed wireless terminal signal shielding system according to claim 3, characterized in that, The coverage unit is used to automatically switch back to the interference transmission mode controlled by the global clock reference signal after the period deviation of the global clock reference signal is re-detected and continuously satisfies |deviation|≤ΔT for y consecutive periods.

7. The distributed wireless terminal signal shielding system according to claim 1, characterized in that, The coverage unit includes a programmable logic device and a digital-to-analog converter; the programmable logic device is used to synthesize digital interference signals for each communication frequency band in real time according to the source information, and the digital-to-analog converter is used to convert the digital interference signals into analog radio frequency signals and then transmit them through a power amplifier.

8. The distributed wireless terminal signal shielding system according to claim 7, characterized in that, The programmable logic device is used to load a waveform template file from a non-volatile memory. The waveform template file contains pilot interference sequences for different communication standards and corresponding carrier frequencies. The waveform template file can receive remote update instructions from the access unit through the multi-core communication cable to achieve online upgrades.

9. The distributed wireless terminal signal shielding system according to claim 1, characterized in that, The access unit is used to transmit the source information and the frame header offset value to the extension unit through a half-duplex serial communication protocol, which operates on a pair of dedicated twisted pairs of the multi-core communication cable.

10. A distributed wireless terminal signal shielding method, applied to a coverage unit in a system as described in any one of claims 1 to 9, characterized in that, Includes the following steps: Receives wireless base station source information, TDD frame header offset value, and periodic global clock reference signal from the extended unit; Digital interference signals for each communication frequency band are generated based on the aforementioned source information; Based on the period reference of the global clock reference signal and the frame header offset value, the TDD downlink time slot is determined, and the digital interference signal is transmitted within the determined downlink time slot; Monitor the timing stability of the global clock reference signal; When the global clock reference signal is determined to be out of sync, the system switches to local synchronization mode, obtains base station frame structure information by listening to the base station synchronization signal in the air interface, and redetermines the TDD downlink time slot based on the base station frame structure information in order to continue transmitting the digital interference signal.

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