A method for testing hardware optimization of a project

Abstract

This invention relates to the field of data storage technology and discloses a hardware optimization method for a test project. The method includes: a host computer (PC); a System-on-Chip (SOC) module, which is the control core of the entire test system and enables communication within the system; an MCU control module, which communicates asynchronously with the host computer via a UART interface and simultaneously exchanges high-speed data with the main SOC module via an SPI interface, thus facilitating communication between the host computer and the SOC module and controlling the SOC module's power supply; and a DDR module, whose DDR pin is connected to the MCU control module, allowing the MCU control module to perform current testing on the DDR module. This invention improves test coverage, signal integrity, and test efficiency.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a hardware optimization method for a test project. Background Technology

[0002] With the continuous improvement of mobile processor performance, POP (Package-on-Package) packaging technology for MTK platforms paired with LPDDR5X memory has become the mainstream solution for high-end mobile devices. The addition of the 496-ball BGA packaging structure places higher demands on testing hardware. However, traditional testing methods can no longer meet the testing requirements of today's high-speed, high-density packaging. Summary of the Invention

[0003] This invention provides a hardware optimization method for test items, which can solve the technical problem that traditional test methods can no longer meet the current test requirements of high-speed and high-density packaging.

[0004] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a hardware optimization method for a test project, the method comprising:

[0005] The host computer is a PC.

[0006] The SOC module is a system-on-a-chip. The SOC module is the control core of the entire test system and enables the communication of the test system.

[0007] The MCU control module communicates asynchronously with the host computer via the UART interface and simultaneously exchanges high-speed data with the main control SOC module via the SPI interface. The MCU control module completes the communication between the host computer and the SOC module and controls the power on and off of the SOC module.

[0008] The DDR module is connected to the DDR terminal of the MCU control module, and the MCU control module performs current testing on the DDR module.

[0009] The beneficial effects of this invention are as follows: Through layered design, each interface adapts to the characteristics of the module, and with retry and verification mechanisms, accurate transmission of commands and data across the entire link is achieved, forming a communication closed loop with "no loss and no errors," improving test coverage, signal integrity, and test efficiency; precise configuration of SOC and DDR voltages by domain, dynamic adjustment of voltage balance performance and power consumption on demand through DVFS, and strict control of power-on sequence and slope, execution of standardized power-off sequences to ensure power supply safety; high-precision monitoring of DDR multi-state current, real-time verification of power supply parameters, structured processing of test data and generation of comparison reports, providing accurate and readable basis for test evaluation; hardware-level rapid protection, software-level fault tolerance, and multi-module collaborative feedback significantly reduce the risk of failure. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the hardware optimization method for a test item according to an embodiment of the present invention.

[0011] Explanation of key component symbols:

[0012] 1. Host computer, 2. SOC module, 3. MCU control module, 4. DDR module. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0014] The terms "comprising" and "having," and any variations thereof, used in this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0015] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0016] Figure 1 This is a schematic diagram of the hardware optimization method for a test item according to an embodiment of the present invention. For example... Figure 1 As shown, the method includes:

[0017] Host computer 1 is a PC.

[0018] SOC module 2 is a system-on-a-chip and serves as the control core of the entire test system, enabling communication within the test system.

[0019] MCU control module 3 communicates asynchronously with host computer 1 (PC) via UART interface, and at the same time exchanges high-speed data with main control SOC module 2 (U1001F) via SPI interface. MCU control module 3 completes the communication between host computer 1 and SOC module 2, and controls the power on and off of SOC module 2.

[0020] The DDR (Dynamic Random Access Memory) module is connected to the DDR module 4 via the MCU control module 3. The MCU control module 3 performs current testing on the DDR module 4.

[0021] The host computer 1 (PC) serves as the "human-computer interaction entry point" and "data processing center" of the testing system, enabling test process control, data visualization, and result analysis. The testing tasks are completed using customized testing software (such as dedicated programs developed based on LabVIEW and Python). Operators can configure test parameters (such as the test voltage range of DDR module 4, current sampling frequency, and the operating timing of SOC module 2), select test types (such as DDR current stability test and SOC communication link verification), and generate executable test task instructions. The host computer 1 provides a graphical user interface (GUI) that receives real-time status data uploaded by the underlying modules (such as the power supply status of SOC module 2 and the real-time current value of DDR module 4), displaying it intuitively in the form of dynamic curves, data tables, and status indicator lights. The host computer 1 supports emergency operations (such as pausing the test and triggering a SOC power-off) to handle abnormal scenarios. After the test, the host computer 1 automatically analyzes the raw data (such as the current curves of DDR in various operating modes and the SOC communication bit error rate), calculates key indicators (such as DDR average power consumption and current fluctuation range), and generates a standardized test report (including data charts and fault location conclusions). Historical data storage and retrieval are supported for easy tracing of test records.

[0022] SOC Module 2 (System-on-a-Chip U1001F) serves as the "hardware control brain" of the system, enabling collaborative work and communication link establishment among the underlying modules. The test logic executes by receiving instructions from the host computer 1, converted by the MCU control module 3, and parsing them into specific hardware operation signals (such as timing signals controlling the DDR module 4 to enter "standby / read / write / high-speed transmission" mode, and configuration signals for its own communication interface), driving the underlying hardware to complete the test actions. SOC Module 2 integrates an SPI interface controller (for high-speed communication with the MCU control module 3) and a DDR controller (for storage interaction with the DDR module 4). On one hand, it receives instructions from the MCU control module 3 and reports its own status; on the other hand, it establishes a data interaction link with the DDR module 4, transmitting the control signals and temporary data required for testing. SOC Module 2 has a built-in simple fault detection unit that can monitor its own power supply voltage and the integrity of its connection with the DDR module 4 in real time (such as whether the data bus is disconnected). If an abnormality is detected, it immediately sends a fault signal to the MCU control module 3 via the SPI interface, triggering an upper-level alarm.

[0023] The circuit design of the main control SOC module 2 (U1001F) uses a BGA496 package with a ball-pitch spacing of 0.65mm. Power management includes 12 independent power domains, with a core voltage of 0.8V±3% and a memory interface voltage of 1.2V±2%. The power network uses a multi-layer PCB design, employing a π-type filter (10μH inductor + 2×100μF capacitors) to suppress noise and ensure voltage ripple is below 2%. The clock system uses a 40MHz crystal oscillator as the master clock source, generating a 2666MHz DDR clock signal via a PLL. The clock signal uses a differential pair design (CK_t / c), with phase deviation controlled within 5ps to reduce timing jitter. Thermal design includes 256 thermal vias (0.3mm in diameter) on the bottom of SOC module 2, connected to a 2oz copper-thick outer thermal pad, ensuring the junction temperature does not exceed 85℃ under full load. It is responsible for performing DDR algorithm functional testing, stress testing, and system initialization, and manages address / command signals through a fly-by topology.

[0024] MCU control module 3 acts as an intermediary bridge between host computer 1 and SOC module 2, resolving communication protocol compatibility issues between different modules and ensuring system power supply safety. Dual-interface communication and protocol conversion: Asynchronous UART communication with host computer 1: Utilizes the standard UART protocol (supporting baud rates of 9600~115200bps, no parity / 1 stop bit) to achieve low-speed, high-reliability instruction and status transmission (e.g., "Start Test" command from host computer 1, "SOC Power Supply Normal" status uploaded by MCU control module 3); High-speed SPI communication with SOC: Employs SPI master-slave mode (MCU control module 3 as master, SOC as slave), supporting a maximum clock frequency of 10Mbps to meet the needs of rapid transmission of large amounts of data (e.g., real-time current sampling data from DDR module 4, SOC test logs); Protocol conversion: Automatically converts UART command frames from host computer 1 (e.g., "0x01 - Start DDR Test") into SOC-recognizable SPI protocols. The I instruction format converts the SOC's SPI feedback data (such as "0x80-DDR current 1.2A") into UART data for uploading, achieving cross-protocol compatibility. Precise SOC power control: An integrated power management unit (PMU) outputs high and low level signals via GPIO pins to control the power supply switch of SOC module 2. Power-on process: After receiving the "Start SOC module 2" command from host computer 1, it supplies power to the SOC according to a preset timing sequence (first core voltage 3.3V, then IO voltage 1.8V). After SOC module 2 completes initialization and sends back a "Ready" signal, it forwards the test command. Power-off process: When the test ends or an "Emergency Power Off" command is received, it first notifies SOC module 2 via SPI to save temporary data before cutting off the power supply to prevent data loss or hardware damage due to sudden power failure.

[0025] The MCU control module 3 communicates asynchronously with the host computer 1 (PC) via a UART interface at a transmission rate of 115200bps. The data format consists of 8 data bits, no parity bit, and 1 stop bit, ensuring real-time display of test status and results. Simultaneously, it exchanges data at high speed with the main control SOC module 2 (U1001F) via an SPI interface with a clock frequency configured at 10MHz, supporting full-duplex mode. The MCU integrates a PMIC (Power Management Integrated Circuit), configuring the output voltage sequence via the I2C bus. For example, the SOC core power supply can be provided by the TPS65086182 chip at 0.8V / 3A, and the DDR power supply can be provided by the TPS51200DRCR chip at 1.2V / 6A, achieving precise timing control (such as power-on / power-off cycles).

[0026] The MCU control module 3 integrates an INA219 high-precision current sensor with a 10-megaohm sampling resistor, supporting a measurement range of 0-3.2A and a resolution of 100µA (microamps). It can monitor the DDR's read / write current, standby current, and sleep current in real time, with a data update rate of 1kSPS, and upload the data to the host computer 1 via an ADC converter. The design of the MCU control module 3 ensures the safety and repeatability of the testing process, for example, by automatically powering off after each test to avoid the risks of live operation.

[0027] DDR module 4 (Dynamic Random Access Memory) is used as the test object for current characteristic testing: the hardware connection is directly connected to the DDR test port of MCU control module 3 through a dedicated DDR interface (including data bus, address bus, and control bus). MCU control module 3 sends a "switch working mode" control signal to DDR module 4 through this interface and collects the power supply current. The test scenario supports current testing in different working modes: standby mode (only maintains data storage, low current), active mode (preparing for read / write operations, medium current), and Burst read / write mode (high-speed continuous data transmission, highest current). MCU control module 3 collects the power supply current of DDR module 4 through a high-precision ADC (12-bit resolution, 1kHz sampling rate), feeds it back to the MCU in real time, and then forwards it to host computer 1 through MCU control module 3 for analysis of current stability and power consumption characteristics. As a data carrier: Temporary storage: Stores temporary data generated by SOC module 2 during testing (such as test instruction cache and status parameters of DDR module 4), avoiding test interruption due to insufficient built-in storage capacity of SOC; Hardware design adaptation: Uses DDR chips that match LPDDR5X (or corresponding test models), supports high-speed data read and write (maximum transmission rate conforms to chip specifications), and reduces the impact of external interference on the accuracy of test data through impedance matching and power supply filtering design.

[0028] The host computer 1 sends a "Start DDR Current Test" command (including test mode and sampling frequency parameters) to the MCU control module 3 via UART. The MCU control module 3 converts the UART command into SPI format and sends it to the SOC module 2. At the same time, it controls the SOC module 2 to power on and waits for it to be ready. After receiving the command, the SOC sends a "Enter Burst Read / Write Mode" control signal to the DDR module 4 through the controller in the DDR module 4. The DDR module 4 enters the target mode, and the MCU control module 3 collects real-time current data through the DDR test port. The MCU control module 3 sends the current data to the SOC via SPI (optional: the SOC temporarily stores some data), and then the MCU control module 3 summarizes it and uploads it to the host computer 1 via UART. The host computer 1 displays the current curve in real time and generates a current analysis report after the test. After the test is completed, the host computer 1 sends a "Stop Test" command, the MCU control module 3 notifies the SOC to save the data, and then cuts off the power supply to the SOC.

[0029] When the test is started, the MCU control module 3 controls the SOC module 2 to power on, and the entire system runs the test program.

[0030] During the test, the MCU control module 3 tested the read / write current, standby current, and sleep current of the DDR module 4 monitored by the current sensor.

[0031] After each test is completed, the MCU control module 3 controls the SOC module 2 to power off, so that the DDR module 4 can be picked up and put down without power, and the current data monitored by the current sensor is uploaded to the host computer 1 through the ADC converter.

[0032] Specifically: Test preparation phase:

[0033] Step A: The host computer 1 initiates the test task configuration. The operator completes the parameter settings in the GUI (such as the interface developed by LabVIEW): Test type: DDR module 4 Burst read / write mode current test; Key parameters: sampling frequency 1kHz, test duration 5 minutes, current over-limit threshold 1.5A, SOC power supply timing (core voltage 3.3V is powered on first, and IO voltage 1.8V is powered on after a delay of 50ms); The software automatically generates a command frame (format: 0xAA [instruction code 0x01] [mode 0x03] [sampling rate 0x04] [duration 0x1388] [threshold 0x05DC] 0x55, a total of 10 bytes, including frame header 0xAA and frame tail 0x55 checksum), and sends it to the MCU through the UART interface (baud rate 115200bps, no parity check, 1 stop bit).

[0034] Step B: The MCU receives and verifies the command, and powers on the SOC. After receiving UART data, it first verifies the frame header / tail and CRC (Cyclic Redundancy Check) to confirm that the command is correct (if the verification fails, it returns a 0xEE alarm to the host computer 1); it triggers the power management unit (PMU): it outputs a high level through the GPIO1 pin to control the 3.3V power supply circuit of the SOC core voltage, and starts the internal timer at the same time; after a 50ms delay of the timer, the GPIO2 pin outputs a high level to conduct the 1.8V SOC I / O voltage circuit; it sends an initialization command to the SOC through the SPI interface (MCU is the master, SCLK clock is 10Mbps, CS# pin is pulled low): 0x01 [SOC address 0x1001F] 0x00, and waits for SOC feedback.

[0035] Step C: The SOC initializes and returns a ready status. After the power supply stabilizes (approximately 100ms), it automatically completes the initialization of the internal DDR controller and SPI interface controller. It checks its own core voltage (3.3V±5%) and IO voltage (1.8V±5%). After confirming that there are no abnormalities, it returns a ready signal via the MISO pin of the SPI: 0x81 [SOC Status 0x00] (0x00 indicates normal). If the voltage is abnormal (such as the core voltage 3.1V being lower than the threshold), it returns 0x81 [Status 0x01], triggering the MCU to retry power-on (up to 3 times; if it still fails, it reports to the host computer 1).

[0036] The MCU sends a message to the host computer 1 indicating that preparation is complete. After receiving the 0x810x00 signal from the SOC, it sends a preparation completion frame to the host computer 1 via UART: 0xAA [Status 0x00] 0x55. The host computer 1 GUI displays "System ready, test can be started".

[0037] Test execution phase (DDR current acquisition and real-time control):

[0038] Step D: The host computer 1 issues a test start command. The operator clicks the "Start Test" button, and the software generates a start command: 0xAA [Instruction Code 0x02] 0x55, which is sent to the MCU via UART.

[0039] Step E: The MCU forwards the instruction, and the SOC drives the DDR to enter test mode. After receiving the instruction, the MCU forwards it to the SOC via SPI: 0x02 [DDR control address 0x2000] [mode 0x03] (0x03 corresponds to Burst read / write mode). After parsing the instruction, the SOC's internal DDR controller generates timing signals (RAS# row address strobe, CAS# column address strobe, WE# write enable), and sends them to DDR module 4 via the DDR bus to control the DDR to enter Burst read / write mode (single Burst length is 8 data cycles). The SOC writes test vectors (such as 0x0000~0xFFFF cyclic data) to DDR module 4 and stores them in the DDR's address range of 0x1000-0x2000. At the same time, it feeds back 0x82 [DDR status 0x00] to the MCU.

[0040] Step F: The MCU acquires and buffers the DDR current. The MCU starts its internal 12-bit ADC (analog-to-digital converter) and acquires the current signal of the DDR power supply terminal (VCC=1.8V) through the current sampling pin of the DDR test port (with a 0.1Ω sampling resistor in series). The analog current signal is converted into a digital value (e.g., 1.2A corresponds to digital value 0x04D2, quantization error ±0.5%) at a sampling frequency of 1kHz (1 acquisition every 1ms). Every 100 data points acquired (taking 100ms) are buffered in the MCU's internal RAM (address 0x4000-0x40C7) to avoid frequent communication consuming bandwidth. The current value is judged in real time: if it exceeds 1.5A (corresponding to digital value 0x05DC), the emergency procedure is immediately triggered (see "Abnormal Handling").

[0041] Real-time uploading and visualization are performed during the data interaction phase (in parallel with the execution phase):

[0042] Step G: The MCU uploads data in batches to the SOC and host computer 1. For every 100 current data points buffered by the MCU, it first uploads the data to the SOC via SPI (data frame format: 0xAA [data length 0x64] [100 2-byte data points] 0x55). After receiving the data, the SOC temporarily stores it in its internal RAM (0x3000-0x30C8) for subsequent data backup. At the same time, the MCU uploads the same data to the host computer 1 in frames via UART (because the UART rate is low, each frame transmits 20 data points, and the 100 points are transmitted in 5 frames, frame format: 0xAA [frame number 0x01] [20 2-byte data points] 0x55).

[0043] Step H: The host computer 1 processes and displays data in real time. After receiving UART data, it verifies the frame sequence number to avoid frame loss. If a frame is found to be lost (e.g., missing frame 0x02), it sends 0xAD [missing frame sequence number] to the MCU to trigger retransmission. It calculates current statistics in real time (e.g., average and maximum values ​​of 100 points) and draws a dynamic current curve on the GUI (X-axis is time, Y-axis is current value). At the same time, it displays "Current current: 1.2A, status: normal".

[0044] Test closing phase (stop and data archiving):

[0045] Step 1: The host computer initiates a stop command. When the test duration ends (5 minutes) or the user manually clicks "Stop", the software sends a stop command: 0xAA [instruction code 0x03] 0x55 to the MCU.

[0046] Step J: The module collaboratively stops the test and power-offs. After receiving the instruction, the MCU sends 0x03 [Stop Flag 0x01] to the SOC via SPI. The SOC immediately stops the timing signals of the DDR controller and switches the DDR to standby mode (current drops below 0.3A). The SOC writes the test data (0x3000-0x30C8) cached in its internal RAM to addresses 0x2000-0x20C8 of the DDR module 4 (permanently stored for easy tracing later) and sends 0x83 [Stop Complete 0x00] back to the MCU. After receiving the feedback, the MCU controls the PMU to power off: first pulls GPIO2 low (cuts off IO voltage 1.8V), and after a 100ms delay, pulls GPIO1 low (cuts off core voltage 3.3V) to prevent the SOC from losing data due to a sudden power failure.

[0047] Step K: Data aggregation and report generation. The MCU reads the complete test data (0x2000-0x20C8) stored in DDR module 4 through the DDR test port, aggregates all sampling points (30,000 points in total, 5 minutes × 60 seconds × 100 points / second); calculates key indicators: average current 1.18A, maximum current 1.25A, fluctuation range ±0.05A, generates a data aggregation frame and uploads it to host computer 1 via UART; after receiving the data, host computer 1 automatically generates a standardized test report (including current curve screenshot, key indicator table, test time, module status), saves it to the local path (e.g., D:\TestReports\20251205_DDR_Current_001.xlsx), and updates the historical data query database at the same time.

[0048] The MCU control module 3 integrates a current sensor, which monitors the read / write current, standby current, and sleep current of the DDR module 4 in real time, and uploads the current data monitored by the current sensor to the host computer 1 through the ADC converter.

[0049] The host computer initiates the test task configuration. In addition to the original parameters, the operator configures the following current monitoring parameters in the GUI: Current monitoring type: DDR read / write current (range 0~2A, accuracy ±1mA), standby current (range 0~500mA, accuracy ±0.5mA), sleep current (range 0~100mA, accuracy ±0.1mA); Sensor filtering parameters: read / write current sampling filter coefficient 0x03 (low filtering, priority response speed), standby / sleep current filter coefficient 0x08 (high filtering, priority stability); The instruction frame adds a current configuration field, and the format is updated to: 0xAA [instruction code 0x01] [mode 0x03] [sampling rate 0x04] [duration 0x1388] [threshold 0x05DC] [read / write range 0x02] [standby range 0x0080] [sleep range 0x0014] [filter coefficient 0x0308] 0x55 (16 bytes in total, 5 new current-related fields).

[0050] The MCU receives and verifies the command, then powers on SOC module 2 (initializing the newly added current sensor). The original verification logic remains unchanged. After successful verification, the integrated current sensor (e.g., model ACS712) is initialized first: configured via the I2C interface (sensor address 0x48): write 0x01 [Read / Write Range Configuration 0x02] (corresponding to 0~2A), 0x02 [Standby Range Configuration 0x0080] (corresponding to 0~500mA), 0x03 [Sleep Range Configuration 0x0014] (corresponding to 0~100mA), and 0x04 [Filter Coefficient 0x0308]; send 0x05 [Self-Test Command]. The sensor returns 0x00, indicating that the self-test is normal (if it returns 0x01, the MCU reports "current sensor fault" to host computer 1); the subsequent SOC power-on process (GPIO control timing) is consistent with the original, and the current sensor enable pin (GPIO3) is set high, and the sensor enters the working state.

[0051] SOC module 2 initializes and returns a ready status (the status of the newly added DDR module 4 is associated with the sensor range). After initialization, in addition to the original voltage detection, the initial DDR status (standby mode) is returned via SPI: 0x81 [SOC status 0x00] [DDR initial status 0x01] (0x01 indicates standby mode). After receiving the initial DDR status 0x01, 0x06 [Switch to standby range] is immediately sent to the current sensor via I2C. The sensor switches to the 0~500mA range to prepare for monitoring standby current.

[0052] The MCU forwards commands, and the SOC drives the DDR to enter test mode (new state switching and range linkage are added): The original command forwarding logic remains unchanged. When the SOC drives the DDR to switch modes, it synchronously feeds back the current DDR status to the MCU via SPI: Entering Burst read / write mode: feedback 0x82 [DDR status 0x00] [Current mode 0x02] (0x02 indicates read / write mode); Entering sleep mode during test intervals: feedback 0x82 [DDR status 0x00] [Current mode 0x03] (0x03 indicates sleep mode); After the MCU receives the mode identifier, it switches the current sensor range within 10us: Upon receiving 0x02 (read / write mode): I2C sends 0x06 [Switch to read / write range], and the sensor switches to 0~2A; Upon receiving 0x03 (sleep mode): I2C sends 0x06 [Switch to sleep range], and the sensor switches to 0~100mA.

[0053] The MCU acquires and buffers the DDR current (replaced with current sensor acquisition logic). The current sensor monitors the DDR power supply circuit current in real time, converting the current signal into a 0~3.3V analog voltage (e.g., 1A corresponds to 1.65V, 0.1A corresponds to 0.33V), and outputs it to the MCU's ADC input pin (AIN0). The MCU starts a 12-bit ADC (sampling rate 1kHz) to acquire the analog voltage output by the sensor, converting it to the actual current value according to the range: Read / write mode: voltage value × (2A / 3.3V) → e.g., 1.98V corresponds to 1.2A (digital value 0x04D2); pending Standby mode: Voltage value × (500mA / 3.3V) → e.g., 0.66V corresponds to 100mA (digital value 0x0190); Sleep mode: Voltage value × (100mA / 3.3V) → e.g., 0.33V corresponds to 10mA (digital value 0x0032); When caching data, add 1 byte of "current type identifier" before each data point: 0x02 (read / write current), 0x01 (standby current), 0x03 (sleep current), and the cache format becomes: [current type 1 byte] [current value 2 bytes] (e.g., read / write current 1.2A corresponds to 0x020x040xD2).

[0054] The MCU uploads data in batches to the SOC and host computer 1 (a new type identifier is added to the data format). For every 100 data points buffered by the MCU, the data frame format uploaded to the SOC is updated to: 0xAA [Data length 0x96] [100 3-byte data (type + value)] 0x55 (originally 200 bytes → 300 bytes, data length field changes from 0x64 → 0x96); the UART frame format uploaded to host computer 1 is updated to: 0xAA [Frame sequence number 0x01] [20 3-byte data] 0x55 (60 bytes per frame, 100 points are transmitted in 5 frames) to ensure that host computer 1 can identify the current type.

[0055] The host computer 1 processes and displays data in real time (distinguishing between multiple state current visualizations). After receiving data, it parses the "current type identifier" and stores it according to type: Read / write current: stored in the Current_RW array and plotted as a red dynamic curve; Standby current: stored in the Current_Standby array and plotted as a blue dynamic curve; Sleep current: stored in the Current_Sleep array and plotted as a green dynamic curve. A new "Current Type Switch" button has been added to the GUI, which supports viewing a certain type of current curve separately and displaying the statistical values ​​of multiple types of current at the same time (such as "average read / write current 1.18A, average standby current 95mA, average sleep current 8mA").

[0056] Preferably, the MCU control module 3 integrates a power management integrated circuit, which configures the output voltage sequence via the I2C bus.

[0057] The MCU's I2C master interface has two specific pins: the SDA pin (corresponding to PA10) and the SCL pin (corresponding to PA9). These two pins are directly connected to the I2C slave interface of the voltage configuration register PMIC (specifically, the TITPS65987). To match the 1.8V I / O level, a 1.8kΩ pull-up resistor is connected to the I2C bus. This hardware connection method is suitable for board-level interconnect scenarios and supports a maximum communication distance of 10 cm.

[0058] The I2C bus communication rate uses I2C fast mode at 400kHz, which meets the real-time requirements of voltage sequence configuration, with a single configuration command transmission time not exceeding 10 microseconds. The address format uses a 7-bit slave device address; the PMIC's default address is 0x48, without read / write bit extension. For read operations, 0x01 is appended to the address, and for write operations, 0x00 is appended. Data frame transmission follows a fixed order: first, the start condition (indicated by "S") is sent; then, the slave device address and read / write bit combination are sent; after waiting for the PMIC to return an acknowledgment (indicated by "ACK"), a 1-byte register address is sent; after waiting for another acknowledgment, 2 bytes of configuration data are transmitted (high-order bits first); finally, after receiving an acknowledgment, a stop condition (indicated by "P") is sent.

[0059] To avoid configuration failures due to bus interference, a timeout retransmission mechanism is implemented: After the MCU sends an I2C command, the timeout period for waiting for a PMIC response is 100 microseconds. If no response is received within the timeout period, a retransmission will be triggered, with a maximum of 3 retransmissions, each with a 50-microsecond interval between retransmissions. Simultaneously, the MCU integrates an I2C bus conflict detection unit. When an abnormal level is detected on the SDA or SCL lines (e.g., multiple master devices simultaneously pulling the lines low), the bus will be immediately released, and communication will be re-initiated after a 1-millisecond delay to prevent data transmission errors.

[0060] Taking the TITPS65987 model as an example, the core voltage configuration registers are mainly divided into three categories: voltage setting registers, enable control registers, and timing configuration registers. The specific functions of each type of register are as follows: Voltage Setting Registers: These include SOC_VCORE_SET (address 0x10), SOC_VIO_SET (address 0x11), DDR_VCORE_SET (address 0x20), and DDR_VDDQ_SET (address 0x21). Among them, SOC_VCORE_SET is used to configure the core voltage (VCORE) of the SOC, SOC_VIO_SET is used to configure the I / O voltage (VIO) of the SOC, DDR_VCORE_SET is used to configure the core voltage (VDDR) of the DDR, and DDR_VDDQ_SET is used to configure the auxiliary voltage (VDDQ) of the DDR. The data bits of these four registers have the same meaning: bits 15 to 4 represent 12-bit voltage encoding values, and bits 3 to 0 are reserved bits. Enable control registers include SOC_PWR_EN (address 0x12) and DDR_PWR_EN (address 0x22). SOC_PWR_EN controls the enable state and power-on sequence of the SOC voltage. Bit 1 corresponds to VCORE enable (1 indicates enable), bit 0 corresponds to VIO enable (1 indicates enable), and bits 7-2 configure the power-on interval in 10 milliseconds. DDR_PWR_EN functions similarly to SOC_PWR_EN. Bit 1 corresponds to VDDR enable (1 indicates enable), bit 0 corresponds to VDDQ enable (1 indicates enable), and bits 7-2 also configure the power-on interval in 10 milliseconds. The timing configuration-related monitoring register, VOLT_MONITOR (address 0x01), is mainly used to read the actual output values ​​of each voltage for configuration verification. Bits 15 to 8 in its data bits represent the measured value of VCORE, bits 7 to 0 represent the measured value of VIO, and the second byte of the register corresponds to the measured values ​​of VDDR and VDDQ.

[0061] The voltage configuration register (PMIC) outputs voltage via a 12-bit DAC (digital-to-analog converter). The conversion formula between the actual output voltage and the voltage encoding value is: Actual voltage (in V) = Encoded value × Voltage step size. The voltage step size is determined by the PMIC's internal reference voltage. The TITPS65987's reference voltage is 1.25V, and the 12-bit DAC's encoding range is 0~4095, thus the basic step size can be calculated to be approximately 0.305mV. However, the step size for different voltage domains can be adjusted through the configuration register. In this system: SOC voltage domain (including VCORE and VIO): the step size is set to 1mV. This step size is achieved by configuring the DAC gain through the 0x0F register. In this case, the encoded value is equal to the millivolts of the target voltage. For example, if the target voltage is 3.3V (i.e., 3300mV), the corresponding encoded value is hexadecimal 0xD05, and the data transmitted to the register is 0x0D (high byte) and 0x05 (low byte). DDR voltage domain (including VDDR and VDDQ): To adapt to the requirements of low voltage and high precision, the step size is set to 0.5mV. At this time, the encoded value is equal to twice the target voltage millivolts. For example, if the target voltage is 1.1V (i.e., 1100mV), the encoded value is 1100×2=2200, which corresponds to 0x8C8 in hexadecimal. The data transferred to the register is 0x08 (high byte) and 0xC8 (low byte) (0x0458 mentioned in the previous document is a simplified expression; this is the actual encoding logic).

[0062] The I2C instruction timing for SOC module 2 voltage sequence configuration is as follows: First, MCU control module 3 sends the first I2C write instruction to the voltage configuration register PMIC. The instruction sequence is: start condition, slave device address 0x48 + write operation flag 0x00, acknowledge, register address 0x10, acknowledge, configuration data 0x0D and 0x05, acknowledge, stop condition. This instruction is used to configure the SOC's VCORE voltage to 3.3V. After sending, PMIC returns an acknowledgement confirming receipt. Next, MCU sends a second write instruction, changing the register address to 0x11 and the configuration data to 0x07 and 0x08, to configure the SOC's VIO voltage to 1.8V (1800mV corresponds to the hexadecimal code 0x708). Similarly, PMIC acknowledges this instruction. Then, MCU control module 3 sends the third write instruction, with register address 0x12 and configuration data 0x00 and 0x03. Bits 1 and 0 are both set to 1 to enable VCORE and VIO respectively, and bits 7 to 2 are set to 0 (the power-on interval is controlled by the internal timer of MCU control module 3). After the voltage configuration register PMIC responds, MCU control module 3 starts the internal timer, sets a delay of 100 milliseconds, and waits for the subsequent power supply operation of DDR module 4. After the timer count is completed, it will send a delay completion signal to MCU control module 3.

[0063] After receiving the timer's delay completion signal, MCU control module 3 begins configuring the voltage of DDR module 4. The first write instruction, with register address 0x20 and configuration data 0x08 and 0xC8, configures the VDDR voltage of DDR module 4 to 1.1V (1100mV × 2 = 2200, corresponding to the encoded value 0x8C8). The voltage configuration register PMIC returns an acknowledgment. The second write instruction, with register address 0x21 and configuration data 0x07 and 0x08, configures the VDDQ voltage of DDR to 0.9V (900mV × 2 = 1800, corresponding to the encoded value 0x708), also receiving an acknowledgment. Finally, MCU control module 3 sends a third write instruction, with register address 0x22 and configuration data 0x00 and 0x03, enabling VDDR and VDDQ. After the PMIC acknowledges, the voltage configuration of DDR module 4 is complete.

[0064] Power-on sequence control is implemented through an internal timer in the MCU control module 3, with a timer accuracy of 1 millisecond. When the MCU sends a SOC voltage enable command to the voltage configuration register (PMIC), it immediately starts counting. Only when the count reaches 100 milliseconds does it send a DDR module 4 voltage enable command to the PMIC. This delay design prevents the DDR module 4 from powering on first, which could cause SOC initialization anomalies. Voltage rise rate control is implemented by a voltage rise rate control unit integrated within the PMIC, which can be configured via register 0x02. In this system, the VCORE voltage rise rate of SOC module 2 is set to 50mV / ms, requiring 66 milliseconds to rise from 0V to 3.3V; the VDDR voltage rise rate of the DDR is set to 30mV / ms, requiring 37 milliseconds to rise from 0V to 1.1V. This slope setting prevents surge currents caused by sudden voltage spikes.

[0065] After voltage enable, MCU control module 3 needs to wait 200 milliseconds to ensure stable voltage output. Then, it reads the PMIC's VOLT_MONITOR register (address 0x01) via I2C read instructions. The read instruction sequence is: start condition, slave device address 0x48 + read operation flag 0x01, acknowledge, register address 0x01, acknowledge, receive high byte data, acknowledge, receive low byte data, NACK, stop condition. After reading the data, it is parsed. For example, if the read register data is 0x0D, 0x02, 0x08, 0xC7, it means that the measured value of VCORE of SOC module 2 is 0x0D02 (corresponding to 3330mV, i.e., 3.33V), which is within the allowable error range of ±5% (3.135V~3.465V) and is qualified. The measured value of VDDR of DDR is 0x08C7 (corresponding to 2247, 2247×0.5mV=1123.5mV, i.e., 1.1235V), which is within the allowable error range of ±3% (1.067V~1.133V) and is also qualified. If the measured value exceeds the corresponding error threshold, MCU control module 3 will send an I2C write command to reconfigure, retrying a maximum of 2 times. If it still fails, it will report "PMIC voltage configuration abnormal" to host computer 1.

[0066] After sending a voltage configuration command to a configuration register, MCU control module 3 immediately reads back the contents of that register via an I2C read command to confirm that the written coded value matches the target value. For example, after writing the coded value 0x0D05 corresponding to 3.3V to register 0x10 (SOC_VCORE_SET), and then reading back register 0x10, if the read result is 0x0D and 0x05, which matches the target code, then the configuration is successful; if they do not match, it indicates an error in the I2C command transmission, and the configuration command needs to be resent to avoid voltage configuration deviation due to transmission errors.

[0067] When the SOC reports to the MCU that DDR module 4 has entered sleep mode, the MCU control module 3 needs to dynamically adjust the voltage of DDR module 4 via I2C instructions. First, a write instruction is sent to configure the VDDR voltage to 0.8V: register address 0x20, configuration data 0x06 and 0x40, where 0.8V corresponds to 800mV, and the encoded value is 800×2=1600 (hexadecimal 0x640). Next, a write instruction is sent to configure the VDDQ voltage to 0.75V: register address 0x21, configuration data 0x05 and 0xDC, where 0.75V corresponds to 750mV, and the encoded value is 750×2=1500 (hexadecimal 0x5DC). After adjustment, the VOLT_MONITOR register (0x01) is read using a read instruction to confirm that the measured value of VDDR is within the range of 0.776V~0.824V (±3% error tolerance), ensuring that the adjusted voltage meets the sleep mode requirements.

[0068] To test the low-power performance of DDR module 4, a corresponding command can be sent from host computer 1. Upon receiving the command, MCU control module 3 configures a lower voltage sequence via I2C instructions. For the SOC's VCORE voltage, it is reduced to 3.0V (corresponding to 3000mV), and the data written to register 0x10 is 0x0B and 0xB8 (the encoding value corresponding to 3000mV is hexadecimal 0xBB8). For the DDR's VDDR voltage, it is reduced to 0.7V (corresponding to 700mV), and the data written to register 0x20 is 0x05 and 0x38 (700mV × 2 = 1400, corresponding to hexadecimal 0x538). Simultaneously, the power-on timing is adjusted, shortening the power-on interval between SOC module 2 and DDR module 4 from 100 milliseconds to 50 milliseconds. This is achieved by modifying the counting time of the internal timer in MCU control module 3 to adapt to the specific requirements of low-power testing.

[0069] Preferably, the power management integrated circuit includes an MT6319 multiphase controller. The SOC module 2 transmits and starts the MT6319 multiphase controller via the SPI bus, configuring various parameters, including at least output voltage, switching sequence, protection threshold, and executing the power-on sequence.

[0070] The MT6319 multiphase controller sequentially turns on the power supplies to the SOC module 2, including at least the core, memory, and I / O components, according to a preset sequence.

[0071] During system operation, SOC module 2 dynamically adjusts the output voltage (DVFS) of the MT6319 multiphase controller via SPI commands transmitted through the SPI bus according to the load conditions, so as to achieve a balance between performance and power consumption.

[0072] The MT6319, as the multiphase controller within the PMIC, adopts SPI slave mode, with SOC module 2 acting as the SPI master. The two are connected via four dedicated pins: SCLK (clock pin, e.g., PC10) provides the synchronization clock; MOSI (master transmit / slave receive pin, e.g., PC12) transmits commands and configuration data; MISO (master receive / slave transmit pin, e.g., PC11) provides feedback on the status and measured data of the MT6319 multiphase controller; and CS# (chip select pin, e.g., PC9) enables / disables the MT6319 multiphase controller (active low). The bus has no additional pull-up resistors, supporting short-distance board-level transmission (maximum distance 5 cm), adapting to the signal synchronization requirements of the multiphase controller.

[0073] The communication rate is set to 1MHz, balancing real-time performance (single instruction transmission time ≤ 10µs) and anti-interference capability (avoiding signal distortion caused by high-speed clocks). Data transmission adopts the "MSBfirst" format, with clock polarity (CPOL) set to 0 (SCLK is low when idle) and clock phase (CPHA) set to 1 (data is sampled on the second edge of SCLK), conforming to the SPI interface timing requirements of the MT6319. The instruction frame structure is fixed at 16 bits: the first 4 bits are the instruction type (e.g., 0x01 indicates start, 0x02 indicates parameter configuration), and the last 12 bits are the data field (including parameter encoding or status information). During transmission, CS# must be pulled low first, and after SCLK synchronization, the complete 16 bits of data are sent. After transmission, CS# is pulled high to complete one communication cycle.

[0074] To ensure reliable command transmission, the MT6319 returns an 8-bit acknowledgment code via the MISO pin after receiving each command from the SOC: 0x00 indicates successful and valid command reception, 0x01 indicates an incorrect command format, and 0x02 indicates parameters are out of range. After sending a command, the SOC waits 1µs (the MT6319's response delay) to read the acknowledgment code from the MISO pin. If the code is 0x01 or 0x02, the command must be resent (maximum of two retries), with a 5µs interval between retryes, to prevent configuration failure due to a single transmission error.

[0075] During the initial power-up phase, the PMIC main power supply provides basic power (e.g., 3.3V) to the MT6319, which then enters standby mode. At this time, the SOC starts the controller via SPI: first, it pulls CS# low to enable the MT6319, sends a 16-bit startup command (0x0100, the first 4 bits being 0x01 for the startup command, and the last 12 bits being 0x00 for default initialization parameters), and after the MISO returns a 0x00 confirmation code, it pulls CS# high to complete the startup. After startup, the MT6319 automatically enters the "parameter configuration ready" state, waiting for the SOC to send specific power supply parameters.

[0076] SPI configuration of key parameters (output voltage, switching timing, protection threshold):

[0077] Output Voltage Configuration: The SOC configures the voltage for each of its three core power domains (Core VCORE, Memory VMEM, and I / O VIO). The MT6319 multiphase controller uses a 10-bit DAC encoding to control the output voltage, with a step size of 1mV. The encoded value equals the target voltage (mV). For example, when configuring VCORE to 1.0V (1000mV), the SOC sends instruction 0x023E8 (the first 4 bits 0x02 are parameter configuration, and the first 10 bits of the last 12 bits 0x3E8 are the hexadecimal code for 1000, with the last 2 bits reserved); to configure VMEM to 1.2V (1200mV), 0x024B0 is sent; to configure VIO to 1.8V (1800mV), 0x02708 is sent. After each voltage configuration instruction is sent, the SOC needs to read the MT6319's MISO feedback to confirm that the voltage code has been correctly written to the internal registers.

[0078] Switching timing configuration: To avoid inrush current caused by simultaneous power-on of multiple power domains, the SOC sets the power-on interval for each power supply via SPI. The instruction format is 0x03XXY (0x03 is the timing configuration instruction, XX is the interval time code between the previous power supply and the current power supply, and Y is the power domain identifier: 1=VCORE, 2=VMEM, 3=VIO). For example, to set VMEM to start after a 200µs delay following VCORE startup, the instruction 0x03C82 is sent (XX=0xC8 corresponds to 200µs, Y=2 corresponds to VMEM); to set VIO to start after a 150µs delay following VMEM startup, the instruction 0x03963 is sent (XX=0x96 corresponds to 150µs, Y=3 corresponds to VIO). After receiving the data, the MT6319 stores the timing parameters in its internal timing controller for subsequent power-on execution.

[0079] Protection threshold configuration: Set overvoltage, overcurrent, and overtemperature protection thresholds for each power domain. The overvoltage protection threshold is set to 120% of the target voltage. For example, when VCORE=1.0V, the overvoltage threshold is 1.2V (1200mV), and the configuration command is 0x043E81 (0x04 is the protection configuration command, 0x3E8 is the 1200mV code, and 1 is the VCORE identifier). The overcurrent protection threshold is set according to the power domain current level. VCORE's maximum current is 3A, so the overcurrent threshold is set to 3.6A, coded as 0x0E10 (corresponding to 3600mA), and the command is 0x050E101. The overtemperature protection threshold is uniformly set to 125℃, coded as 0x7D, and the command is 0x067D (0x06 is the temperature protection command). After configuration, the MT6319 monitors each parameter in real time. When the threshold is exceeded, it automatically triggers protection (such as shutting down the corresponding power supply) and sends an alarm signal via MISO.

[0080] After the SOC completes all parameter configurations, it sends a power-on execution command 0x0700 (0x07 is the power-on command, 0x00 is the execution identifier). Upon receiving this command, the MT6319 starts its internal timing logic, activating each power domain in a preset order: First, it activates the core power supply VCORE. The internal DAC increases the output voltage from 0V to the target value of 1.0V at a slope of 50mV / us. After the voltage stabilizes (approximately 20us), it sends a "VCORE ready" signal (0x0801) to the SOC via MISO. Second, after a delay of 200us (according to the previously configured timing interval), it activates the memory power supply VMEM, which also increases the voltage to 1.2V at a slope of 50mV / us. After stabilization, it sends a "VMEM ready" signal (0x0802).

[0081] The third step involves a 150µs delay before enabling the I / O power supply (VIO). The voltage ramp is increased to 1.8V, and once stable, a "VIO Ready" signal (0x0803) is sent. The entire power-on process takes approximately 400µs. After the SOC receives all the "Ready" signals, it confirms that the MT6319 has completed full power supply to the SOC and can begin subsequent system initialization.

[0082] When the MT6319 is powered on in each power domain, it maintains voltage stability through the feedback regulation mechanism of the multi-phase Buck circuit: for example, when the VCORE is powered on, the internal current sampling resistor monitors the output current in real time. If the voltage drops due to load fluctuations (such as dropping to 0.98V), the feedback circuit immediately adjusts the PWM duty cycle to increase the output voltage to 1.0V; at the same time, it controls the voltage rise slope to avoid inductor current spikes caused by excessively fast slopes (the maximum spike current is controlled within 1.5 times the rated current), ensuring the stability of the SOC power supply.

[0083] During system operation, the SOC monitors core computing load (such as CPU utilization), memory bandwidth utilization, and core temperature in real time through internal sensors. When the load rate exceeds 80% for 50ms (high load scenario), or the temperature exceeds 85℃ (power consumption reduction is required), or the load rate is below 30% for 100ms (low load scenario), the DVFS adjustment logic is triggered to determine the target output voltage of the MT6319. For example, under high load, VCORE needs to be increased to enhance performance, and under low load, VCORE needs to be decreased to save power.

[0084] Based on the load assessment, the SOC sends a dynamic adjustment command to the MT6319 via SPI. Taking a high load scenario where VCORE increases from 1.0V to 1.2V: the SOC sends command 0x094B01 (0x09 is the DVFS adjustment command, 0x4B0 is the 1200mV code, and 1 is the VCORE identifier). Upon receiving this command, the MT6319 immediately adjusts its internal DAC, increasing the VCORE voltage to 1.2V at a rate of 30mV / µs (to avoid sudden voltage spikes affecting system operation). During the adjustment process, the MISO provides real-time feedback on the current voltage value (e.g., 0x0A4A0 indicates a current voltage of 1184mV).

[0085] Once the voltage stabilizes at 1.2V, the MT6319 sends an "adjustment complete" signal (0x0B00), which is confirmed by the SOC to complete the DVFS adjustment. In low-load scenarios, VCORE drops from 1.0V to 0.8V (800mV, encoded 0x320), with the instruction 0x093201. The adjustment slope is also 30mV / us, ensuring a smooth voltage transition and balancing performance and power consumption.

[0086] After each DVFS adjustment, the SOC reads the measured voltage register of the MT6319 via SPI (instruction 0x0C01, where 0x0C is the read instruction and 01 is the VCORE identifier) ​​to confirm that the deviation between the measured voltage and the target voltage is within ±2% (e.g., if the target is 1.2V, the measured voltage should be between 1.176V and 1.224V). If the deviation exceeds the range, the SOC resends the adjustment command (retrying a maximum of 2 times). If the error persists, an alarm is triggered and the system switches to a safe voltage (e.g., 1.0V) to ensure stable system operation.

[0087] This embodiment achieves precise transmission of commands and data across the entire link through a layered design, adapting each interface to the characteristics of the modules, and incorporating retry and verification mechanisms, forming a communication closed loop with "no loss and no errors." It precisely configures the SOC and DDR voltages by domain, dynamically adjusting voltage balance performance and power consumption as needed via DVFS, and strictly controls the power-on sequence and slope, executing standardized power-off sequences to ensure power supply safety. It provides high-precision monitoring of DDR multi-state currents, real-time verification of power supply parameters, and structured processing of test data to generate comparison reports, providing accurate and readable data for test evaluation. Hardware-level rapid protection, software-level fault tolerance, and multi-module collaborative feedback significantly reduce the risk of failure.

[0088] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0089] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0090] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0091] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A hardware optimization method for a test project, characterized in that, The method includes: The host computer is a PC. The SOC module is a system-on-a-chip. The SOC module is the control core of the entire test system and enables the communication of the test system. The MCU control module communicates asynchronously with the host computer via the UART interface and simultaneously exchanges high-speed data with the main control SOC module via the SPI interface. The MCU control module completes the communication between the host computer and the SOC module and controls the power on and off of the SOC module. The DDR module is connected to the DDR terminal of the MCU control module, and the MCU control module performs current testing on the DDR module. The MCU control module integrates a current sensor, which monitors the read / write current, standby current, and sleep current of the DDR module in real time, and uploads the current data monitored by the current sensor to the host computer through an ADC converter. The MCU control module integrates a current sensor, which monitors the read / write current, standby current, and sleep current of the DDR module in real time. The steps of uploading the current data monitored by the current sensor to the host computer via an ADC converter include: When the test is started, the MCU control module controls the SOC module to power on, and the entire system runs the test program. During the test, the MCU control module tested the read / write current, standby current, and sleep current of the DDR module by monitoring the current sensor. After each test, the MCU control module controls the SOC module to power off, so that the DDR module can be picked up and put down without power, and the current data monitored by the current sensor is uploaded to the host computer through the ADC converter. The steps for testing the read / write current, standby current, and sleep current of the DDR module monitored by the current sensor during the testing process include: When the host computer issues a test start command, the "Start Test" button is turned on and a start command is generated, which is then sent to the MCU control module via UART; When the MCU control module receives the start command, it forwards it to the SOC module via the SPI bus, and the SOC module drives the DDR module to enter the test mode. The SOC module parses the boot command and generates timing signals through its internal DDR controller. These timing signals are then sent to the DDR module via the DDR bus, controlling the DDR module to enter Burst read / write mode and acquiring the read / write current of the DDR module. Within 10µs, after receiving the mode identifier, the MCU control module switches the current sensor range: upon receiving the read / write mode identifier, the current sensor switches to 0~2A; upon receiving the sleep mode identifier, the current sensor switches to 0~100mA. The MCU control module then starts the ADC to collect the analog voltage output by the current sensor and converts it into the actual current value according to the range.

2. The hardware optimization method for the test item as described in claim 1, characterized in that, The MCU control module integrates a power management integrated circuit, which configures the output voltage sequence via the I2C bus.

3. The hardware optimization method for the test item as described in claim 2, characterized in that, The power management integrated circuit includes an MT6319 multiphase controller. The SOC module transmits and starts the MT6319 multiphase controller via the SPI bus, configuring various parameters, including at least the output voltage, switching sequence, protection threshold, and executing the power-on sequence. The MT6319 multiphase controller sequentially turns on the power supplies to the SOC module, including at least the core, memory, and I / O, according to a preset sequence. During system operation, the SOC module dynamically adjusts the output voltage of the MT6319 multiphase controller according to the load conditions via SPI commands transmitted through the SPI bus, in order to achieve a balance between performance and power consumption.

4. The hardware optimization method for the test item as described in claim 1, characterized in that, When the test is initiated, the MCU control module controls the SOC module to power on, and the steps for the entire system to run the test program include: The host computer initiates the test task configuration, and the operator completes the parameter settings in the GUI interface; The MCU control module receives and verifies the command, and then powers on the SOC module. The SOC module initializes and reports its ready status; The MCU control module sends a preparation completion message to the host computer. After receiving the signal from the SOC module, it sends a preparation completion frame to the host computer via UART.

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