A forgetting mechanism conditioned reflex circuit based on memristor neural network

Abstract

This invention discloses a conditioned reflex circuit for a forgetting mechanism based on a memristor neural network. The circuit consists of three signal conditioning modules, two feedback control modules, and two reflection generation modules. The signal conditioning modules use comparators and operational amplifiers to discriminate, control the amplitude, and shape the delay of the input signal. The feedback control modules output an enhancement voltage, a weak inhibition voltage, or a strong inhibition voltage based on the combination of reward and behavioral signals, thereby achieving differentiation control of synaptic weights. The reflection generation modules utilize the write-read characteristics of the memristor to dynamically change or detect the memristor resistance value and output conditioned reflex behavioral signals through logic gates. The proposed conditioned reflex circuit for a forgetting mechanism can realize learning, forgetting, generalization, and differentiation functions at the hardware level, and relatively completely simulates the conditioned reflex mechanism in biological neural networks. It has high biological realism and hardware implementation value.

Description

Technical Field

[0001] This invention relates to the field of memristor neural network circuit design, and particularly to a conditioned reflex circuit based on the forgetting mechanism of a memristor neural network. Background Technology

[0002] As the most complex and efficient information processing system currently available, biological neural networks have been extensively studied for their information processing methods. Constructing mathematical models based on the operating principles of biological neural networks to realize artificial neural networks has gradually become a research hotspot.

[0003] Artificial neural networks can be implemented primarily through software and hardware approaches. While software implementation remains the mainstream method, the "memory wall" problem of traditional von Neumann computing architectures severely restricts information processing efficiency due to the explosive growth of data volume. Therefore, implementing artificial neural networks using hardware circuits is gradually becoming a feasible path.

[0004] Similar to the synaptic connections between neurons in biological neural networks, the variable connection weights in artificial neural networks correspond to the changes in synaptic weights in biological neural networks.

[0005] The memristor, the fourth fundamental electronic component in circuit theory, has become a core component in the hardware circuit implementation of artificial neural networks due to its resistance plasticity. The resistance plasticity of a memristor means that its resistance changes when a specific external electric field is applied; furthermore, this plasticity is directional, meaning that an external electric field in the opposite direction will produce the opposite resistance change. This property of the memristor perfectly reflects the plasticity of biological synaptic weights, thus making it crucial in the hardware circuit implementation of artificial neural networks.

[0006] In addition to exhibiting bio-synaptic-like properties, memristors also possess advantages such as low power consumption, nanoscale size, and compatibility with MOSFETs. These advantages make the research on using memristors to realize artificial neural network hardware circuits a promising area for development.

[0007] Current research on conditioned reflex mechanisms shows that the resistance of a memristor can be controlled through the interaction of trigger signals, reward signals, and activity signals. This process essentially involves altering neuron weights, thereby achieving the learning function of a conditioned reflex. The conditioned reflex circuit of the forgetting mechanism mainly consists of three parts: a signal conditioning module, a feedback control module, and a reflex generation module. The signal conditioning module not only possesses a certain degree of anti-interference capability but also allows for changes in signal delay duration, providing a stable foundation for subsequent signal processing. The feedback control module can match corresponding enhancement voltage, weak inhibition voltage, and strong inhibition voltage based on the specific input voltage. These three voltages correspond to the learning process, natural extinction process, and instrumental extinction process in biological mechanisms, respectively, accurately simulating the dynamic regulatory logic of biological reflexes. The reflex generation module controls the resistance of the memristor through a "write-read" process; simultaneously, this circuit can read the state of the synaptic memristor and monitor the training effect in real time based on the memristor's resistance, forming a closed-loop "control-monitoring" function.

[0008] With the continuous development of memristor technology, its application in neural network hardware circuits has become increasingly mature. Various types of neural networks can now be implemented using memristor circuits, such as competitive neural networks, feedforward neural networks, and convolutional neural networks. However, to date, the integration of the biological mechanism of conditioned reflex with memristors has not achieved further breakthroughs or substantial progress. Based on this, this invention proposes a conditioned reflex circuit for the forgetting mechanism based on memristor neural networks, leveraging the plasticity of memristor resistance. The memristor neural network circuit proposed in this invention can simulate the biological mechanism of conditioned reflex at the hardware level. Summary of the Invention

[0009] The forgetting mechanism conditioned reflex circuit is a neural network built on unsupervised learning. It distinguishes between enhancing, weakly inhibiting, and strongly inhibiting voltages through the synergistic effect of trigger signals, reward signals, and activity signals, thereby controlling the resistance value of the memristor. The essence of this process is the implementation of conditioned reflex learning.

[0010] Based on the biological mechanism of conditioned reflex, this invention proposes a conditioned reflex circuit for forgetting mechanism based on memristor neural network. This circuit utilizes the resistance plasticity of the novel two-terminal device memristor to construct a memristor neural network circuit, ultimately simulating conditioned reflex at the hardware level.

[0011] This invention is achieved through the following technical solution: a conditioned reflex circuit for a forgetting mechanism based on a memristor neural network, such as... Figure 1 As shown, it includes a signal conditioning module, a feedback control module, and a reflection generation module.

[0012] This invention proposes a conditioned reflex circuit for a forgetting mechanism based on a memristor neural network. It comprises three signal conditioning modules, abbreviated as SD-A1, SD-R, and SD-A2. For example... Figure 2 The signal conditioning module SD-A1 shown here consists of an external DC voltage source V. Pd1 -V Pd6 V Nd1 -V Nd6 V d1 -V d2 NMOS transistor N d1 -N d6 PMOS transistor P d1 -P d6 Operational amplifier U d1 Dual-input single-output analog behavioral device ABM d1 -ABM d2 memristor M d1 and resistance R d1 Composition. Among them, V in V is the input signal for this module circuit. a1 Its output signal. ABM d1 -ABM d2 Used to simulate the addition behavior of two input signals IN1 and IN2. NMOS transistor N d1 -N d3 and PMOS transistor P d1 -P d3 Together they form comparator COM1. NMOS transistor N d4 -N d6 PMOS transistor P d4 -P d6 and ABM d1 -ABM d2 Together they form comparator COM2. Operational amplifier U d1 memristor M d1 and resistance R d1 Together, they constitute an inverting operational amplifier with a variable output ratio. In COM1, the external DC voltage source V... Pdn V Ndn respectively with P dn and N dn The source is connected; N dn gate and P dn The gate is connected; N dn The drain and P dn The drains are connected; where n = 1, 2, 3. When n = 1, N dn With P dn The gate is connected to the external input voltage V. in When n=2 or 3, N dn With Pdn The gate is connected to and receives N dn-1 With P dn-1 The drain output signal is used to transmit the signal. In COM2, the PMOS transistor P... d4 The source and ABM d1 The output terminal is connected to the NMOS transistor N. d4 The source and ABM d2 Connect the output terminal of ABM; d1 The input terminals are respectively connected to an external DC voltage source V. Pd4 V d1 ABM d2 The input terminals are respectively connected to an external DC voltage source V. Nd4 V d2 By adjusting V d1 V d2 The voltage amplitude can be adjusted to change the pulse width, thereby achieving signal conditioning. The output voltage of the inverting operational amplifier is related to the memristor M. d1 The resistance is proportional to the voltage applied. When the applied voltage is positive and higher than the positive threshold voltage of the memristor, the voltage applied to the memristor M... d1 Make M d1 The resistance increases. When the applied voltage is negative and lower than the negative threshold voltage of the memristor, the voltage applied to the memristor M... d1 Make M d1 The resistance decreases.

[0013] The working principle of the signal conditioning module is as follows. When the input signal V... in In the first half of the cycle, V in At this time, P is at a high level. d1 N d2 P d3 When the circuit is turned on, the output voltage of comparator COM1 is equal to P. d3 External power supply voltage V of the source Pd3 And connected to operational amplifier U d1 The inverting input terminal. In this state, U d1 The output voltage is positive and greater than the positive threshold voltage of the memristor, M d1 The resistance increases, and N d4 P d5 N d6 When the circuit is turned on, the output voltage of comparator COM2 is equal to N. d6 Source power supply voltage V Nd6 In the input signal V in In the latter half of the cycle, V in When N is low, d1 P d2 N d3 When the circuit is turned on, the output voltage of comparator COM1 is equal to N.d3 External power supply voltage V of the source Nd3 And connected to operational amplifier U d1 The inverting input terminal. In this state, U d1 The output voltage is negative and less than the negative threshold voltage of the memristor, M d1 The resistance decreases. Based on the operational amplifier U... d1 With changes in output voltage, the circuit further exhibits two operating states: when U d1 When the output voltage is less than -0.5V, P d4 N d5 P d6 When the circuit is turned on, the output voltage of comparator COM2 is equal to P. d6 Source voltage source V Pd6 The voltage; when the memristor resistance decreases until U d1 When the output voltage is greater than -0.5V, N d4 P d5 N d6 When the circuit is turned on, the output voltage of comparator COM2 switches to N. d6 Source power supply voltage V Nd6 This means completing the signal adjustment process from high level to low level.

[0014] This invention proposes a conditioned reflex circuit for a forgetting mechanism based on a memristor neural network, which includes two feedback control modules 1 and 2. For example... Figure 3 The diagram shows feedback control module 1, which consists of an external DC voltage source V. s1 -V s2 Switch S S1 -S S3 Operational amplifier U s1 -U s2 Resistance R s1 -R s5 Composition. To achieve an accurate description of the circuit, Figure 3 The two modules, SD-A1 and SD-R, represent two signal conditioning modules respectively. Switch S S1 -S S3 This collaborative mechanism distinguishes between enhancement-mode, weak suppression-mode, and strong suppression-mode voltages. Switch S S1 The control conduction positive terminal and switch S S2 The control conduction negative terminal is connected, S S1 The control conduction negative terminal and S S2 The control conduction positive terminals are all connected to ground. S S1 S S2 The input terminals of the access circuit are respectively connected to an external DC voltage source V. s1 V s2 The outputs of the two are connected and output a voltage signal. Operational amplifier Us1 -U s2 and resistance R s1 -R s5 Together, they form a two-stage inverting amplifier. The input reward signal V... reward After being processed by the signal conditioning module SD-R, the signal serves two purposes: firstly, as the input signal to the first-stage inverting amplifier, and secondly, as the control signal for switch S. S3 The on / off state of the input activity signal V. action1 After processing by the signal conditioning module SD-A1, it is used to control switch S. S1 S S2 On / off state. When V reward When the signal is high, a high-level signal is generated by the signal conditioning module SD-R, and its amplitude is equal to the output voltage V of the signal conditioning module. dr At this time, switch S S3 S is in the disconnected state. S1 S S2 The output signal at the output terminal of the circuit cannot be transmitted to resistor R. s1 At this time, feedback control module 1 outputs an enhanced voltage. When V reward When the signal is low, the corresponding signal is generated by the signal conditioning module SD-R, and at this time the switch S S3 Switch to closed state, S S1 S S2 The output voltage is transmitted to a two-stage inverting amplifier, the specific voltage type being determined by V. action1 The voltage level determines this. If V action1 High level, switch S S1 Closed, S S2 Disconnect, external power supply voltage V s1 When connected to the circuit and used as the output voltage of a switch, the output voltage type is a strongly suppressed voltage. If V action1 When the voltage is low, switch S S2 Closed, S S1 Disconnect, external power supply voltage V s2 When connected to the circuit and used as the output voltage of the switch, the output voltage type is a weakly suppressed voltage.

[0015] This invention proposes a conditioned reflex circuit based on a memristor neural network for a forgetting mechanism, which includes two reflex generation modules 1 and 2. For example... Figure 4 The image shows reflection generation module 1, which consists of an external DC voltage source V. Pg1 -V Pg2 V Ng1 -V Ng2 Operational amplifier U g1 NMOS transistor N g1 -N g2 PMOS transistor P g1 -Pg2 ABM, a single-input single-output analog behavioral device g1 , digital logic OR gate OR1, switch S g1 -S g5 memristor M g1 and resistance R g1 Composition. The trigger signal V... cue1 Activity signal V action-e1 The input signal of the circuit, the active signal V action1 This is the output signal. External DC voltage source V Pdn V Ndn respectively with P dn and N dn The source is connected; N dn gate and P dn The gate is connected; N dn The drain and P dn The drains are connected, where n=1, 2. When n=1, N dn With P dn The gate is connected and a trigger signal V is applied. cue1 When n=2, N dn With P dn The gate is connected and receives N dn-1 With P dn-1 The drain outputs a signal to achieve signal transmission. Switch S g1 S g3 The control conduction positive terminal and S g2 S g4 The control conduction negative terminal is connected; S g1 S g3 The control conduction negative terminal and S g2 S g4 The control conduction positive terminals are all grounded. Switch S g1 The input terminal of the access circuit is connected to an external power supply voltage V. g1 S g2 The input terminal of the access circuit is connected to the output signal V of the feedback control module 1. s1out The output terminals of the above two circuits are connected to form a memristor M. g1 The input signal. M g1 The output signal is simultaneously connected to switch S g3 and S g4 The input terminal of the circuit. Switch S g4 The output terminal of the access circuit is grounded; switch S g3 The output terminal of the access circuit is connected to the operational amplifier U. g1 The inverting input terminal is connected. Operational amplifier U g1 The non-inverting input terminal is grounded, and the operational amplifier U g1 The output terminal of the analog behavior device ABMg1 The input signal is connected. ABM g1 The input signal is evaluated using the logic IF(V(%IN)>2,1,-1): when the input voltage signal is greater than 2V, ABM... g1 The output is 1V, otherwise it is -1V. This output is used as one of the input signals of the OR1 digital logic gate. The other input of the OR1 gate is connected to switch S. g5 Connect V action-e1 By switch S g5 State control. Switch S g5 The control conduction positive terminal is connected to the trigger signal V cue1 The control circuit's negative terminal is grounded; its input terminal is connected to the active signal V. action-e1 The output terminal of the access circuit is connected to the second input terminal of OR1 to realize V. action-e1 Signal transmission to OR1 gate.

[0016] The working principle of the reflection generation module is as follows. When the trigger signal V... cue1 When N is low, g2 The drain and P g2 The drain output voltage amplitude is equal to that of the external DC voltage source V. Ng2 Switch S g5 When the circuit is open, one of the input terminals of the OR1 gate has no valid input signal; switch S in the circuit... g2 S g4 On, S g1 S g3 Disconnect. At this time, memristor M g1 The positive terminal receives the output voltage signal V from the feedback control module 1. s1out M g1 The negative terminal is grounded. Based on the polarity and amplitude of the output voltage of feedback control module 1, M... g1 The memristor resistance value exhibits two changes: when the output voltage is positive and greater than M... g1 When the positive threshold voltage is reached, M g1 The resistance increases. When the output voltage is negative and less than M... g1 When the negative threshold voltage is reached, M g1 The resistance decreases. The rate of change of the memristor's resistance is determined by the output voltage of feedback control module 1; this process is called the "write process." During this process, M... g1 The memristor value is dynamically modified based on the training voltage. Because S g3 Disconnect, M g1 The output signal is not connected to the operational amplifier U. g1 The inverting input terminal of the OR gate has no valid input signal at the other input terminal, therefore the active signal V... action1 Always keep it low. When V cue1When N is high, g2 The drain and P g2 The drain output voltage amplitude is equal to that of the external DC voltage source V. Pg2 Switch S in the circuit g2 S g4 Disconnect, S g1 S g3 Conduction. At this time, M g1 The positive terminal receives the input signal V. g1 Because of V g1 The amplitude is at M g1 Within the threshold voltage range, M g1 The resistance value of the memristor remains unchanged. g1 The output signal is transmitted through the conducting switch S. g3 Access operational amplifier U g1 The inverting input terminal of the operational amplifier U g1 The output signal is further connected to the analog behavior device ABM g1 The logical judgment is executed, and the result is the conditioned reflex behavior signal. This process is defined as the "reading process," which reads M... g1 This allows for real-time monitoring of training effectiveness. Synaptic weights are inversely proportional to the memristor's resistance. When M... g1 When the memristor resistance is greater than 1kΩ, it indicates that the synaptic connection is weak and the conditioned reflex has not yet been successfully established; when M g1 When the memristor resistance drops to 1kΩ, it indicates that the conditioned reflex has been successfully established.

[0017] This invention proposes a conditioned reflex circuit based on a memristor neural network, which consists of three signal conditioning modules, two feedback control modules, and two reflection generation modules. The signal conditioning modules, acting as the circuit's signal preprocessing unit, primarily operate based on the activity signal V. action1 and V action2 and reward signal V reward The output voltage is generated based on the voltage level. The feedback control module is responsible for the core functions of dynamically adjusting synaptic weights and monitoring training effects. By outputting a specific training voltage to the synaptic memristor, the resistance value of the memristor is dynamically modified, thereby controlling the synaptic weights. Simultaneously, the changes in the memristor resistance value provide real-time feedback on the current training effect, providing a basis for circuit function optimization. By configuring different input voltages, this memristor neural network circuit can achieve various functions.

[0018] The proposed memristor neural network circuit can achieve multiple functions, including learning, forgetting, generalization, and differentiation. During the learning and forgetting processes, the reward signal V... reward With activity signal V action1 and V action2Maintain synchronization. The combination of their levels directly determines the output characteristics of the feedback control module, specifically as follows: when V reward and V action1 V action2 When both are high, the feedback control module outputs a high level, indicating "behavior accompanied by reward," thereby generating an enhanced voltage; when V reward and V action1 V action2 When both are low, the circuit outputs a weak negative voltage. This state corresponds to a scenario of "no behavior and no reward," generating a weak inhibitory voltage, which is a normal forgetting process; when V action1 and V action2 For high level and V reward When the voltage is low, it outputs a strong suppression voltage, which corresponds to the scenario of "behavior without reward", thus generating a strong reflection extinction voltage. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of a forgetting mechanism based on a memristor neural network.

[0020] Figure 2 This is a schematic diagram of the signal conditioning module.

[0021] Figure 3 This is a schematic diagram of the feedback control module.

[0022] Figure 4 This is a schematic diagram of the reflection generation module.

[0023] Figure 5 The diagram shows the changes in synaptic weights in the conditioned reflex circuit of the forgetting mechanism.

[0024] Figure 6 The diagram shows the learning, forgetting, generalization, and differentiation results in the conditioned reflex circuit of the forgetting mechanism. Detailed Implementation

[0025] To make the technical solution, objectives, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] like Figure 1 As shown, this invention proposes a conditional reflex circuit for a forgetting mechanism based on a memristor neural network, which includes three signal conditioning modules, two feedback control modules, and two reflection generation modules.

[0027] like Figure 1 As shown, this invention proposes a conditioned reflex circuit for a forgetting mechanism based on a memristor neural network, which includes three signal conditioning modules, abbreviated as SD-A1, SD-R, and SD-A2. Signal conditioning module 1 (SD-A1) is powered by an external voltage source V. Pd1 -VPd6 V Nd1 -V Nd6 V d1 -V d2 NMOS transistor N d1 -N d6 PMOS transistor P d1 -P d6 Analog behavioral device ABM d1 -ABM d2 memristor M d1 resistance R d1 and operational amplifier U d1 Composition. Signal conditioning module 2 (SD-R) consists of an external voltage source V. Pd7 -V Pd12 V Nd7 -V Nd12 V d3 -V d4 NMOS transistor N d7 -N d12 PMOS transistor P d7 -P d12 Analog behavioral device ABM d3 -ABM d4 memristor M d2 resistance R d2 and operational amplifier U d2 Composition. Signal conditioning module 3 (SD-A2) consists of an external voltage source V. Pd13 -V Pd18 V Nd13 -V Nd18 V d5 -V d6 NMOS transistor N d13 -N d18 PMOS transistor P d13 -P d18 Analog behavioral device ABM d5 -ABM d6 memristor M d3 resistance R d3 and operational amplifier U d3 Composition. N d1 With P d1 The gate is connected to and connected to the output signal V of the reflection generation module 1. action1 External voltage source V Pd1 With P d1 The source is connected, V Nd1 With N d1 The source is connected; N d1 With P d1 The drain is connected to N d2 With P d2The gates are connected together. External voltage source V Pd2 With P d2 The source is connected, V Nd2 With N d2 The source and the pole are connected. N d2 With P d2 The drains are connected together and with N d3 With P d3 The gate is connected. External voltage source V Pd3 With P d3 The source is connected, V Nd3 With N d3 The source is connected; N d3 With P d3 The drain is connected to the resistor R. d1 One end is connected. Resistor R d1 The other end is connected to the operational amplifier U d1 The inverting input terminal is connected in parallel with the memristor M. d1 One end is connected together, U d1 The non-inverting input terminal is grounded. U d1 The output terminal and M d1 The other end is connected to N d4 With P d4 The gates are connected together. Analog behavioral device ABM d1 The output terminal and P d4 The source is connected to the analog behavioral device ABM. d2 The output terminal and N d4 The source and pole are connected. ABM d1 The two input terminals IN1 and IN2 are respectively connected to V Pd4 With V d1 ABM d2 The two input terminals IN1 and IN2 are respectively connected to V Nd4 With V d2 N d4 With P d4 The drain is connected to N d5 With P d5 The gates are connected together. External voltage source V Pd5 With P d5 The source is connected, V Nd5 With N d5 The source and pole are connected. N d5 With P d5 The drain is connected to N d6 With P d6 The gates are connected together. External voltage source V Pd6 With P d6 The source is connected, V Nd6 With N d6 The source and pole are connected. N d6 With Pd6 The drains are connected together and serve as the output signal V of the SD-A1 module. a1 V a1 Same as switch S S1 The control conduction positive terminal and switch S S2 The control conduction negative terminals are connected together. N d7 With P d7 The gates are connected together and connected to the reward signal V. reward External voltage source V Pd7 With P d7 The source is connected, V Nd7 With N d7 The source and pole are connected. N d7 With P d7 The drain is connected to N d8 With P d8 The gates are connected together. External voltage source V Pd8 With P d8 The source is connected, V Nd8 With N d8 The source and pole are connected. N d8 With P d8 The drain is connected to N d9 With P d9 The gates are connected together. External voltage source V Pd9 With P d9 The source is connected, V Nd9 With N d9 The source and pole are connected. N d9 With P d9 The drain is connected to the resistor R. d2 One end of each resistor is connected together. Resistor R d2 The other end and U d2 The inverting input is connected together with M d2 One end is connected. U d2 The non-inverting input terminal is grounded. U d2 The output terminal and M d2 The other end is connected to N d10 With P d10 The gates are connected together. Analog behavioral device ABM d3 The output terminal and P d10 The source is connected to the analog behavioral device ABM. d4 The output terminal and N d10 The source and pole are connected. ABM d3 The two input terminals IN1 and IN2 are connected to V Pd10 With V d3 ABM d4 The two input terminals IN1 and IN2 are connected to V Nd10 With V d4 Nd10 With P d10 The drain is connected to N d11 With P d11 The gates are connected together. External voltage source V Pd11 With P d11 The source is connected, V Nd11 With N d11 The source and pole are connected. N d11 With P d11 The drain is connected to N d12 With P d12 The gates are connected together. External voltage source V Pd12 With P d12 The source is connected, V Nd12 With N d12 The source and pole are connected. N d12 With P d12 The drains are connected together and serve as the output signal V of the SD-R module. r V r Same as switch S S3 S S4 The control on-side negative terminal is connected to resistor R. s2 R s6 One end is connected together. N d13 With P d13 The gate is connected to and connected to the output signal V of the reflection generation module 2. action2 External voltage source V Pd13 With P d13 The source is connected, V Nd13 With N d13 The source and pole are connected. N d13 With P d13 The drain is connected to N d14 With P d14 The gates are connected together. External voltage source V Pd14 With P d14 The source is connected, V Nd14 With N d14 The source and pole are connected. N d14 With P d14 The drain is connected to N d15 With P d15 The gates are connected together. External voltage source V Pd15 With P d15 The source is connected, V Nd15 With N d15 The source and pole are connected. N d15 With P d15 The drain is connected to the resistor R. d3 One end is connected. Resistor R d3 The other end and U d3 The inverting input terminal is connected to M.d3 One end is connected together. U d3 The non-inverting input terminal is grounded. U d3 The output terminal and M d3 The other end is connected to N d16 With P d16 The gates are connected together. Analog behavioral device ABM d5 The output terminal and P d16 The source is connected to the analog behavioral device ABM. d6 The output terminal and N d16 The source and pole are connected. ABM d5 The two input terminals IN1 and IN2 are connected to V Pd16 With V d5 ABM d6 The two input terminals IN1 and IN2 are connected to V Nd16 With V d6 N d16 With P d16 The drain is connected to N d17 With P d17 The gates are connected together. External voltage source V Pd17 With P d17 The source is connected, V Nd17 With N d17 The source and pole are connected. N d17 With P d17 The drain is connected to N d18 With P d18 The gates are connected together. External voltage source V Pd18 With P d18 The source is connected, V Nd18 With N d18 The source and pole are connected. N d18 With P d18 The drains are connected together and serve as the output signal V of the SD-A2 module. a2 V a2 Same as switch S S5 The control conduction positive terminal and switch S S6 The control conduction negative terminals are connected together.

[0028] like Figure 1 As shown, this invention proposes a conditioned reflex circuit for a forgetting mechanism based on a memristor neural network, which includes two feedback control modules 1 and 2. Feedback control module 1 is powered by an external voltage source V. s1 -V s2 Switch S S1 -S S3 Operational amplifier U s1 -U s2 and resistance R s1 -R s5Composition. The feedback control module 2 consists of an external voltage source V. s5 -V s6 Switch S S4 -S S6 Operational amplifier U s3 -U s4 and resistance R s6 -R s10 Composition. Switch S S1 The control conduction negative terminal and S S2 The control conduction positive terminals are all connected to ground. External voltage source V s1 V s2 Respectively with switch S S1 S S2 The input terminal of the access circuit is connected. S S1 S S2 The output terminals of the access circuits are connected together and connected to S. S3 The input terminal of the circuit. Switch S S3 S S4 Control of the positive terminal and operational amplifier U s1 U s2 U s3 U s4 The non-inverting input terminals are all grounded. Resistor R s1 One end is connected to switch S S3 The input circuit output terminal is connected, and the resistor R s1 The other end is connected to resistor R s2 The other end, R s3 One end and operational amplifier U s1 The inverting input terminals are connected together. Resistor R s3 The other end is connected to resistor R s4 One end is connected to the operational amplifier U s1 The output terminals are connected together. Resistor R s5 One end is connected to resistor R s4 The other end is connected to the operational amplifier U s2 The inverting input terminals are connected together. Resistor R s5 The other end is the same as the operational amplifier U s2 The output terminal is connected and used as the output signal V of the feedback control module 1. s1out V s1out With switch S in reflection generation module 1 g2 The input terminals of the access circuit are connected together. Switch S S5 The control conduction negative terminal and S S6 The control conduction positive terminals are all connected to ground. External voltage source V s5 V s6 Respectively with switch S S5 S S6The input terminal of the access circuit is connected. S S5 S S6 The output terminals of the access circuits are connected together and connected to S. S4 The input terminal of the circuit. Resistor R s7 One end is connected to switch S S4 The input circuit output terminal is connected, and the resistor R s7 The other end is connected to resistor R s6 The other end, R s8 One end is connected together with the operational amplifier U s3 The inverting input terminals are connected together. Resistor R s8 The other end is connected to resistor R s9 One end is connected to the operational amplifier U s3 The output terminals are connected together. Resistor R s10 One end is connected to resistor R s9 The other end is connected to the operational amplifier U s4 The inverting input terminals are connected together. Resistor R s10 The other end is the same as the operational amplifier U s4 The output terminal is connected and used as the output signal V of the feedback control module 2. s2out V s2out With switch S in reflection generation module 2 g6 The input terminals of the access circuits are connected together.

[0029] like Figure 1 As shown, this invention proposes a conditional reflex circuit based on a memristor neural network for a forgetting mechanism, which includes two reflection generation modules 1 and 2. Reflection generation module 1 is powered by an external voltage source V. Pg1 -V Pg2 V Ng1 -V Ng2 V g1 NMOS transistor N g1 -N g2 PMOS transistor P g1 -P g2 Operational amplifier U g1 ABM, a single-input single-output analog behavioral device g1 Switch S g1 -S g5 Two-input OR gate OR1, memristor M g1 and resistance R g1 Composition. The reflection generation module 2 consists of an external voltage source V. Pg3 -V Pg4 V Ng3 -V Ng4 V g7 NMOS transistor N g3 -N g4PMOS transistor P g3 -P g4 Operational amplifier U g2 ABM, a single-input single-output analog behavioral device g2 Switch S g6 -S g10 Two-input OR gate OR2, memristor M g2 and resistance R g2 Composition. External voltage source V Pg1 With P g1 The source is connected, V Ng1 With N g1 The source and pole are connected. N g1 With P g1 The gate is connected and a trigger signal V is applied. cue1 N g1 With P g1 The drain is connected to N g2 With P g2 The gates are connected together. External voltage source V Pg2 With P g2 The source is connected, V Ng2 With N g2 The source and pole are connected. N g2 With P g2 The drain is connected to the switch S. g1 S g3 Control of the positive terminal of the conductor, switch S g2 S g4 The control conduction negative terminals are connected together. Switch S g1 S g3 S g5 The control conduction negative terminals are all grounded, switch S g2 S g4 Control of the positive terminal and switch S g4 The output terminals of the access circuit are all grounded. V g1 Connect to switch S g1 The input terminal of the circuit. Switch S g1 S g2 The output terminal of the access circuit is connected to M g1 One end. M g1 The other end is connected to switch S g3 The input terminal of the access circuit and switch S g4 The input terminal of the circuit. Switch S g3 The output terminal of the access circuit is connected to the resistor R. g1 One end is connected to the operational amplifier U g1 The inverting inputs are connected together. U g1 The non-inverting input terminal is grounded. Resistor R g1 The other end is the same as the operational amplifier U g1The output terminal is connected to the analog behavior device ABM. g1 The input terminals are connected together. ABM g1 The output terminal of OR1 is connected to one input terminal of OR1. The other input terminal of OR1 is connected to switch S. g5 The input circuit output terminal is connected. Switch S g5 The control conduction positive terminal is connected to the trigger signal V cue1 Switch S g5 The input terminal of the access circuit is connected to the active signal V. action-e1。 The output signal of OR1 is the activity signal V of reflection generation module 1. action1 External voltage source V Pg3 With P g3 The source is connected, V Ng3 With N g3 The source and pole are connected. N g3 With P g3 The gate is connected and a trigger signal V is applied. cue2 N g3 With P g3 The drain is connected to N g4 With P g4 The gates are connected together. External voltage source V Pg4 With P g4 The source is connected, V Ng4 With N g4 The source and pole are connected. N g4 With P g4 The drain is connected to the switch S. g7 S g9 Control of the positive terminal of the conductor, switch S g6 S g8 The control conduction negative terminals are connected together. Switch S g7 S g9 S g10 The control conduction negative terminals are all grounded, switch S g6 S g8 Control of the positive terminal and switch S g8 The output terminals of the access circuit are all grounded. V g7 Connect to switch S g7 The input terminal of the circuit. Switch S g6 S g7 The output terminal of the access circuit is connected to M g2 One end. M g2 The other end is connected to switch S g8 The input terminal of the access circuit and switch S g9 The input terminal of the circuit. Switch S g9 The output terminal of the access circuit is connected to the resistor R. g2 One end is connected to the operational amplifier U g2The inverting inputs are connected together. U g2 The non-inverting input terminal is grounded. Resistor R g2 The other end is the same as the operational amplifier U g2 The output terminal is connected to the analog behavior device ABM. g2 The input terminals are connected together. ABM g2 The output of OR2 is connected to one input of OR2. The other input of OR2 is connected to switch S. g10 The input circuit output terminal is connected. Switch S g10 The control conduction positive terminal is connected to the trigger signal V cue2 Switch S g10 The input terminal of the access circuit is connected to the active signal V. action-e2。 The output signal of OR2 is the activity signal V of the reflection generation module 2. action2 .

[0030] Taking the conditioning training of mice as an example, the learning process involves mice randomly pressing a round button to receive a food reward. Through repeated training, the mice gradually form an association between pressing the round button and receiving a food reward, increasing the probability of pressing the round button when hungry. Even if the food reward is removed, this association persists, causing the mice to continue pressing the round button. However, if pressing the round button does not provide a food reward, after repeated training, the mice will eventually forget to press the round button, entering the forgetting process. The generalization process is similar to the training process, except that after training, round and square buttons appear randomly. Through training, hungry mice not only increase their tendency to press the round button but also increase the probability of pressing the square button. Therefore, the mice simultaneously establish associations between pressing the round button and receiving a food reward, as well as between pressing the square button and receiving a food reward. That is, during the learning process, the mice only form an association between the button and the food reward but cannot distinguish the shape of the button. After completing the generalization process, the discrimination process is trained: initially, the round button appears and lights up, and the mouse receives a food reward after pressing it. Next, the square button appears and lights up, but even if the mouse presses this button, it does not receive food. This training process is repeated multiple times in an alternating manner. Ultimately, the mice reduced the likelihood of pressing the square button and successfully acquired the ability to distinguish the relationship between buttons of different shapes and food rewards. Figure 5 The diagram shows the changes in synaptic weights in the conditioned reflex circuit of the forgetting mechanism. g1 The memristor synapse representing the mouse's action of pressing a circular button, M g2 This represents the memristor synapse representing the mouse's behavior of pressing the square button. The generalization process is shown over a time interval of 0–240 seconds. This time interval corresponds to the circuit's random exploration phase, during which no conditional differentiation training is introduced; only the circular button stimulus is continuously presented. When the circular button is triggered, M… g1The memristor values ​​showed a gradual decreasing trend, indicating a positive enhancement of synaptic weights associated with the "pressing the round button" behavior. Simultaneously, because mice cannot yet distinguish button shapes, during training with the round button, even without the presentation of a square button stimulus, M... g2 The memristor resistance continued to decrease synchronously, confirming the generalization effect of the circuit, i.e., the conditioned reflex had been initially formed, but the mouse did not yet have the ability to distinguish the button shape. The differentiation and forgetting process was demonstrated during the 240s-450s time period. During this stage, the round button provided a reward signal when triggered, while the square button did not. The neuron containing the square button was in a strong forgetting state during this stage. g2 The memristor value of the mice gradually increased to over 1kΩ after training, indicating that the mice had lost the associative memory between "pressing the square button" and "receiving a reward"; in contrast, M g1 The memristor resistance remained below 1kΩ, indicating that the mice stably retained the association between "pressing the round button" and "receiving a reward," demonstrating the initial effectiveness of circuit differentiation. To verify the stability of circuit differentiation, all reward signals were stopped from 405 seconds onwards. The results showed that only the round button elicited high-frequency pressing behavior, while the square button only elicited pressing behavior at the frequency observed during the exploration phase. These results confirm that the proposed memristor neural network circuit can effectively distinguish between round and square buttons and autonomously select the correct button associated with the "reward."

[0031] Figure 6 The diagram shows the learning, forgetting, generalization, and differentiation results in the conditioned reflex circuit of the forgetting mechanism. cue1 V represents the trigger signal of the circular button. cue2 This indicates the square button's trigger signal. V review This is a reward signal. V action1 V corresponds to the mouse pressing the round button. action2 This represents the mouse's activity signal from pressing the square button. The time period from 0 to 240 seconds illustrates the generalization process. This period represents the random exploration and generalization formation phase of the circuit; no conditional differentiation training was introduced, and only the circular button stimulus was continuously presented, therefore V cue1 It is a continuous high level. In the initial stage before conditioned reflex is formed, V action1 The frequency of occurrence is V cue1 50%. After 13 cycles of random exploration, a conditioned reflex is formed, manifested as V. action1 The frequency of occurrence of V cue1 Fully synchronized. To verify the training effectiveness during the generalization phase, reward signals were stopped from 216s to 240s. During 216s to 240s, V cue2 (The square button signal) switches to a high level, and V is observed. action2This results in a corresponding high-level signal. This phenomenon indicates that the mouse has initially learned the conditioned reflex, and the generalization training effect has been achieved, meaning that the association between "button triggering" and "pressing behavior" has been established. To establish a clear association between "pressing different shaped buttons" and "receiving a reward signal," a differentiation training process was implemented to distinguish different conditions. The differentiation and forgetting process was demonstrated from 240s to 450s. Each training cycle lasted 48s, with four reward signals provided in each cycle. The training rule was: only on V... cue1 (Circular button signal) synchronously outputs V when triggered. review V cue2 (Square button signal) does not provide V when triggered. review Because the circuit employs two differentiated forgetting mechanisms: neuron 1 corresponding to the circular button exhibits weak forgetting characteristics, while neuron 2 corresponding to the square button exhibits strong forgetting characteristics, this leads to M... g1 and M g2 The changes in memristor resistance showed significant differences. After four cycles of differentiation training, to assess the final differentiation effect, all reward signals were stopped from 405 seconds onwards. Observations showed that only V cue1 (Circular button) can trigger high-frequency pressing behavior (corresponding to V) action1 (high frequency output), while V cue2 (Square button) trigger press frequency (corresponding to V) action2 The output frequency remained at the level of the random exploration phase. These results confirm that the mice can effectively distinguish between round and square buttons and autonomously select the correct button (i.e., the round button) that is associated with a reward. In summary, the memristor neural network circuit proposed in this invention successfully realizes the complete functional processes of learning, forgetting, generalization, and differentiation, and simulation results verify the effectiveness of the circuit design.

Claims

1. A conditioned reflex circuit based on a forgetting mechanism using a memristor neural network, characterized in that, The circuit consists of three signal conditioning modules, two feedback control modules, and two reflection generation modules. The three signal conditioning modules are respectively denoted as signal conditioning module SD-A1, signal conditioning module SD-R, and signal conditioning module SD-A2; signal conditioning module SD-A1 is powered by an external voltage source V. Pd1 -V Pd6 V Nd1 -V Nd6 V d1 -V d2 NMOS transistor N d1 -N d6 PMOS transistor P d1 -P d6 Analog behavioral device ABM d1 -ABM d2 memristor M d1 resistance R d1 and operational amplifier U d1 Composition; the signal conditioning module SD-R consists of an external voltage source V Pd7 -V Pd12 V Nd7 -V Nd12 V d3 -V d4 NMOS transistor N d7 -N d12 PMOS transistor P d7 -P d12 Analog behavioral device ABM d3 -ABM d4 memristor M d2 resistance R d2 and operational amplifier U d2 Composition; the signal conditioning module SD-A2 consists of an external voltage source V Pd13 -V Pd18 V Nd13 -V Nd18 V d5 -V d6 NMOS transistor N d13 -N d18 PMOS transistor P d13 -P d18 Analog behavioral device ABM d5 -ABM d6 memristor M d3 resistance R d3 and operational amplifier U d3 Composition; N d1 With P d1 The gate is connected to and connected to the output signal V of the reflection generation module 1. action1 External voltage source V Pd1 With P d1 The source is connected, V Nd1 With N d1 The source is connected; N d1 With P d1 The drain is connected to N d2 With P d2 The gates are connected together; external voltage source V Pd2 With P d2 The source is connected, V Nd2 With N d2 The source is connected; N d2 With P d2 The drains are connected together and with N d3 With P d3 The gate is connected; external voltage source V Pd3 With P d3 The source is connected, V Nd3 With N d3 The source is connected; N d3 With P d3 The drain is connected to the resistor R. d1 One end is connected; resistor R d1 The other end is connected to the operational amplifier U d1 The inverting input terminal is connected in parallel with the memristor M. d1 One end is connected together, U d1 The non-inverting input terminal is grounded; U d1 The output terminal and M d1 The other end is connected to N d4 With P d4 The gates are connected together; analog behavior device ABM d1 The output terminal and P d4 The source is connected to the analog behavioral device ABM. d2 The output terminal and N d4 The source is connected; ABM d1 The two input terminals IN1 and IN2 are respectively connected to V Pd4 With V d1 ABM d2 The two input terminals IN1 and IN2 are respectively connected to V Nd4 With V d2 N d4 With P d4 The drain is connected to N d5 With P d5 The gates are connected together; external voltage source V Pd5 With P d5 The source is connected, V Nd5 With N d5 The source is connected; N d5 With P d5 The drain is connected to N d6 With P d6 The gates are connected together; external voltage source V Pd6 With P d6 The source is connected, V Nd6 With N d6 The source is connected; N d6 With P d6 The drains are connected together and serve as the output signal V of the SD-A1 module. a1 V a1 Same as switch S S1 The control conduction positive terminal and switch S S2 The control conduction negative terminals are connected together; N d7 With P d7 The gates are connected together and connected to the reward signal V. reward External voltage source V Pd7 With P d7 The source is connected, V Nd7 With N d7 The source is connected; N d7 With P d7 The drain is connected to N d8 With P d8 The gates are connected together; external voltage source V Pd8 With P d8 The source is connected, V Nd8 With N d8 The source is connected; N d8 With P d8 The drain is connected to N d9 With P d9 The gates are connected together; external voltage source V Pd9 With P d9 The source is connected, V Nd9 With N d9 The source is connected; N d9 With P d9 The drain is connected to the resistor R. d2 One end is connected together; resistor R d2 The other end and U d2 The inverting input is connected together with M d2 One end is connected; U d2 The non-inverting input terminal is grounded; U d2 The output terminal and M d2 The other end is connected to N d10 With P d10 The gates are connected together; analog behavior device ABM d3 The output terminal and P d10 The source is connected to the analog behavioral device ABM. d4 The output terminal and N d10 The source is connected; ABM d3 The two input terminals IN1 and IN2 are connected to V Pd10 With V d3 ABM d4 The two input terminals IN1 and IN2 are connected to V Nd10 With V d4 N d10 With P d10 The drain is connected to N d11 With P d11 The gates are connected together; external voltage source V Pd11 With P d11 The source is connected, V Nd11 With N d11 The source is connected; N d11 With P d11 The drain is connected to N d12 With P d12 The gates are connected together; external voltage source V Pd12 With P d12 The source is connected, V Nd12 With N d12 The source is connected; N d12 With P d12 The drains are connected together and serve as the output signal V of the SD-R module. r V r Same as switch S S3 S S4 The control on-side negative terminal is connected to resistor R. s2 R s6 One end is connected together; N d13 With P d13 The gate is connected to and connected to the output signal V of the reflection generation module 2. action2 External voltage source V Pd13 With P d13 The source is connected, V Nd13 With N d13 The source is connected; N d13 With P d13 The drain is connected to N d14 With P d14 The gates are connected together; external voltage source V Pd14 With P d14 The source is connected, V Nd14 With N d14 The source is connected; N d14 With P d14 The drain is connected to N d15 With P d15 The gates are connected together; external voltage source V Pd15 With P d15 The source is connected, V Nd15 With N d15 The source is connected; N d15 With P d15 The drain is connected to the resistor R. d3 One end is connected; resistor R d3 The other end and U d3 The inverting input terminal is connected to M. d3 One end is connected together; U d3 The non-inverting input terminal is grounded; U d3 The output terminal and M d3 The other end is connected to N d16 With P d16 The gates are connected together; analog behavior device ABM d5 The output terminal and P d16 The source is connected to the analog behavioral device ABM. d6 The output terminal and N d16 The source is connected; ABM d5 The two input terminals IN1 and IN2 are connected to V Pd16 With V d5 ABM d6 The two input terminals IN1 and IN2 are connected to V Nd16 With V d6 N d16 With P d16 The drain is connected to N d17 With P d17 The gates are connected together; external voltage source V Pd17 With P d17 The source is connected, V Nd17 With N d17 The source is connected; N d17 With P d17 The drain is connected to N d18 With P d18 The gates are connected together; external voltage source V Pd18 With P d18 The source is connected, V Nd18 With N d18 The source is connected; N d18 With P d18 The drains are connected together and serve as the output signal V of the SD-A2 module. a2 V a2 Same as switch S S5 The control conduction positive terminal and switch S S6 The control conduction negative terminals are connected together.

2. The forgetting mechanism conditioned reflex circuit based on a memristor neural network according to claim 1, characterized in that, The circuit includes two feedback control modules 1 and 2; feedback control module 1 is powered by an external voltage source V. s1 -V s2 Switch S S1 -S S3 Operational amplifier U s1 -U s2 and resistance R s1 -R s5 Composition; Feedback control module 2 consists of an external voltage source V s5 -V s6 Switch S S4 -S S6 Operational amplifier U s3 -U s4 and resistance R s6 -R s10 Composition; Switch S S1 The control conduction negative terminal and S S2 The control conduction positive terminals are all connected to ground; external voltage source V s1 V s2 Respectively with switch S S1 S S2 The input terminal of the access circuit is connected; S S1 S S2 The output terminals of the access circuits are connected together and connected to S. S3 The input terminal of the access circuit; switch S S3 S S4 Control of the positive terminal and operational amplifier U s1 U s2 U s3 U s4 The non-inverting input terminals are all grounded; resistor R s1 One end is connected to switch S S3 The input circuit output terminal is connected, and the resistor R s1 The other end is connected to resistor R s2 The other end, R s3 One end and operational amplifier U s1 The inverting input terminals are connected together; resistor R s3 The other end is connected to resistor R s4 One end is connected to the operational amplifier U s1 The output terminals are connected together; resistor R s5 One end is connected to resistor R s4 The other end is connected to the operational amplifier U s2 The inverting input terminals are connected together; resistor R s5 The other end is the same as the operational amplifier U s2 The output terminal is connected and serves as the output signal V of the feedback control module 1. s1out V s1out With switch S in reflection generation module 1 g2 The input terminals of the access circuit are connected together; switch S S5 The control conduction negative terminal and S S6 The control conduction positive terminals are all connected to ground; external voltage source V s5 V s6 Respectively with switch S S5 S S6 The input terminal of the access circuit is connected; S S5 S S6 The output terminals of the access circuits are connected together and connected to S. S4 The input terminal of the access circuit; resistor R s7 One end is connected to switch S S4 The input circuit output terminal is connected, and the resistor R s7 The other end is connected to resistor R s6 The other end, R s8 One end is connected together with the operational amplifier U s3 The inverting input terminals are connected together; resistor R s8 The other end is connected to resistor R s9 One end is connected to the operational amplifier U s3 The output terminals are connected together; resistor R s10 One end is connected to resistor R s9 The other end is connected to the operational amplifier U s4 The inverting input terminals are connected together; resistor R s10 The other end is the same as the operational amplifier U s4 The output terminal is connected and used as the output signal V of the feedback control module 2. s2out V s2out With switch S in reflection generation module 2 g6 The input terminals of the access circuits are connected together.

3. The forgetting mechanism conditioned reflex circuit based on a memristor neural network according to claim 1, characterized in that, The circuit contains two reflection generation modules 1 and 2; reflection generation module 1 is powered by an external voltage source V. Pg1 -V Pg2 V Ng1 -V Ng2 V g1 NMOS transistor N g1 -N g2 PMOS transistor P g1 -P g2 Operational amplifier U g1 ABM, a single-input single-output analog behavioral device g1 Switch S g1 -S g5 Two-input OR gate OR1, memristor M g1 and resistance R g1 Composition; the reflection generation module 2 consists of an external voltage source V Pg3 -V Pg4 V Ng3 -V Ng4 V g7 NMOS transistor N g3 -N g4 PMOS transistor P g3 -P g4 Operational amplifier U g2 ABM, a single-input single-output analog behavioral device g2 Switch S g6 -S g10 Two-input OR gate OR2, memristor M g2 and resistance R g2 Composition; External voltage source V Pg1 With P g1 The source is connected, V Ng1 With N g1 The source is connected; N g1 With P g1 The gate is connected and a trigger signal V is applied. cue1 N g1 With P g1 The drain is connected to N g2 With P g2 The gates are connected together; external voltage source V Pg2 With P g2 The source is connected, V Ng2 With N g2 The source is connected; N g2 With P g2 The drain is connected to the switch S. g1 S g3 Control of the positive terminal of the conductor, switch S g2 S g4 The control conduction negative terminals are connected together; switch S g1 S g3 S g5 The control conduction negative terminals are all grounded, switch S g2 S g4 Control of the positive terminal and switch S g4 The output terminals of the access circuits are all grounded; V g1 Connect to switch S g1 The input terminal of the access circuit; switch S g1 S g2 The output terminal of the access circuit is connected to M g1 One end; M g1 The other end is connected to switch S g3 The input terminal of the access circuit and switch S g4 The input terminal of the access circuit; switch S g3 The output terminal of the access circuit is connected to the resistor R. g1 One end is connected to the operational amplifier U g1 The inverting input terminals are connected together; U g1 The non-inverting input is grounded; resistor R g1 The other end is the same as the operational amplifier U g1 The output terminal is connected to the analog behavior device ABM. g1 The input terminals are connected together; ABM g1 The output terminal of OR1 is connected to one input terminal of OR1; the other input terminal of OR1 is connected to switch S. g5 The input circuit output terminal is connected; switch S g5 The control conduction positive terminal is connected to the trigger signal V cue1 Switch S g5 The input terminal of the access circuit is connected to the active signal V. action-e1； The output signal of OR1 is the activity signal V of reflection generation module 1. action1 External voltage source V Pg3 With P g3 The source is connected, V Ng3 With N g3 The source is connected; N g3 With P g3 The gate is connected and a trigger signal V is applied. cue2 N g3 With P g3 The drain is connected to N g4 With P g4 The gates are connected together; external voltage source V Pg4 With P g4 The source is connected, V Ng4 With N g4 The source is connected; N g4 With P g4 The drain is connected to the switch S. g7 S g9 Control of the positive terminal of the conductor, switch S g6 S g8 The control conduction negative terminals are connected together; switch S g7 S g9 S g10 The control conduction negative terminals are all grounded, switch S g6 S g8 Control of the positive terminal and switch S g8 The output terminals of the access circuits are all grounded; V g7 Connect to switch S g7 The input terminal of the access circuit; switch S g6 S g7 The output terminal of the access circuit is connected to M g2 One end; M g2 The other end is connected to switch S g8 The input terminal of the access circuit and switch S g9 The input terminal of the access circuit; switch S g9 The output terminal of the access circuit is connected to the resistor R. g2 One end is connected to the operational amplifier U g2 The inverting input terminals are connected together; U g2 The non-inverting input is grounded; resistor R g2 The other end is the same as the operational amplifier U g2 The output terminal is connected to the analog behavior device ABM. g2 The input terminals are connected together; ABM g2 The output terminal of OR2 is connected to one input terminal of OR2; the other input terminal of OR2 is connected to switch S. g10 The input circuit output terminal is connected; switch S g10 The control conduction positive terminal is connected to the trigger signal V cue2 Switch S g10 The input terminal of the access circuit is connected to the active signal V. action-e2； The output signal of OR2 is the activity signal V of the reflection generation module 2. action2 .

4. The forgetting mechanism conditioned reflex circuit based on a memristor neural network according to claim 1, characterized in that, The signal conditioning module, as the signal preprocessing unit of the circuit, mainly adjusts the signal based on the active signal V. action1 and V action2 and reward signal V reward The circuit generates the output voltage based on the input voltage level. The feedback control module can match the corresponding enhancement voltage, weak inhibition voltage, and strong inhibition voltage according to the specific situation of the input voltage. These three voltages correspond to the learning process, natural extinction process, and instrumental extinction process in biological mechanisms, respectively. The reflection generation module realizes the control of the memristor resistance value through the "write-read" process. At the same time, this module can also read the state of the synaptic memristor and monitor the training effect in real time based on the resistance value of the memristor, forming a closed-loop function of "control-monitoring". The forgetting mechanism conditioned reflex circuit proposed in this invention can realize the functions of learning, forgetting, generalization, and differentiation at the hardware level.

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