Decoder, decoder control method, storage medium and program product

Abstract

This application discloses a decoder, a decoder control method, a storage medium, and a program product, relating to the field of data decoding technology. The decoder includes: a signal input module for receiving a signal to be decoded; a signal output module including at least two signal output ports for outputting decoded signals; a signal decoding module including at least two decoding chips, each decoder chip being connected to the signal input module and each signal output port respectively, for decoding the signal to be decoded through a target decoding chip and transmitting the decoded signal to the corresponding signal output port; and a decoding control module connected to each decoding chip, for generating decoding control instructions according to a mode selection instruction and sending the decoding control instructions to the signal decoding module to determine the target decoding chip. This application achieves the effect of flexibly selecting different decoding chips for signal processing on the same decoder and supporting multi-channel parallel output.

Description

Technical Field

[0001] This application relates to the field of data decoding technology, and in particular to a decoder, decoder control method, storage medium and program product. Background Technology

[0002] In the field of audio equipment, a decoder is a key device that converts digital audio signals into analog audio signals, and its performance directly affects the final sound reproduction effect and listening experience. Currently, common decoders on the market typically use a single model or brand of decoding chip for signal processing, and their output interface generally only has one analog audio output.

[0003] This traditional structure reveals significant limitations in practical use. On the one hand, because it only has one built-in decoding chip, users cannot compare the sound characteristics and performance differences of different brands or models of decoding chips on the same device, making it difficult to make flexible choices based on personal preferences or the characteristics of different audio sources. On the other hand, the single audio output design means that when users need to connect multiple power amplifiers (such as power amplifiers, headphone amplifiers, active speakers, etc.) simultaneously, they must purchase multiple decoders or frequently switch cables. This not only increases the cost of decoding but also complicates the system connection and affects ease of use. Summary of the Invention

[0004] The main purpose of this application is to propose a decoder, a decoder control method, a storage medium, and a program product, aiming to solve the technical problem that the decoding function of current decoders is relatively limited.

[0005] To achieve the above objectives, this application proposes a decoder, the decoder comprising:

[0006] A signal input module, wherein the signal input module is used to receive the signal to be decoded;

[0007] A signal output module, comprising at least two signal output ports, wherein the signal output module is used to output a decoded signal corresponding to the signal to be decoded;

[0008] A signal decoding module includes at least two decoding chips, each of which is connected to the signal input module and each of the signal output ports. The signal decoding module is used to decode the signal to be decoded by the target decoding chip in each of the decoding chips to obtain the decoded signal, and to transmit the decoded signal to the corresponding signal output port.

[0009] A decoding control module is connected to each of the decoding chips and is used to generate decoding control instructions according to the received mode selection instructions, and send the decoding control instructions to the signal decoding module, wherein the decoding control instructions are used to determine the target decoding chip.

[0010] In one embodiment, the decoding control module is connected to each of the decoding chips via an I2C bus, and the decoding control command is transmitted to the signal decoding module via the I2C bus.

[0011] In one embodiment, the decoding control module is also connected to the address pins of each of the decoding chips. The decoding control module is also used to receive the level signal of the address pin, identify the chip model of each of the decoding chips according to the level signal, and load the corresponding decoding chip driver according to the chip model to drive and control the corresponding decoding chip to perform decoding and output.

[0012] In one embodiment, the decoding control module is further configured to generate an output control instruction according to the mode selection instruction, and send the output control instruction to the output switching module, wherein the output switching instruction is used to determine the target output port among the signal output ports;

[0013] The decoder also includes:

[0014] An output switching module is connected to each of the decoding chips, each of the signal output ports, and the decoding control module, respectively, and is used to receive the output control command and the decoding signal, and output the decoding signal to the target output port.

[0015] In one embodiment, the output switching module includes:

[0016] A signal amplification unit, connected to the decoding control module, is used to receive the output control command and output the amplified output control command.

[0017] A switch control unit is connected to each of the decoding chips, each of the signal output ports, and the signal amplification unit, respectively, and is used to control the connection status of the signal path between each of the decoding chips and each of the signal output ports according to the amplified output control command.

[0018] In one embodiment, the output control command includes a first independent output command, a second independent output command, and a synchronous output command, and the signal amplification unit includes:

[0019] The first switch transistor has its first terminal grounded, its second terminal connected to the decoding control module, and its third terminal connected to the switch control unit. It is used to receive the first independent output command and output the amplified first independent output command.

[0020] The second switch has its first terminal grounded, its second terminal connected to the decoding control module, and its third terminal connected to the switch control unit. It is used to receive the second independent output command and output the amplified second independent output command.

[0021] The third switch has its first terminal grounded, its second terminal connected to the decoding control module, and its third terminal connected to the switch control unit. It is used to receive the synchronization output command and output the amplified synchronization output command.

[0022] In one embodiment, the signal decoding module includes a first decoding chip and a second decoding chip, the signal output module includes a first signal output port and a second signal output port, and the switch control unit includes:

[0023] The first relay has its control terminal connected to the third pole of the first switching transistor, its common terminal connected to the first decoding chip, and its normally open terminal connected to the first signal output port.

[0024] The second relay has its control terminal connected to the third pole of the second switching transistor, its common terminal connected to the second decoding chip, and its normally open terminal connected to the second signal output port.

[0025] The third relay has its control terminal connected to the third pole of the third switching transistor, its common terminal connected to the normally open terminal of the first relay, and its normally open terminal connected to the second signal output port.

[0026] This application also proposes a decoder control method, which is applied to the decoder described above, and the decoder control method includes:

[0027] The decoding control module receives mode selection instructions and generates decoding control instructions based on the mode selection instructions. The decoding control instructions are used to determine the target decoding chip among the decoding chips in the signal decoding module.

[0028] The decoding control module transmits the decoding control command to the signal decoding module, so that the signal decoding module determines the target decoding chip among the decoding chips according to the decoding control command, and decodes the signal to be decoded transmitted by the signal input module through the target decoding chip to obtain the decoded signal, and transmits the decoded signal to the corresponding signal output port in the signal output module for output.

[0029] This application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and which, when executed by a processor, implements the steps of the decoder control method described above.

[0030] This application also proposes a computer program product comprising a computer program that, when executed by a processor, implements the steps of the decoder control method described above.

[0031] This application achieves the effect of flexibly selecting different decoding chips for signal processing and supporting multi-channel parallel output by setting a signal input module to receive the signal to be decoded, a signal decoding module integrating at least two decoding chips and respectively connecting the signal input module and a signal output module including at least two signal output ports, and a decoding control module generating decoding control instructions according to mode selection instructions to determine the target decoding chip and control the signal decoding module to perform decoding output.

[0032] Specifically, because the signal decoding module contains multiple decoding chips, users can switch between one or more different brands or models of decoding chips as the target decoding chip via selection commands from the decoding control module. This allows for direct comparison of the sound quality and performance differences of different decoding chips on the same device, solving the problem that traditional single-chip decoders cannot provide comparison functionality. Simultaneously, the signal output module has at least two signal output ports, enabling the decoded signal to be output to multiple downstream devices simultaneously. Users no longer need to set up multiple decoders or frequently switch wiring, reducing system cost and space requirements, simplifying device connection complexity, and improving ease of use. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0034] Figure 1A schematic diagram of the structure of an embodiment of the decoder provided in this application;

[0035] Figure 2 A schematic diagram of another embodiment of the decoder provided in this application;

[0036] Figure 3 A schematic diagram of the structure of yet another embodiment of the decoder provided in this application;

[0037] Figure 4 A circuit diagram of an embodiment of the output switching module in the decoder provided in this application;

[0038] Figure 5 This is a flowchart illustrating the decoder control method of this application.

[0039] Explanation of icon numbers:

[0040]

[0041] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0044] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0045] Currently, most decoders on the market use a single model or brand of decoding chip for signal processing, and their output interface typically only has one analog audio output. This traditional structure reveals significant limitations in practical use. On the one hand, because only one decoding chip is built in, users cannot compare the sound characteristics and performance differences of different brands or models of decoding chips on the same device, making it difficult to flexibly choose according to personal preference or the characteristics of different audio sources. On the other hand, the single audio output design means that when users need to connect multiple power amplifiers (such as power amplifiers, headphone amplifiers, active speakers, etc.) simultaneously, they must purchase multiple decoders or frequently switch cables. This not only increases the cost of decoding but also complicates the system connection and affects ease of use.

[0046] Based on this, this application proposes a decoder, the decoder comprising: a signal input module for receiving a signal to be decoded; a signal output module including at least two signal output ports for outputting a decoded signal corresponding to the signal to be decoded; a signal decoding module including at least two decoding chips, each decoding chip being connected to the signal input module and each of the signal output ports respectively, the signal decoding module being used to decode the signal to be decoded by a target decoding chip in each of the decoding chips to obtain the decoded signal, and transmitting the decoded signal to the corresponding signal output port; and a decoding control module connected to each of the decoding chips, for generating a decoding control instruction according to a received mode selection instruction, and sending the decoding control instruction to the signal decoding module, wherein the decoding control instruction is used to determine the target decoding chip.

[0047] Because the signal decoding module contains multiple decoding chips, users can switch between one or more different brands or models of decoding chips as the target decoding chip via selection commands on the decoding control module. This allows for direct comparison of the sound quality and performance differences of different decoding chips on the same device, solving the problem that traditional single-chip decoders cannot provide comparison functionality. Simultaneously, the signal output module has at least two signal output ports, enabling the decoded signal to be output to multiple downstream devices simultaneously. Users no longer need to set up multiple decoders or frequently switch wiring, reducing system cost and space requirements, simplifying device connection complexity, and improving ease of use.

[0048] This application proposes a decoder.

[0049] Please see Figure 1 In one embodiment of this application, the decoder includes:

[0050] Signal input module 10, the signal input module 10 is used to receive the signal to be decoded;

[0051] The signal output module 20 includes at least two signal output ports and is used to output the decoded signal corresponding to the signal to be decoded.

[0052] The signal decoding module 30 includes at least two decoding chips. Each decoding chip is connected to the signal input module 10 and each signal output port. The signal decoding module 30 is used to decode the signal to be decoded by the target decoding chip in each decoding chip to obtain the decoded signal, and transmit the decoded signal to the corresponding signal output port.

[0053] A decoding control module 40 is connected to each of the decoding chips and is used to generate decoding control instructions according to the received mode selection instructions, and send the decoding control instructions to the signal decoding module 30. The decoding control instructions are used to determine the target decoding chip.

[0054] It should be noted that the signal input module 10 is a component of the decoder, specifically responsible for receiving the signal to be decoded from an external signal source. This module typically includes various digital audio input interfaces, such as S / PDIF coaxial, optical TOSLINK, USB, or HDMI, for receiving digital audio data streams of different formats. As the entry point for the signal into the decoder, the signal input module 10 performs preliminary processing on the incoming signal to be decoded, such as signal buffering, format recognition, or clock synchronization, to ensure that the signal is transmitted completely and stably to subsequent processing modules. In this embodiment, the signal input module 10 is directly connected to the signal decoding module 30, simultaneously or distributing the signal to be decoded to each decoding chip, providing the signal input foundation for multi-chip decoding. The signal to be decoded refers to the original digital audio signal input to the decoder that needs to be decoded and processed. These signals are usually in digital encoding formats, such as PCM (Pulse Code Modulation) data streams, DSD (Direct Stream Digital) signals, or other compressed audio streams. They carry audio information but have not yet been converted into an analog form that can drive speakers or headphones. Their source can be a CD (Compact Disc) player, digital music player, computer, or streaming media device, etc.

[0055] The signal output module 20 is the output section of the decoder, and it includes at least two independent signal output ports for outputting the decoded analog audio signal. These output ports can be analog interface types, such as RCA single-ended output, XLR balanced output, or 6.35mm headphone output. Each port can be connected to a power amplifier, active speaker, or headphone amplifier. The function of this module is to output the decoded signal generated by the signal decoding module 30 through the designated port, supporting multi-channel parallel transmission. In this embodiment, the signal output module 20 allows users to connect multiple sets of power amplifiers simultaneously, avoiding the hassle of frequently switching cables required by traditional single-output decoders, and improving system scalability and ease of use. The decoded signal refers to the analog audio signal obtained after processing by the decoding chip. It is the output result of the target decoding chip after decoding the input signal to be decoded (including but not limited to digital-to-analog conversion and signal reconstruction), and is usually a continuous-time voltage signal that can directly drive audio devices. The quality of this signal depends on the performance of the decoding chip, such as signal-to-noise ratio, dynamic range, and distortion. Different decoding chips may present different tonal styles. The decoded signal is output through the port of the signal output module 20 to provide the user with the final audible audio.

[0056] The signal decoding module 30 is the core processing part of the decoder, comprising at least two independent decoding chips, each of which can be a DAC (Digital to Analog Converter) of a different brand or model. These decoding chips are connected to the signal input module 10 and each signal output port, enabling each chip to receive the signal to be decoded and output a decoded signal. The function of this module is to select one of the chips as the target decoding chip through internal circuitry or logic to perform the decoding operation, thereby achieving signal conversion. The signal decoding module 30 supports the coexistence of multiple chips, allowing users to dynamically switch chips as needed, thus experiencing different decoding characteristics on the same device, enhancing flexibility and comparability.

[0057] The decoding control module 40 is the control component of the decoder, connected to each decoding chip, and responsible for coordinating the decoder's operating mode. This module receives mode selection commands from external sources, generates corresponding decoding control commands based on these commands, and sends them to the signal decoding module 30 to determine which decoding chip to activate as the target decoding chip. The decoding control module 40 can be implemented using a microcontroller, integrating control algorithms and drivers to ensure accurate command execution.

[0058] The mode selection command is a configuration command sent by the user or external device to the decoding control module 40 to specify the desired decoder operating mode. This command can be input through a physical interface (such as a remote control or front panel button) or a software interface (such as a mobile application or computer software), and transmitted in the form of digital signals or protocol data, instructing the decoder to select a specific decoding chip or output path.

[0059] The decoding control command is an internal command generated by the decoding control module 40 and sent specifically to the signal decoding module 30 to explicitly specify which decoding chip is the target decoding chip. This command may contain chip address, enable signal, or configuration parameters, and is transmitted via electrical signals or bus protocols (such as I2C) to directly control the chip selection logic of the signal decoding module 30.

[0060] Understandably, traditional decoders, with their single decoding chip and single output port design, prevent users from comparing the performance differences of different decoding chips on the same device. Furthermore, connecting multiple downstream devices requires repeated purchases or frequent wiring changes, resulting in high costs, complex operation, and space consumption. Therefore, to address both issues simultaneously, this embodiment employs a technical solution where a signal input module 10 receives the signal to be decoded, a signal decoding module 30 integrates at least two decoding chips connected to the signal input module 10 and a signal output module 20 with at least two signal output ports, and a decoding control module 40 generates decoding control commands based on mode selection instructions to determine the target decoding chip and control the signal decoding module 30 to perform decoding output. This avoids the problems of traditional designs where a single chip prevents comparison and a single output port prevents parallel connection of multiple devices. It achieves the dual technical effects of flexibly switching between different decoding chips on the same device for real-time comparison of sound quality styles and simultaneously driving multiple downstream devices through multi-channel output. This significantly improves usability, reduces user equipment investment costs and system connection complexity, and saves installation space.

[0061] For example, the signal input module 10 can be implemented as a circuit board integrating multiple digital audio interfaces such as coaxial and USB Type-B, used to receive the signal to be decoded from external audio sources such as CD players or computers, i.e., PCM format digital audio streams without digital-to-analog conversion. The signal decoding module 30 contains two physically independent decoding chips, such as an ESS decoding chip and an AKM decoding chip. The input terminals of these two decoding chips are connected to the output terminals of the signal input module 10 in parallel to receive the same signal to be decoded simultaneously. The signal output module 20 specifically provides two analog audio output ports, namely a set of RCA single-ended outputs and a set of XLR balanced outputs, whose input terminals are connected to the signal decoding module 30 through internal wiring. The decoding control module 40 is implemented by a built-in STM32 series microcontroller, whose general-purpose input / output pins are connected to the enable control pins of the two decoding chips through wires. When the user issues a mode selection command representing "selecting the first chip" through an external infrared remote control, the infrared receiver transmits the command to the microcontroller of the decoding control module 40. The microcontroller then parses the instruction and generates a specific high-level decoding control instruction signal, which is sent to the enable pin of the ESS decoding chip via a wire, while simultaneously sending a low-level signal to the enable pin of the AKM decoding chip. This identifies the ESS decoding chip as the target decoding chip, thereby activating its internal circuitry to perform digital-to-analog conversion on the signal to be decoded from the signal input module 10, generating an analog decoding signal, which is then simultaneously output to the first signal output port 21 and the second signal output port 22 connected to it. At this time, the user can use the two outputs to simultaneously connect two different power amplifier devices, thereby comparing the sound quality of the power amplifier devices with the same decoding chip. By sending different mode selection commands via remote control, the user can switch the target decoding chip to both the ESS and AKM decoding chips, thereby instantly experiencing and comparing the sound quality differences presented by the two different decoding chips when processing the same sound source on two identical power amplifier devices, in order to compare the compatibility of the two decoding chips with the power amplifier devices.

[0062] In the specific implementation process, the decoding control module 40 is connected to each of the decoding chips via an I2C bus, and the decoding control command is transmitted to the signal decoding module 30 via the I2C bus.

[0063] Understandably, if non-standard or parallel direct connection methods are used, it may result in a large number of control lines, complex wiring, and susceptibility to signal interference. Furthermore, it may lead to insufficient scalability when multiple chips are coordinated or upgraded. Therefore, a technical solution can be adopted where the decoding control module 40 is connected to each decoding chip via an I2C bus, and the decoding control commands are transmitted to the signal decoding module 30 via the I2C bus. This avoids the problems of crowded circuit layout, decreased signal integrity, increased power consumption, and difficulty in supporting multi-device addressing and expansion caused by traditional point-to-point connection or parallel bus methods. It achieves unified and reliable transmission of control commands with a single two-wire serial bus, thereby improving the integration and anti-interference capability of multi-decoding chip management, reducing hardware design and production costs, and laying a communication foundation for achieving more complex chip configurations and future functional upgrades.

[0064] This application employs a technical solution that includes a signal input module 10 receiving the signal to be decoded, a signal decoding module 30 integrating at least two decoding chips connected to the signal input module 10 and a signal output module 20 with at least two signal output ports, and a decoding control module 40 generating decoding control commands based on mode selection instructions to determine the target decoding chip and control the signal decoding module 30 to perform decoding output. This achieves the effect of flexibly selecting different decoding chips for signal processing and supporting multi-channel parallel output on the same decoder. Specifically, since the signal decoding module 30 contains multiple decoding chips, users can switch between using one or more different brands or models of decoding chips as the target decoding chip through the selection commands of the decoding control module 40. This allows for direct comparison of the sound quality and performance differences of different decoding chips on the same device, solving the problem that traditional single-chip decoders cannot provide comparison functionality. Simultaneously, the signal output module 20 has at least two signal output ports, enabling the decoded signal to be output to multiple downstream devices simultaneously. Users do not need to set up multiple decoders or frequently switch wiring, reducing system cost and space occupation, simplifying device connection complexity, and improving ease of use.

[0065] In one feasible implementation, the decoding control module 40 is also connected to the address pins of each of the decoding chips. The decoding control module 40 is also used to receive the level signal of the address pin, identify the chip model of each of the decoding chips according to the level signal, and load the corresponding decoding chip driver based on the chip model to drive and control the corresponding decoding chip to perform decoding and output.

[0066] Understandably, simply establishing a communication connection is insufficient for automatically identifying different models or batches of pluggable decoding chips. If the system cannot automatically identify the inserted chip model, manual configuration or pre-storing of a single driver is required. This necessitates tedious manual settings and is prone to errors when upgrading or replacing chips, severely limiting the usability and user experience of the decoder. Therefore, this embodiment further employs a decoding control module 40 that connects to the address pins of each decoding chip and receives the level signals from the address pins to identify the chip model. Based on the identified chip model, the corresponding driver is automatically loaded to drive and control the decoding chip. This avoids the operational complexity, configuration errors, and poor compatibility issues caused by manual identification, jumper settings, or fixed drivers required when supporting multiple chips or chip upgrades. It achieves automatic detection and plug-and-play functionality of the decoder for the inserted decoding chip model, eliminating the need for any manual software configuration during chip replacement and significantly improving the convenience and reliability of product upgrades.

[0067] For example, the decoding control module 40 is implemented by an STM32F series microcontroller. In addition to being connected to the I2C communication pins of the first decoding chip 31 and the second decoding chip 32 in the slot via the I2C bus, the microcontroller's two general-purpose input / output ports (GPIO1 and GPIO2) are also specially configured as address signal reading ports and are connected to the dedicated address pins of the two decoding chip modules respectively via circuit board traces. Each decoding chip is designed as a pluggable daughterboard module. Its address pins are configured with a specific high / low level combination via internally connected pull-up or pull-down resistors, forming a hardware code representing the chip model. For example, the first decoding chip 31 sets the level signals of its three address pins to (0,0,1) via internal pull-down resistors, while the second decoding chip 32 sets the level signals of its three address pins to (1,1,0) via internal pull-up resistors. When a user inserts any decoding chip module into a standard slot on the motherboard, the microcontroller of the decoding control module 40 reads the level signal combination from the chip's address pins through its GPIO1 and GPIO2 ports during the power-on initialization phase. After obtaining the level signal, the microcontroller compares it with an internally preset model lookup table to uniquely identify the chip model of the currently inserted decoding chip. For example, it identifies the level combination (0,0,1) as corresponding to the first decoding chip 31. Subsequently, based on the identified chip model, the decoding control module 40 automatically loads a driver program that perfectly matches the chip model from its internal memory, such as Flash. This driver program includes a specific register configuration sequence for initializing the chip, filter setting parameters, and clock management routines. After loading, the decoding control module 40 runs this driver program via the I2C bus, thereby correctly driving and controlling the identified decoding chip to perform normal decoding and signal output operations. This achieves automatic identification and plug-and-play driving of pluggable decoding chips without requiring any software settings or jumper operations.

[0068] In one feasible implementation, the decoding control module 40 is further configured to generate an output control instruction according to the mode selection instruction, and send the output control instruction to the output switching module 50, wherein the output switching instruction is used to determine the target output port among the signal output ports;

[0069] Please refer to Figure 2 The decoder also includes:

[0070] The output switching module 50 is connected to each of the decoding chips, each of the signal output ports and the decoding control module 40, respectively, and is used to receive the output control command and the decoding signal, and output the decoding signal to the target output port.

[0071] It should be noted that the output control command is an additional control command generated by the decoding control module 40 after receiving the mode selection command, in addition to the decoding control command. This command is specifically used to control and configure the signal sources and connection status of multiple signal output ports in the signal output module 20, determining which one or more signal output ports are activated and which decoding chip they should receive decoding signals from. For example, the command could indicate "only the first signal output port 21 outputs a signal from the first decoding chip 31", or "both the first and second signal output ports 22 output signals from the same decoding chip". In practical implementation, this output control command can also be transmitted to the signal decoding module 30 via the I2C bus.

[0072] The output switching module 50 is a circuit located within the decoder, between the signal decoding module 30 and the signal output module 20. This module connects to the output terminals of each decoding chip, each signal output port, and the decoding control module 40. It receives output control commands from the decoding control module 40 and, according to these commands, switches internal signal paths physically or electronically, thereby routing the decoded signal generated by a specified decoding chip to one or more specified signal output ports. For example, different connection combinations can be switched using an internal set of relays or multiplexed analog switches. The introduction of this module allows for flexible reconfiguration of the functions of multiple fixed physical output ports and is a key actuator for achieving "one machine, multiple modes" output, enabling functions such as comparing different chips and driving multiple sets of downstream devices.

[0073] Understandably, although the above technical solutions achieve chip selection and multiple physical outputs, the connection relationship between each signal output port and each decoding chip may be fixed or pre-set in hardware. This makes it difficult for users to flexibly and dynamically route the signal of any decoding chip to any output port without changing the physical wiring, thus limiting the rapid switching and convenient use of a single decoder in various application scenarios. To address the lack of dynamic configuration, an output switching module 50 is added. The decoding control module 40 generates a dedicated output control command based on the mode selection instruction and sends it to this module. The output switching module 50 then uses this command to determine and connect the signal path between a specific decoding chip and a specific signal output port in real time. This avoids the cumbersome operation of manually changing physical connections to switch between different listening modes due to fixed output paths, as well as the associated risks of interface wear and signal interference. It enables users to define and instantly switch between multiple output connection modes via software commands. For example, two ports can output signals from two chips for comparison, or both ports can output signals from the same chip to drive two sets of downstream devices. This greatly enhances the functional flexibility, ease of use, and adaptability of a single decoder.

[0074] In one feasible implementation, please refer to Figure 3 The output switching module 50 includes:

[0075] The signal amplification unit 51 is connected to the decoding control module 40 and is used to receive the output control command and output the amplified output control command.

[0076] A switch control unit 52 is connected to each of the decoding chips, each of the signal output ports, and the signal amplification unit 51, respectively, and is used to control the connection state of the signal path between each of the decoding chips and each of the signal output ports according to the amplified output control command.

[0077] It is understandable that since the output control commands directly output by the decoding control module 40 are usually low-power logic level signals with limited driving capability, directly using them to control switching elements may lead to slow switching action, unreliable contact, or even failure to drive, thereby causing technical risks such as signal path switching failure, audio interruption, or the introduction of noise. Therefore, this embodiment further constructs the output switching module 50 as including a signal amplification unit 51 and a switch control unit 52. Specifically, the signal amplification unit 51 receives and amplifies the output control commands to improve its driving capability, while the switch control unit 52 precisely controls the physical connection and disconnection of the signal paths between each decoding chip and each signal output port based on the amplified commands. This solution avoids problems such as insensitive switching, poor reliability, and potential signal degradation caused by insufficient control signal power, achieving fast, stable, and error-free electronic switching of the audio signal path, thereby ensuring the response speed, operational reliability, and audio transmission quality of the decoder when switching between various output modes.

[0078] In specific implementation, the output control commands include a first independent output command, a second independent output command, and a synchronous output command, and the signal amplification unit 51 includes:

[0079] The first switch transistor has its first terminal grounded, its second terminal connected to the decoding control module 40, and its third terminal connected to the switch control unit 52. It is used to receive the first independent output command and output the amplified first independent output command.

[0080] The second switch has its first terminal grounded, its second terminal connected to the decoding control module 40, and its third terminal connected to the switch control unit 52. It is used to receive the second independent output command and output the amplified second independent output command.

[0081] The third switch has its first terminal grounded, its second terminal connected to the decoding control module 40, and its third terminal connected to the switch control unit 52. It is used to receive the synchronization output command and output the amplified synchronization output command.

[0082] It should be noted that the first independent output command is a specific type of output control command generated by the decoding control module 40. Its function is to control the output switching module 50 to establish a signal path state, so that the decoding signal output by the first decoding chip 31 is routed separately to the first signal output port 21, while ensuring the independent connection between the second decoding chip 32 and the second signal output port 22. This enables the two decoding chips to drive an independent downstream device, making it convenient for users to directly compare the sound quality performance of the two different decoding chips on their respective independent back-end devices.

[0083] The second independent output instruction is another specific type of output control instruction generated by the decoding control module 40. Its function is similar to that of the first independent output instruction, but its target is different. It controls the output switching module 50 to establish another signal path state, so that the decoding signal output by the second decoding chip 32 is routed separately to the second signal output port 22, while ensuring that the first decoding chip 31 and the first signal output port 21 remain independently connected. This is also to realize the dual decoding chip independent output mode and provide users with another port allocation option for flexibility.

[0084] The synchronous output instruction is the third specific type of output control instruction generated by the decoding control module 40. Its function is to control the output switching module 50 to establish a special signal path state, so that the decoding signal output by the first decoding chip 31 (or the second decoding chip 32, depending on the specific design) is simultaneously routed to the first signal output port 21 and the second signal output port 22. This enables the signal from the same decoding chip to synchronously drive two different sets of power stage devices, making it convenient for users to compare and evaluate the performance differences of different power stage devices (such as power amplifiers and speakers) under the same audio source and front-end decoding conditions.

[0085] Additionally, it should be noted that the first, second, and third switching transistors can be transistors (such as NPN transistors) or MOSFETs (such as NMOS transistors), etc. This embodiment does not limit the specific type of switching transistors.

[0086] Understandably, basic amplification and switching capabilities alone are insufficient to accurately correspond to and implement the specific, discrete output modes required by the decoder in actual use, such as the independent comparison mode of "chip A outputs to port 1, chip B outputs to port 2" or the synchronous drive mode of "chip A outputs to both port 1 and port 2". If the control commands are not clearly logically classified and physically isolated, it is easy to cause confusion in the control logic, unclear switching states, and an inability to reliably reproduce the specific signal connection scenario expected by the user. To address the issues of mode definition and precise execution, a technical solution is adopted that specifically limits output control commands to at least three types: a first independent output command, a second independent output command, and a synchronous output command. Correspondingly, a signal amplification unit 51 composed of three independent switching transistors is set up, so that each command is amplified through a dedicated switching transistor path. This avoids ambiguity, cross-interference, and mode switching errors that may occur when interpreting and executing general control signals. It achieves clear definition, electrical isolation, and one-to-one reliable drive for application modes such as "dual-chip independent output" and "single-chip synchronous dual-channel output". This ensures that the output switching module 50 can accurately establish the expected signal path every time the user selects a functional mode, greatly improving the intuitiveness of operation, functional certainty, and system reliability.

[0087] The signal decoding module 30 includes a first decoding chip 31 and a second decoding chip 32; the signal output module 20 includes a first signal output port 21 and a second signal output port 22; and the switch control unit 52 includes:

[0088] The first relay has its control terminal connected to the third pole of the first switching transistor, its common terminal connected to the first decoding chip 31, and its normally open terminal connected to the first signal output port 21.

[0089] The second relay has its control terminal connected to the third pole of the second switching transistor, its common terminal connected to the second decoding chip 32, and its normally open terminal connected to the second signal output port 22.

[0090] The third relay has its control terminal connected to the third pole of the third switching transistor, its common terminal connected to the normally open terminal of the first relay, and its normally open terminal connected to the second signal output port 22.

[0091] It is understandable that since the amplified control commands still need to rely on specific and reliable actuators to physically realize the switching of audio signals between complex paths, if only general-purpose or multi-channel analog switches and other components are used, contact resistance, crosstalk or distortion may be introduced when switching high-fidelity audio signals, and it is difficult to simultaneously meet the requirements of synchronous switching of multiple signals, electrical isolation and long-term stability. To address the issue of lossless and reliable routing of high-quality audio signals, a technical solution is adopted that specifically constructs the switch control unit 52 as a combination of three relays. Specifically, the first relay is connected to the first switching transistor, the first decoding chip 31, and the first signal output port 21; the second relay is connected to the second switching transistor, the second decoding chip 32, and the second signal output port 22; and the third relay is linked to the third switching transistor and bridging the first signal output port 21 and the second signal output port 22. This avoids problems such as signal degradation, insufficient isolation between channels, and transient noise that may arise from using electronic switches. It achieves a clear and isolated signal path by physically switching mechanical relay contacts, thus ensuring that audio signals can be routed with extremely low loss and interference in various decoding modes. Ultimately, this guarantees the high fidelity of the overall decoder output sound quality and the reliability of mode switching.

[0092] Please refer to Figure 4In one specific example, since the decoding signal output by the decoding chip is divided into two signals, the left channel decoding signal and the right channel decoding signal, the output of each decoding chip will be configured with two relays. That is, the first relay may include LS1 and LS2, where LS1 corresponds to the right channel decoding signal and LS2 corresponds to the left channel decoding signal. Similarly, the second relay may include LS3 and LS4, and the third relay may include LS5 and LS6. The decoding control module 40 generates corresponding output control commands based on the mode selection command sent by the user's remote control. If the user selects the "independent output" mode, the decoding control module 40 outputs the first independent output command ES_SW (a high-level logic signal) to the base of the first switching transistor Q1 (such as an NPN transistor) in the signal amplification unit 51 via the first resistor R1. This drives the coils of the first relays LS1 and LS2 to be energized and engaged, connecting the common terminal of the first relays LS1 and LS2 to their normally open terminals. This routes the decoding signal output by the first decoding chip 31 to the first signal output port 21. Simultaneously, it outputs the second independent output command AK_SW to the base of the second switching transistor Q2 via the second resistor R2. Similarly, this routes the decoding signal output by the second decoding chip 32 to the second signal output port 22. The synchronous output command OP_SW, output via the third resistor R3, is an invalid low-level logic signal, causing the third relays LS5 and LS6 to disconnect, thus enabling independent output from both chips. If the user selects the "synchronous output of the first decoding chip 31" mode, the decoding control module 40 simultaneously outputs the first independent output command and the synchronous output command. The first switch Q1 drives the first relays LS1 and LS2 to engage, while the third switch Q3 drives the third relays LS5 and LS6 to engage. The third relays LS5 and LS6 connect their common terminal (connected to the normally open terminal of the engaged first relays LS1 and LS2) to their normally open terminal, thereby connecting the decoding signal output by the first decoding chip 31 to both the first signal output port 21 and the second signal output port 22, achieving single-chip synchronous drive of dual-channel downstream devices.

[0093] Furthermore, it should be noted that this embodiment provides a specific implementation example based on two decoding chips (i.e., the first decoding chip 31 and the second decoding chip 32) and two signal output ports (i.e., the first signal output port 21 and the second signal output port 22), wherein a limited number of output mode switching is achieved through three specific output control instructions and corresponding combinations of switching transistors and relays. However, this is only one specific implementation method under the most simplified configuration of this application. In actual implementation, the concept of this technical solution, namely, generating classification instructions through the decoding control module 40, driving them through the signal amplification unit 51, and executing signal path switching by the switch control unit 52, can be fully extended to more decoding chips and more signal output ports. For example, using three or more decoding chips and three or more output ports, by increasing the corresponding number of instruction types, switching transistors and relays or other switching elements, a more complex signal routing matrix can be constructed, thereby realizing more diverse chip comparison and output configuration combinations. This does not deviate from the basic principle and protection scope of this application to achieve flexible routing of multiple chips and multiple outputs.

[0094] This application also proposes a decoder control method, which is applied to the decoder described in the above embodiments, and the decoder control method includes steps S10-S20:

[0095] Step S10: Receive mode selection instruction through the decoding control module, and generate decoding control instruction according to the mode selection instruction, wherein the decoding control instruction is used to determine the target decoding chip among the decoding chips in the signal decoding module;

[0096] Step S20: The decoding control module transmits the decoding control command to the signal decoding module, so that the signal decoding module determines the target decoding chip in each decoding chip according to the decoding control command, and decodes the signal to be decoded transmitted by the signal input module through the target decoding chip to obtain the decoded signal, and transmits the decoded signal to the corresponding signal output port in the signal output module for output.

[0097] It should be noted that the specific structure of the decoder is as described in the above embodiments. Since the decoder control method can adopt all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated here.

[0098] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the decoder control method in the above embodiments.

[0099] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0100] The aforementioned computer-readable storage medium may be included in the decoder; or it may exist independently and not be assembled into the decoder.

[0101] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by the decoder, the decoder: receives a mode selection instruction through a decoding control module and generates a decoding control instruction according to the mode selection instruction, wherein the decoding control instruction is used to determine the target decoding chip among the decoding chips in the signal decoding module; transmits the decoding control instruction to the signal decoding module through the decoding control module, so that the signal decoding module determines the target decoding chip among the decoding chips according to the decoding control instruction, decodes the signal to be decoded transmitted by the signal input module through the target decoding chip to obtain a decoded signal, and transmits the decoded signal to the corresponding signal output port in the signal output module for output.

[0102] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0104] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0105] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described decoder control method, which can solve the technical problem that the decoding function of current decoders is relatively limited. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as the beneficial effects of the decoder control method provided in the above embodiments, and will not be repeated here.

[0106] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the decoder control method described above.

[0107] The computer program product provided in this application can solve the technical problem that the decoding function of current decoders is relatively limited. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the decoder control method provided in the above embodiments, and will not be repeated here.

[0108] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A decoder, characterized in that, The decoder includes: A signal input module for receiving a signal to be decoded; A signal output module including a first signal output port and a second signal output port, for outputting a decoded signal corresponding to the signal to be decoded; A signal decoding module including a first decoding chip and a second decoding chip, the first decoding chip and the second decoding chip are respectively connected to the signal input module, the first signal output port and the second signal output port, and the signal decoding module is used to decode the signal to be decoded through a target decoding chip in the first decoding chip and the second decoding chip to obtain the decoded signal, and transmit the decoded signal to the corresponding signal output port; A decoding control module is respectively connected to the I2C communication pins of the first decoding chip and the second decoding chip through an I2C bus, and is used to generate a decoding control instruction according to the received mode selection instruction, and send the decoding control instruction to the signal decoding module through the I2C bus, wherein the decoding control instruction is used to determine the target decoding chip; The general input / output port of the decoding control module is connected to the address pins of the first decoding chip and the second decoding chip, and the decoding control module is further used to receive the level signals of the address pins, identify the chip models of the first decoding chip and the second decoding chip according to the level signals and a preset model look-up table, and load the driver programs of the corresponding decoding chips based on the chip models to drive and control the corresponding decoding chips to perform decoding and output; The decoding control module is further used to generate an output control instruction according to the mode selection instruction, and send the output control instruction to an output switching module, wherein the output control instruction is used to determine a target output port among the first signal output port and the second signal output port, and the output control instruction includes a first independent output instruction, a second independent output instruction and a synchronous output instruction; The decoder further includes: An output switching module respectively connected to the first decoding chip, the second decoding chip, each signal output port and the decoding control module, for receiving the output control instruction and the decoded signal, and outputting the decoded signal to the target output port; The output switching module includes: A first switching tube, the first pole of the first switching tube is grounded, and the second pole of the first switching tube is connected to the decoding control module, for receiving the first independent output instruction and outputting an amplified first independent output instruction; A second switching tube, the first pole of the second switching tube is grounded, and the second pole of the second switching tube is connected to the decoding control module, for receiving the second independent output instruction and outputting an amplified second independent output instruction; A third switching transistor, a first pole of the third switching transistor is grounded, a second pole of the third switching transistor is connected to the decoding control module, and is configured to receive the synchronous output instruction and output an amplified synchronous output instruction; A first relay, a control end of the first relay is connected to a third pole of the first switching transistor, a common end of the first relay is connected to the first decoding chip, and a normally open end of the first relay is connected to the first signal output port; A second relay, a control end of the second relay is connected to a third pole of the second switching transistor, a common end of the second relay is connected to the second decoding chip, and a normally open end of the second relay is connected to the second signal output port; A third relay, a control end of the third relay is connected to a third pole of the third switching transistor, a common end of the third relay is connected to the normally open end of the first relay, and a normally open end of the third relay is connected to the second signal output port.

2. A decoder control method, characterized in that, The decoder control method is applied to the decoder as described in claim 1, and the decoder control method includes: Receiving a mode selection instruction through a decoding control module, and generating a decoding control instruction according to the mode selection instruction, wherein the decoding control instruction is used to determine a target decoding chip in the first decoding chip and the second decoding chip in the signal decoding module; Transmitting the decoding control instruction to the signal decoding module through the I2C bus by the decoding control module, so that the signal decoding module determines the target decoding chip in the first decoding chip and the second decoding chip according to the decoding control instruction, and decodes the signal to be decoded transmitted by the signal input module through the target decoding chip to obtain a decoded signal, and transmits the decoded signal to a corresponding signal output port in the signal output module for output, wherein the decoding control module is respectively connected to the I2C communication pins of each decoding chip through the I2C bus, and the decoding control module is also connected to the address pins of the first decoding chip and the second decoding chip; Receiving a level signal of the address pin through a general input / output port of the decoding control module, identifying the chip model of each decoding chip according to the level signal and a preset model look-up table, and loading a driver program of the corresponding decoding chip based on the chip model to drive and control the corresponding decoding chip to perform decoding and output; Generating an output control instruction according to the mode selection instruction through the decoding control module, and sending the output control instruction to the output switching module, so that the output switching module outputs the decoded signal transmitted by the target decoding chip to the target output port, wherein the output control instruction is used to determine the target output port in the first signal output port and the second signal output port.

3. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the decoder control method as described in claim 2 are implemented.

4. A computer program product, characterized in that, The computer program product includes a computer program which, when executed by a processor, implements the steps of the decoder control method as described in claim 2.

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