Frequency response mismatch error correction apparatus and method for time-interleaved analog-to-digital converters

Abstract

The application discloses a frequency response mismatch error correction device and method of a time-interleaved analog-to-digital converter, comprising an input module, a frequency domain correction module and an output module. The input module is used for separating the parallel data stream output by the time-interleaved analog-to-digital converter in sequence in units of data blocks, each data block comprising data of a plurality of continuous sampling points; the frequency domain correction module is used for converting the time domain data of the data block into frequency domain data, and converting the time domain data back after completing the mismatch error correction in the frequency domain; and the output module is used for merging the data blocks output by the frequency domain correction module, and outputting the parallel data stream obtained after merging. Since the parallel data stream output by the time-interleaved analog-to-digital converter is separated by channel, then switched to the frequency domain to perform the frequency response mismatch error correction, compared with the frequency response mismatch error correction in the time domain, the real-time performance is high, the processing delay is small, the required hardware resource consumption is less and the processing speed is faster.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital conversion technology, and more specifically to a frequency response mismatch error correction device and method for a time-interleaved analog-to-digital converter. Background Technology

[0002] The TIADC system (Time-Interleaved Analog-to-Digital Converter) uses M parallel sub-ADCs that work together in a time-interleaved manner. Besides the M parallel sub-ADCs, it includes an input signal distribution network, a precision clock generation and distribution circuit, a digital multiplexer (MUX), and a digital background correction engine. The input signal distribution network ensures that the analog input signal is transmitted simultaneously and without distortion to the inputs of all M sub-ADCs, with each sub-ADC responsible for converting a portion of the total data stream. The precision clock generation and distribution circuit generates a master sampling clock, then uses a time-locked loop (DLL) or other precision delay circuit to generate M strictly phase-differentiated sub-clock signals, each distributed to its corresponding sub-ADC. The digital multiplexer receives the digital codes output from the M sub-ADCs and interleaves and merges them into a single high-speed data stream according to the sampling time sequence. The digital background correction engine uses real-time or offline calibration algorithms to detect, estimate, and compensate for various mismatch errors. The TIADC system operates by simultaneously connecting an input signal to M sub-ADCs, with each sub-ADC's sampling clock phase differing by T. s / M, where T s This is the total sampling period of the target system. The sub-ADC of the k-th channel at time t = k × T s / M+n× T s Sampling is performed, where n is an integer. Finally, a digital multiplexer interleaves the outputs of the M channels in time sequence, resulting in an output data stream with a sampling rate M times that of a single sub-ADC. TIADC technology is key to achieving ultra-high-speed data acquisition, but the performance bottleneck of a TIADC system does not stem from the sub-ADCs themselves, but rather from mismatch errors between channels. Mismatch errors generate fixed spurs in the output spectrum, severely reducing the system's signal-to-noise ratio (SINAD) and spurious-free dynamic range (SFDR), rendering the ultra-high sampling rate meaningless. Therefore, improving the ability to suppress and correct various mismatch errors is crucial for achieving high performance using TIADC technology. Summary of the Invention

[0003] The main technical problem solved by this invention is how to achieve real-time correction of the frequency response mismatch error of the sampling sequence output by the TIADC system.

[0004] According to a first aspect, one embodiment provides a frequency response mismatch error correction device for a time-interleaved analog-to-digital converter, comprising:

[0005] The input module is used to receive the parallel data stream output by the time-interleaved analog-to-digital converter, and to separate the parallel data stream into data blocks in sequence and output them. Each data block includes data from N consecutive sampling points; where N is an integer greater than 1.

[0006] The frequency domain correction module is used to receive the data block, convert the time domain data of the data block into frequency domain data, and perform mismatch error correction in the frequency domain; the frequency domain correction module is also used to convert the corrected frequency domain data back into time domain data and output it in the form of the data block;

[0007] The output module is used to merge the data blocks output by the frequency domain correction module and output the merged parallel data stream.

[0008] In one embodiment, the input module includes:

[0009] The data input control / conversion unit is used to separate the parallel data stream output by the interleaved analog-to-digital converter into data blocks.

[0010] An input data buffer is used to cache the separated data blocks;

[0011] The data reading control unit is used to control the reading of data in the input data buffer, and to read out the data and output it to the frequency domain correction module in units of data blocks.

[0012] In one embodiment, the frequency domain correction module includes:

[0013] A time-domain to frequency-domain transformation unit is used to convert the data block read from the input data buffer into frequency-domain data in parallel;

[0014] A filtering unit is used to filter each sampling point in the data block, which has been converted into frequency domain data, according to pre-configured filtering coefficients.

[0015] The frequency-domain-time-domain transformation unit is used to convert the filtered frequency-domain data into time-domain data in parallel and output the data in blocks.

[0016] In one embodiment, the time-domain frequency-domain transformation unit and the frequency-domain time-domain transformation unit respectively include C parallel L-point Fourier transform subunits, a phase rotation subunit, and a C-point Fourier transform subunit.

[0017] The C parallel L-point Fourier transform subunits are used to perform C-path parallel processing on the data block. The processed frequency domain data is phase-rotated by the phase rotation subunit and then output to the C-point Fourier transform subunit.

[0018] The C-point Fourier transform subunit processes the frequency domain data output by C parallel L-point Fourier transform subunits to obtain a C×L data matrix.

[0019] The frequency domain correction module further includes a first conjugate conversion unit and a second conjugate conversion unit;

[0020] The first conjugate conversion unit is used to perform conjugate conversion on the data block output by the filtering unit, and output the conjugate-converted data block to the frequency domain time domain transformation unit;

[0021] The second conjugate transformation unit is used to perform conjugate transformation on the time-domain data output by the frequency-domain time-domain transformation unit to obtain the data block.

[0022] In one embodiment, the time-domain frequency-domain transformation unit and the frequency-domain time-domain transformation unit further include matrix transformation sub-units, which are connected between the C-point Fourier transform sub-unit and the filtering unit, and are used to adjust the row and column data positions in the C×L data matrix output by the C-point Fourier transform sub-unit.

[0023] In one embodiment, the output module includes:

[0024] The overlap processing unit is used to perform overlap processing on data blocks as units of data blocks on data that have been converted from parallel to time-domain data.

[0025] The overlap processing includes:

[0026] For adjacent data blocks, the tail data of the preset number of points in the previous data block and the header data of the same number of points in the next data block are added together, and the result of the addition is used as the tail data of the previous data block; or, for adjacent data blocks, the header data of the preset number of points in the previous data block is discarded.

[0027] In one embodiment, the output module further includes:

[0028] The delay unit is used to delay the data blocks after the overlap processing, so that the data order of each data block is staggered by a preset number of sampling points;

[0029] An extraction unit is used to extract M times the data from the data block after delay processing;

[0030] The combination unit recombines and merges the extracted data and outputs the merged parallel data stream.

[0031] According to a second aspect, one embodiment provides a method for correcting frequency response mismatch error in a time-interleaved analog-to-digital converter, comprising:

[0032] The system receives the parallel data stream output by the time-interleaved analog-to-digital converter, and then outputs the parallel data stream sequentially in units of data blocks, each of which includes data from multiple consecutive sampling points.

[0033] The time-domain data of the data block is converted into frequency-domain data, and mismatch error correction is performed in the frequency domain.

[0034] The corrected frequency domain data is then converted back into time domain data and output in the form of data blocks.

[0035] The data blocks obtained after being converted to time domain data are merged, and the merged parallel data stream is output.

[0036] In one embodiment, the step of performing mismatch error correction in the frequency domain includes:

[0037] Each sampling point in the data block, converted to frequency domain data, is filtered according to pre-configured filtering coefficients.

[0038] The step of converting the corrected frequency domain data back into time domain data includes:

[0039] The filtered frequency domain data is converted into time domain data in parallel.

[0040] In one embodiment, merging the data blocks obtained after conversion to time-domain data includes:

[0041] The data blocks that are converted into time-domain data in parallel are sequentially subjected to overlap processing, delay processing, and extraction processing. The data obtained after extraction processing are then recombined and merged to obtain the parallel data stream.

[0042] The overlapping process includes:

[0043] For adjacent data blocks, the tail data of the preset number of points in the previous data block and the header data of the same number of points in the next data block are added together, and the result of the addition is used as the tail data of the previous data block; or, for adjacent data blocks, the header data of the preset number of points in the previous data block is discarded.

[0044] The delay processing includes:

[0045] The overlapping data blocks are delayed so that the data order of each data block is staggered by a preset number of sampling points.

[0046] The extraction process includes:

[0047] Extract M times the data from the data block after delay processing;

[0048] The step of recombining and merging the data obtained after extraction and processing includes:

[0049] The extracted data is recombined and merged, and the merged parallel data stream is output.

[0050] According to a third aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the method as described in the second aspect.

[0051] According to the fourth aspect, one embodiment provides a computer program product including a computer program and / or instructions that, when executed by a processor, implement the method as described in the second aspect.

[0052] The frequency response mismatch error correction device according to the above embodiment consumes less hardware and has a faster processing speed than performing frequency response mismatch error correction in the time domain, because it separates the parallel data stream output by the time-interleaved analog-to-digital converter by channel and then switches to the frequency domain to perform frequency response mismatch error correction. Attached Figure Description

[0053] Figure 1 This is a functional block diagram of a frequency response mismatch error correction device in one embodiment;

[0054] Figure 2 This is a schematic diagram of data block caching in the input data buffer in one embodiment;

[0055] Figure 3 This is a schematic diagram of data block caching in the input data buffer in another embodiment;

[0056] Figure 4 This is a functional structure diagram of a frequency domain correction module in one embodiment;

[0057] Figure 5 This is a flowchart illustrating a frequency response mismatch error correction method in one embodiment.

[0058] Figure 6 This is a schematic diagram of 80-point FFT decomposition in one embodiment;

[0059] Figure 7 This is a schematic diagram illustrating the principle of frequency domain filtering in one embodiment;

[0060] Figure 8 This is a schematic diagram illustrating the processing of an overlap-add method.

[0061] Figure 9 This is a schematic diagram of the processing procedure for an overlap-save method;

[0062] Figure 10 This is a functional block diagram of the frequency response mismatch error correction device in another embodiment;

[0063] Figure 11 A schematic diagram showing the functional location setting for frequency response mismatch error correction in existing technologies;

[0064] Figure 12 This is a schematic diagram showing the functional location setting for frequency response mismatch error correction in one embodiment. Detailed Implementation

[0065] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0066] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0067] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0068] The data streams output by TIADC sampling systems are high-speed parallel data streams. In applications with stringent latency requirements, such as 5G communication and moving target detection, minimizing data processing latency is crucial. Furthermore, while the M sub-ADCs of a TIADC system should possess completely identical characteristics (gain, timing, and DC bias, etc.), variations in manufacturing processes, slight differences in component parameters, changes in the operating environment, and asymmetry in layout and routing mean that the actual characteristics of each sub-ADC cannot be exactly the same. These inherent, random differences are the main causes of mismatch errors. Mismatch errors in TIADC systems primarily include offset mismatch, gain mismatch, timing skew, bandwidth mismatch, and nonlinearity mismatch, each with a different mechanism of impact on system performance. The combined effect of these mismatch errors leads to a sharp deterioration in the dynamic performance of the TIADC system. Among them, gain mismatch error and time mismatch error are often related to the frequency of the input signal. That is, signals of different frequencies will have different gain mismatch and time mismatch, which is the frequency response mismatch error.

[0069] Frequency response mismatch error can be obtained by calculating the frequency response of each channel's output data using a frequency sweep method or FFT processing, thereby calculating the frequency response mismatch error between channels. Correction of frequency response mismatch error is performed at the digital back-end, requiring digital filters for correction or compensation. The number of digital filters needed is related to the number of channels in the TIADC, and the order of each digital filter depends on the frequency response mismatch error characteristics. Bias mismatch error, gain mismatch error, time mismatch error, and frequency-related frequency response mismatch error in a TIADC system are generally classified as linear mismatch errors. These mismatch errors constitute a major factor in the TIADC system error signal, manifesting as a large number and wide distribution of spurious spectra. Nonlinear mismatch errors, on the other hand, mainly exist in the form of signal harmonics in the TIADC system error, and their impact is less than that of the aforementioned linear mismatch errors.

[0070] Currently, the correction of frequency response mismatch error is basically performed on serial data streams. However, in practical applications, the data streams output by high-speed TIADC sampling systems are high-speed parallel data streams (for example, a TIADC system with a sampling rate of 20Gsps may output 80 channels of high-speed parallel data streams at a rate of 250MHz). In application scenarios with stringent requirements for data processing latency (such as 5G communication and moving target detection), it is desirable to minimize the latency of data processing.

[0071] In this embodiment, when correcting the frequency response mismatch error of the high-speed parallel data stream output by the TIADC system, the parallel data stream is first separated, and the frequency response mismatch error is converted to the frequency domain using parallel FFT and frequency domain filtering techniques before correction and compensation. In one embodiment, the correction and compensation of the frequency response mismatch error is set at the digital back-end of the TIADC system, enabling the correction and compensation of the frequency response mismatch error of the TIADC system to be processed in real time, thereby achieving fast processing speed, low latency, and less hardware resource consumption.

[0072] Example 1:

[0073] Please refer to Figure 1 This is a functional block diagram of a frequency response mismatch error correction device in one embodiment. The device is used to correct the frequency response mismatch error of a parallel data stream output from a time-interleaved analog-to-digital converter (ADC). It includes an input module 1, a frequency domain correction module 2, and an output module 3. The input module 1 receives the parallel data stream output from the ADC and sequentially separates it into data blocks before outputting each block. Each data block includes N consecutive sampling points, where N is an integer greater than 1. The frequency domain correction module 2 receives the data blocks, converts the time-domain data of the data blocks into frequency-domain data, and performs mismatch error correction in the frequency domain. The module also converts the corrected frequency-domain data back into time-domain data and outputs it in data block form. The output module 3 merges the data blocks output by the frequency domain correction module 2 and outputs the merged parallel data stream.

[0074] In one embodiment, the input module 1 includes a data input control / conversion unit 11, an input data buffer 12, and a data read control unit 13. The data input control / conversion unit 11 is used to separate the parallel data stream output by the interleaved analog-to-digital converter into data blocks. The input data buffer 12 is used to buffer the separated data blocks. The data read control unit 13 is used to control the reading of data in the input data buffer 12, reading out the data in data blocks and outputting it to the frequency domain correction module 2.

[0075] In one embodiment, the number of channels in the TIADC system is set to M, such as... Figure 1 As shown, the parallel data stream acquired and output by the TIADC is buffered separately according to each channel number after passing through the data input control / conversion unit 11. In the input data buffer, data blocks are buffered in sections according to channel number order. Please refer to... Figure 2 This is a schematic diagram illustrating the caching of data blocks in the input data buffer in one embodiment, where data blocks are cached primarily based on the channel number sequence. Please refer to [link / reference]. Figure 3 This is a schematic diagram of data block caching in the input data buffer in another embodiment, where data blocks are cached primarily based on their sequence numbers. The data input control / conversion unit separates the parallel data stream output by the TIADC and caches the data blocks from each channel. The size of the data block can be determined based on the number of FFT points used in the subsequent frequency domain correction module. Assuming the number of FFT points is N, and N can be represented as the product of two integers, i.e., N = L × C, then the size of the data block is N sampling points, and its storage structure can be L rows and C columns or C rows and L columns. In one embodiment, the data read control unit 13 is used to control the reading of data from the input data buffer 12, reading out data in units of data blocks and outputting it to the subsequent frequency domain correction module 2. The bit width of the output port of each data block can be flexibly configured according to real-time processing requirements and hardware logic resources. For example, the size of each data block can be N sampling points, cached in an L row and C column structure, or cached in a C row and L column structure. Therefore, the output port of the data block can be a bit width of L sampling points or a bit width of C sampling points.

[0076] Please refer to Figure 4 This is a functional structure diagram of a frequency domain correction module in one embodiment. The frequency domain correction module 2 includes a time-domain-frequency domain transformation unit 21, a filtering unit 22, and a frequency-domain-time domain transformation unit 23. The time-domain-frequency domain transformation unit 21 is used to convert data blocks read from the input data buffer into frequency domain data in parallel. The filtering unit 22 is used to filter each sampling point in the converted frequency domain data according to pre-configured filtering coefficients. The frequency-domain-time domain transformation unit 23 is used to convert the filtered frequency domain data into time domain data in parallel and output it in units of data blocks. The time-domain-frequency domain transformation unit 21 and the frequency-domain-time domain transformation unit 23 each include C parallel L-point Fourier transform subunits, a phase rotation subunit, and a C-point Fourier transform subunit. The C parallel L-point Fourier transform subunits are used to perform C-path parallel processing on the data blocks. The processed frequency domain data is phase-rotated by the phase rotation subunit and then output to the C-point Fourier transform subunit. The C-point Fourier transform subunit processes the frequency domain data output from C parallel L-point Fourier transform subunits to obtain a C×L data matrix.

[0077] like Figure 4As shown, the frequency domain correction module also includes a first conjugate conversion unit 24 and a second conjugate conversion unit 25. The first conjugate conversion unit 24 is used to perform a conjugate conversion on the data block output by the filtering unit and output the conjugate-converted data block to the frequency domain-time domain transformation unit 23. The second conjugate conversion unit 25 is used to perform a conjugate conversion on the time domain data output by the frequency domain-time domain transformation unit to obtain a data block. The time domain-frequency domain transformation unit 21 and the frequency domain-time domain transformation unit 23 also include matrix transformation subunits, which are connected between the C-point Fourier transform subunit and the filtering unit, and are used to adjust the row and column data positions in the C×L data matrix output by the C-point Fourier transform subunit.

[0078] like Figure 1 As shown, the output module 3 includes an overlap processing unit 31, a delay unit 32, an extraction unit 33, and a combination unit 34. The overlap processing unit 31 performs overlap processing on the data converted from parallel data to time-domain data, in units of data blocks. In one embodiment, for adjacent data blocks, the overlap processing adds the tail data of a preset number of points from the previous data block to the header data of the same number of points from the next data block, and uses the sum as the tail data of the previous data block. In another embodiment, the overlap processing discards the header data of a preset number of points from the previous data block for adjacent data blocks. The delay unit 32 performs delay processing on the overlapped data blocks, so that the data order of each data block is staggered by a preset number of sampling points. The extraction unit 33 extracts M times the data from the delayed data blocks. The combination unit 34 recombines and merges the extracted data, and outputs the merged parallel data stream.

[0079] Please refer to Figure 5 The diagram below is a flowchart illustrating a frequency response mismatch error correction method in one embodiment. In another embodiment of this application, a frequency response mismatch error correction method is also disclosed, applied to the frequency response mismatch error correction device described above. This frequency response mismatch error correction method includes:

[0080] Step 101: Obtain the data block.

[0081] It receives the parallel data stream output from the time-interleaved analog-to-digital converter, and outputs the parallel data stream sequentially in units of data blocks. Each data block includes data from multiple consecutive sampling points.

[0082] Step 102, frequency domain conversion.

[0083] The time-domain data of the data block is converted into frequency-domain data, and mismatch error correction is performed in the frequency domain. Specifically, mismatch error correction in the frequency domain involves filtering each sampling point in the converted frequency-domain data block according to pre-configured filtering coefficients.

[0084] Step 103, time domain transformation.

[0085] The corrected frequency domain data is then converted back to time domain data and output in data blocks. In one embodiment, the filtered frequency domain data is converted to time domain data in parallel.

[0086] Step 104: Output data.

[0087] The data blocks obtained after being converted to time-domain data are merged, and the merged parallel data stream is output. In one embodiment, the data blocks converted to time-domain data in parallel are sequentially subjected to overlap processing, delay processing, and decimation processing. The data obtained after decimation processing is then recombined and merged to obtain a parallel data stream. Specifically, overlap processing involves adding the tail data of a predetermined number of points from the previous data block to the header data of the next data block with the same number of points, and using the sum as the tail data of the previous data block; or, for adjacent data blocks, discarding the header data of a predetermined number of points from the previous data block. Delay processing involves delaying the overlapped data blocks so that the data order of each data block is staggered by a predetermined number of sampling points. Decimation processing involves decimating the data of the delayed data blocks by a factor of M. Data recombining and merging involves recombining and merging the decimated data and outputting the merged parallel data stream.

[0088] The frequency response mismatch error correction device disclosed in this application includes an input module, a frequency domain correction module, and an output module. The input module sequentially separates the parallel data stream output from the time-interleaved analog-to-digital converter into data blocks, each data block including data from multiple consecutive sampling points. The frequency domain correction module converts the time-domain data of the data blocks into frequency-domain data, performs mismatch error correction in the frequency domain, and then converts it back to the time domain. The output module merges the data blocks output by the frequency domain correction module and outputs the merged parallel data stream. Because separating the parallel data stream output from the time-interleaved analog-to-digital converter by channel and then switching to the frequency domain for frequency response mismatch error correction results in higher real-time performance, lower processing latency, lower hardware resource consumption, and faster processing speed compared to correcting frequency response mismatch errors in the time domain.

[0089] To facilitate understanding of the principle and implementation of the frequency response mismatch error correction method disclosed in this application, specific embodiments are described below, including:

[0090] In one embodiment of this application, parallel Fourier transform refers to the process of decomposing a large-point one-dimensional FFT into multiple small-point multi-dimensional FFTs and performing parallel operations. For example:

[0091] Let the input sequence be x[n], then the formula for calculating the N-point FFT (DFT) is:

[0092] (1)

[0093] Decompose the N-point input sequence x[n] into L rows and C columns, that is, let N = L × C, then the input index n and the output index k can be expressed as:

[0094] n=Cl+c, k=Lr+s; (2)

[0095] Where c = 0, 1, ..., C-1;

[0096] l=0,1,…,L-1;

[0097] r=0,1,…,C-1;

[0098] s=0,1,…,L-1;

[0099] From formulas (1) and (2), we can obtain:

[0100] (3)

[0101] ;

[0102] Then we have:

[0103] (4)

[0104] Predefined:

[0105] (5)

[0106] Therefore, when c takes a certain fixed value, q[s,c], (s=0,1,…,L-1) corresponds to the L-point DFT of the c-th column of the original data two-dimensional matrix, and its butterfly factor is Therefore, we have:

[0107]

[0108] (6)

[0109] Formula (6) can be viewed as an expression for the intermediate result matrix q[s,c]. The DFT of point C in the s-th row has a butterfly factor of The calculation process of formula (6) is as follows:

[0110] First, the original input data matrix (L rows, C columns) is processed column by column using formula (5) with L-point DFT operations. The column indices c are sequentially 0, 1, ..., C-1; for each value of c, the s values ​​are sequentially 0, 1, ..., L-1. Thus, for each given c value, L q[s,c] values ​​are obtained (forming a column). After processing the C columns of data, a... The intermediate matrix q[s,c] is in row C and column C, where c=0,1,…,C-1 and s=0,1,…,L-1.

[0111] Then, each element of matrix q[s,c] is multiplied by the corresponding... We obtain matrix Q[s,c].

[0112] Next, perform a C-point DFT operation on matrix Q[s,c] row by row, that is, let the s value (row index) take the values ​​0, 1, ..., L-1 in sequence, and for each value of s, let the r value (column index) in X[Lr+s] take the values ​​0, 1, ..., C-1 in sequence. Where:

[0113] ;

[0114] Thus, the C values ​​of X[k] corresponding to the s-th row are obtained as follows:

[0115] (X[s],X[L+s],X[2L+s],X[3L+s],…,X[(C-1)L+s]);

[0116] Each time an X[Lr+s] value is obtained, it is equivalent to requiring C butterfly operations, that is, the results are added together. When the s and r values ​​have been traversed, the final X[k] in L rows and C columns is obtained.

[0117] The following example uses an 80-point FFT. Please refer to it. Figure 6 This is a schematic diagram of an 80-point FFT decomposition in one embodiment. The input sequence x[n] is decomposed into L=10 rows and C=8 columns, i.e., 80=10×8. Note the index order during the decomposition of the input sequence x[n]. Figure 6 The matrix q[s,c] in the matrix also needs to be multiplied by (Not explicitly marked) Decomposing an N-point FFT using the above method significantly increases processing speed. This is because an N-point FFT, processed sequentially in one dimension using traditional methods (e.g., the FFT IP cores provided by most FPGA chip manufacturers), employs a pipelining approach. Under ideal conditions without considering fixed delays, it requires N clock cycles to complete. However, with parallel decomposition, using C L-point FFTs in parallel processing (as disclosed in the embodiments of this application), under ideal conditions without considering fixed delays, only L clock cycles are needed to complete the N-point FFT. Since performing an L-point FFT column-wise involves C FFTs in parallel, each clock cycle can generate C intermediate output results. Conversely, performing a C-point FFT row-wise requires only one C-point FFT operation. This parallel processing data format is highly suitable for performing FFT operations on multiple high-speed parallel data streams.

[0118] Please refer to Figure 7 This is a schematic diagram illustrating the principle of frequency domain filtering in one embodiment. According to signal processing theory, time-domain convolutional filtering can be performed in the frequency domain using the Discrete Fourier Transform (DFT). First, the input data is transformed to the frequency domain using the FFT. Then, it is multiplied by the frequency response coefficients corresponding to the filter impulse response in the frequency domain, and finally, the filtered data is restored to the time domain using the IFFT. However, in practice, frequency domain filtering is not directly implemented like... Figure 7 It's not as simple as it looks; rather, it requires appropriate overlap processing of the input or output based on the filter's impulse response length. In practical applications, overlap-add and overlap-save methods can be used. Please refer to [reference needed]. Figure 8 and Figure 9 The diagrams illustrate the processing steps of two methods: overlap-add and overlap-save. In the overlap-add method, the number of FFT points is set to N, the filter impulse response length is P, and the length of input data that can be effectively processed by each FFT is NP points. For the overlap-add method, each FFT input data takes NP points and is padded with P zeros. In the FFT output, the first P points of the k-th FFT output are added to the last P points of the (k-1)-th FFT output, and the result is used as the final value of the first P points of the k-th FFT output. In the overlap-save method, the first P points of the input data for the k-th FFT are the same as the last P points of the input data for the (k-1)-th FFT (overlap), and the first P points are discarded during each FFT output process.

[0119] The process of frequency domain filtering of parallel data streams is as follows: Figure 4As shown in the figure (only the key processes are shown; in actual processing, the input or output data needs to be cached, format converted, etc., depending on the overlap method used), the phase rotation sub-unit multiplies each element of the matrix q[s,c] by the corresponding... The operation to obtain matrix Q[s,c]; the role of the matrix transformation sub-unit is to make the data format (data arrangement order) suitable for the requirements of the next operation stage. Furthermore, as can be seen from the formulas for DFT and IDFT, the overall structure of the filtered IFFT can reuse the structure of the preceding FFT, but the first conjugate transformation unit needs to perform a conjugate operation on the filtered data first, and then the second conjugate transformation unit performs a conjugate operation on the FFT output (and divides it by N). In practice, the data bit width related to the IFFT stage needs to be adjusted according to requirements such as data bit width and precision. It should be noted that... Figure 4 The FFT at point C can be further decomposed as needed (parallel FFT decomposition can be recursively processed).

[0120] Please refer to Figure 10 This is a functional block diagram of the frequency response mismatch error correction device in another embodiment. It illustrates the architecture for real-time correction of frequency response mismatch errors in a TIADC system using high-speed parallel sampling data streams in the frequency domain, utilizing FFT parallel decomposition technology and frequency domain filtering technology. The input parallel data stream is the parallel sampling data stream output by the TIADC system. After data block separation by the input module, each block undergoes Fourier transform to the frequency domain. The frequency domain data is then fed to M filter sub-units for filtering. These M filter sub-units correspond to the M frequency response mismatch error correction filters of the TIADC system, where M is the number of interleaving channels in the TIADC system. After filtering, the data from each channel undergoes IFFT and overlap processing. Each channel's data then undergoes a corresponding delay processing before being decimated by a factor of M. Finally, the decimated data streams are reassembled and output. The delay processing ensures that the data from each channel are staggered by one sampling point before decimation. The data stream at any stage of each channel is a high-speed parallel data stream. Taking a TIADC system with a sampling rate of 20 GSPS as an example, assuming its output sampled data stream is an 80-channel parallel data stream at a rate of 250 MHz, and the TIADC interleaving channel number is M=8, therefore there are 8 filter subunits and 8 IFFT channels. The input data stream is also an 80-channel parallel data stream at a rate of 250 MHz. To achieve fully real-time processing, assuming a processing clock of 250 MHz, then... Figure 10 The data flow at each stage will exceed 80 channels because frequency domain filtering overlap processing requires additional time overhead. Assume the order P of the frequency response mismatch error correction filter is... If we choose an FFT of 1024 points (N), we can decompose the 1024-point FFT into 128 8-point FFTs, where L=8 and C=128. In the input data stream, each data block has NP=1024-256=768 points. The time corresponding to 80 parallel data streams is 768 / 80 / 250MHz, or 38.4ns. When the 1024-point FFT is decomposed into 128 8-point FFTs, all operations are pipelining. The N-point FFT processing only requires 8 clock cycles, or 32ns, which is less than 38.4ns, thus sufficient for real-time processing requirements.

[0121] Please refer to Figure 11 This diagram illustrates the functional location of frequency response mismatch error correction in existing technologies. In these technologies, frequency response mismatch error correction requires a preset trigger control to cache the high-speed data stream in a storage medium (such as DDR3 or DDR4). This caching is intermittent; that is, each trigger continuously acquires and caches data for a specific time period, then reads the data from the storage area as a serial data stream for mismatch error correction. This method involves triggering once, acquiring one frame of data, and then processing that frame. Because the algorithm for frequency response mismatch error correction is designed for serial data streams, its processing speed is low. For example, if the FPGA's operating clock is 250MHz, processing one point takes 4ns. Assuming continuous processing of 1 mega-points, the processing time would be 4ms. Clearly, the real-time data stream rate of the TIADC system is 160×250MHz, meaning the processing speed of this method is only 1×250MHz, far from meeting real-time requirements. Even theoretically, when the real-time rate of the input data stream is 160×250MHz, real-time processing cannot be achieved if the subsequent processing rate does not reach 160×250Msps (160×250 megasamples per second). Even in some special cases where multiple parallel data streams can be used for simultaneous processing in the time domain (for example, when the number of TIADC sub-channels is 16, 16 or 32 parallel data streams can be used simultaneously for mismatch error correction), it still cannot meet the requirements of practical real-time processing. Furthermore, if real-time correction is achieved by directly filtering multiple parallel data streams in the time domain, the correction filter order corresponding to the frequency response mismatch error is relatively high (not less than 256th order). If 160 parallel data streams are directly filtered, 40,960 multipliers are required, which is generally not available in FPGAs.

[0122] When performing frequency response mismatch error correction according to the method disclosed in the embodiments of this application, when the TIADC output data stream is 160 channels at 250MHz, C=256, L=8, data block size N=2048 can be set, using 256 parallel 8-point FFT operations, with a working clock of 250MHz. Then, each working clock can process 256 points, meaning the processing rate can reach 256×250MHz. Since this is higher than the TIADC sampling data stream rate, fully real-time processing can be achieved (with redundancy). Based on the above parameter settings, the required multiplier resources are:

[0123] 1) An 8-point FFT operation can be implemented using 3 multipliers in a pipelined manner. Therefore, a 256-way parallel 8-point FFT only requires 256×3, or 768 multipliers.

[0124] 2) A 256-point FFT operation only requires 27 multipliers using pipelined operation.

[0125] 3) When performing phase rotation, 256 complex multiplications are required, which necessitates 256 × 4 multipliers.

[0126] 4) The filtering operation corresponds to 256 complex multiplications, requiring 256 × 4 multipliers;

[0127] 5) The number of multipliers consumed by IFFT operation is the same as that of FFT operation.

[0128] The total multiplier cost required is:

[0129] (768+27+256×4)×2+256×4=4662.

[0130] In summary, the comparison between existing technologies for frequency response mismatch error correction (time-domain serial processing and time-domain parallel processing) and the frequency response mismatch error correction method disclosed in the embodiments of this application is shown in Table 1 below:

[0131] Table 1:

[0132] Error correction processing method Number of parallel processing paths Is it real-time? Multiplier consumption Time-domain serial processing Route 1 Non-real-time 256 (filter order) Temporal parallel processing Route 160 real time 160×256=40960 Frequency domain parallel processing ≥160 routes real time 4662

[0133] Also, please refer to Figure 12 This is a schematic diagram illustrating the functional location setting of frequency response mismatch error correction in one embodiment. In this embodiment, frequency response mismatch error correction is set after the TIADC system and before the digital triggering system and the acquisition and storage control (in the prior art, such as...). Figure 8 As shown, the frequency response mismatch error correction setting is implemented after the acquisition and storage control. This can prevent the frequency response mismatch error signal from interfering with or affecting the digital triggering system, thus making the triggering accuracy of the digital triggering system higher and more stable.

[0134] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0135] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A frequency response mismatch error correction device for a time-interleaved analog-to-digital converter, characterized in that, include: The input module is used to receive the parallel data stream output by the time-interleaved analog-to-digital converter, and to separate the parallel data stream into data blocks in sequence and output them. Each data block includes data from N consecutive sampling points; where N is an integer greater than 1. The frequency domain correction module is used to receive the data block, convert the time domain data of the data block into frequency domain data, and perform mismatch error correction in the frequency domain; the frequency domain correction module is also used to convert the corrected frequency domain data back into time domain data and output it in the form of the data block; The output module is used to merge the data blocks output by the frequency domain correction module and output the merged parallel data stream. The input module includes: The data input control / conversion unit is used to separate the parallel data stream output by the interleaved analog-to-digital converter into data blocks. An input data buffer is used to cache the separated data blocks; The data reading control unit is used to control the reading of data in the input data buffer, and to read out and output the data to the frequency domain correction module in units of data blocks; The frequency domain correction module includes: A time-domain to frequency-domain transformation unit is used to convert the data block read from the input data buffer into frequency-domain data in parallel; A filtering unit is used to filter each sampling point in the data block, which has been converted into frequency domain data, according to pre-configured filtering coefficients. The frequency-domain-time-domain transformation unit is used to convert the filtered frequency-domain data into time-domain data in parallel and output the data in blocks.

2. The frequency response mismatch error correction device as described in claim 1, characterized in that, The time-domain frequency-domain transformation unit and the frequency-domain time-domain transformation unit each include C parallel L-point Fourier transform subunits, a phase rotation subunit, and a C-point Fourier transform subunit. The C parallel L-point Fourier transform subunits are used to perform C-path parallel processing on the data block. The processed frequency domain data is phase-rotated by the phase rotation subunit and then output to the C-point Fourier transform subunit. The C-point Fourier transform subunit processes the frequency domain data output by C parallel L-point Fourier transform subunits to obtain a C×L data matrix. The frequency domain correction module further includes a first conjugate conversion unit and a second conjugate conversion unit; The first conjugate conversion unit is used to perform conjugate conversion on the data block output by the filtering unit, and output the conjugate-converted data block to the frequency domain time domain transformation unit; The second conjugate transformation unit is used to perform conjugate transformation on the time-domain data output by the frequency-domain time-domain transformation unit to obtain the data block.

3. The frequency response mismatch error correction device as described in claim 2, characterized in that, The time-domain-frequency-domain transformation unit and the frequency-domain-time-domain transformation unit each include a matrix transformation subunit. The matrix transformation subunit is connected between the C-point Fourier transform subunit and the filtering unit and is used to adjust the row and column data positions in the C×L data matrix output by the C-point Fourier transform subunit.

4. The frequency response mismatch error correction device as described in claim 1, characterized in that, The output module includes: The overlap processing unit is used to perform overlap processing on data blocks as units of data blocks on data that have been converted from parallel to time-domain data. The overlap processing includes: For adjacent data blocks, the tail data of the preset number of points in the previous data block and the header data of the same number of points in the next data block are added together, and the result of the addition is used as the tail data of the previous data block; or, for adjacent data blocks, the header data of the preset number of points in the previous data block is discarded.

5. The frequency response mismatch error correction device as described in claim 4, characterized in that, The output module also includes: The delay unit is used to delay the data blocks after the overlap processing, so that the data order of each data block is staggered by a preset number of sampling points; An extraction unit is used to extract M times the data from the data block after delay processing; The combination unit is used to recombine and merge the extracted data and output the merged parallel data stream.

6. A method for correcting frequency response mismatch error in a time-interleaved analog-to-digital converter, characterized in that, include: The system receives the parallel data stream output by the time-interleaved analog-to-digital converter, and then outputs the parallel data stream sequentially in units of data blocks, each of which includes data from multiple consecutive sampling points. The time-domain data of the data block is converted into frequency-domain data, and mismatch error correction is performed in the frequency domain. The corrected frequency domain data is then converted back into time domain data and output in the form of data blocks. The data blocks obtained after being converted to time-domain data are merged, and the merged parallel data stream is output. The process of correcting mismatch errors in the frequency domain includes: Each sampling point in the data block, converted to frequency domain data, is filtered according to pre-configured filtering coefficients. The step of converting the corrected frequency domain data back into time domain data includes: The filtered frequency domain data is converted into time domain data in parallel.

7. The frequency response mismatch error correction method as described in claim 6, characterized in that, The process of merging the data blocks obtained after converting them to time-domain data includes: The data blocks that are converted into time-domain data in parallel are sequentially subjected to overlap processing, delay processing, and extraction processing. The data obtained after extraction processing are then recombined and merged to obtain the parallel data stream. The overlapping process includes: For adjacent data blocks, the tail data of the preset number of points in the previous data block and the header data of the same number of points in the next data block are added together, and the result of the addition is used as the tail data of the previous data block; or, for adjacent data blocks, the header data of the preset number of points in the previous data block is discarded. The delay processing includes: The overlapping data blocks are delayed so that the data order of each data block is staggered by a preset number of sampling points. The extraction process includes: Extract M times the data from the data block after delay processing; The step of recombining and merging the data obtained after extraction and processing includes: The extracted data is recombined and merged, and the merged parallel data stream is output.

8. A computer-readable storage medium, characterized in that, The medium stores a computer program that can be executed by a processor to implement the method as described in any one of claims 6-7.

9. A computer program product, comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the method of any one of claims 6-7.

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