A fully pipelined general-purpose Montgomery modular multiplication method for x86-64 platform

Abstract

This invention discloses a fully pipelined general Montgomery modular multiplication method for the x86-64 platform. Utilizing the BMI2 and ADX instruction sets, combined with the pipelined and multi-issue mechanisms of the x86-64 platform, and through register allocation and adjustment of computation steps, it implements general Montgomery modular multiplication and modular squaring operations for 256-bit elliptic curve cryptography algorithms. Specifically, the general Montgomery modular multiplication operation includes multiplication, and the general Montgomery modular squaring operation includes squaring; both operations also include general Montgomery modular reduction. The computation steps for multiplication and squaring are adjusted to allow the two addition chains in the operation to execute in parallel. The computation steps for Montgomery modular reduction are also adjusted to extend the previous round of addition in the loop calculation step to the next round, and execute it in parallel with the next round of multiplication. This invention enables general Montgomery modular multiplication on the x86-64 platform, optimizing computational performance.

Description

Technical Field

[0001] This invention relates to the field of cryptographic algorithm technology, and in particular to a fully pipelined general Montgomery modular multiplication method for the x86-64 platform. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Modular multiplication is a fundamental core step in elliptic curve cryptography (ECC), and its performance directly impacts the overall performance and efficiency of the entire ECC algorithm. Among all modular multiplication algorithms, the Montgomery modular multiplication algorithm is widely used due to its superior performance and low memory footprint. However, existing cryptographic libraries have certain shortcomings in supporting Montgomery modular multiplication: on the one hand, some libraries often adopt general optimization strategies to ensure universality, resulting in poor adaptability to the x86-64 platform and failing to fully utilize the platform's performance; on the other hand, some libraries have optimized for the x86-64 platform, but the optimization strategies only apply to specific elliptic curves such as secp256r1 and sm2, lacking universality.

[0004] Specifically, in commonly used cryptographic libraries such as WolfSSL, OpenSSL, and GMSSSL, while some algorithms use the BMI2 and ADX instruction sets for modular multiplication on the x86-64 platform, these are optimized for specific curves such as secp256r1 and sm2, lacking general applicability. Conversely, some elliptic curves applicable to arbitrary bit widths do not use the BMI2 and ADX instruction sets; similarly, some implementations applicable to 256-bit elliptic curves also do not. For example, in the existing WolfSSL library, implementations for secp256r1 and sm2 use the BMI2 and ADX instruction sets, but general 256-bit implementations do not; the OpenSSL library only uses these instruction sets in its secp256r1 implementation, but not in general implementations; and the GMSSSL library's implementation for sm2 also does not use the BMI2 and ADX instruction sets, but not in general implementations. Therefore, there is currently a lack of solutions that use the BMI2 and ADX instruction sets on the x86-64 platform and are applicable to any 256-bit elliptic curve. General Montgomery modular multiplication is difficult to adapt to the x86-64 platform and cannot balance the versatility and high performance of the operation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a fully pipelined, universal Montgomery modular multiplication method for the x86-64 platform. Utilizing the BMI2 and ADX instruction sets of the x86-64 platform, and combining the platform's pipelined and multi-issue mechanisms, this method achieves universal Montgomery modular multiplication through reasonable register allocation and a logical arrangement of computational steps. This solves the problem in existing cryptographic algorithm libraries where Montgomery modular multiplication suffers from insufficient performance and high memory consumption due to the difficulty in simultaneously achieving x86-64 platform compatibility and universality with arbitrary 256-bit elliptic curves.

[0006] In one aspect, the present invention provides a fully pipelined general Montgomery modular multiplication method for the x86-64 platform.

[0007] A fully pipelined, general-purpose Montgomery modular multiplication method for the x86-64 platform includes:

[0008] By utilizing the BMI2 and ADX instruction sets, combined with the pipeline and multiple issue mechanism of the x86-64 platform, and by allocating registers and adjusting computation steps, a general Montgomery modular multiplication and a general Montgomery modular square operation for 256-bit elliptic curve cryptography are implemented.

[0009] Among them, the general Montgomery modular multiplication operation includes multiplication operation, the general Montgomery modular square operation includes square operation, and both operations also include the general Montgomery modular reduction operation.

[0010] The calculation steps are adjusted, including: adjusting the calculation steps of multiplication and squaring operations so that the two addition chains in the operation are executed in parallel; adjusting the calculation steps of Montgomery modulo reduction operation so that the previous round of addition operation in the loop calculation step is extended to the next round and executed in parallel with the next round of multiplication operation.

[0011] A further technical solution is that the multiplication operation is as follows: input two arrays A and B, each consisting of 4-element 64-bit unsigned numbers, and store them in memory; calculate the multiplication using a grouped product and a double-addition chain in parallel accumulation method; output data C, consisting of 8-element 64-bit unsigned numbers, and store it in the stack area or register of memory.

[0012] The calculation method using grouped multiplication and parallel accumulation of double addition chains is as follows: load two arrays A and B, perform grouped multiplication calculations according to the grouping logic of B0-B3 with A0-A1 and A2-A3 respectively, and perform parallel accumulation of the results of each group of multiplication calculations using double addition chains. After summarizing, the output array C is obtained.

[0013] A further technical solution is that the square operation is as follows: input an array A consisting of 4 elements and 64 bits of unsigned numbers, which is stored in memory; calculate using a method of full coverage of square terms and cross products; output data C consisting of 8 elements and 64 bits of unsigned numbers, which is stored in a register.

[0014] The calculation method using full coverage of squared terms and cross products is as follows: load the input array A, calculate the squared terms and cross products of each element in array A, and perform parallel accumulation of each product result using a chain of double additions. After summarizing, the output array C is obtained.

[0015] A further technical solution is that the general Montgomery modular reduction operation is as follows: the input is an array C output by multiplication or squaring operation, the modulus N and the pre-calculated value k0, and the output is an array D composed of 4 elements and 64 bits of unsigned numbers through four rounds of parallel loop calculation.

[0016] Each iteration includes calculating Y=(k0*Tm)mod The result is calculated by summing Y*N, where Tm is the key intermediate result of the previous loop; after four loops, the output array D is obtained by summing and conditional subtraction.

[0017] Secondly, the present invention also provides an electronic device.

[0018] An electronic device includes: a memory for storing executable instructions; and a processor for implementing the above-described fully pipelined general-purpose Montgomery modular multiplication method for the x86-64 platform when executing the executable instructions stored in the memory.

[0019] Thirdly, the present invention also provides a computer-readable storage medium.

[0020] A computer-readable storage medium storing executable instructions for causing a processor to execute the executable instructions to implement the above-described fully pipelined general-purpose Montgomery modular multiplication method for the x86-64 platform.

[0021] Fourthly, the present invention also provides a computer program product.

[0022] A computer program product includes executable instructions stored in a computer-readable storage medium; wherein, when a processor of an electronic device reads and executes the executable instructions from the computer-readable storage medium, it implements the aforementioned fully pipelined general-purpose Montgomery modular multiplication method for the x86-64 platform.

[0023] The above one or more technical solutions have the following beneficial effects:

[0024] 1. This invention proposes a fully pipelining general-purpose Montgomery modular multiplication method for the x86-64 platform. Utilizing the BMI2 and ADX instruction sets of the x86-64 platform, combined with its pipelining and multi-issue mechanism, and through reasonable allocation of registers and arrangement of computation steps, a general-purpose Montgomery modular multiplication operation for the x86-64 platform is achieved. This reduces data dependency, improves register utilization and instruction parallelism. Compared with existing methods, this invention has stronger versatility, better performance, and lower memory consumption.

[0025] 2. The general Montgomery modular multiplication method proposed in this invention includes multiplication and squaring operations. By adjusting the order of multiplication and squaring operations, the two addition chains in the operation do not interfere with each other. This ensures that the registers used by the adcx and adox instructions (two addition chains) do not conflict within the same clock cycle. The adcx and adox instructions do not need to wait for each other's operation results, enabling instruction parallelism. This reduces data dependency, improves register utilization and instruction parallelism, optimizes performance and versatility, and reduces memory usage.

[0026] 3. The general Montgomery modular multiplication method proposed in this invention also includes Montgomery modular reduction. A 256-bit Montgomery modular reduction requires four loop operations, each containing both multiplication and addition. Typically, each loop performs multiplication before addition, with the next loop starting only after the addition is complete. Unlike existing methods, this invention adjusts the operation order, extending the addition operation from one round to the next. Combined with the pipeline and multi-issue mechanism of the x86-64 platform, the addition operation from one round and the multiplication operation from the next can be executed in parallel. This reduces data dependency, improves register utilization and instruction parallelism, and enables operations applicable to any 256-bit elliptic curve. It effectively solves the problem in existing cryptographic algorithm libraries where Montgomery modular multiplication struggles to balance x86-64 platform compatibility with the universality of any 256-bit elliptic curve, resulting in insufficient performance and high memory consumption.

[0027] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0029] Figure 1 This is a schematic diagram of the multiplication operation in the general Montgomery modular multiplication operation proposed in the embodiments of the present invention;

[0030] Figure 2 This is a schematic diagram of the squaring operation in the general Montgomery modular squaring operation proposed in the embodiments of the present invention;

[0031] Figure 3 This is a schematic diagram of the general Montgomery modulo reduction operation proposed in the embodiments of the present invention. Detailed Implementation

[0032] It should be noted that the following detailed descriptions are exemplary and are intended only to describe specific embodiments and to provide further explanation of the invention, and are not intended to limit the scope of exemplary embodiments of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0033] Example 1

[0034] This embodiment provides a fully pipelined general Montgomery modular multiplication method for the x86-64 platform, including: utilizing the BMI2 and ADX instruction sets, combined with the pipelined and multi-issue mechanisms of the x86-64 platform, and by allocating registers and adjusting calculation steps, to realize general Montgomery modular multiplication and general Montgomery modular square operations for 256-bit elliptic curve cryptography algorithms.

[0035] The general Montgomery modular multiplication operation includes multiplication, the general Montgomery modular squaring operation includes squaring, and both operations also include the general Montgomery modular reduction operation. The calculation steps are adjusted, including: adjusting the calculation steps of multiplication and squaring operations so that the two addition chains in the operation are executed in parallel; adjusting the calculation steps of Montgomery modular reduction operation so that the previous round of addition in the loop calculation step is extended to the next round and executed in parallel with the next round of multiplication.

[0036] The method described in this embodiment essentially utilizes the BMI2 and ADX instruction sets to implement Montgomery modular multiplication and Montgomery modular squaring operations for 256-bit systems.

[0037] First, the calculation method proposed in this embodiment mainly uses instructions from the BMI2 and ADX instruction sets: mulx, adcx, and adox. Specifically, the mulx instruction is used to multiply two numbers and store the product in two registers, where the high 64 bits of the mulx calculation result are recorded as... The lower 64 bits are recorded as One multiplier is stored in memory or a register, while the other multiplier must be placed in the rcx register. The register where the product is stored can be specified. The adcx and adox instructions are used to add register values, that is, to add the value of one register to another. The difference is that once a carry occurs in the addition operation, the adcx instruction changes the CF flag from 0 to 1, while the adox instruction changes the OF flag from 0 to 1. Subsequent addition operations directly call and add the flags to perform the operation.

[0038] Secondly, for ease of explanation, this embodiment assigns aliases to the 64-bit registers rax, rbx, rcx, rdi, rsi, r8, r9, r10, r11, r12, r13, r14, r15, rbp, and rdx used in the x86-64 architecture: T0, T1, T2, T3, T4, T5, T6, T7, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, and Mult. During the operation, the 64-bit registers T0-T7, tmp0-tmp5, and Mult on the x86-64 platform are allocated. Mult is fixed as the rdx register, serving as the implicit multiplier for the mulx instruction. The remaining registers are used to store the calculated values, and the aliases of the remaining registers can be flexibly adjusted according to actual needs.

[0039] Then, the specific calculation process of multiplication, squaring, and modulo reduction will be explained in detail below.

[0040] (1) Multiplication operation

[0041] In the multiplication operation, the input consists of two arrays A={A0,A1,A2,A3} and B={B0,B1,B2,B3}, both composed of 64-bit unsigned numbers with 4 elements. Arrays A and B are stored in memory. The multiplication is performed using a combination of grouped multiplication and parallel accumulation via a chain of double additions. The output is C={C0,C1,C2,C3,C4,C5,C6,C7}, composed of 64-bit unsigned numbers with 8 elements. Each element of array C is stored in a register or in memory. Furthermore, C0 and C1 are stored on the stack, specifically 64 (%rsp) and 72 (%rsp), where rsp is the stack pointer. C2, C3, C4, C5, C6, and C7 are stored in registers T2, T3, T4, T5, T6, and T7, respectively.

[0042] The above calculation, employing grouped multiplication and parallel accumulation via a double-adder chain, proceeds as follows: Two arrays A and B are loaded. Grouped multiplication is performed using the logic of grouping B0-B3 with A0-A1 and A2-A3 respectively. The results of each group are then accumulated using a parallel double-adder chain. The summation yields the output array C, as shown below. Figure 1 As shown, the specific steps are as follows:

[0043] Step 1: Divide the data into groups 1 through 4. Load B0-B3 into the Mult register sequentially for each group. Calculate the product of each group with A0 and A1 using the mulx instruction, storing the high / low 64-bit results in designated registers. Then, use the adcx and adox instructions to perform parallel accumulation of the multiplication results for each group using two addition chains, storing the intermediate results in designated registers. The specific process is as follows:

[0044] Calculate B0*A0 and B0*A1, and store the lower 64 bits of the result of B0*A0 onto the stack as the result C0. That is: set the tmp1 register to zero, use movq (the movq instruction is used to copy data from the source location to the destination location) to load B0 into the Mult register, use mulx to multiply Mult with A0 and store the higher 64 bits of the result into the tmp3 register and the lower 64 bits into the T7 register, use mulx to multiply Mult with A1 and store the higher 64 bits of the result into the T4 register and the lower 64 bits into the T3 register, and store the value of the T7 register onto the stack at the stack address 64 (%rsp);

[0045] Calculate B1*A0 and B1*A1, calculate Let it be TC1, calculate This is denoted as TO1, where "TC" represents the result of addition performed by the adcx instruction, and "TO" represents the result of addition performed by the adox instruction. Specifically: movq loads B1 into the Mult register; mulx multiplies Mult by A0 and stores the high 64 bits of the result in the tmp4 register and the low 64 bits in the T7 register; mulx multiplies Mult by A1 and stores the high 64 bits of the result in the T5 register and the low 64 bits in the tmp0 register; adcx adds the value of T7 to the value of tmp3 and stores the result in the tmp3 register; adox adds the value of tmp0 to the value of T4 and stores the result in the T4 register.

[0046] Calculate B2*A0 and B2*A1, calculate Let it be TC2, calculate Let's call this TO2. That is: use movq to load B2 into the Mult register, use mulx to multiply Mult by A0 and store the high 64 bits of the result in the tmp5 register and the low 64 bits in the T7 register, use mulx to multiply Mult by A1 and store the high 64 bits of the result in the T1 register and the low 64 bits in the tmp0 register, use adcx to add the values ​​of T7 and tmp4 registers and store the result in the tmp4 register, and use adox to add the values ​​of tmp0 and T5 registers and store the result in the T5 register.

[0047] Calculate B3*A0, calculate Let it be TC3, calculate B3*A1, calculate... Let's call this TO3. That is: use movq to load B3 into the Mult register, use mulx to multiply Mult by A0 and store the high 64 bits of the result in the tmp0 register and the low 64 bits in the T7 register, use adcx to add the value of T7 to the value of the tmp5 register and store the result in the tmp5 register, use mulx to multiply Mult by A1 and store the high 64 bits of the result in the tmp2 register and the low 64 bits in the T7 register, use adox to add the value of T7 to the value of the T1 register and store the result in the T1 register.

[0048] Step 2: Perform a single-addition chain summation on the intermediate results of groups 1 to 4 to obtain a temporary summary result. In this embodiment, the intermediate results are summed by calculating... Let it be TC4, calculate Let it be TO4, calculate Let TC5 be the result of TO1 + TC2, let TC6 be the result of TO1 + TC2, store TC5 in the stack as the result of TO2 + TC3, let TC7 be the result of TO3 + TC4, let TC8 be the result of TO4 + 0, and let TC9 be the result of TO4 + 0. That is: use adcx to add the values ​​of tmp1 and tmp0 registers and store the result in tmp0 register; use adcx to add the values ​​of tmp1 and tmp2 registers and store the result in tmp2 register; use adcx to add the values ​​of tmp3 and T3 registers and store the result in T3 register; store the value of T3 register on the stack at stack address 72 (%rsp); use adcx to add the values ​​of tmp4 and T4 registers and store the result in T4 register; use adcx to add the values ​​of tmp5 and T5 registers and store the result in T5 register; use adcx to add the values ​​of tmp0 and T1 registers and store the result in T1 register; use adcx to add the values ​​of tmp1 and tmp2 registers and store the result in tmp2 register.

[0049] Step 3: Divide the data into groups 5 through 8. Load B0-B3 into the Mult register sequentially for each of the four groups. Calculate the product of each group with A2 and A3 using the mulx instruction, storing the high / low 64-bit results in designated registers. Then, use the adcx and adox instructions to perform parallel accumulation of the multiplication results for each group using two addition chains, storing the intermediate results in designated registers. The specific process is as follows:

[0050] Calculate B0*A2, calculate Let C2 be the value of B0*A3. Calculate... This is denoted as TO5. Specifically: use movq to load B0 into the Mult register; use mulx to multiply Mult by A2 and store the high 64 bits of the result in the tmp3 register and the low 64 bits in the T2 register; use adox to add the value of T4 to the value of T2 and store the result in the T2 register; use mulx to multiply Mult by A3 and store the high 64 bits of the result in the T4 register and the low 64 bits in the T3 register; use adox to add the value of T5 to the value of T3 and store the result in the T3 register.

[0051] Calculate B1*A2 and B1*A3, calculate Let it be TC10, calculate This is denoted as TO6. Specifically: use movq to load B1 into the Mult register; use mulx to multiply Mult by A2 and store the high 64 bits of the result in the tmp4 register and the low 64 bits in the T7 register; use mulx to multiply Mult by A3 and store the high 64 bits of the result in the T5 register and the low 64 bits in the tmp5 register; use adcx to add the values ​​of T7 and tmp3 registers and store the result in the tmp3 register; use adox to add the values ​​of tmp5 and T4 registers and store the result in the T4 register.

[0052] Calculate B2*A2 and B2*A3, calculate Let it be TC11, calculate This is denoted as TO7. Specifically: use movq to load B2 into the Mult register; use mulx to multiply Mult by A2 and store the high 64 bits of the result in the tmp5 register and the low 64 bits in the T7 register; use mulx to multiply Mult by A3 and store the high 64 bits of the result in the tmp1 register and the low 64 bits in the tmp0 register; use adcx to add the values ​​of T7 and tmp4 registers and store the result in the tmp4 register; use adox to add the values ​​of tmp0 and T5 registers and store the result in the T5 register.

[0053] Calculate B3*A2, calculate Let it be TC12, calculate B3*A3, calculate... Let it be TO8, calculate Let it be TC13, calculate This is denoted as TO9. Specifically: Use movq to load B3 into the Mult register; use mulx to multiply Mult by A2 and store the high 64 bits of the result in register tmp0 and the low 64 bits in register T7; use adcx to add the value of register T7 to the value of register tmp5 and store the result in register tmp5; use mulx to multiply Mult by A3 and store the high 64 bits of the result in register T0 and the low 64 bits in register T6; use adox to add the value of register tmp1 to the value of register T6 and store the result in register T6; set register T7 to zero; use adcx to add the value of register T7 to the value of register tmp0 and store the result in register tmp0; use adox to add the value of register T7 to the value of register T0 and store the result in register T0.

[0054] Step 4: Perform single-addition chain accumulation on the intermediate results of groups 5 to 8, then integrate the temporary summary results, determine the value of each element in the 8-element array C, store C0 and C1 in array C into stack area 64 (%rsp) and 72 (%rsp) respectively, and store C2-C7 into registers T2-T7 respectively to form the final output.

[0055] The final result is obtained by accumulating the results in step 4. Specifically, the calculation of TO5+TC10 is recorded as C3, the calculation of TO6+TC11 is recorded as TC14, the calculation of TC8+TC14 is recorded as C4, the calculation of TO7+TC12 is recorded as TC15, the calculation of TC9+TC15 is recorded as C5, the calculation of TO8+TC13 is recorded as TC16, the calculation of TC16+0 is recorded as C6, the calculation of TO9+0 is recorded as TC17, and the calculation of TC17+0 is recorded as C7. That is: use adcx to add the values ​​of tmp3 and T3 registers and store the result in T3 register; use adcx to add the values ​​of tmp4 and T4 registers and store the result in T4 register; use adox to add the values ​​of T1 and T4 registers and store the result in T4 register; use adcx to add the values ​​of tmp5 and T5 registers and store the result in T5 register; use adox to add the values ​​of tmp2 and T5 registers and store the result in T5 register; use adcx to add the values ​​of tmp0 and T6 registers and store the result in T6 register; use adox to add the values ​​of T7 and T6 registers and store the result in T6 register; use adcx to add the values ​​of T7 and T0 registers and store the result in T0 register; use adox to add the values ​​of T0 and T7 registers and store the result in T7 register.

[0056] Next, all calculation results are summarized to determine the values ​​of each element in the 8-element array C, resulting in the multiplication result C={C0,C1,C2,C3,C4,C5,C6,C7}. C0 and C1 are stored on the stack, i.e., 64 (%rsp) and 72 (%rsp), while C2, C3, C4, C5, C6, and C7 are stored in registers T2, T3, T4, T5, T6, and T7, respectively, forming the final output.

[0057] In the x64 platform, pipelined and multiple-issue mechanisms allow multiple instructions to be issued within the same cycle. If there are no data dependencies between instructions, multiple instructions can be executed simultaneously; otherwise, the next instruction must wait for the previous instruction to complete. Traditional multiplication operations have data dependencies between instructions, which prevents the full utilization of the pipelined and multiple-issue mechanisms. This embodiment leverages this performance characteristic of the x64 platform, reconstructing the product calculation order and parallel accumulation of the double-adder chain through the aforementioned computational process, achieving a performance breakthrough.

[0058] (2) Squaring operations

[0059] In the square operation, the input is an array A = {A0, A1, A2, A3} consisting of 4 elements and 64 bits of unsigned numbers. The array A is stored in memory. The calculation is performed by grouping multiplication and parallel accumulation of double addition chains. The output is data C = {C0, C1, C2, C3, C4, C5, C6, C7} consisting of 8 elements and 64 bits of unsigned numbers. Each element of array C is stored in a register, that is, C0, C1, C2, C3, C4, C5, C6, and C7 are stored in registers T0, T1, T2, T3, T4, T5, T6, and T7, respectively.

[0060] The calculation employs a full coverage approach using squared terms and cross products, as follows: Input array A is loaded, the squared terms and cross products of each element in array A are calculated, and the results of each product are accumulated in parallel using a chain of double additions. The summation yields the output array C, as shown below. Figure 2 As shown, the specific steps are as follows:

[0061] Step 1: Data Loading and Initial Product Calculation. Load A0-A3 of the input array A from memory into the specified registers (i.e., Mult, T3, tmp0, T6 registers), and copy A0 to the specified registers. Use the mulx instruction to calculate the product of A0 with A1 and A3 respectively, and store the high / low 64-bit results into the specified registers (i.e., tmp2, tmp1, T5, T4 registers).

[0062] Specifically, set the tmp5 register to zero, use movq to load A0 into the Mult register, use movq to load A1 into the T3 register, use movq to load A2 into the tmp0 register, use movq to load A3 into the T6 register, and use movq to copy the value of the Mult register into the T0 register; use mulx to multiply Mult and T3 and store the high 64 bits of the result into the tmp2 register and the low 64 bits into the tmp1 register; use mulx to multiply Mult and T6 and store the high 64 bits of the result into the T5 register and the low 64 bits into the T4 register.

[0063] Step 2: Calculation of the full product of squared and cross terms. The full product calculation sequentially copies A2, A3, A0, A1, and A3 to the Mult register. Multiple product calculations are performed using the mulx instruction, including the product of A2 and A0-A3, the product of A3 and A1, and the product of the squared terms of A0, A1, and A3. The high / low 64-bit result of each product is stored in a designated register. During the multiple product calculations, the adcx and adox instructions are used to perform parallel accumulation of the product results of all squared and cross terms using two addition chains. During the accumulation process, intermediate values ​​are gradually integrated and the accumulated data in the register is updated. The specific process is as follows:

[0064] Copy A2 to the Mult register, use the mulx instruction to calculate the product of A2 with A1, A3, A0, and A2, store the corresponding high / low 64-bit result in the specified register, and accumulate the multiplication results except for A2*A2. That is: calculate A2*A1, calculate... Let it be TC1, calculate Let it be TC2. Calculate A2*A3 and A2*A0. Let it be TC3, calculate Let it be TO1, calculate Let it be TC4, calculate Let this be TO2. Calculate A2*A2. Specifically: Use `movq` to copy the value of register tmp0 into register Mult; use `mulx` to multiply Mult by T3 and store the high 64 bits of the result in register tmp3 and the low 64 bits in register T7; use `adcx` to add the values ​​of registers T4 and T7 and store the result in register T7; use `adcx` to add the values ​​of registers T5 and tmp3 and store the result in register tmp3; use `mulx` to multiply Mult by T6 and store the high 64 bits of the result in register tmp4 and the low 64 bits in register tmp0; use `mulx` to multiply Mult by T0 and store the result... The high 64 bits are stored in register T1 and the low 64 bits are stored in register T2. The values ​​of registers Tmp5 and Tmp0 are added using adcx and the result is stored in register Tmp0. The values ​​of registers T2 and Tmp2 are added using adox and the result is stored in register Tmp2. The values ​​of registers Tmp5 and Tmp4 are added using adcx and the result is stored in register Tmp4. The values ​​of registers T1 and T7 are added using adox and the result is stored in register T7. The Mult is multiplied by Mult and the high 64 bits of the result are stored in register T5 and the low 64 bits are stored in register T4.

[0065] Copy A3 to the Mult register, use the mulx instruction to calculate the product of A3 and A1, store the corresponding high / low 64-bit result in the specified register, and accumulate the multiplication result. That is: calculate A3*A1, calculate... Let it be TO3, calculate This is denoted as TC5. Specifically: use movq to copy the value of register T6 into register Mult, use mulx to multiply Mult by T3 and store the high 64 bits of the result into register T2 and the low 64 bits into register Mult, use adox to add Mult to the value of register tmp3 and store the result into register tmp3, and use adcx to add the values ​​of registers tmp1 and tmp1 and store the result into register tmp1.

[0066] Copy A0 to the Mult register, use the mulx instruction to calculate the product of A0 and A0, store the corresponding high / low 64-bit result in the specified register, and accumulate the multiplication result. That is: calculate A0 * A0, calculate... Let's denote it as TO4, and calculate TO1+TO1 as TC6. Specifically: use movq to copy the value of register T0 into register Mult, use mulx to multiply Mult and store the high 64 bits of the result into register T1 and the low 64 bits into register T0, use adox to add the value of register T2 to register tmp0 and store the result into register tmp0, and use adcx to add the values ​​of register tmp2 to register tmp2 and store the result into register tmp2.

[0067] Copy A1 to the Mult register, use the mulx instruction to calculate the product of A1 and A1, store the corresponding high / low 64-bit result in the specified register, and accumulate the multiplication result. That is: calculate A1*A1, calculate TC4+0 and record it as TO5, calculate TO2+TO2 and record it as TC7, calculate... Let it be C1, calculate TO3+TO3 and record it as TC8, calculate TO4+TO4 and record it as TC9, calculate... Let it be C2, calculate Let's denote it as C3. Specifically: use movq to copy the value of register T0 into register Mult; use mulx to multiply Mult and store the high 64 bits of the result into register T3 and the low 64 bits into register T2; use adox to add the values ​​of registers tmp5 and tmp4 and store the result into register tmp4; use adcx to add the values ​​of registers T7 and T7 and store the result into register T7; use adox to add the values ​​of registers tmp1 and T1 and store the result into register T1; use adcx to add the values ​​of registers tmp3 and tmp3 and store the result into register tmp3; use adcx to add the values ​​of registers tmp0 and tmp0 and store the result into register tmp0; use adox to add the values ​​of registers tmp2 and T2 and store the result into register T2; use adox to add the values ​​of registers T7 and T3 and store the result into register T3.

[0068] Copy A3 to the Mult register, use the mulx instruction to calculate the product of A3 and A3, store the corresponding high / low 64-bit result in the specified register, and accumulate the multiplication result. That is: calculate A3*A3, calculate TO5+TO5 (denoted as TC10), calculate... Let it be C4, calculate Let it be TC11, calculate Let it be C5, calculate Let C6 be the value of the T6 register and C7 be the value of the TC11+0 register. Specifically: use `movq` to copy the value of the T6 register into the Mult register; use `mulx` to multiply Mult by Mult and store the high 64 bits and low 64 bits of the result in the T7 register; use `adcx` to add the value of the T6 register to the tmp4 register and store the result in the tmp4 register; use `adox` to add the value of the T4 register to the tmp3 register and store the result in the T4 register; use `adcx` to add the value of the T7 register to the tmp5 register and store the result in the T7 register; use `adox` to add the value of the T5 register to the tmp0 register and store the result in the T5 register; use `adox` to add the value of the T6 register to the tmp4 register and store the result in the T6 register; use `adox` to add the value of the T7 register to the tmp5 register and store the result in the T7 register.

[0069] Step 3: Result Integration. Integrate all accumulated results and summarize the values ​​of each element in the 8-element array C to obtain the squared result C={C0,C1,C2,C3,C4,C5,C6,C7}. Each element C0,C1,C2,C3,C4,C5,C6,C7 is stored in registers T0, T1, T2, T3, T4, T5, T6, and T7 respectively, forming the final output.

[0070] Considering that in the existing 256-bit Montgomery modular squaring operation, the accumulation of all product terms needs to be performed serially, resulting in severe data dependency, the squaring operation proposed in this embodiment, with the help of the pipeline and multiple-issue mechanism in the x86-64 architecture, reconstructs the product calculation order and the parallel accumulation of the double-adder chain through the above operation process, achieving a performance breakthrough.

[0071] (3) General Montgomery Modular Reduction Operation

[0072] In the general Montgomery modular reduction operation, the input is the result of the above multiplication or squaring operation, i.e., the array C={C0,C1,C2,C3,C4,C5,C6,C7}, the modulus N={N0,N1,N2,N3} stored in stack 0 (%rsp) in memory, and the pre-calculated value k0 stored in stack 32 (%rsp). Through four rounds of parallel loop calculation, the output is an array D={D0,D1,D2,D3} consisting of 4 elements and 64 bits of unsigned numbers. For multiplication, C0, C1, C2, C3, C4, C5, C6, and C7 are stored in memory stack areas 64 (%rsp) and 72 (%rsp) and registers T2, T3, T4, T5, T6, and T7, respectively. For squaring, C0, C1, C2, C3, C4, C5, C6, and C7 are stored in registers T0, T1, T2, T3, T4, T5, T6, and T7, respectively. This modulo-subtraction operation mainly includes four loop steps, where each loop includes calculating Y = (k0 * Tm) modulo... The result is calculated by summing Y*N, where Tm is the key intermediate result of the previous loop; after four loops, the output array D is obtained by summing and conditional subtraction.

[0073] like Figure 3 As shown, the specific steps of the general Montgomery modulo reduction operation are as follows:

[0074] Step 1: Perform the first round of modulo reduction calculation, which involves loading the pre-calculated value k0 into the Mult register and calculating Y1 = (k0 * C0) modulo. Y1 is stored in the Mult register, where C0 is the initial key result. The mulx instruction is used to calculate the product of Y1 and N0-N3 of the modulus N. Combined with the adcx and adox instructions, the first round of parallel accumulation is performed to obtain the intermediate result of this round of calculation. That is: calculate Y1 = (k0 * C0) modulo N. Calculate Y1*N0, calculate Let it be TC1, calculate Y1*N1, calculate Y1*N2, calculate... Let it be TC2, calculate Let it be TO1, and calculate Y1*N3.

[0075] Specifically, set the tmp5 register to zero, load k0 into the Mult register using movq, multiply Mult by T0 using mulx and store the high 64 bits and low 64 bits of the result into the tmp1 register, and the low 64 bits into the Mult register. Multiply Mult by N0 using mulx and store the high 64 bits and low 64 bits of the result into the tmp1 register, and the low 64 bits into the tmp0 register. Add the value in T0 (or 64(%rsp)) to the value in the tmp0 register using adcx and store the result into the tmp0 register. If the previous step was a multiplication operation, the result is 64(%rsp); if the previous step was a squaring operation, the result is T0. Multiply Mult by N1 using mulx and store the high 64 bits and low 64 bits of the result into the tmp0 register. 4 bits are stored in register T0, and the lower 64 bits are stored in register tmp4. Mult is multiplied by N2 using mulx, and the higher 64 bits of the result are stored in register tmp3, and the lower 64 bits are stored in register tmp2. T1 (or 72(%rsp)) is added to the value in register tmp1 using adcx, and the result is stored in register tmp1. If the previous step was a multiplication operation, the result is 72(%rsp); if the previous step was a squaring operation, the result is T1. Adox is added to the value in register tmp4 and the value in register tmp1, and the result is stored in register tmp1. Mult is multiplied by N3 using mulx, and the higher 64 bits of the result are stored in register tmp4, and the lower 64 bits are stored in register tmp0.

[0076] Step 2: Perform the second to fourth rounds of iterative calculations sequentially. In each round, first calculate Y = (k0 * key intermediate result of the previous round) modulo 0 based on the key intermediate result of the previous round. Then, calculate the product of Y and the modulus N (N0-N3). Use the `adcx` instruction to accumulate the residual result from the previous addition and the current product value. Use the `adox` instruction to accumulate the corresponding results in parallel, achieving parallel execution of the previous addition and the current multiplication, and obtaining the corresponding intermediate results. The specific process is as follows:

[0077] Perform the second iteration of modulo reduction, and calculate... Let TC3 be the value of C2 + TC3, let TO2 be the value of C2 + TC3, and calculate Y2 = (k0 * TO1) modulo TC3. ,calculate Let TC4 be the value of C3 + TC4, let TO3 be the value of C3 + TC4, calculate Y2 * N0, and calculate... Let TC5 be the value of C4 + TC5, let TC5 be the value of TO4, calculate Y2 * N1, calculate C5 + 0, let TC5 be the value of TO5, calculate Y2 * N2, and calculate... Let TC6 be the value of C6+0, let TO6 be the value of C6+0, calculate Y2*N3, let TO7 be the value of C7+0, and calculate... Let TC7 be the value of the first register, and let TO2 + TC7 be the value of the second register, denoted as TO8. Specifically, movq loads k0 into the Mult register; adcx adds the values ​​of T2 and tmp2 registers and stores the result in tmp2 register; adox adds the values ​​of tmp2 and T2 registers and stores the result in T2 register; mulx multiplies Mult by tmp1 and stores the high 64 bits of the result in T1 register and the low 64 bits in Mult register; adcx adds the values ​​of tmp0 and tmp3 registers and stores the result in tmp3 register; adox adds the values ​​of tmp3 and T3 registers and stores the result in T3 register; mulx multiplies Mult by N0 and stores the high 64 bits of the result in tmp2 register and the low 64 bits in tmp0 register; adcx adds the values ​​of tmp5 and tmp4 registers and stores the result in tmp4 register; adox adds the values ​​of tmp4 and T4 registers and stores the result in T4 register; mulx... Multiply Mult by N1 and store the high 64 bits of the result in register T1 and the low 64 bits in register T0. Use adox to add tmp5 to the value in register T5 and store the result in register T5. Use mulx to multiply Mult by N2 and store the high 64 bits of the result in register Tmp3 and the low 64 bits in register Tmp4. Use adcx to add tmp0 to the value in register Tmp1 and store the result in register Tmp1. Use adox to add tmp5 to the value in register T6 and store the result in register T6. Use mulx to multiply Mult by N3 and store the high 64 bits of the result in register Tmp1 and the low 64 bits in register Tmp0. Use adox to add tmp5 to the value in register T7 and store the result in register T7. Use adcx to add tmp2 to the value in register T0 and store the result in register T0. Use adox to add the values ​​in register T0 and T2 and store the result in register T2.

[0078] Perform the third iteration of the modulo-decimation loop and calculate... Let TC8 be the value of TO3 + TC8, let TC9 be the value of TO3, and let Y3 = (k0 * TO8) mod TC8. ,calculate Let it be TC9, calculate TO4 + TC9 and let it be TO10, calculate Y3 * N0, calculate... Let TC10 be the value, calculate TO5 + TC10 and let it be TO11, calculate Y3 * N1, calculate TO6 + 0 and let it be TO12, calculate Y3 * N2, calculate... Let it be TC11, calculate TO7+0 and let it be TO13, calculate Y3*N3, calculate... Let TC12 be the value, and let TO9 + TC12 be the value, denoted as TO14. Specifically, movq loads k0 into the Mult register; adcx adds tmp4 to the value in register T1 and stores the result in register T1; adox adds the values ​​in registers T1 and T3 and stores the result in register T3; mulx multiplies Mult by T2 and stores the high 64 bits of the result in register T1 and the low 64 bits in register Mult; adcx adds tmp0 to the value in register Tmp3 and stores the result in register Tmp3; adox adds tmp3 to the value in register T4 and stores the result in register T4; mulx multiplies Mult by N0 and stores the high 64 bits of the result in register Tmp4 and the low 64 bits in register Tmp0; adcx adds tmp5 to the value in register Tmp1 and stores the result in register Tmp1; adox adds tmp1 to the value in register T5 and stores the result in register T1. The result is stored in register T5. Mult is multiplied by N1 using mulx, and the high 64 bits of the result are stored in register T1, and the low 64 bits are stored in register T0. Adox is used to add the value of tmp5 to the value of register T6 and the result is stored in register T6. Mult is multiplied by N2 using mulx, and the high 64 bits of the result are stored in register tmp3, and the low 64 bits are stored in register tmp2. Adox is used to add the value of tmp0 to the value of register T2 and the result is stored in register T2. Adox is used to add the value of tmp5 to the value of register T7 and the result is stored in register T7. Mult is multiplied by N3 using mulx, and the high 64 bits of the result are stored in register tmp1, and the low 64 bits are stored in register tmp0. Adox is used to add the value of tmp4 to the value of register T0 and the result is stored in register T0. Adox is used to add the values ​​of T0 and T3 and the result is stored in register T3.

[0079] Perform the fourth iteration of the modulo-subtraction loop and calculate... Let TC13 be the value of TO10 + TC13, let TC13 be the value of TO15, and calculate Y4 = (k0 * TO14) mod TC13. ,calculate Let it be TC14, calculate TO11 + TC14 and let it be TO16, calculate Y4 * N0, calculate... Let it be TC15. Calculate TO12 + TC15, let it be TO17. Calculate Y4 * N1. Calculate TO13 + 0, let it be TO18. Calculate Y4 * N2. Let's denote it as TC16 and calculate Y4*N3. Specifically, use movq to load k0 into the Mult register, use adcx to add the value of tmp2 to the value of T1 register and store the result in T1 register, use adox to add the value of T1 to the value of T4 register and store the result in T4 register, use mulx to multiply Mult by T3 and store the high 64 bits of the result in T1 register and the low 64 bits in Mult register, use adcx to add the value of tmp0 to the value of tmp3 register and store the result in tmp3 register, use adox to add the value of tmp3 to the value of T5 register and store the result in T5 register, use mulx to multiply Mult by N0 and store the high 64 bits of the result in tmp4 register and the low 64 bits in tmp0 register, use adcx to multiply tmp5 by N0... The values ​​in register tmp1 are added together and the result is stored in register tmp1. ADOX is used to add the values ​​in register tmp1 and T6 and the result is stored in register T6. MULX is used to multiply Mult and N1 and the high 64 bits of the result are stored in register T1 and the low 64 bits are stored in register T2. ADOX is used to add the values ​​in register tmp5 and T7 and the result is stored in register T7. MULX is used to multiply Mult and N2 and the high 64 bits of the result are stored in register tmp3 and the low 64 bits are stored in register tmp2. ADCX is used to add the values ​​in register tmp0 and T3 and the result is stored in register T3. MULX is used to multiply Mult and N3 and the high 64 bits of the result are stored in register tmp1 and the low 64 bits are stored in register tmp0.

[0080] Step 3: Summarizing and Copying Intermediate Results. Using the `adcx` and `adox` instructions, accumulate all intermediate results from the four loops, update the values ​​stored in registers T4-T7, and then copy the results stored in registers T4-T7 to designated registers (i.e., registers T2, T1, tmp3, and tmp1), retaining the original accumulated results. In other words: Calculate... Let it be TC17, calculate TO15 + TC17 and let it be D0, calculate... Let it be TC18. Calculate TO16 + TC18, denoted as D1. Calculate... Let it be TC19. Calculate TO17 + TC19, denoted as D2. Calculate... Let TC20 be the result, and let D3 be the result of TC20 + TO18. D0, D1, D2, and D3 are stored in registers T4, T5, T6, and T7 respectively. Then, the results in registers T4-T7 are copied to registers T2, T1, tmp3, and tmp1 respectively, and the original accumulated result is retained.

[0081] Specifically, the intermediate results are accumulated and stored in registers T4, T5, T6, and T7 respectively. The results are then copied to registers T2, T1, tmp3, and tmp1 respectively. This includes: using `adcx` to add the values ​​of registers T4 and T2 and storing the result in register T2; using `adox` to add the values ​​of registers T2 and T4 and storing the result in register T4; using `movq` to copy the value of register T4 to register T2; using `adcx` to add the values ​​of registers T1 and T1 and storing the result in register T1; using `adox` to add the values ​​of registers T1 and T5 and storing the result in register T5; and using `movq` to copy the value of register T5 to register T2. Copy the value to register T1. Use adcx to add the values ​​of registers tmp0 and tmp3 and store the result in register tmp3. Use adox to add the values ​​of registers tmp3 and T6 and store the result in register T6. Use movq to copy the value of register T6 to register tmp3. Use adcx to add the values ​​of registers tmp5 and tmp1 and store the result in register tmp1. Use adox to add the values ​​of registers tmp1 and T7 and store the result in register T7. Use movq to copy the value of register T7 to register tmp1. Use adox to add the values ​​of registers tmp5 and T3 and store the result in register T3.

[0082] Step 4: Perform the subtraction operation. Use the `subq` and `sbbq` instructions to perform the subtraction operation, subtracting N0-N3 of the modulus N from the accumulated result in registers T4-T7 respectively. The subtraction result affects the CF flag. Specifically, the `sub` instruction performs the subtraction operation without carry, i.e., calculating a – b; while the `sbb` instruction performs the subtraction operation with carry, i.e., calculating ab – CF, where CF is equal to 0 or 1.

[0083] Specifically, subtract the modulus N from the values ​​in the results T4, T5, T6, and T7. The subtraction result affects the flag bit CF, including: using subq to calculate T4 minus N0 and storing the result in T4; using sbbq to calculate T5 minus N1 and storing the result in T5; using sbbq to calculate T6 minus N2 and storing the result in T6; using sbbq to calculate T7 minus N3 and storing the result in T7; and using sbbq to calculate T3 minus 0 and storing the result in T3.

[0084] Step 5: Conditional Copy and Result Output. A conditional copy operation is performed based on the CF flag. If the CF flag is 1, indicating a negative subtraction result, the cmovc instruction is used to copy the original accumulated result from the specified registers (T2, T1, tmp3, and tmp1 registers) to registers T4-T7. The values ​​in registers T4-T7 are the 4-element output array D, completing the modulo subtraction operation.

[0085] Specifically, a conditional copy operation is performed based on the CF flag. If the CF flag is 1, the values ​​in registers T2, T1, tmp3, and tmp1 are copied to registers T4, T5, T6, and T7. This includes: using the cmovc instruction to perform a conditional copy, assigning the value of register T2 to register T4; using cmovc to perform a conditional copy, assigning the value of register T1 to register T5; using cmovc to perform a conditional copy, assigning the value of register tmp3 to register T6; and using cmovc to perform a conditional copy, assigning the value of register tmp1 to register T7. Thus, the result D = {D0, D1, D2, D3} obtained from the modulo reduction is stored in registers T4, T5, T6, and T7 respectively. The cmovc instruction, when the CF flag is 1, copies the source operand to the destination register; otherwise, the destination register remains unchanged.

[0086] Traditional 256-bit Montgomery modulo reduction also requires four loops, each containing multiplication and addition operations. The addition operation needs to sum the results of the multiplication operations, meaning the addition operation must wait for the multiplication results before proceeding to the next loop. Unlike the traditional approach, this embodiment extends the addition operation from one round to the next. Combined with the pipeline and multi-issue mechanism of the x86-64 platform, the addition operation in one round and the multiplication operation in the next round can be executed in parallel. This reduces data dependencies, improves register utilization and instruction parallelism, optimizes performance and versatility, and reduces memory usage.

[0087] Example 2

[0088] This embodiment provides an electronic device, including: a memory for storing executable instructions; and a processor for executing the executable instructions stored in the memory to implement the method provided in this embodiment.

[0089] Example 3

[0090] This embodiment also provides a computer-readable storage medium storing executable instructions, which, when executed by a processor, will cause the processor to execute the method described above in this embodiment.

[0091] Example 4

[0092] This embodiment provides a computer program product including executable instructions, which are computer instructions; the executable instructions are stored in a computer-readable storage medium. When the processor of an electronic device reads the executable instructions from the computer-readable storage medium and executes the executable instructions, the electronic device performs the method described in this embodiment.

[0093] The steps and methods involved in Embodiments 2 to 4 above correspond to those in Embodiment 1. For specific implementation details, please refer to the relevant description section of Embodiment 1. The term "computer-readable storage medium" should be understood as a single medium or multiple media including one or more instruction sets; it should also be understood as including any medium capable of storing, encoding, or carrying an instruction set for execution by a processor and enabling the processor to perform any of the methods in this invention.

[0094] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.

[0095] The above description is only a preferred embodiment of the present invention. Although the specific implementation of the present invention has been described in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that, based on the technical solution of the present invention, various modifications or variations that can be made by those skilled in the art without creative effort are still within the scope of protection of the present invention.

Claims

1. A fully pipelined, general-purpose Montgomery modular multiplication method for the x86-64 platform, characterized in that, include: By utilizing the BMI2 and ADX instruction sets, combined with the pipeline and multiple issue mechanism of the x86-64 platform, and by allocating registers and adjusting computation steps, a general Montgomery modular multiplication and a general Montgomery modular square operation for 256-bit elliptic curve cryptography are implemented. Among them, the general Montgomery modular multiplication operation includes multiplication operation, the general Montgomery modular square operation includes square operation, and both operations also include the general Montgomery modular reduction operation. The calculation steps are adjusted, including: adjusting the calculation steps of multiplication and squaring operations so that the two addition chains in the operation are executed in parallel; adjusting the calculation steps of Montgomery modulo reduction operation so that the previous round of addition operation in the loop calculation step is extended to the next round and executed in parallel with the next round of multiplication operation. The multiplication operation is as follows: input two arrays A and B, each consisting of 4-element 64-bit unsigned numbers, and store them in memory. Calculate the multiplication using a grouped product and a double-addition chain in parallel accumulation method. Output data C, consisting of 8-element 64-bit unsigned numbers, and store it in the stack area or register of memory. The calculation method using grouped multiplication and parallel accumulation of double addition chains is as follows: load two arrays A and B, perform grouped multiplication calculations according to the grouping logic of B0-B3 with A0-A1 and A2-A3 respectively, and perform parallel accumulation of the results of each group of multiplication calculations using double addition chains. After summarizing, the output array C is obtained. The multiplication operation process includes: Divide the data into groups 1 to 4. Load B0-B3 into the Mult register in sequence for each group. Use the mulx instruction to calculate the product with A0 and A1 respectively. Store the high / low 64-bit results in the specified register. Use the adcx and adox instructions to perform parallel accumulation of the multiplication results of each group using two addition chains. Store the intermediate results in the specified register. The intermediate results of groups 1 to 4 are summed using a single addition chain to obtain a temporary summary result; Divide the data into groups 5 to 8. Load B0-B3 into the Mult register in sequence for each of the four groups. Use the mulx instruction to calculate the product with A2 and A3 respectively. Store the high / low 64-bit results in the specified register. Use the adcx and adox instructions to perform parallel accumulation of the multiplication results of each group using two addition chains. Store the intermediate results in the specified register. The intermediate results of groups 5 to 8 are accumulated by single addition chain, and then the temporary summary results are integrated to determine the value of each element in the 8-element array C. C0 and C1 in array C are stored in stack area 64 (%rsp) and 72 (%rsp) respectively, and C2-C7 are stored in registers T2-T7 respectively to form the final output. The square operation is as follows: input an array A consisting of 4 elements and 64 bits of unsigned numbers, which is stored in memory; calculate using a method of full coverage of square terms and cross products; output data C consisting of 8 elements and 64 bits of unsigned numbers, which is stored in a register. The calculation method using full coverage of square terms and cross products is as follows: load the input array A, calculate the square term and cross product of each element in array A, and perform parallel accumulation of each product result using a chain of double additions. After summarizing, the output array C is obtained. The squaring operation process includes: Load A0-A3 of the input array A from memory into the specified register, and copy A0 to the specified register. Use the mulx instruction to calculate the product of A0 with A1 and A3 respectively, and store the high / low 64-bit result into the specified register. The full product calculation sequentially copies A2, A3, A0, A1, and A3 to the Mult register. Multiple product calculations are performed using the mulx instruction, including the product of A2 and A0-A3, the product of A3 and A1, and the product of the squared terms of A0, A1, and A3. The high / low 64-bit result of each product is stored in a designated register. During the multiple product calculations, the adcx and adox instructions are used to perform parallel accumulation of the product results of all squared terms and cross terms using two addition chains. During the accumulation process, intermediate values ​​are gradually integrated and the accumulated data in the register is updated. Integrate all the accumulated results and summarize the values ​​of each element in the 8-element array C. Store C0-C7 in array C into registers T0-T7 respectively to form the final output. The general Montgomery modular reduction operation is as follows: the input is an array C output by multiplication or squaring operation, the modulus N and the pre-calculated value k0, and the output is an array D consisting of 4 elements and 64 bits of unsigned numbers through four rounds of parallel loop calculation. Each iteration includes calculating Y=(k0*Tm)mod The result is calculated by summing Y*N, where Tm is the key intermediate result of the previous loop; after four loops, the output array D is obtained by summing and conditional subtraction. The general Montgomery modulo reduction operation process includes: The first round of loop calculation is performed as follows: load the pre-calculated value k0 into the Mult register, and calculate Y1 = (k0 * C0) modulo 1. The mulx instruction is used to calculate the product of Y1 and N0-N3 in the modulus N respectively. The adcx and adox instructions are combined to perform the first round of parallel accumulation to obtain the intermediate result of this round of calculation. The second to fourth rounds of iterative calculations are performed sequentially. In each round, Y=(k0*Tm)mod is calculated based on the key intermediate results of the previous round. Then calculate the product of Y and the modulus N from N0 to N3, use the adcx instruction to accumulate the residual result of the previous addition and the product value of the current round, and use the adox instruction to accumulate the corresponding result in parallel, so as to realize the parallel execution of the previous round of addition and the current round of multiplication and obtain the corresponding intermediate result. The adcx and adox instructions are used to accumulate all the intermediate results of the four loops, update the values ​​stored in registers T4-T7, and then copy the results stored in registers T4-T7 to the specified registers, retaining the original accumulated results. The subq and sbbq instructions are used to perform subtraction operations, subtracting N0-N3 of the modulus N from the accumulated results in registers T4-T7 respectively. The subtraction results affect the CF flag. The conditional copy operation is performed based on the CF flag. If the CF flag is 1, the cmovc instruction is used to copy the original accumulated result in the specified register to the T4-T7 registers. The value in the T4-T7 registers is the 4-element output array D, completing the modulo reduction operation.

2. An electronic device, characterized in that, include: Memory, used to store executable instructions; The processor, when executing executable instructions stored in the memory, implements the fully pipelined general-purpose Montgomery modular multiplication method for the x86-64 platform as described in claim 1.

3. A computer-readable storage medium, characterized in that, It stores executable instructions that, when executed by the processor, implement the fully pipelined general-purpose Montgomery modular multiplication method for the x86-64 platform as described in claim 1.

4. A computer program product, characterized in that, The computer program product includes executable instructions stored in a computer-readable storage medium; When the processor of the electronic device reads the executable instructions from the computer-readable storage medium and executes the executable instructions, it implements the fully pipelined general Montgomery modular multiplication method for the x86-64 platform as described in claim 1.

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