Dual-conversion gain reading circuit, reading method and image sensor

Abstract

The invention provides a dual-conversion gain reading circuit, a reading method and an image sensor, and the circuit comprises a comparison module which carries out the pre-comparison of a high-gain photosensitive signal and a ramp signal, so as to obtain a pre-comparison result, comparing the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal and the low-gain photosensitive signal with a ramp signal to output corresponding comparison signals; and the counting module selects a counting mode according to the pre-comparison result to count the comparison signals so as to output data signals. A comparison module is used for pre-comparing a high-gain photosensitive signal with a ramp signal, and a counting module is used for selecting a corresponding counting mode for counting quantization according to a pre-comparison result, so that the corresponding counting mode can be adaptively selected according to a voltage difference value between a high-gain reset signal and the high-gain photosensitive signal; therefore, the dynamic power consumption of the counting module is effectively reduced, the overall power consumption of the reading circuit is reduced, and the problem that an existing dual-conversion gain reading circuit is large in dynamic power consumption is solved.

Description

Technical Field

[0001] This invention relates to the field of image signal processing technology, and in particular to a dual-conversion gain readout circuit and readout method, and an image sensor. Background Technology

[0002] With the rapid development of image sensor technology, there is a growing demand for image sensors with higher dynamic range. Among these, DCG (Dual Conversion Gain) pixel structures are widely used in HDR (High Dynamic Range) scenarios due to their high image quality and simple circuit structure.

[0003] To facilitate the readout of pixel signals from the DCG pixel structure, a column-parallel SS ADC (Single-Slope Analog-to-Digital Converter) architecture is typically employed. However, SS ADCs have low power efficiency, and the dynamic power consumption of their internal counters increases with the amplitude of the input signal. Therefore, when an SS ADC is used in conjunction with a DCG pixel structure in HCG (High Conversion Gain) mode, the pixel signal voltage can easily reach or even exceed the full-scale input voltage of the SS ADC as the DCG pixel structure converts photogenerated electrons into pixel signals. This causes the SS ADC's internal counter to continuously count to its full-scale value, resulting in significant dynamic power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a dual-conversion gain readout circuit and readout method, as well as an image sensor, to solve the problem of high dynamic power consumption in existing dual-conversion gain readout circuits.

[0005] To solve the above-mentioned technical problems, the present invention provides a dual-conversion gain readout circuit, comprising: The comparison module is used to pre-compare the high-gain photosensitive signal with the ramp signal to obtain a pre-comparison result. The pre-comparison result includes a first pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the full-scale voltage value of the ramp signal, and a second pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the most significant bit voltage value of the ramp signal. It is also used to compare the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal, and the low-gain photosensitive signal with the ramp signal respectively to output corresponding comparison signals. The counting module is used to select the appropriate counting mode to count the comparison signal according to the pre-comparison result, so as to output a data signal.

[0006] Optionally, in the dual-conversion gain readout circuit, if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, the counting module counts the comparison signal according to a first counting mode; if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the most significant bit voltage value of the ramp signal and less than the full-scale voltage value of the ramp signal, the counting module counts the comparison signal according to a second counting mode; if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the most significant bit voltage value of the ramp signal, the counting module counts the comparison signal according to a third counting mode. In the first counting mode: for the comparison signal corresponding to the high-gain photosensitive signal, the data signal output by the counting module is the full-scale count value; for the comparison signal corresponding to the low-gain photosensitive signal, the counting module counts the comparison signal after reducing the counting frequency and increasing the counting weight. In the second counting mode: for the comparison signal corresponding to the high-gain photosensitive signal, the counting module counts the comparison signal after reducing the counting frequency and increasing the counting weight; for the comparison signal corresponding to the low-gain photosensitive signal, the counting module counts the comparison signal using the original counting frequency and the original counting weight. In the third counting mode: the counting module counts the comparison signal using the original counting frequency and the original counting weight.

[0007] Optionally, in the dual-conversion gain readout circuit, the comparison module includes a first non-inverting input terminal, a second non-inverting input terminal, and an inverting input terminal; the first non-inverting input terminal is connected to the high-gain reset signal and the high-gain photosensitive signal through a first coupling capacitor and a first connection switch; the second non-inverting input terminal is connected to the low-gain reset signal and the low-gain photosensitive signal through a second coupling capacitor and a second connection switch; and the inverting input terminal is connected to the ramp signal through a third coupling capacitor.

[0008] Optionally, in the dual-conversion gain readout circuit, the comparison module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first control switch, and a second control switch. The sources of the first transistor, the second transistor, and the third transistor are all connected to a power supply voltage; the gate of the first transistor is shorted to its drain and connected to the gate of the second transistor; the drain of the second transistor is connected to the gate of the third transistor and to the first terminal of the first control switch and the first terminal of the second control switch; the second terminal of the first control switch is connected to the drain of the fourth transistor and the drain of the fifth transistor; the gate of the fourth transistor is connected to a first comparison reset signal; the source of the fourth transistor is connected to the gate of the fifth transistor, serving as the first positive input terminal of the comparison module; the second terminal of the second control switch is connected to the drain of the sixth transistor and the drain of the seventh transistor; the gate of the sixth transistor is connected to a second comparison reset signal. The source of the sixth transistor is connected to the gate of the seventh transistor, serving as the second non-inverting input terminal of the comparator module; the drain of the eighth transistor is connected to the drain of the first transistor and the drain of the ninth transistor; the gate of the eighth transistor is connected to a second comparator reset signal; the source of the eighth transistor is connected to the gate of the ninth transistor, serving as the inverting input terminal of the comparator module; the drain of the tenth transistor is connected to the source of the fifth transistor, the source of the seventh transistor, and the source of the ninth transistor; the gate of the tenth transistor is connected to a bias voltage; the source of the tenth transistor is grounded; the gate of the eleventh transistor is connected to a bias voltage; the source of the eleventh transistor is grounded; the drain of the eleventh transistor is connected to the drain of the third transistor, serving as the output terminal of the comparator module.

[0009] Optionally, in the dual-conversion gain readout circuit, the counting module includes a first counting unit and a second counting unit; the first counting unit is used to count the comparison signal corresponding to the high-gain reset signal and the comparison signal corresponding to the high-gain photosensitive signal to output a high-gain data signal; the second counting unit is used to count the comparison signal corresponding to the low-gain reset signal and the comparison signal corresponding to the low-gain photosensitive signal to output a low-gain data signal.

[0010] Optionally, in the dual-conversion gain readout circuit, the first counting unit includes a first trigger circuit, a first logic circuit, and a first counting circuit; The first trigger circuit includes a first flip-flop and a second flip-flop; the input terminals of the first flip-flop and the second flip-flop are both connected to the comparison signal; the clock terminal of the first flip-flop is connected to the first pre-comparison result signal, and the output terminal of the first flip-flop outputs a first sampling signal; the clock terminal of the second flip-flop is connected to the second pre-comparison result signal, and the output terminal of the second flip-flop outputs a second sampling signal. The first logic circuit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, and a fifth AND gate; the two inputs of the first AND gate respectively receive the first sampling signal and the second sampling signal; the two inputs of the second AND gate respectively receive the first sampling signal and the second sampling signal; the two inputs of the third AND gate respectively receive a ramp enable signal and a connection control signal; the four inputs of the fourth AND gate are respectively connected to the outputs of the first AND gate, the third AND gate, the original clock signal, and the comparison signal; the four inputs of the fifth AND gate are respectively connected to the outputs of the second AND gate, the third AND gate, the down-clocked clock signal, and the comparison signal; the output of the fourth AND gate outputs a first counting signal, and the output of the fifth AND gate outputs a second counting signal. The first counting circuit includes multiple cascaded counters, a third flip-flop, and a first OR gate. Among the cascaded counters, the clock input of the first counter is connected to the first counting signal; the clock input of the second counter is connected to the output of the first counter via a first counting switch and to the second counting signal via a second counting switch; the clock input of each subsequent counter is connected to the output of the preceding counter; and the output of the last counter is connected to the clock input of the third flip-flop. The inverted output of the third flip-flop is connected to its input. The two inputs of the first OR gate are respectively connected to the non-inverted output of the third flip-flop and connected to the first sampling signal. The output of the first OR gate outputs a count set signal, and the set inputs of all counters except the last counter are connected to this count set signal.

[0011] Optionally, in the dual-conversion gain readout circuit, the second counting unit includes a second trigger circuit, a second logic circuit, and a second counting circuit; The second trigger circuit includes a fourth flip-flop; the input terminal of the fourth flip-flop is connected to the comparison signal, the clock terminal is connected to the first pre-comparison result signal, and the output terminal outputs a third sampling signal; The second logic circuit includes a sixth AND gate, a seventh AND gate, and an eighth AND gate; the two inputs of the sixth AND gate receive a ramp enable signal and a connection control signal, respectively; the four inputs of the seventh AND gate are respectively connected to the output of the sixth AND gate, the original clock signal, the comparison signal, and the positive third sampling signal; the four inputs of the eighth AND gate are respectively connected to the output of the sixth AND gate, the down-frequency clock signal, the comparison signal, and the inverted third sampling signal; the output of the seventh AND gate outputs a third counting signal, and the output of the eighth AND gate outputs a fourth counting signal. The second counting circuit includes multiple cascaded counters; among the multiple cascaded counters, the clock terminal of the first counter is connected to the third counting signal, the clock terminal of the second counter is connected to the output terminal of the first counter through the third counting switch, and is connected to the fourth counting signal through the fourth counting switch, and the clock terminal of the subsequent counter is connected to the output terminal of the previous counter.

[0012] Optionally, in the dual-conversion gain readout circuit, the counter includes a second OR gate, a first NAND gate, a first NOT gate, a second NOT gate, a second NAND gate, a third NOT gate, a transmission gate, a fourth NOT gate, a fifth NOT gate, and a third OR gate. The two inputs of the second OR gate are the latch enable and clock inputs of the counter, respectively; the output of the second OR gate is connected to one input of the first NAND gate; the other input of the first NAND gate is the conversion enable of the counter; the input of the first NOT gate, the enable of the transmission gate, and the enable of the third NOT gate are connected to the output of the first NAND gate; the output of the first NOT gate is connected to the enable of the second NOT gate and the enable of the fifth NOT gate; the input of the second NOT gate is connected to the output of the fourth NOT gate; the output of the second NOT gate is connected to... One input of the second NAND gate is connected to the output of the third NOT gate; the other input of the second NAND gate is the reset terminal of the counter; the output of the second NAND gate is connected to the input of the transmission gate and the input of the third NOT gate; the output of the transmission gate is connected to the input of the fourth NOT gate and the output of the fifth NOT gate; the output of the fourth NOT gate is connected to the input of the fifth NOT gate and one input of the third OR gate; the other input of the third OR gate is the set terminal of the counter, and the output of the third OR gate is the output of the counter.

[0013] To address the aforementioned technical problems, the present invention also provides a dual-conversion gain readout method, applied to the dual-conversion gain readout circuit as described in any of the preceding claims, wherein the dual-conversion gain readout method includes: Read the low-gain reset signal and perform count quantization on it to obtain the low-gain reset data signal; Read the high-gain reset signal and perform count quantization on it to obtain the high-gain reset data signal; Read the high-gain photosensitive signal and pre-compare it with the ramp signal to obtain the pre-comparison result; Based on the pre-comparison results, the appropriate counting mode is selected to count and quantize the high-gain photosensitive signal to obtain the high-gain photosensitive data signal; The low-gain photosensitive signal is read, and based on the pre-comparison result, the corresponding counting mode is selected to count and quantize the low-gain photosensitive signal to obtain the low-gain photosensitive data signal.

[0014] Optionally, in the dual-conversion gain readout method, the method of reading the high-gain photosensitive signal and pre-comparing it with the ramp signal to obtain the pre-comparison result includes: Read high-gain photosensitized signals; The voltage difference between the high-gain reset signal and the high-gain photosensitive signal is pre-compared with the full-scale voltage value of the ramp signal to obtain the first pre-comparison result signal. The voltage difference between the high-gain reset signal and the high-gain photosensitive signal is pre-compared with the highest effective bit voltage value of the ramp signal to obtain the second pre-comparison result signal.

[0015] Optionally, in the dual-conversion gain readout method, the method of selecting an appropriate counting mode to count and quantize the high-gain photosensitive signal based on the pre-comparison result to obtain the high-gain photosensitive data signal includes: If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, then the full-scale count value will be used as the high-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the highest effective bit voltage of the ramp signal and less than the full-scale voltage of the ramp signal, then the high-gain photosensitive signal is counted and quantized after reducing the counting frequency and increasing the counting weight to obtain the high-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the highest effective bit voltage of the ramp signal, the high-gain photosensitive signal is counted and quantized using the original counting frequency and the original counting weight to obtain the high-gain photosensitive data signal.

[0016] Optionally, in the dual-conversion gain readout method, the method of selecting an appropriate counting mode to count and quantize the low-gain photosensitive signal based on the pre-comparison result to obtain the low-gain photosensitive data signal includes: If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, then the low-gain photosensitive signal is counted and quantized after reducing the counting frequency and increasing the counting weight to obtain the low-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the full-scale voltage value of the ramp signal, the low-gain photosensitive signal is counted and quantized using the original counting frequency and the original counting weight to obtain the low-gain photosensitive data signal.

[0017] To address the aforementioned technical problems, the present invention also provides an image sensor, including the dual-conversion gain readout circuit as described in any of the preceding claims.

[0018] The present invention provides a dual-conversion gain readout circuit and readout method, and an image sensor, comprising: a comparison module, configured to pre-compare a high-gain photosensitive signal with a ramp signal to obtain a pre-comparison result, the pre-comparison result including a first pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the full-scale voltage value of the ramp signal, and a second pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the most significant bit voltage value of the ramp signal; further configured to compare a low-gain reset signal, a high-gain reset signal, a high-gain photosensitive signal, and a low-gain photosensitive signal with the ramp signal respectively to output corresponding comparison signals; and a counting module, configured to select a corresponding counting mode to count the comparison signals according to the pre-comparison result to output a data signal. The comparison module performs a pre-comparison between the high-gain photosensitive signal and the ramp signal to obtain the pre-comparison result. The counting module then selects the appropriate counting mode for counting quantization based on the pre-comparison result. This allows the counting mode to be adaptively selected based on the voltage difference between the high-gain reset signal and the high-gain photosensitive signal, thereby effectively reducing the dynamic power consumption of the counting module and the overall power consumption of the readout circuit. This solves the problem of high dynamic power consumption in existing dual-conversion gain readout circuits. Attached Figure Description

[0019] Figure 1 This is a block diagram of the dual-conversion gain readout circuit provided in this embodiment; Figure 2 This is a schematic diagram of the connection structure of the comparison module provided in this embodiment; Figure 3 The circuit schematic of the comparison module provided in this embodiment; Figure 4 This is a schematic diagram of the circuit structure of the dual-conversion gain readout circuit provided in this embodiment; Figure 5 This is a schematic diagram of the circuit structure of the first counting unit provided in this embodiment; Figure 6 This is a schematic diagram of the circuit structure of the second counting unit provided in this embodiment; Figure 7 This is a schematic diagram of the circuit structure of the counter provided in this embodiment; Figure 8 This is a flowchart of the dual-conversion gain readout method provided in this embodiment; Figure 9 This is a timing diagram for reading out weak light pixel signals provided in this embodiment; Figure 10 This is a timing diagram for reading out medium-light pixel signals provided in this embodiment; Figure 11This is a timing diagram for reading out the strong light pixel signal in this embodiment. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the dual-conversion gain readout circuit and readout method, as well as the image sensor proposed in this invention. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0021] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] This embodiment provides a dual-conversion gain readout circuit, such as Figure 1 As shown, it includes: The comparison module is used to pre-compare the high-gain photosensitive signal with the ramp signal to obtain a pre-comparison result. The pre-comparison result includes a first pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the full-scale voltage value of the ramp signal, and a second pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the most significant bit voltage value of the ramp signal. It is also used to compare the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal, and the low-gain photosensitive signal with the ramp signal respectively to output corresponding comparison signals. The counting module is used to select the appropriate counting mode to count the comparison signal according to the pre-comparison result, so as to output a data signal.

[0023] The dual-conversion gain readout circuit provided in this embodiment pre-compares the high-gain photosensitive signal and the ramp signal through a comparison module to obtain a pre-comparison result. Then, a counting module selects the corresponding counting mode for counting quantization based on the pre-comparison result. This enables the corresponding counting mode to be adaptively selected based on the voltage difference between the high-gain reset signal and the high-gain photosensitive signal, thereby effectively reducing the dynamic power consumption of the counting module and the overall power consumption of the readout circuit. This solves the problem of high dynamic power consumption in existing dual-conversion gain readout circuits.

[0024] It should be noted that, in this embodiment, the low-gain reset signal, high-gain reset signal, low-gain photosensitive signal, and high-gain photosensitive signal are collectively referred to as pixel signal V. PIXEL The signals are obtained from the DCG pixel structure. The low-gain reset signal and low-gain photosensitive signal correspond to the reset and photosensitive signals generated by the DCG pixel structure in LCG (Low Conversion Gain) mode; the high-gain reset signal and high-gain photosensitive signal correspond to the reset and photosensitive signals generated by the DCG pixel structure in HCG (High Conversion Gain) mode. The voltage difference between the high-gain reset signal and the high-gain photosensitive signal is the voltage value corresponding to the actual photoelectric conversion of the DCG pixel structure in HCG mode. The terms "high" and "low" are only used to distinguish between the two conversion gains and do not represent the actual signal value being high or low, nor do they imply a difference in high or low between the two signals.

[0025] Specifically, in this embodiment, if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, the counting module counts the comparison signal according to a first counting mode; if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the most significant bit voltage value of the ramp signal and less than the full-scale voltage value of the ramp signal, the counting module counts the comparison signal according to a second counting mode; if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the most significant bit voltage value of the ramp signal, the counting module counts the comparison signal according to a third counting mode. In the first counting mode: for the comparison signal corresponding to the high-gain photosensitive signal, the data signal output by the counting module is the full-scale count value; for the comparison signal corresponding to the low-gain photosensitive signal, the counting module counts the comparison signal after reducing the counting frequency and increasing the counting weight. In the second counting mode: for the comparison signal corresponding to the high-gain photosensitive signal, the counting module counts the comparison signal after reducing the counting frequency and increasing the counting weight; for the comparison signal corresponding to the low-gain photosensitive signal, the counting module counts the comparison signal using the original counting frequency and the original counting weight. In the third counting mode: the counting module counts the comparison signal using the original counting frequency and the original counting weight.

[0026] Thus, by performing two pre-comparisons between the voltage difference between the high-gain reset signal and the high-gain photosensitive signal and the full-scale voltage value and the most significant bit voltage value (half-scale voltage value) of the ramp signal, and based on the pre-comparison results, the counting quantization of the high-gain photosensitive signal adopts three modes: direct assignment, down-frequency counting, and normal counting, while the counting quantization of the low-gain photosensitive signal adopts two modes: down-frequency counting and normal counting. Direct assignment and down-frequency counting can effectively reduce the dynamic power consumption of the counting module, thereby reducing the system power consumption of the entire readout circuit.

[0027] Furthermore, in this embodiment, as Figure 2 As shown, the comparison module includes a first non-inverting input terminal VinH+, a second non-inverting input terminal VinL+, and an inverting input terminal Vin-; the first non-inverting input terminal VinH+ is connected to a first coupling capacitor C. PH and the first connection switch S PH1 The high-gain reset signal and the high-gain photosensitive signal are connected; the second non-inverting input terminal VinL+ is connected through the second coupling capacitor C. PL Second connection switch S PL1 The low-gain reset signal and the low-gain photosensitive signal are connected; the inverting input terminal Vin- is connected through the third coupling capacitor C. N Access the ramp signal V RAMP .

[0028] Specifically, in this embodiment, the first connection switch S PH1 Second connection switch S PL1 Connect to the output of the DCG pixel structure to receive the pixel signal V. PIXEL The first connection switch S is controlled by the connection control signal KH. PH1 Second connection switch S PL1 The on / off state is used to realize the pixel signal V input to the first non-inverting input terminal VinH+ and the second non-inverting input terminal VinL+ of the comparison module. PIXEL It can be a high-gain reset signal and a high-gain photosensitive signal or a low-gain reset signal and a low-gain photosensitive signal.

[0029] In practical applications, if the connection control signal KH is high (KH+ is active), then the first connection switch S PH1 On, second connection switch S PL1 Disconnected, at this time the pixel signal V is connected to the first positive input terminal VinH+. PIXEL This is for high-gain reset signal and high-gain photosensitive signal; if the connection control signal KH is low (KH- active), then the second connection switch S... PL1 On, first connection switch S PH1 Disconnected, at this time the pixel signal V is connected to the second positive input terminal VinL+. PIXEL These are the low-gain reset signal and the low-gain photosensitive signal. KH- is the inverted signal of KH+.

[0030] Furthermore, in practical applications, a ramp signal V can be provided by a ramp generator. RAMP To the inverting input of the comparator module, Vin-.

[0031] Furthermore, in this embodiment, as Figure 3 As shown, the comparison module includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a first control switch S. PH2 Second control switch S PL2 .

[0032] The sources of the first transistor M1, the second transistor M2, and the third transistor M3 are all connected to the power supply voltage VDD; the gate and drain of the first transistor M1 are shorted together and connected to the gate of the second transistor M2; the drain of the second transistor M2 is connected to the gate of the third transistor M3 and connected to the first control switch S. PH2 The first end and the second control switch S PL2 The first end is connected; the first control switch S PH2 The second terminal is connected to the drain of the fourth transistor M4 and the drain of the fifth transistor M5; the gate of the fourth transistor M4 is connected to the first comparison reset signal RST_H; the source of the fourth transistor M4 is connected to the gate of the fifth transistor M5, serving as the first positive input terminal VinH+ of the comparison module; the second control switch S PL2The second terminal is connected to the drain of the sixth transistor M6 and the drain of the seventh transistor M7; the gate of the sixth transistor M6 is connected to the second comparison reset signal RST_L; the source of the sixth transistor M6 is connected to the gate of the seventh transistor M7, serving as the second positive input terminal VinL+ of the comparison module; the drain of the eighth transistor M8 is connected to the drain of the first transistor M1 and the drain of the ninth transistor M9; the gate of the eighth transistor M8 is connected to the second comparison reset signal RST_L; the source of the eighth transistor M8 is connected to the drain of the ninth transistor M9. The gate of the tenth transistor M10 is connected to the source of the fifth transistor M5, the source of the seventh transistor M7, and the source of the ninth transistor M9. The gate of the tenth transistor M10 is connected to a bias voltage VB. The source of the tenth transistor M10 is grounded. The gate of the eleventh transistor M11 is connected to a bias voltage VB. The source of the eleventh transistor M11 is grounded. The drain of the eleventh transistor M11 is connected to the drain of the third transistor M3, serving as the output terminal VOUT of the comparator module.

[0033] Specifically, in this embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 are PMOS transistors, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are NMOS transistors. The first control switch S PH2 Second control switch S PL2 It is also controlled by the connection control signal KH.

[0034] Viewing the comparison module as a comparator, internally, the first transistor M1 and the second transistor M2 are the load transistors of the first-stage comparator; the third transistor M3 is the input transistor or common-source amplifier of the second-stage comparator; the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are the reset transistors of the comparator, used to reset the comparator; the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 are the input pair transistors of the comparator; the tenth transistor M10 is the bias transistor of the first-stage comparator; and the eleventh transistor M11 is the bias transistor of the second-stage comparator.

[0035] If the connection control signal KH is high (KH+ is active), then the first control switch S PH2 On, second control switch S PL2When disconnected, the first non-inverting input terminal VinH+ is connected to both the high-gain reset signal and the high-gain photosensitive signal. The comparator module compares the high-gain reset signal and the high-gain photosensitive signal with the ramp signal. If the connection control signal KH is low (KH- active), then the second control switch S... PL2 On, first control switch S PH2 When disconnected, the second positive input terminal VinL+ is connected to the low-gain reset signal and the low-gain photosensitive signal. The comparison module compares the low-gain reset signal and the low-gain photosensitive signal with the ramp signal.

[0036] Furthermore, in this embodiment, as Figure 4 As shown, the comparison module and the counting module are connected through an inverter INV0. That is, the comparison signal Comp_out output by the comparison module is inverted by the inverter INV0 and becomes Comp_out-. The inverted comparison signal Comp_out- is then input to the counting module for counting.

[0037] Furthermore, in order to achieve counting under different counting modes for the comparison signal corresponding to the high-gain reset signal and the comparison signal corresponding to the high-gain photosensitive signal, and to achieve counting under different counting modes for the comparison signal corresponding to the low-gain reset signal and the comparison signal corresponding to the low-gain photosensitive signal, in this embodiment, as follows: Figure 4 As shown, the counting module includes a first counting unit and a second counting unit; the first counting unit is used to count the comparison signal corresponding to the high-gain reset signal and the comparison signal corresponding to the high-gain photosensitive signal to output a high-gain data signal; the second counting unit is used to count the comparison signal corresponding to the low-gain reset signal and the comparison signal corresponding to the low-gain photosensitive signal to output a low-gain data signal.

[0038] In practical applications, both the first and second counting units receive clock signals CLK at two different frequencies, and set corresponding counting weights for each clock signal frequency. In one specific embodiment, the clock signal CLK is divided into the original clock signal CLK[0] and the down-frequency clock signal CLK[1]. The frequency of the down-frequency clock signal CLK[1] is half the frequency of the original clock signal CLK[0]. Correspondingly, the counting weight used by the down-frequency clock signal CLK[1] is twice the counting weight used by the original clock signal CLK[0].

[0039] Specifically, in this embodiment, such as Figure 5 As shown, the first counting unit includes a first trigger circuit, a first logic circuit, and a first counting circuit.

[0040] The first trigger circuit includes a first flip-flop DFF1 and a second flip-flop DFF2; the input terminals D of both the first flip-flop DFF1 and the second flip-flop DFF2 are connected to the comparison signal Comp_out-; the clock terminal CLK of the first flip-flop DFF1 is connected to the first pre-comparison result signal CPULSE1, and the output terminal Q of the first flip-flop DFF1 outputs the first sampling signal. The clock input CLK of the second flip-flop DFF2 is connected to the second pre-compare result signal CPULSE2, and the output Q of the second flip-flop DFF2 outputs the second sampling signal. 1.

[0041] In practical applications, both the first flip-flop DFF1 and the second flip-flop DFF2 are D flip-flops. The non-inverting output Q of the first flip-flop DFF1 outputs the positive-inverting first sampled signal. Inverting output terminal Output the inverted first sampled signal The positive output Q of the second flip-flop DFF2 outputs a positive second sampling signal. Inverting output terminal Output the inverted second sampled signal The reset terminal R of the first flip-flop DFF1 and the second flip-flop DFF2 is connected to the count reset signal DRST.

[0042] Furthermore, the first logic circuit includes a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, and a fifth AND gate AND5; the two inputs of the first AND gate AND1 respectively receive the first sampling signal. and the second sampling signal The two inputs of the second AND gate AND2 respectively receive the first sampled signal. and the second sampling signal The two inputs of the third AND gate AND3 receive the ramp enable signal EN_RAMP and the connection control signal KH, respectively; the four inputs of the fourth AND gate AND4 are respectively connected to the output of the first AND gate AND1, the output of the third AND gate AND3, the original clock signal CLK[0] and the comparison signal Comp_out-; the four inputs of the fifth AND gate AND5 are respectively connected to the output of the second AND gate AND2, the output of the third AND gate AND3, the down-frequency clock signal CLK[1] and the comparison signal Comp_out-; the output of the fourth AND gate AND4 outputs the first counting signal Counter[0], and the output of the fifth AND gate AND5 outputs the second counting signal Counter[1].

[0043] In practical applications, AND1, AND2, and AND3 are two-input AND gates, while AND4 and AND5 are four-input AND gates. The two inputs of AND1 specifically receive the in-phase first sampled signal. and the inverted second sampled signal The two inputs of the second AND gate AND2 specifically receive the positive-inverted first sampled signal. and the inverted second sampled signal The two inputs of the third AND gate AND3 specifically receive the ramp enable signal EN_RAMP and the inverted connection control signal KH-, respectively.

[0044] Furthermore, the first counting circuit includes multiple cascaded counters CNT0~CNT N, a third flip-flop DFF3, and a first OR gate OR1; among the multiple cascaded counters, the clock terminal CLK of the first counter CNT0 is connected to the first counting signal Counter[0], the clock terminal CLK of the second counter CNT1 is connected to the output terminal Q of the first counter CNT0 through the first counting switch K0, and is connected to the second counting signal Counter[1] through the second counting switch K1, the clock terminal of the next counter is connected to the output terminal of the previous counter, and the output terminal Q of the last counter CNT N is connected to the clock terminal CLK of the third flip-flop DFF3; the inverted output terminal of the third flip-flop DFF3... The first OR gate OR1 is connected to input D; the two inputs of the first OR gate OR1 are respectively connected to the non-inverting output Q of the third flip-flop DFF3 and connected to the first sampling signal. The output terminal of the first OR gate OR1 outputs a count set signal DSST, and the set terminals S of all the counters except the last counter are connected to the count set signal DSST.

[0045] In practical applications, the latch enable terminals of all counters are connected to the latch enable signal LOCK_EN, the switching enable terminals of all counters are connected to the switching enable signal SWITCH_EN, and the output terminals Q of all counters output the current bit's count signal Q. The reset terminal R of all counters is connected to the count reset signal DRST. The third flip-flop DFF3 is a D flip-flop; the reset terminal R of the third flip-flop DFF3 is connected to an AND gate AND0, and the two input terminals of AND gate AND0 are connected to the switching enable signal SWITCH_EN and the count reset signal DRST, respectively. The first sampling signal is connected to the first OR gate OR1. Specifically, the inverted first sampling signal The first counting switch K0 and the second counting switch K1 are controlled by the second sampling signal. Control, wherein, when the second sampling signal High level ( When the signal is valid, the first counting switch K0 is closed and the second counting switch K1 is open; when the second sampling signal... Low level ( When valid, the first counting switch K0 is open and the second counting switch K1 is closed.

[0046] Furthermore, in this embodiment, as Figure 6 As shown, the second counting unit includes a second trigger circuit, a second logic circuit, and a second counting circuit.

[0047] The second trigger circuit includes a fourth flip-flop DFF4; the input D of the fourth flip-flop DFF4 is connected to the comparison signal Comp_out-, the clock CLK is connected to the first pre-comparison result signal CPULSE1, and the output Q outputs the third sampling signal. .

[0048] In practical applications, the fourth flip-flop, DFF4, is a D flip-flop. The reset terminal R of the fourth flip-flop, DFF4, is connected to the count reset signal DRST. The non-inverting output Q of the fourth flip-flop, DFF4, outputs a positive-inverting third sampling signal. Inverting output terminal Output the inverted third sampled signal Since the signal connected to the fourth flip-flop DFF4 is the same as the signal connected to the first flip-flop DFF1, the third sampled signal output by the fourth flip-flop DFF4 is... With the first sampled signal Consistent.

[0049] Furthermore, the second logic circuit includes a sixth AND gate AND6, a seventh AND gate AND7, and an eighth AND gate AND8; the two inputs of the sixth AND gate AND6 receive the ramp enable signal EN_RAMP and the connection control signal KH, respectively; the four inputs of the seventh AND gate AND7 are respectively connected to the output of the sixth AND gate AND6, the original clock signal CLK[0], the comparison signal Comp_out-, and the positive third sampling signal. The four inputs of the eighth AND gate AND8 are respectively connected to the output of the sixth AND gate AND6, the down-frequency clock signal CLK[1], the comparison signal Comp_out-, and the inverted third sampling signal. The output of the seventh AND gate AND7 outputs the third counting signal Counter[2], and the output of the eighth AND gate AND8 outputs the fourth counting signal Counter[3].

[0050] In practical applications, AND6 is a two-input AND gate, while AND7 and AND8 are four-input AND gates. The connection control signal KH connected to AND6 is an inverted connection control signal KH-.

[0051] The second counting circuit includes multiple cascaded counters CNT0~CNT N; among the multiple cascaded counters, the clock terminal CLK of the first counter CNT0 is connected to the third counting signal Counter[2], the clock terminal CLK of the second counter CNT1 is connected to the output terminal Q of the first counter CNT0 through the third counting switch K2, and is connected to the fourth counting signal Counter[3] through the fourth counting switch K3, and the clock terminal of the latter counter is connected to the output terminal of the former counter.

[0052] In practical applications, the latch enable terminal of all counters is connected to the latch enable signal LOCK_EN, the conversion enable terminal of all counters is connected to the conversion enable signal SWITCH_EN, and the output terminal Q of all counters outputs the current bit's count signal Q.

[0053] Furthermore, in this embodiment, as Figure 7 As shown, all counters in the first and second counting circuits include a second OR gate OR2, a first NAND gate NAND1, a first NOT gate INV1, a second NOT gate INV2, a second NAND gate NAND2, a third NOT gate INV3, a transmission gate TG, a fourth NOT gate INV4, a fifth NOT gate INV5, and a third OR gate OR3.

[0054] Specifically, the two inputs of the second OR gate OR2 are the latch enable terminal of the counter (connected to the latch enable signal LOCK_EN) and the clock terminal CLK, respectively; the output of the second OR gate OR2 is connected to one input of the first NAND gate NAND1; the other input of the first NAND gate NAND1 is the conversion enable terminal of the counter (connected to the conversion enable signal SWITCH_EN); the input of the first NOT gate INV1, the enable terminal of the transmission gate TG, and the enable terminal of the third NOT gate INV3 are connected to the output of the first NAND gate NAND1; the output of the first NOT gate INV1 is connected to the enable terminals of the second NOT gate INV2 and the fifth NOT gate INV5; the input of the second NOT gate INV2 is connected to the fourth NOT gate INV4. The output of the second NOT gate INV2 is connected to one input of the second NAND gate NAND2 and the output of the third NOT gate INV3; the other input of the second NAND gate NAND2 is the reset terminal R of the counter; the output of the second NAND gate NAND2 is connected to the input of the transmission gate TG and the input of the third NOT gate INV3; the output of the transmission gate TG is connected to the input of the fourth NOT gate INV4 and the output of the fifth NOT gate INV5; the output of the fourth NOT gate INV4 is connected to the input of the fifth NOT gate INV5 and one input of the third OR gate OR3; the other input of the third OR gate OR3 is the set terminal S of the counter, and the output of the third OR gate OR3 is the output terminal Q of the counter.

[0055] In practical applications, the second NOT gate INV2, the third NOT gate INV3, and the fifth NOT gate INV5 can be inverters with enable control, which transmit signals in reverse when enabled at a high level; the transmission gate TG can be a switch that transmits signals when enabled at a high level.

[0056] This embodiment also provides a dual-conversion gain readout method, applied to the dual-conversion gain readout circuit described above, such as... Figure 8 As shown, the dual-conversion gain readout method includes: S1, Read the low-gain reset signal and count and quantize it to obtain the low-gain reset data signal; S2, read the high-gain reset signal and count and quantize it to obtain the high-gain reset data signal; S3, read the high-gain photosensitive signal and pre-compare it with the ramp signal to obtain the pre-comparison result; S4. Based on the pre-comparison result, select the appropriate counting mode to count and quantize the high-gain photosensitive signal to obtain the high-gain photosensitive data signal. S5 reads the low-gain photosensitive signal and selects the appropriate counting mode to count and quantize the low-gain photosensitive signal according to the pre-comparison result, so as to obtain the low-gain photosensitive data signal.

[0057] Specifically, in this embodiment, the specific implementation method of step S3 includes: first, reading the high-gain photosensitive signal; then, performing a pre-comparison between the voltage difference between the high-gain reset signal and the high-gain photosensitive signal and the full-scale voltage value of the ramp signal to obtain a first pre-comparison result signal, wherein if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, the first pre-comparison result signal is high (valid); otherwise, the first pre-comparison result signal is low (invalid); and performing a pre-comparison between the voltage difference between the high-gain reset signal and the high-gain photosensitive signal and the most significant bit voltage value of the ramp signal to obtain a second pre-comparison result signal, wherein if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the most significant bit voltage value of the ramp signal, the second pre-comparison result signal is high (valid); otherwise, the second pre-comparison result signal is low (invalid).

[0058] Furthermore, in this embodiment, the specific implementation method of step S4 includes: If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, that is, the first pre-comparison result signal is high (valid), then the full-scale count value is used as the high-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the highest effective bit voltage of the ramp signal and less than the full-scale voltage of the ramp signal, that is, the first pre-comparison result signal is low (invalid) and the second pre-comparison result signal is high (valid), then the high-gain photosensitive signal is counted and quantized after reducing the counting frequency and increasing the counting weight to obtain the high-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the highest effective bit voltage of the ramp signal, that is, the first pre-comparison result signal is low (invalid) and the second pre-comparison result signal is low (invalid), then the high-gain photosensitive signal is counted and quantized using the original counting frequency and the original counting weight to obtain the high-gain photosensitive data signal.

[0059] When the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the most significant bit voltage of the ramp signal but less than the full-scale voltage of the ramp signal, the clock frequency used in the counting and quantization process of the high-gain photosensitive signal is halved, resulting in increased quantization noise in the counter. However, in practical applications, the photon shot noise of the high-gain photosensitive signal itself is much greater than the quantization noise at this point. Therefore, reducing the clock frequency has almost no impact on the noise performance and accuracy of the SS ADC in the readout circuit.

[0060] Furthermore, in this embodiment, the specific implementation method of step S5 includes: If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, that is, the first pre-comparison result signal is high (valid), then the low-gain photosensitive signal is counted and quantized after reducing the counting frequency and increasing the counting weight to obtain the low-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the full-scale voltage value of the ramp signal, that is, the first pre-comparison result signal is low (invalid), then the low-gain photosensitive signal is counted and quantized using the original counting frequency and the original counting weight to obtain the low-gain photosensitive data signal.

[0061] In practical applications, when the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, the clock frequency used in the counting and quantization process of the low-gain photosensitive signal is halved, which increases the quantization noise of the counter. However, in practical applications, the photon shot noise of the low-gain photosensitive signal itself is much greater than the quantization noise at this time. Therefore, reducing the clock frequency has almost no impact on the noise performance and accuracy of the SS ADC in the readout circuit.

[0062] The following is for reference Figure 9 The process of reading pixel signals when the photosensitive signal is a weak light pixel signal, that is, when the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the highest effective bit voltage value of the ramp signal, is explained.

[0063] During the readout phase of the low-gain reset signal LCG VLR, the connection control signal KH+ remains low, and the second comparison reset signal RST_L changes from low to high, thereby resetting the second non-inverting input terminal VinL+ and the inverting input terminal Vin- of the comparison module. Subsequently, the second comparison reset signal RST_L goes low, and the comparison module compares the low-gain reset signal input at the second non-inverting input terminal VinL+ with the ramp signal input at the inverting input terminal Vin-, outputting the corresponding comparison signal. The counting module then counts the comparison signals, and the counting result is expressed as follows:

[0064] in, This indicates the clock frequency at which the 0th counter starts counting, and S represents the voltage slope of the ramp signal. This indicates the maximum voltage value of the ramp signal. This indicates the voltage value corresponding to the ramp signal during reset. This indicates the decimal count result output by the second counting unit after counting and quantizing the low-gain reset signal LCG VLR.

[0065] During the readout phase of the high-gain reset signal HCG VHR, the connection control signal KH+ goes low, and the first comparison reset signal RST_H goes high, thereby resetting the first non-inverting input terminal VinH+ and the inverting input terminal Vin- of the comparison module. Subsequently, the first comparison reset signal RST_H goes low, and the comparison module compares the high-gain reset signal input at the first non-inverting input terminal VinH+ with the ramp signal input at the inverting input terminal Vin-, outputting the corresponding comparison signal. Then, the counting module counts the comparison signal, and the counting result at this time is expressed as:

[0066] in, This indicates the voltage value corresponding to the ramp signal during reset. This represents the decimal count result output by the first counting unit after counting and quantizing the high-gain reset signal HCG VHR.

[0067] During the readout phase of the high-gain photosensitive signal HCG VHS, a pre-comparison is performed on the high-gain photosensitive signal HCG VHS. The result of the first pre-comparison is that the voltage difference between the high-gain photosensitive signal and the high-gain reset signal is less than the full-scale voltage value of the ramp signal (V). REF1 -V REF4 When the output comparison signal Comp_out- is low, the inverted first sampling signal in the first counting unit... The clock signal is always low, so the counting clock in the first counting unit uses the original clock signal CLK[0] (original clock frequency and original counting weight). The first counting circuit starts counting from the 0th bit counter. The result of the second pre-comparison is that the voltage difference between the high-gain photosensitive signal and the high-gain reset signal is less than the highest effective bit voltage value of the ramp signal (V). REF1 -V REF5 When the output comparison signal Comp_out- is low, the inverted second sampling signal in the first counting unit... Since it is always low, the counting clock in the first counting unit still uses the original clock signal CLK[0] (original clock frequency and original counting weight), and the first counting circuit starts counting from the 0th bit counter.

[0068] After completing two pre-comparisons, the comparison module compares the high-gain photosensitive signal input at the first positive input terminal VinH+ with the ramp signal input at the inverting input terminal Vin-, and outputs the corresponding comparison signal. Then, the first counting circuit in the counting module uses the original clock signal CLK[0] (original clock frequency and original counting weight) to count and quantize the high-gain photosensitive signal HCG VHS. In practical applications, the 0th bit counter needs to perform an increment operation once. The data obtained from the two counts is the complement data of the data before inversion. The count value of the two stages is read out by resetting the complement of the count value in the readout stage to replace the subtraction operation of the data in the two stages, so as to realize the DCDS function. The counting result at this time is expressed as:

[0069] The final high-gain data signal is represented as follows:

[0070] During the readout phase of the low-gain photosensitive signal LCG VLS, the connection control signal KH+ goes low, and the comparison module compares the low-gain photosensitive signal input at the second non-inverting input terminal VinL+ with the ramp signal input at the inverting input terminal Vin-, and outputs the corresponding comparison signal; the inverted third sampling signal in the second counting unit... Since the clock signal is always low, the counting clock in the second counting unit uses the original clock signal CLK[0] (original clock frequency and original counting weight). The second counting circuit starts counting from the 0th bit counter, and the counting result at this time is expressed as:

[0071] The final data signal obtained under low gain is represented as follows:

[0072] The following is for reference Figure 10 The process of reading pixel signals is explained when the photosensitive signal is a medium-light pixel signal, that is, the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the highest effective bit voltage value of the ramp signal and less than the full-scale voltage value.

[0073] The readout phases of the low-gain reset signal LCG VLR and the high-gain reset signal HCG VHR are consistent with the readout method when the photosensitive signal is a weak-light pixel signal, and will not be described again in this application.

[0074] During the readout phase of the high-gain photosensitive signal HCG VHS, a pre-comparison is performed on the high-gain photosensitive signal HCG VHS. The result of the first pre-comparison is that the voltage difference between the high-gain photosensitive signal and the high-gain reset signal is less than the full-scale voltage value of the ramp signal (V). REF1 -V REF4 When the output comparison signal Comp_out- is low, the inverted first sampling signal in the first counting unit... The clock signal is always low, so the counting clock in the first counting unit uses the original clock signal CLK[0] (original clock frequency and original counting weight). The first counting circuit starts counting from the 0th bit counter. The result of the second pre-comparison is that the voltage difference between the high-gain photosensitive signal and the high-gain reset signal is greater than or equal to the highest effective bit voltage value of the ramp signal (V). REF1 -V REF5 The output comparison signal Comp_out- is high, and the inverted second sampling signal in the first counting unit... When the clock signal goes high, the counting clock in the first counting unit uses a down-frequency clock signal CLK[1] (half of the original clock frequency and twice the original counting weight), and the first counting circuit starts counting from the first bit counter.

[0075] After completing two pre-comparisons, the comparison module compares the high-gain photosensitive signal input at the first non-inverting input terminal VinH+ with the ramp signal input at the inverting input terminal Vin-, and outputs the corresponding comparison signal. Then, the first counting circuit in the counting module uses the down-frequency clock signal CLK[1] (half of the original clock frequency and twice the original counting weight) to count and quantize the high-gain photosensitive signal HCG VHS. The counting result at this time is expressed as:

[0076] The final high-gain data signal is represented as follows:

[0077]

[0078] During the readout phase of the low-gain photosensitive signal LCG VLS, the connection control signal KH+ goes low, and the comparison module compares the low-gain photosensitive signal input at the second non-inverting input terminal VinL+ with the ramp signal input at the inverting input terminal Vin-, and outputs the corresponding comparison signal; the inverted third sampling signal in the second counting unit... Since the clock signal is always low, the counting clock in the second counting unit uses the original clock signal CLK[0] (original clock frequency and original counting weight). The second counting circuit starts counting from the 0th bit counter, and the counting result at this time is expressed as:

[0079] The final data signal obtained under low gain is represented as follows:

[0080] The following is for reference Figure 11 The process of reading pixel signals when the photosensitive signal is a strong light pixel signal, that is, when the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, is explained.

[0081] The readout phases of the low-gain reset signal LCG VLR and the high-gain reset signal HCG VHR are consistent with the readout method when the photosensitive signal is a weak-light pixel signal, and will not be described again in this application.

[0082] During the readout stage of the high-gain photosensitive signal HCG VHS, a pre-comparison is first performed on the high-gain photosensitive signal HCG VHS. The result of the first pre-comparison is that the voltage difference between the high-gain photosensitive signal and the high-gain reset signal is greater than or equal to the full-scale voltage value of the ramp signal (V). REF1 -V REF4 When the output comparison signal Comp_out- is high, the inverted first sampling signal in the first counting unit... When the signal goes high, the DSST signal becomes high, and the outputs of the counters from bit 0 to bit (N-1) are set high. The first counting unit performs a full-range count operation. At this time, only the data inside the first counting unit is inverted, resulting in the high-gain data signal as follows:

[0083] During the readout phase of the low-gain photosensitive signal LCG VLS, the connection control signal KH+ goes low, and the comparison module compares the low-gain photosensitive signal input at the second non-inverting input terminal VinL+ with the ramp signal input at the inverting input terminal Vin-, and outputs the corresponding comparison signal; the inverted third sampling signal in the second counting unit... The clock signal becomes high, so the counting clock in the second counting unit uses a down-frequency clock signal CLK[1] (half the original clock frequency and twice the original counting weight). The second counting circuit starts counting from the first bit counter, and the counting result at this time is expressed as:

[0084] The final data signal obtained under low gain is represented as follows:

[0085]

[0086] In one specific embodiment, both the first and second counting units in the counting module contain 11-bit counters, and the high conversion gain (HCG) is five times that of the low conversion gain (LCG). In this example, compared with existing readout circuits, the dual conversion gain readout circuit provided in this embodiment can achieve a power saving rate of over 60% in the counter during the readout of strong light pixel signals, effectively reducing the dynamic power consumption of the counting module and thus reducing the overall power consumption of the readout circuit.

[0087] Furthermore, this embodiment also provides an image sensor, including the dual-conversion gain readout circuit as described in any of the preceding claims.

[0088] In practical applications, image sensors are also equipped with a DCG pixel architecture.

[0089] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0090] The dual-conversion gain readout circuit and readout method, and image sensor provided in this embodiment include: a comparison module, used to pre-compare a high-gain photosensitive signal with a ramp signal to obtain a pre-comparison result, the pre-comparison result including a first pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the full-scale voltage value of the ramp signal, and a second pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the most significant bit voltage value of the ramp signal; and also used to compare a low-gain reset signal, a high-gain reset signal, a high-gain photosensitive signal, and a low-gain photosensitive signal with the ramp signal respectively to output corresponding comparison signals; and a counting module, used to select a corresponding counting mode to count the comparison signals according to the pre-comparison result to output data signals. The comparison module performs a pre-comparison between the high-gain photosensitive signal and the ramp signal to obtain the pre-comparison result. The counting module then selects the appropriate counting mode for counting quantization based on the pre-comparison result. This allows the counting mode to be adaptively selected based on the voltage difference between the high-gain reset signal and the high-gain photosensitive signal, thereby effectively reducing the dynamic power consumption of the counting module and the overall power consumption of the readout circuit. This solves the problem of high dynamic power consumption in existing dual-conversion gain readout circuits.

[0091] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A dual-conversion gain readout circuit, characterized in that, include: The comparison module is used to pre-compare the high-gain photosensitive signal with the ramp signal to obtain a pre-comparison result. The pre-comparison result includes a first pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the full-scale voltage value of the ramp signal, and a second pre-comparison result signal obtained by pre-comparing the voltage difference between the high-gain reset signal and the high-gain photosensitive signal with the most significant bit voltage value of the ramp signal. It is also used to compare the low-gain reset signal, the high-gain reset signal, the high-gain photosensitive signal, and the low-gain photosensitive signal with the ramp signal respectively to output corresponding comparison signals. The counting module is used to select the appropriate counting mode to count the comparison signal according to the pre-comparison result, so as to output a data signal.

2. The dual-conversion gain readout circuit according to claim 1, characterized in that, If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, the counting module counts the comparison signal according to the first counting mode; if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the most significant bit voltage value of the ramp signal and less than the full-scale voltage value of the ramp signal, the counting module counts the comparison signal according to the second counting mode; if the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the most significant bit voltage value of the ramp signal, the counting module counts the comparison signal according to the third counting mode. In the first counting mode: for the comparison signal corresponding to the high-gain photosensitive signal, the data signal output by the counting module is the full-scale count value; for the comparison signal corresponding to the low-gain photosensitive signal, the counting module counts the comparison signal after reducing the counting frequency and increasing the counting weight. In the second counting mode: for the comparison signal corresponding to the high-gain photosensitive signal, the counting module counts the comparison signal after reducing the counting frequency and increasing the counting weight; for the comparison signal corresponding to the low-gain photosensitive signal, the counting module counts the comparison signal using the original counting frequency and the original counting weight. In the third counting mode: the counting module counts the comparison signal using the original counting frequency and the original counting weight.

3. The dual-conversion gain readout circuit according to claim 1, characterized in that, The comparison module includes a first positive input terminal, a second positive input terminal, and an inverting input terminal; the first positive input terminal is connected to the high-gain reset signal and the high-gain photosensitive signal through a first coupling capacitor and a first connection switch; the second positive input terminal is connected to the low-gain reset signal and the low-gain photosensitive signal through a second coupling capacitor and a second connection switch; the inverting input terminal is connected to the ramp signal through a third coupling capacitor.

4. The dual-conversion gain readout circuit according to claim 1, characterized in that, The comparison module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first control switch, and a second control switch. The sources of the first transistor, the second transistor, and the third transistor are all connected to a power supply voltage; the gate of the first transistor is shorted to its drain and connected to the gate of the second transistor; the drain of the second transistor is connected to the gate of the third transistor and to the first terminal of the first control switch and the first terminal of the second control switch; the second terminal of the first control switch is connected to the drain of the fourth transistor and the drain of the fifth transistor; the gate of the fourth transistor is connected to a first comparison reset signal; the source of the fourth transistor is connected to the gate of the fifth transistor, serving as the first positive input terminal of the comparison module; the second terminal of the second control switch is connected to the first... The drain of the sixth transistor is connected to the drain of the seventh transistor; the gate of the sixth transistor is connected to a second comparison reset signal; the source of the sixth transistor is connected to the gate of the seventh transistor, serving as the second non-inverting input terminal of the comparison module; the drain of the eighth transistor is connected to the drain of the first transistor and the drain of the ninth transistor; the gate of the eighth transistor is connected to the second comparison reset signal; the source of the eighth transistor is connected to the gate of the ninth transistor, serving as the inverting input terminal of the comparison module; the drain of the tenth transistor is connected to the source of the fifth transistor, the source of the seventh transistor, and the source of the ninth transistor; the gate of the tenth transistor is connected to a bias voltage. The source of the tenth transistor is grounded; the gate of the eleventh transistor is connected to a bias voltage; the source of the eleventh transistor is grounded; the drain of the eleventh transistor is connected to the drain of the third transistor, serving as the output terminal of the comparator module.

5. The dual-conversion gain readout circuit according to claim 1, characterized in that, The counting module includes a first counting unit and a second counting unit; the first counting unit is used to count the comparison signal corresponding to the high-gain reset signal and the comparison signal corresponding to the high-gain photosensitive signal to output a high-gain data signal; the second counting unit is used to count the comparison signal corresponding to the low-gain reset signal and the comparison signal corresponding to the low-gain photosensitive signal to output a low-gain data signal.

6. The dual-conversion gain readout circuit according to claim 5, characterized in that, The first counting unit includes a first trigger circuit, a first logic circuit, and a first counting circuit; The first trigger circuit includes a first flip-flop and a second flip-flop; the input terminals of the first flip-flop and the second flip-flop are both connected to the comparison signal; the clock terminal of the first flip-flop is connected to the first pre-comparison result signal, and the output terminal of the first flip-flop outputs a first sampling signal; the clock terminal of the second flip-flop is connected to the second pre-comparison result signal, and the output terminal of the second flip-flop outputs a second sampling signal. The first logic circuit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, and a fifth AND gate; the two inputs of the first AND gate respectively receive the first sampling signal and the second sampling signal; the two inputs of the second AND gate respectively receive the first sampling signal and the second sampling signal; the two inputs of the third AND gate respectively receive a ramp enable signal and a connection control signal; the four inputs of the fourth AND gate are respectively connected to the outputs of the first AND gate, the third AND gate, the original clock signal, and the comparison signal; the four inputs of the fifth AND gate are respectively connected to the outputs of the second AND gate, the third AND gate, the down-clocked clock signal, and the comparison signal; the output of the fourth AND gate outputs a first counting signal, and the output of the fifth AND gate outputs a second counting signal. The first counting circuit includes multiple cascaded counters, a third flip-flop, and a first OR gate. Among the cascaded counters, the clock input of the first counter is connected to the first counting signal; the clock input of the second counter is connected to the output of the first counter via a first counting switch and to the second counting signal via a second counting switch; the clock input of each subsequent counter is connected to the output of the preceding counter; and the output of the last counter is connected to the clock input of the third flip-flop. The inverted output of the third flip-flop is connected to its input. The two inputs of the first OR gate are respectively connected to the non-inverted output of the third flip-flop and connected to the first sampling signal. The output of the first OR gate outputs a count set signal, and the set inputs of all counters except the last counter are connected to this count set signal.

7. The dual-conversion gain readout circuit according to claim 5, characterized in that, The second counting unit includes a second trigger circuit, a second logic circuit, and a second counting circuit; The second trigger circuit includes a fourth flip-flop; the input terminal of the fourth flip-flop is connected to the comparison signal, the clock terminal is connected to the first pre-comparison result signal, and the output terminal outputs a third sampling signal; The second logic circuit includes a sixth AND gate, a seventh AND gate, and an eighth AND gate; the two inputs of the sixth AND gate receive a ramp enable signal and a connection control signal, respectively; the four inputs of the seventh AND gate are respectively connected to the output of the sixth AND gate, the original clock signal, the comparison signal, and the positive third sampling signal; the four inputs of the eighth AND gate are respectively connected to the output of the sixth AND gate, the down-frequency clock signal, the comparison signal, and the inverted third sampling signal; the output of the seventh AND gate outputs a third counting signal, and the output of the eighth AND gate outputs a fourth counting signal. The second counting circuit includes multiple cascaded counters; among the multiple cascaded counters, the clock terminal of the first counter is connected to the third counting signal, the clock terminal of the second counter is connected to the output terminal of the first counter through the third counting switch, and is connected to the fourth counting signal through the fourth counting switch, and the clock terminal of the subsequent counter is connected to the output terminal of the previous counter.

8. The dual-conversion gain readout circuit according to claim 6 or 7, characterized in that, The counter includes a second OR gate, a first NAND gate, a first NOT gate, a second NOT gate, a second NAND gate, a third NOT gate, a transmission gate, a fourth NOT gate, a fifth NOT gate, and a third OR gate; The two inputs of the second OR gate are the latch enable and clock inputs of the counter, respectively; the output of the second OR gate is connected to one input of the first NAND gate; the other input of the first NAND gate is the conversion enable of the counter; the input of the first NOT gate, the enable of the transmission gate, and the enable of the third NOT gate are connected to the output of the first NAND gate; the output of the first NOT gate is connected to the enable of the second NOT gate and the fifth NOT gate; the input of the second NOT gate is connected to the output of the fourth NOT gate; the output of the second NOT gate is connected to one input of the second NAND gate and the output of the third NOT gate; the other input of the second NAND gate is the reset input of the counter. The output of the second NAND gate is connected to the input of the transmission gate and the input of the third NOT gate; the output of the transmission gate is connected to the input of the fourth NOT gate and the output of the fifth NOT gate; the output of the fourth NOT gate is connected to the input of the fifth NOT gate and one input of the third OR gate; the other input of the third OR gate is the set terminal of the counter, and the output of the third OR gate is the output of the counter.

9. A dual-conversion gain readout method, applied to the dual-conversion gain readout circuit as described in any one of claims 1 to 8, characterized in that, The dual-conversion gain readout method includes: Read the low-gain reset signal and perform count quantization on it to obtain the low-gain reset data signal; Read the high-gain reset signal and perform count quantization on it to obtain the high-gain reset data signal; Read the high-gain photosensitive signal and pre-compare it with the ramp signal to obtain the pre-comparison result; Based on the pre-comparison results, the appropriate counting mode is selected to count and quantize the high-gain photosensitive signal to obtain the high-gain photosensitive data signal; The low-gain photosensitive signal is read, and based on the pre-comparison result, the corresponding counting mode is selected to count and quantize the low-gain photosensitive signal to obtain the low-gain photosensitive data signal.

10. The dual-conversion gain readout method according to claim 9, characterized in that, The method for reading the high-gain photosensitive signal and pre-comparing it with the ramp signal to obtain the pre-comparison result includes: Read high-gain photosensitized signals; The voltage difference between the high-gain reset signal and the high-gain photosensitive signal is pre-compared with the full-scale voltage value of the ramp signal to obtain the first pre-comparison result signal. The voltage difference between the high-gain reset signal and the high-gain photosensitive signal is pre-compared with the highest effective bit voltage value of the ramp signal to obtain the second pre-comparison result signal.

11. The dual-conversion gain readout method according to claim 9, characterized in that, The method of selecting an appropriate counting mode to count and quantize the high-gain photosensitive signal based on the pre-comparison result to obtain the high-gain photosensitive data signal includes: If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, then the full-scale count value will be used as the high-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the highest effective bit voltage of the ramp signal and less than the full-scale voltage of the ramp signal, then the high-gain photosensitive signal is counted and quantized after reducing the counting frequency and increasing the counting weight to obtain the high-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the highest effective bit voltage of the ramp signal, the high-gain photosensitive signal is counted and quantized using the original counting frequency and the original counting weight to obtain the high-gain photosensitive data signal.

12. The dual-conversion gain readout method according to claim 9, characterized in that, The method of selecting an appropriate counting mode to count and quantize the low-gain photosensitive signal based on the pre-comparison result to obtain the low-gain photosensitive data signal includes: If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is greater than or equal to the full-scale voltage value of the ramp signal, then the low-gain photosensitive signal is counted and quantized after reducing the counting frequency and increasing the counting weight to obtain the low-gain photosensitive data signal. If the voltage difference between the high-gain reset signal and the high-gain photosensitive signal is less than the full-scale voltage value of the ramp signal, the low-gain photosensitive signal is counted and quantized using the original counting frequency and the original counting weight to obtain the low-gain photosensitive data signal.

13. An image sensor, characterized in that, Includes the dual-conversion gain readout circuit as described in any one of claims 1 to 8.

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