An instruction prediction method and apparatus, electronic device, medium, and product

Abstract

The application discloses an instruction prediction method and device, electronic equipment, medium and product. The method comprises the following steps: acquiring the address of a prediction block, and predicting a branch instruction according to the address of the prediction block; if the prediction block contains the branch instruction, taking the prediction block as a to-be-monitored prediction block, starting monitoring of the to-be-monitored prediction block, and updating first branch target buffer entry information corresponding to the to-be-monitored prediction block according to a monitoring result, wherein the first branch target buffer entry information at least comprises branch span distance information; if the prediction block does not contain the branch instruction, determining a next prediction block according to the branch span distance information in the first branch target buffer entry information corresponding to the prediction block to realize instruction span, taking the next prediction block as a new prediction block, and returning to the step of acquiring the address of the prediction block; the method solves the power consumption and resource waste caused by the query of a BTB in the instruction prediction process; the BTB does not need to be queried in sequence, and the query power consumption and resources are effectively saved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an instruction prediction method, apparatus, electronic device, medium, and product. Background Technology

[0002] In the pipeline design of modern high-performance processors, to continuously supply instructions to the execution units, the instruction fetch unit must predict the behavior of a branch instruction before the actual execution result (i.e., whether to jump and where to jump) is calculated, and fetch the instruction from the predicted path in advance. The accuracy of this prediction directly affects processor performance. Incorrect predictions cause the pipeline to be flushed, requiring re-fetching from the correct path, resulting in a performance loss of tens of clock cycles. Therefore, the Branch Prediction Unit (BPU) is the core and key component of processor front-end design.

[0003] During each fetch cycle, the BPU queries the Branch Target Buffer (BTB) based on the current PC address. If a hit occurs, the BPU considers the instruction being fetched to be a branch instruction and retrieves its predicted target address from the BTB. If a miss occurs, the current instruction is not considered a branch, and the fetch unit continues fetching the next instruction in sequence (e.g., PC+4).

[0004] The classic prediction mechanism described above is designed entirely around improving the accuracy of predicting branch instructions themselves. It aims to determine the direction and target of a branch instruction as accurately as possible when encountering it. However, this classic framework has an inherent, unresolved efficiency problem: it requires querying the BTB (Branch Targeting) in every fetch cycle. For a long, sequential code block that doesn't contain any branches, each BTB query will result in an invalid miss. This continuous querying leads to significant power consumption and resource waste. Summary of the Invention

[0005] This application provides an instruction prediction method, apparatus, electronic device, medium, and product to save query power consumption and resources.

[0006] According to one aspect of this application, an instruction prediction method is provided, comprising:

[0007] Obtain the address of the prediction block, and predict the branch instruction based on the address of the prediction block;

[0008] If the prediction block contains a branch instruction, the prediction block is taken as the prediction block to be monitored, the monitoring of the prediction block to be monitored is started, and the first branch target cache entry information corresponding to the prediction block to be monitored is updated according to the monitoring results. The first branch target cache entry information includes at least: branch span distance information.

[0009] If the predicted block does not contain a branch instruction, the next predicted block is determined based on the branch scramble distance information in the first branch target cache entry information corresponding to the predicted block to achieve instruction scramble, and the next predicted block is used as a new predicted block. The process then returns to the step of obtaining the address of the predicted block.

[0010] According to another aspect of this application, an instruction prediction apparatus is provided, comprising:

[0011] A branch prediction unit is used to obtain the address of the prediction block and predict branch instructions based on the address of the prediction block.

[0012] A branch span distance monitoring unit is used to, if the prediction block contains a branch instruction, take the prediction block as a prediction block to be monitored, start monitoring the prediction block to be monitored, and update the first branch target cache entry information corresponding to the prediction block to be monitored according to the monitoring results. The first branch target cache entry information includes at least: branch span distance information.

[0013] The branch prediction unit is configured to, if the predicted block does not contain a branch instruction, determine the next predicted block based on the branch traversal distance information in the first branch target cache entry information corresponding to the predicted block to achieve instruction traversal, and use the next predicted block as a new predicted block, and return to the step of obtaining the address of the predicted block.

[0014] According to another aspect of this application, an electronic device is provided, the electronic device comprising:

[0015] At least one processor, and a memory communicatively connected to said at least one processor;

[0016] The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the instruction prediction method described in any embodiment of this application.

[0017] According to another aspect of this application, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the instruction prediction method described in any embodiment of this application.

[0018] According to another aspect of this application, a computer program product is provided, the computer program product including a computer program that, when executed by a processor, implements the instruction prediction method described in any embodiment of this application.

[0019] The technical solution of this application embodiment obtains the address of the prediction block and predicts branch instructions based on the address of the prediction block; if the prediction block contains branch instructions, the prediction block is designated as a prediction block to be monitored, monitoring of the prediction block to be monitored is initiated, and the first branch target cache entry information corresponding to the prediction block to be monitored is updated based on the monitoring results. The first branch target cache entry information includes at least: branch traversal distance information; if the prediction block does not contain branch instructions, the next prediction block is determined based on the branch traversal distance information in the first branch target cache entry information corresponding to the prediction block to achieve instruction traversal, and the next prediction block is designated as a new prediction block. The process of obtaining the prediction block is then returned. The steps for addressing the problem are as follows: This solves the power consumption and resource waste caused by querying the BTB during instruction prediction; In this embodiment, the branch span distance is stored in the first branch target cache entry information. During instruction prediction, if the predicted block contains a branch instruction, the predicted block is designated as the prediction block to be monitored, and monitoring of the prediction block to be monitored is initiated. The first branch target cache entry information corresponding to the prediction block to be monitored is updated according to the monitoring results. If the predicted block does not contain a branch instruction, the next predicted block is determined according to the branch span distance information in the first branch target cache entry information corresponding to the predicted block. This achieves instruction spanning without sequentially querying the BTB, and can span predicted blocks that do not contain branch instructions, effectively saving query power consumption and resources.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of an instruction prediction method provided according to Embodiment 1 of this application;

[0023] Figure 2 This is a flowchart of an instruction prediction method provided according to Embodiment 2 of this application;

[0024] Figure 3 This is an example diagram of branch target cache entry information provided according to Embodiment 2 of this application;

[0025] Figure 4 This is an example diagram of monitoring and recording information provided according to Embodiment 2 of this application;

[0026] Figure 5 This is an example diagram illustrating the implementation of instruction prediction according to Embodiment 2 of this application;

[0027] Figure 6 This is a flowchart illustrating a branch-crossing distance update according to Embodiment 2 of this application;

[0028] Figure 7 This is a schematic diagram of the structure of an instruction prediction device according to Embodiment 3 of this application;

[0029] Figure 8 This is a schematic diagram of the structure of an electronic device that implements the instruction prediction method of the embodiments of this application. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Example 1

[0033] Figure 1This is a flowchart illustrating an instruction prediction method provided in Embodiment 1 of this application. This embodiment is applicable to situations involving instruction prediction. The method can be executed by an instruction prediction device, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes:

[0034] S101. Obtain the address of the prediction block and predict the branch instruction based on the address of the prediction block.

[0035] In this embodiment, a prediction block refers to an instruction set containing multiple instructions. In modern superscalar processors, to meet the requirement of parallel execution of multiple instructions, instruction fetching is not performed one instruction at a time, but rather in units of a fixed-size instruction set, fetching multiple instructions from the instruction cache within one clock cycle. This instruction set, processed uniformly in the context of branch prediction and instruction fetching, is called a prediction block. The prediction block is determined by directly obtaining its address. The prediction block can be the first prediction block in the branch instruction prediction process, or any prediction block in the prediction process. Branch instructions are predicted based on the address of the prediction block to determine whether it contains branch instructions. For example, the historical execution process of the prediction block can be used to determine whether it contains branch instructions, and this information is saved. When predicting this prediction block again, the historical data can be used to directly determine whether it contains branch instructions.

[0036] S102. If the prediction block contains branch instructions, the prediction block is taken as the prediction block to be monitored, the monitoring of the prediction block to be monitored is started, and the information of the first branch target cache entry corresponding to the prediction block to be monitored is updated according to the monitoring results. The information of the first branch target cache entry includes at least: branch span distance information.

[0037] In this embodiment, the prediction block to be monitored can be understood as a prediction block with monitoring requirements. This embodiment monitors the branch scrambling distance of the prediction block to be monitored. The first branch target cache entry information can be understood as the branch target cache entry information corresponding to the prediction block to be monitored. In this embodiment, the first branch target cache entry information includes at least branch scrambling distance information, which is used to indicate how many prediction blocks need to be skipped next.

[0038] If the predicted block contains branch instructions, it is designated as the predicted block to be monitored, and monitoring of this predicted block is initiated, including monitoring the branch span distance of the predicted block to be monitored. Monitoring of the predicted block to be monitored can involve checking whether subsequent predicted blocks contain branch instructions, with the monitoring result indicating whether branch instructions are present or absent, etc. The first branch target cache entry information corresponding to the predicted block to be monitored is determined; for example, a correspondence between predicted blocks and their corresponding branch target cache entry information is pre-established, and the first branch target cache entry information corresponding to the predicted block to be monitored is determined based on this correspondence; alternatively, branch tags are stored in the branch target cache entry information, and the predicted block to be monitored is matched with the branch tags in each branch target cache entry information to determine the corresponding first branch target cache entry information. Matching the predicted block to be monitored with the branch tags in each branch target cache entry information can involve matching the high-order bits of the address of the predicted block to be monitored with the branch tags. Based on the monitoring results, the information of the first branch target cache entry corresponding to the prediction block to be monitored is updated. Updating the information of the first branch target cache entry can be done by updating the branch span distance information in the information of the first branch target cache entry, thereby realizing the monitoring and updating of the branch span distance. For example, if the next prediction block is found to contain a branch instruction, the branch span distance in the information of the first branch target cache entry corresponding to the prediction block to be monitored remains unchanged. If the next prediction block is found not to contain a branch instruction, the branch span distance in the information of the first branch target cache entry corresponding to the prediction block to be monitored is incremented by 1, and so on.

[0039] S103. If the prediction block does not contain branch instructions, determine the next prediction block according to the branch span distance information in the first branch target cache entry information corresponding to the prediction block to achieve instruction span, and take the next prediction block as the new prediction block, and return to execute S101.

[0040] If the predicted block does not contain branch instructions, determine the first branch target cache entry information corresponding to the predicted block, query the first branch target cache entry information to determine the branch span distance information it contains, and determine the next predicted block based on the branch span distance to achieve instruction traversal. During instruction prediction, predictive blocks that do not contain branch instructions are traversed. For traversed predictive blocks, it is not necessary to query the branch target cache entry information of this part of the predicted block. The next predicted block is taken as the new predicted block, and the process returns to the step of obtaining the address of the predicted block to continue to determine whether to monitor the new predicted block.

[0041] In this embodiment, after obtaining the address of the predicted block, it determines whether to detect the predicted block based on the prediction result of the branch instruction of the predicted block. If the detection of the predicted block is started, the predicted block is used as the predicted block to be monitored until the first branch target cache entry information of the predicted block to be monitored is updated. If the detection of the predicted block is not started, the next predicted block is determined directly based on the branch traversal distance information in the first branch target cache entry information corresponding to the predicted block, thereby realizing instruction traversal and traversing predicted blocks that do not contain branch instructions, effectively saving query power consumption and resources.

[0042] This application provides an instruction prediction method that solves the power consumption and resource waste caused by querying the BTB during instruction prediction. This application stores the branch span distance in the first branch target cache entry information. During instruction prediction, if the predicted block contains a branch instruction, the predicted block is designated as a prediction block to be monitored, monitoring of the prediction block to be monitored is initiated, and the first branch target cache entry information corresponding to the prediction block to be monitored is updated according to the monitoring results. If the predicted block does not contain a branch instruction, the next predicted block is determined based on the branch span distance information in the first branch target cache entry information corresponding to the predicted block. This achieves instruction spanning without sequentially querying the BTB, and can span prediction blocks that do not contain branch instructions, effectively saving query power consumption and resources.

[0043] Example 2

[0044] Figure 2 This is a flowchart of an instruction prediction method provided in Embodiment 2 of this application. This embodiment is a refinement based on the above embodiments. Figure 2 As shown, the method includes:

[0045] S201. Obtain the address of the prediction block and predict the branch instruction based on the address of the prediction block.

[0046] S202. If the prediction block contains branch instructions, the prediction block is taken as the prediction block to be monitored. The information of the first branch target cache entry corresponding to the prediction block to be monitored is queried to determine the next prediction block and the next prediction block is taken as the current prediction block.

[0047] In this embodiment, the current prediction block can be understood as the prediction block currently used to monitor the branch span distance of the prediction block to be monitored. If the prediction block contains a branch instruction, the prediction block is monitored as the prediction block to be monitored, the first branch target cache entry information corresponding to the prediction block to be monitored is determined, the branch span distance information in the first branch target cache entry information is queried, the next prediction block is determined based on the branch span distance information, and the next prediction block is used as the current prediction block.

[0048] S203. Obtain the address of the current prediction block and predict the branch instruction based on the address of the current prediction block.

[0049] The address of the current prediction block is obtained, and based on the address of the current prediction block and historical information, it is determined whether the current prediction block contains branch instructions. In this embodiment, the method for predicting branch instructions for different prediction blocks can be the same.

[0050] S204. Update the monitoring record information based on the prediction results. The monitoring record information shall include at least the branch crossing distance and branch jump information.

[0051] In this embodiment, the monitoring record information can be understood as information used to record relevant information generated during the monitoring process; the branch jump information is used to indicate whether to perform a branch jump, and the branch jump information can be a branch jump or a branch not jump.

[0052] Monitoring records are pre-built and updated in real time during the monitoring of the predicted block. After monitoring a predicted block is completed, the monitoring records are reset to allow monitoring of the next predicted block to continue. The monitoring records include at least branch span distance and branch jump information. Branch jump information can be determined simultaneously with the determination of the predicted block. For example, when determining the predicted block, the historical information of the branch prediction unit is queried using the address of the predicted block to determine whether the predicted block has jumped, thus determining the branch jump information and writing it into the monitoring records. During monitoring, the monitoring records are updated based on the prediction results of the branch instructions of the current predicted block. Updating the monitoring records can involve writing the branch jump information of the predicted block, determining the latest branch span distance of the predicted block, and updating it. For example, if the branch jump information has already been written into the monitoring records, only the branch span distance can be updated. That is, during the monitoring of the predicted block, the branch jump information of the predicted block remains unchanged after determination; only the branch span distance is updated.

[0053] Optionally, the monitoring record information can be updated based on the prediction results, including: if the prediction result is that the current prediction block does not contain branch instructions, the branch span distance in the monitoring record information can be incremented.

[0054] If the prediction result indicates that the current prediction block does not contain a branch instruction, increment the branch span distance in the monitoring record information, for example, by 1.

[0055] S205. If the entry update condition is met, update the first branch target cache entry information according to the monitoring record information, reset the monitoring record information, and end the monitoring of the prediction block to be monitored.

[0056] In this embodiment, the entry update condition can be understood as a condition used to determine whether to update the first branch target cache entry information. The entry update condition can be preset, and during the monitoring of the prediction block to be monitored, it is monitored in real time whether the entry update condition is met. If the entry update condition is detected to be met, it is determined that the first branch target cache entry information needs to be updated. The first branch target cache entry information is updated based on the branch span distance and branch jump information in the monitoring record information. For example, the branch jump information determines which field in the first branch target cache entry information to update, and then this field is updated based on the branch span distance. After completing the update of the first branch target cache entry information, the monitoring record information is reset, for example, the monitoring record information is cleared; the monitoring of the prediction block to be monitored ends.

[0057] Optionally, the entry update conditions include at least one of the following: the branch span distance in the monitoring record information exceeds a set distance threshold; the prediction result is that the current prediction block contains a branch instruction.

[0058] In this embodiment, the distance threshold can be preset, for example, the distance threshold is 5. If the branch crossing distance in the monitoring record information exceeds the set distance threshold, it can be considered that the entry update condition is met, and the first branch target cache entry information is updated; or, if the prediction result is that the current prediction block contains a branch instruction, it can be considered that the entry update condition is met, and the first branch target cache entry information is updated; or, if both of the above conditions are met, it can be considered that the entry update condition is met.

[0059] Optionally, the branch traversal distance information includes the branch jump traversal distance and the branch non-jump traversal distance; the monitoring record information also includes: branch target cache entry location information.

[0060] In this embodiment, the branch jump traversal distance can be understood as the distance that the instruction jumps across; the branch no-jump traversal distance can be understood as the distance that the instruction does not jump across. The branch target cache entry location information can be understood as the location information of the branch target cache entry information, that is, the location where the branch target cache entry information is located.

[0061] Optionally, the target cache entry information of the first branch is updated based on the monitoring record information, including steps A1-A3:

[0062] A1. Determine the location of the first branch target cache entry information based on the branch target cache entry location information in the monitoring record information.

[0063] Query the monitoring record information to determine the location information of the branch target cache entry in the monitoring record information. Based on the location information of the branch target cache entry, locate the first branch target cache entry information and determine the position of the first branch target cache entry information. For example, if the branch target cache entry location information is id=8, it means that the first branch target cache entry information is located in the 8th data in the data table.

[0064] A2. If the branch jump information in the monitoring record indicates a branch jump, based on the position of the first branch target cache entry information, update the branch jump span distance in the first branch target cache entry information according to the branch cross-domain distance in the monitoring record information.

[0065] The system determines the information indicated by the branch jump information in the monitoring record information. The branch jump information can indicate a branch jump or no branch jump. If it indicates a branch jump, the system determines the location of the first branch target cache entry information to be updated based on the location of the first branch target cache entry information. The system also obtains the branch cross-domain distance in the monitoring record information, queries the corresponding location to obtain the first branch target cache entry information, and updates the branch jump cross-domain distance in the first branch target cache entry information at the corresponding location by using the branch cross-domain distance. In other words, the system replaces the branch jump cross-domain distance stored in the first branch target cache entry information at the corresponding location with the branch cross-domain distance.

[0066] A3. If the branch jump information in the monitoring record indicates that the branch does not jump, based on the position of the first branch target cache entry information, update the branch non-jump traversal distance in the first branch target cache entry information according to the branch cross-domain distance in the monitoring record information.

[0067] If the branch jump information in the monitoring record indicates that the branch does not jump, then the location of the first branch target cache entry information to be updated is determined based on the location of the first branch target cache entry information, and the branch cross-domain distance in the monitoring record information is obtained. The first branch target cache entry information is obtained by querying the corresponding location, and the branch non-jump cross distance in the first branch target cache entry information at the corresponding location is updated by the branch cross distance. That is, the branch non-jump cross distance stored in the first branch target cache entry information at the corresponding location is replaced by the branch cross distance.

[0068] Optionally, the monitoring and recording information may also include: branch target cache entry location information; the first branch target cache entry information may also include branch label and branch position; the method may also include steps B1-B4:

[0069] B1. If the prediction block contains branch instructions, determine the branch position corresponding to the branch instructions in the prediction block.

[0070] In this embodiment, the branch position can be understood as information indicating the location of a branch instruction. If the prediction block contains a branch instruction, the location of the branch instruction in the prediction block is determined and recorded as the branch position. The prediction block contains multiple instructions, each of which may or may not be a branch instruction; that is, the number of branch instructions included in the prediction block can be 0, 1, or more. When performing branch prediction, if multiple branch instructions are predicted in the prediction block, only the branch position corresponding to the first branch instruction can be recorded. Subsequent branch instructions are usually skipped after the execution of the first branch instruction, so they do not need to be recorded.

[0071] B2. Determine the branch label based on the address of the predicted block.

[0072] The address of the branch prediction block is used to determine the corresponding branch label based on the conversion relationship between the address of the prediction block and the branch label. For example, the high-order information in the address of the prediction block can be extracted and used as the branch label, or the high-order information can be processed by an algorithm to convert it into a branch label, and so on.

[0073] B3. Query the branch target cache entry information based on the branch position and branch label, and determine the location information of the first matching branch target cache entry information.

[0074] Based on the branch position and branch label, query the stored multiple branch target cache entries, determine the position information of the first branch target cache entry that matches the branch position and branch label, that is, match the branch position and branch label with the branch position and branch label in each of the stored branch target cache entries, determine the successfully matched branch target cache entry, and use this branch target cache entry as the first branch target cache entry.

[0075] B4. Write the location information as branch target cache entry location information into the monitoring record information. The branch target cache entry location information is used to indicate the location of the first branch target cache entry information.

[0076] The location information of the first successfully matched branch target cache entry is written into the monitoring record information as the branch target cache entry location information. This branch target cache entry location information can indicate the location of the first branch target cache entry information, that is, indicate which branch target cache entry information this monitoring record information is used to update.

[0077] S206. If it is detected that the entry update condition is not met, determine the new current prediction block according to the branch span distance information in the second branch target cache entry information corresponding to the current prediction block, and return to execute S203.

[0078] If the entry update conditions are not met, monitoring of the prediction block to be monitored needs to continue. The second branch target cache entry information corresponding to the current prediction block is determined, the branch span distance information in the second branch target cache entry information is queried, and the next prediction block is determined based on the branch span distance information. This next prediction block is then used as the new current prediction block. In this embodiment, determining the next prediction block using the first branch target cache entry information is the same as determining the next prediction block using the second branch target cache entry information.

[0079] S207. If the prediction block does not contain branch instructions, determine the next prediction block according to the branch span distance information in the first branch target cache entry information corresponding to the prediction block to achieve instruction span, and take the next prediction block as the new prediction block, and return to execute S201.

[0080] Optionally, the branch traversal distance information includes: branch jump traversal distance and branch non-jump traversal distance, and the first branch target cache entry information also includes the branch target address.

[0081] In this embodiment, the branch target address can be understood as the address of the predicted block after the jump.

[0082] Optionally, the next prediction block is determined based on the branch strait distance information in the first branch target cache entry information corresponding to the prediction block, including: if the prediction block does not jump, the next prediction block is determined based on the address of the prediction block, the size of the prediction block, and the branch strait distance if the prediction block jumps, the next prediction block is determined based on the branch target address and the branch strait distance if the prediction block jumps.

[0083] To determine whether a predicted block needs to jump, the branch prediction unit can be queried. If the predicted block jumps, the span distance is determined based on the size of the predicted block and the non-jump distance of the branch. The next predicted block is then determined based on the cross-domain distance and the address of the predicted block. If the predicted block jumps, the span distance is determined based on the branch jump distance. The next predicted block is then determined based on the cross-domain distance and the branch target address to which the branch needs to jump.

[0084] Optionally, the next predicted block is determined based on the address of the predicted block, the size of the predicted block, and the branch non-jump distance, including: determining the length of the predicted block based on the size of the predicted block and a predetermined instruction byte length, denoted as the first length; determining the first distance based on the branch non-jump distance and the first length; and summing the address of the predicted block, the first length, and the first distance to obtain the address of the next predicted block.

[0085] The size of the prediction block can be preset. For example, a prediction block size of 8 indicates that the prediction block contains 8 instructions. The instruction byte length is used to represent the length of bytes occupied by the instruction. The instruction byte length is also predetermined; for example, the instruction byte length is 4. The product of the prediction block size and the instruction byte length is taken as the length of the prediction block, and this length is denoted as the first length. The product of the non-jump distance of the branch and the first length is taken as the first distance. The address of the prediction block, the first length, and the first distance are added together to obtain the address of the next prediction block.

[0086] Optionally, the next predicted block is determined based on the branch target address and the branch jump distance, including: determining the second distance based on the branch jump distance and the first length; and summing the branch target address and the second distance to obtain the address of the next predicted block.

[0087] Multiply the branch jump distance by the first length, and the product is called the second distance; add the branch target address and the second distance together to get the address of the next predicted block.

[0088] Optionally, the method further includes: when a prediction failure of a branch instruction in a prediction block is detected, clearing the branch span distance information in the first branch target cache entry information.

[0089] Instructions in the prediction block are executed sequentially. While the prediction block can be skipped during prediction, it executes normally during execution. When executing instructions in the prediction block, it can be determined whether there are branch instructions. If a branch instruction with a jump is detected in the skipped instruction segment, the branch prediction is considered to have failed, and the branch scramble distance information in the first branch target cache entry is cleared.

[0090] Optionally, the second branch target cache entry information may also include the branch target address.

[0091] Optionally, a new current prediction block is determined based on the branch strait distance information in the second branch target cache entry information corresponding to the current prediction block, including: if the current prediction block does not jump, a new current prediction block is determined based on the address of the current prediction block, the size of the prediction block, and the branch strait distance without jumping; if the current prediction block jumps, a new current prediction block is determined based on the branch target address and the branch strait distance.

[0092] Optionally, a new current prediction block is determined based on the address of the current prediction block, the size of the prediction block, and the branch-without-jump distance, including: determining the length of the prediction block based on the size of the prediction block and a predetermined instruction byte length, denoted as the first length; determining the first distance based on the branch-without-jump distance and the first length; and summing the address of the current prediction block, the first length, and the first distance to obtain the address of the new current prediction block.

[0093] Optionally, a new current prediction block is determined based on the branch target address and the branch jump distance, including: determining a third distance based on the branch jump distance and the first length; and summing the branch target address and the third distance to obtain the address of the new current prediction block.

[0094] It should be noted that the principle for determining the next prediction block and the new current prediction block in this application embodiment is the same. The branch strapping distance information and the branch target address included in the first branch target cache entry information and the second branch target cache entry information may be different. Therefore, the results obtained may be different. Among them, the difference in branch strapping distance information may be at least one of the branch jump strapping distance and the branch non-jump strapping distance.

[0095] For example, Figure 3An example diagram of branch target cache entry information is provided, which can also be called BTB entry information. The branch target cache entry information includes branch jump distance, branch non-jump distance, branch target address, branch label, branch position, and entry validity information. The entry validity information indicates whether the BTB entry is valid. Typically, when the branch prediction unit predicts a prediction block for the first time, it determines the branch target address, branch label, branch position, and entry validity information and writes them into the BTB entry information. At this time, the branch jump distance and branch non-jump distance corresponding to this prediction block do not yet have corresponding values. When the prediction block is predicted again in subsequent iterations, the corresponding branch jump distance and branch non-jump distance are generated and updated in the BTB entry information. This embodiment adds a branch jump distance to the traditional BTB entry, which represents how many prediction blocks need to be skipped next. Assuming the prediction block width is 8, which is 8 instructions, and one instruction occupies a fixed number of bytes in most modern processors, typically 4 bytes (32-bit instruction). Therefore, the byte length corresponding to 8 instructions is 32 bytes. The address of the currently predicted instruction is PCA (i.e., the address of the prediction block is PCA). If the branch does not jump and the distance spanned by the non-jumping branch is 0, then the next branch prediction unit executes the normal prediction process, and the predicted address is PCA+32 (the CPU's program counter (PC) points to the byte address of the instruction, not the instruction sequence number. If the current instruction address is PCA, the address of the next instruction is PCA+4 (assuming an instruction is 4 bytes). The address corresponding to 8 instructions is: PCA+8×4=PCA+32). If the branch does not jump and the distance spanned by the non-jumping branch is 3, then the next branch prediction unit executes the normal prediction process, and the predicted address is PCA+32+96. If the branch jumps, the target address of the jump is PCB. If the branch jump distance is 0, then the next branch prediction unit executes the normal prediction process, and the predicted address is PCB. If the branch jump distance is 2, then the next branch prediction unit executes the normal prediction process, and the predicted address is PCB+64. When the fetching unit receives the prediction information from the branch prediction unit, it needs to split the prediction block according to the branch span distance. For example, if PCA is used for prediction, and the branch does not jump and the branch span distance is 3, then the fetching unit needs to split it into 3 fetching blocks: PCA, PCA+32, and PCA+64.

[0096] Figure 4An example diagram of monitoring record information is provided. This information includes branch scramble distance, branch jump information, BTB entry location information (i.e., branch target cache entry location information), and monitoring information validity information. The BTB entry location information indicates the position of the monitored branch instruction within the BTB entry, so that when updating the scramble distance information at the end of monitoring, it can be determined which BTB entry to update. The branch jump information indicates whether the branch instruction jumps or not, representing where the branch scramble distance in the monitoring record information should be updated. The branch scramble distance is the number of prediction blocks that need to be scrambled. During the update of the BTB entry information, if the branch scramble distance stored in the BTB entry information is the same as the branch scramble distance detected this time, no update is needed; otherwise, the branch scramble distance information is updated according to the current branch scramble distance. The branch scramble distance originally stored in the BTB entry information can also be called the old branch scramble distance, representing the branch scramble distance predicted during the prediction phase, used to determine whether this scramble distance needs to be updated. The monitoring information validity information indicates whether the monitoring record information is valid.

[0097] Figure 5This document provides an example diagram of instruction prediction implementation, where instructions are executed by a branch execution unit. The branch prediction unit predicts branch instructions for prediction blocks, while the branch span distance monitoring unit monitors the prediction blocks to be monitored. The specific workflow is as follows: When a prediction block is predicted to contain a branch instruction based on its PCA, the prediction information for that branch instruction is sent to the branch span distance monitoring unit. This prediction information includes one or more of the following: whether the instruction is a branch instruction, the jump target, and the jump direction (i.e., whether a jump occurs). After determining that the prediction block contains a branch instruction, the branch prediction unit queries the BTB entry information to identify the matched BTB entry for subsequent updates. Upon receiving the prediction information, the branch span distance monitoring unit initiates monitoring and continuously monitors the prediction information from the branch prediction unit. After each prediction block is completed, the branch prediction unit sends its prediction information to the branch span distance monitoring unit. If no branch prediction information is found, it means that the subsequent prediction block does not contain any branch instructions, or even if branch instructions exist, they have not been updated in the branch prediction unit, and a query will not yield any results. After each prediction of a block without branch instructions, the branch span distance recorded by the branch span distance monitoring unit is incremented by one until the branch span distance reaches a preset distance threshold, or the branch prediction unit predicts a new branch instruction. At this point, the monitoring by the branch span distance monitoring unit ends, and the detected branch span distance is sent to the branch prediction unit to update the corresponding BTB entry. When the branch execution unit finds a jump branch instruction in the spanned instruction, that is, when the branch prediction fails, the relevant entries of the branch span distance information stored in the BTB are cleared directly.

[0098] Figure 6 A flowchart illustrating branch distance-based updates is provided, comprising the following steps:

[0099] S1. Obtain branch prediction information.

[0100] The branch prediction information may include the address of the prediction block.

[0101] S2. Determine if there is a branch instruction in the prediction block. If yes, execute S3; otherwise, return to execute S1.

[0102] S3. Start monitoring.

[0103] The predicted block is monitored as a prediction block to be monitored.

[0104] S4. Does the next prediction block contain a branch instruction or has a branch spanning a distance threshold? If not, proceed to S5; if yes, proceed to S6.

[0105] S5, increment the branch span distance by 1, and return to execute S4.

[0106] S6. End monitoring.

[0107] S7. Determine if the crossing distance has changed. If yes, execute S8; otherwise, execute S9.

[0108] Specifically, it determines whether the branch crossing distance recorded in the monitoring record information is the same as the branch crossing distance information originally stored in the BTB entry information. If they are the same, then execute S9; if they are different, then execute S8.

[0109] S8, Update branch span distance.

[0110] S9. Do not update branch span distance.

[0111] This application provides an instruction prediction method that overcomes the inherent defects in processing sparse branch instruction streams, resulting in significant energy efficiency improvements, higher prediction intelligence, and dynamic adaptive capabilities. By monitoring and recording the monitoring results of the block to be predicted, and updating the branch target cache entry information after meeting the entry update conditions, accurate prediction across distances is achieved. During the prediction of the block, the next prediction block is determined by whether the branch jumps across the distance or not, thus achieving block skipping and reducing invalid queries. Through accurate distance prediction, redundant BTB queries are fundamentally eliminated, significantly reducing power consumption and optimizing front-end performance. The blind, continuous invalid queries in existing technologies are transformed into a highly efficient mode of one prediction and N skips, directly avoiding significant SRAM read / write power consumption and significantly reducing the overall power consumption of the processor front-end. Simultaneously, by bypassing the critical path of BTB queries, conditions are created for increasing processor operating frequency or reducing front-end pipeline latency.

[0112] Example 3

[0113] Figure 7 This is a schematic diagram of the structure of an instruction prediction device provided in Embodiment 3 of this application. Figure 7 As shown, the device includes: a branch prediction module 31, a monitoring module 32, and a next prediction block determination module 33.

[0114] Branch prediction module 31 is used to obtain the address of the prediction block and predict the branch instruction based on the address of the prediction block.

[0115] The monitoring module 32 is used to, if the prediction block contains a branch instruction, take the prediction block as a prediction block to be monitored, start monitoring the prediction block to be monitored, and update the first branch target cache entry information corresponding to the prediction block to be monitored according to the monitoring results. The first branch target cache entry information includes at least: branch span distance information.

[0116] The next prediction block determination module 33 is used to determine the next prediction block to achieve instruction crossing based on the branch crossing distance information in the first branch target cache entry information corresponding to the prediction block if the prediction block does not contain branch instructions, and to use the next prediction block as a new prediction block and return to the step of obtaining the address of the prediction block.

[0117] This application provides an instruction prediction device that solves the power consumption and resource waste caused by querying the BTB during instruction prediction. This application stores the branch span distance in the first branch target cache entry information. During instruction prediction, if the predicted block contains a branch instruction, the predicted block is designated as a prediction block to be monitored, monitoring of the prediction block to be monitored is initiated, and the first branch target cache entry information corresponding to the prediction block to be monitored is updated according to the monitoring results. If the predicted block does not contain a branch instruction, the next predicted block is determined based on the branch span distance information in the first branch target cache entry information corresponding to the predicted block. This achieves instruction spanning without sequentially querying the BTB, and can span predicted blocks that do not contain branch instructions, effectively saving query power consumption and resources.

[0118] Optionally, monitoring module 32 includes:

[0119] The current prediction block determination unit is used to query the first branch target cache entry information corresponding to the prediction block to be monitored, determine the next prediction block, and take the next prediction block as the current prediction block.

[0120] The instruction prediction unit is used to obtain the address of the current prediction block and predict branch instructions based on the address of the current prediction block.

[0121] The monitoring information update unit is used to update the monitoring record information according to the prediction results. The monitoring record information includes at least the branch crossing distance and branch jump information.

[0122] An entry update unit is used to update the first branch target cache entry information according to the monitoring record information if the entry update condition is detected, reset the monitoring record information, and end the monitoring of the prediction block to be monitored.

[0123] A new prediction block determination unit is used to determine a new current prediction block based on the second branch target cache entry information corresponding to the current prediction block if the entry update condition is not detected, and return to the step of obtaining the address of the current prediction block.

[0124] Optionally, the monitoring information update unit is specifically used to: if the prediction result is that the current prediction block does not contain a branch instruction, increment the branch span distance in the monitoring record information.

[0125] Optionally, the branch traversal distance information includes the branch jump traversal distance and the branch non-jump traversal distance; the monitoring record information also includes: branch target cache entry location information;

[0126] Optionally, the entry update unit is specifically configured to: determine the position of the first branch target cache entry information based on the branch target cache entry position information in the monitoring record information; if the branch jump information in the monitoring record information indicates a branch jump, update the branch jump span distance in the first branch target cache entry information based on the position of the first branch target cache entry information and the branch cross-domain distance in the monitoring record information; if the branch jump information in the monitoring record information indicates no branch jump, update the branch no jump span distance in the first branch target cache entry information based on the position of the first branch target cache entry information and the branch cross-domain distance in the monitoring record information.

[0127] Optionally, the monitoring record information further includes: branch target cache entry location information; the first branch target cache entry information further includes branch tag and branch location;

[0128] Optionally, the device may also include:

[0129] A branch position determination module is used to determine the branch position corresponding to the branch instruction in the prediction block if the prediction block contains a branch instruction.

[0130] A branch label determination module is used to determine the branch label based on the address of the prediction block;

[0131] The location information determination module is used to query branch target cache entry information based on the branch position and the branch label, and determine the location information of the matching first branch target cache entry information.

[0132] The location information writing module is used to write the location information as the branch target cache entry location information into the monitoring record information, and the branch target cache entry location information is used to indicate the location of the first branch target cache entry information.

[0133] Optionally, the entry update conditions include at least one of the following: the branch span distance in the monitoring record information exceeds a set distance threshold; the prediction result is that the current prediction block contains a branch instruction.

[0134] Optionally, the branch traversal distance information includes: branch jump traversal distance and branch non-jump traversal distance, and the first branch target cache entry information also includes the branch target address;

[0135] Optionally, the next prediction block determination module 33 includes:

[0136] The first prediction block determination unit is used to determine the next prediction block based on the address of the prediction block, the size of the prediction block, and the distance spanned by the branch without jumping if the prediction block does not jump.

[0137] The second prediction block determination unit is used to determine the next prediction block based on the branch target address and the branch jump distance if the prediction block jumps.

[0138] Optionally, the first prediction block determination unit is specifically used for: determining the length of the prediction block based on the size of the prediction block and a predetermined instruction byte length, denoted as the first length; determining the first distance based on the branch non-jump crossing distance and the first length; and summing the address of the prediction block, the first length, and the first distance to obtain the address of the next prediction block.

[0139] Optionally, the second prediction block determination unit is specifically used for: determining a second distance based on the branch jump traversal distance and the first length; summing the branch target address and the second distance to obtain the address of the next prediction block.

[0140] Optionally, the device may also include:

[0141] The clearing module is used to clear the branch span distance information in the first branch target cache entry information when the prediction of the branch instruction of the prediction block fails.

[0142] The instruction prediction device provided in this application can execute the instruction prediction method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects of the execution method.

[0143] Example 4

[0144] Figure 8A schematic diagram of an electronic device 40 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0145] like Figure 8 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded from storage unit 48 into the RAM 43. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0146] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0147] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as instruction prediction methods.

[0148] In some embodiments, the instruction prediction method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the instruction prediction method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to execute the instruction prediction method by any other suitable means (e.g., by means of firmware).

[0149] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0150] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0151] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements the instruction prediction method described in any embodiment of this application.

[0152] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0153] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0154] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0155] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0156] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0157] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An instruction prediction method, characterized in that, include: Obtain the address of the prediction block, and predict the branch instruction based on the address of the prediction block; If the prediction block contains a branch instruction, the prediction block is taken as the prediction block to be monitored, the monitoring of the prediction block to be monitored is started, and the first branch target cache entry information corresponding to the prediction block to be monitored is updated according to the monitoring results. The first branch target cache entry information includes at least: branch span distance information. If the predicted block does not contain a branch instruction, the next predicted block is determined based on the branch scramble distance information in the first branch target cache entry information corresponding to the predicted block to achieve instruction scramble, and the next predicted block is used as a new predicted block. The process then returns to the step of obtaining the address of the predicted block. The step of initiating monitoring of the prediction block to be monitored and updating the first branch target cache entry information corresponding to the prediction block to be monitored based on the monitoring results includes: Query the first branch target cache entry information corresponding to the prediction block to be monitored, determine the next prediction block, and use the next prediction block as the current prediction block; Obtain the address of the current prediction block, and predict the branch instruction based on the address of the current prediction block; The monitoring record information is updated based on the prediction results, and the monitoring record information includes at least the branch crossing distance and branch jump information; If the entry update condition is met, the first branch target cache entry information is updated according to the monitoring record information, the monitoring record information is reset, and the monitoring of the prediction block to be monitored ends. If the entry update condition is not met, a new current prediction block is determined based on the branch span distance information in the second branch target cache entry information corresponding to the current prediction block, and the process returns to the step of obtaining the address of the current prediction block. The branch traversal distance information includes the branch jump traversal distance and the branch non-jump traversal distance; the monitoring record information also includes: branch target cache entry location information; The step of updating the first branch target cache entry information based on the monitoring record information includes: The location of the first branch target cache entry information is determined based on the branch target cache entry location information in the monitoring record information; If the branch jump information in the monitoring record information indicates a branch jump, the branch jump span distance in the first branch target cache entry information is updated based on the position of the first branch target cache entry information and the branch cross-domain distance in the monitoring record information. If the branch jump information in the monitoring record information indicates that the branch does not jump, the branch non-jump distance in the first branch target cache entry information is updated based on the position of the first branch target cache entry information and the branch cross-domain distance in the monitoring record information.

2. The method according to claim 1, characterized in that, The step of updating the monitoring record information based on the prediction results includes: If the prediction result indicates that the current prediction block does not contain a branch instruction, the branch span distance in the monitoring record information is incremented.

3. The method according to claim 1, characterized in that, The monitoring record information also includes: branch target cache entry location information; the first branch target cache entry information also includes branch tag and branch location; and further includes: If the prediction block contains a branch instruction, determine the branch position corresponding to the branch instruction in the prediction block; The branch label is determined based on the address of the predicted block; Based on the branch position and the branch label, query the branch target cache entry information to determine the location information of the matching first branch target cache entry information; The location information is written into the monitoring record information as the branch target cache entry location information, and the branch target cache entry location information is used to indicate the location of the first branch target cache entry information.

4. The method according to claim 1, characterized in that, The entry update conditions include at least one of the following: The branch spans a distance exceeding a set distance threshold in the monitoring record information; The prediction result is that the current prediction block contains a branch instruction.

5. The method according to any one of claims 1-4, characterized in that, Also includes: When the prediction of the branch instruction of the prediction block fails, the branch span distance information in the first branch target cache entry information is cleared.

6. An instruction prediction device, characterized in that, include: The branch prediction module is used to obtain the address of the prediction block and predict the branch instruction based on the address of the prediction block. The monitoring module is used to, if the prediction block contains a branch instruction, take the prediction block as a prediction block to be monitored, start monitoring the prediction block to be monitored, and update the first branch target cache entry information corresponding to the prediction block to be monitored according to the monitoring results. The first branch target cache entry information includes at least: branch span distance information. The next prediction block determination module is used to determine the next prediction block to achieve instruction crossing based on the branch crossing distance information in the first branch target cache entry information corresponding to the prediction block if the prediction block does not contain a branch instruction, and to use the next prediction block as a new prediction block and return to the step of obtaining the address of the prediction block. The monitoring module includes: The current prediction block determination unit is used to query the first branch target cache entry information corresponding to the prediction block to be monitored, determine the next prediction block, and take the next prediction block as the current prediction block. The instruction prediction unit is used to obtain the address of the current prediction block and predict branch instructions based on the address of the current prediction block. The monitoring information update unit is used to update the monitoring record information according to the prediction results. The monitoring record information includes at least the branch crossing distance and branch jump information. An entry update unit is used to update the first branch target cache entry information according to the monitoring record information if the entry update condition is detected, reset the monitoring record information, and end the monitoring of the prediction block to be monitored. A new prediction block determination unit is used to determine a new current prediction block based on the second branch target cache entry information corresponding to the current prediction block if the entry update condition is not detected, and return to the step of obtaining the address of the current prediction block. The branch spanning distance information includes the branch jump spanning distance and the branch non-jump spanning distance; The monitoring record information also includes: branch target cache entry location information; The entry update unit is specifically used for: The location of the first branch target cache entry information is determined based on the branch target cache entry location information in the monitoring record information; If the branch jump information in the monitoring record information indicates a branch jump, the branch jump span distance in the first branch target cache entry information is updated based on the position of the first branch target cache entry information and the branch cross-domain distance in the monitoring record information. If the branch jump information in the monitoring record information indicates that the branch does not jump, the branch non-jump distance in the first branch target cache entry information is updated based on the position of the first branch target cache entry information and the branch cross-domain distance in the monitoring record information.

7. An electronic device, characterized in that, The electronic device includes: At least one processor, and a memory communicatively connected to said at least one processor; The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the instruction prediction method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the instruction prediction method of any one of claims 1-5.

9. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the instruction prediction method according to any one of claims 1-5.

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