Meta-thread scheduling methods, electronic devices, and computer-readable storage media

Abstract

This disclosure provides a meta-thread scheduling method, an electronic device, and a computer-readable storage medium. The method includes: firstly, acquiring a meta-thread scheduling queue and first workload information of resident meta-threads in each functional unit; then, determining a target unit from multiple functional units based on the first workload information of the resident meta-threads, wherein the target unit is the functional unit with the lowest workload level; next, determining a target meta-thread from multiple pending meta-threads in the meta-thread scheduling queue; and finally, scheduling the target meta-thread to the target unit. In this disclosure, by selecting the functional unit with the lowest workload level as the target unit, load balancing among multiple functional units is achieved. Furthermore, by optimizing the meta-thread scheduling strategy and scheduling meta-threads to the functional unit with the lowest workload level, the latency of multi-thread processing is reduced, enabling the computing system to handle large-scale parallel computing tasks more efficiently.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a meta-thread scheduling method, electronic device, and computer-readable storage medium. Background Technology

[0002] In the field of parallel computing, multi-threaded concurrent execution technology is widely used in computing devices such as graphics processing units (GPUs) and artificial intelligence accelerators to improve processing efficiency. These computing devices typically require basic computing components (such as arithmetic logic units) to perform core functions such as control flow management, data scheduling, and auxiliary calculations, and distribute and coordinate computing tasks through control thread bundles.

[0003] In existing technologies, the parallel execution of multiple thread bundles typically relies on a single arithmetic logic unit (ALU). Specifically, when multiple independent thread bundles are scheduled to the same ALU and processed sequentially to perform basic operations, resource contention for the ALU occurs between different thread bundles. This leads to frequent queuing of computational tasks, significantly increasing overall processing latency and reducing the utilization of computing resources. Summary of the Invention

[0004] This disclosure provides a meta-thread scheduling method, an electronic device, and a computer-readable storage medium, which realizes load balancing among multiple functional units, reduces multi-thread processing latency, and enables the computing system to process large-scale parallel computing tasks more efficiently.

[0005] According to one aspect of this disclosure, a meta-thread scheduling method is provided, characterized in that it is applied to a scheduling unit, the scheduling unit being communicatively connected to multiple functional units; the meta-thread scheduling method includes:

[0006] Obtain the meta-thread scheduling queue and the first workload information of the resident meta-threads of each functional unit;

[0007] The target unit is determined from the plurality of functional units based on the first workload information of the resident meta thread, wherein the target unit is the functional unit with the lowest workload level;

[0008] The target meta-thread is determined from the multiple meta-threads to be executed in the meta-thread scheduling queue;

[0009] The target meta-thread is scheduled to the target unit.

[0010] In some embodiments, the functional unit is a scalar processing unit, and the first workload information includes a first preset workload weight and a first scalar operation count for the resident meta-thread of each scalar processing unit. The step of determining the target unit from the plurality of functional units based on the first workload information of the resident meta-thread includes:

[0011] The first expected workload weight of the scalar processing unit where the resident meta-thread is located is calculated based on the first preset workload weight of the resident meta-thread, wherein the first expected workload weight is proportional to the workload level of the scalar processing unit.

[0012] The first expected workload weights of all the scalar processing units are traversed, and the scalar processing unit with the smallest first expected workload weight is determined as the target unit.

[0013] In some embodiments, the first workload information includes the first number of scalar operations performed by the resident metathread of each scalar processing unit, and the method further includes:

[0014] The first expected number of operations of the scalar processing unit where the resident meta-thread is located is calculated based on the first scalar operation count of the resident meta-thread, wherein the first expected number of operations is proportional to the workload level of the scalar processing unit;

[0015] The first expected number of operations is traversed for all the scalar processing units, and the scalar processing unit with the fewest first expected number of operations is determined as the target unit.

[0016] In some embodiments, determining the target meta-thread from a plurality of pending meta-threads in the meta-thread scheduling queue includes:

[0017] The second workload information of each meta-thread to be executed is obtained based on the meta-thread scheduling queue. The second workload information includes the second preset workload weight of the meta-thread to be executed.

[0018] All the pending meta-threads in the meta-thread scheduling queue are sorted in descending order of their second preset workload weights, and the pending meta-thread with the largest second preset workload weight in the meta-thread scheduling queue is determined as the target meta-thread.

[0019] In some embodiments, the second workload information further includes the second scalar operation count of the meta-thread to be executed, and the method further includes:

[0020] All the pending metathreads in the metathread scheduling queue are sorted in order of the number of second scalar operations performed on the pending metathreads, from most to least, and the pending metathread with the most second scalar operations in the metathread scheduling queue is determined as the target metathread.

[0021] In some embodiments, scheduling the target meta-thread to the target unit includes:

[0022] The target meta-thread is scheduled to the target unit, and the second expected workload weight of the target unit is increased according to the third preset workload weight of the target meta-thread.

[0023] In some embodiments, the method further includes:

[0024] After the target unit completes a first preset number of scalar operations, the second expected workload weight of the target unit is reduced based on the first preset value.

[0025] In some embodiments, scheduling the target meta-thread to the target unit includes:

[0026] The target meta-thread is scheduled to the target unit, and the second expected number of operations of the target unit is increased according to the third scalar operation count of the target meta-thread.

[0027] In some embodiments, the method further includes:

[0028] After the target unit performs a scalar operation, the second expected number of operations of the target unit is reduced based on a second preset value.

[0029] According to one aspect of this disclosure, an electronic device is proposed, characterized in that the electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection communication between the processor and the memory, wherein the program is executed by the processor to implement the meta-thread scheduling method as described above.

[0030] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores one or more programs, which can be executed by one or more processors to implement the meta-thread scheduling method described above.

[0031] The present disclosure discloses a meta-thread scheduling method, electronic device, and computer-readable storage medium. The method includes: firstly, acquiring a meta-thread scheduling queue and first workload information of resident meta-threads in each functional unit; then, determining a target unit from multiple functional units based on the first workload information of the resident meta-threads, wherein the target unit is the functional unit with the lowest workload level; next, determining a target meta-thread from multiple pending meta-threads in the meta-thread scheduling queue; and finally, scheduling the target meta-thread to the target unit. In this disclosure, by selecting the functional unit with the lowest workload level as the target unit, load balancing among multiple functional units is achieved. Furthermore, by optimizing the meta-thread scheduling strategy and scheduling meta-threads to the functional unit with the lowest workload level, the latency of multi-thread processing is reduced, enabling the computing system to handle large-scale parallel computing tasks more efficiently.

[0032] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objectives and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0033] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0034] Figure 1 This is a system architecture diagram of a system applying the meta-thread scheduling method of the present disclosure embodiments;

[0035] Figure 2 This is a schematic diagram illustrating the relationship between meta-threads, ordinary worker threads, thread bundles, thread blocks, and thread clusters in one embodiment of this disclosure;

[0036] Figure 3 This is a main flowchart of a meta-thread scheduling method according to an embodiment of this disclosure;

[0037] Figure 4 yes Figure 3 A flowchart of a sub-step of one embodiment of step S302;

[0038] Figure 5 yes Figure 3 A flowchart of a sub-step of another embodiment of step S302;

[0039] Figure 6 yes Figure 3 A flowchart of a sub-step of one embodiment of step S303;

[0040] Figure 7This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this disclosure.

[0042] Before providing a further detailed description of the embodiments of this disclosure, the terms and concepts used in these embodiments are explained, and they are subject to the following interpretations:

[0043] Chip: A chip typically refers to an integrated circuit, a miniature electronic device that integrates circuitry onto a tiny silicon wafer. Chips are widely used in various electronic devices, such as computers, mobile phones, and automobiles, to perform various functions, such as computing, storage, and communication. A chip is a packaged, bare die that can be used in actual electronic systems. A chip may include a command processor and multiple block processing modules, each of which is connected to the command processor via data communication.

[0044] A Graphics Processing Unit (GPU) is a microprocessor specifically designed for parallel processing of large numbers of graphics and general computing tasks. Its core function is as a processor designed for highly parallel computing tasks, excelling at handling a large number of simple, repetitive computational operations simultaneously. Originally designed to accelerate image rendering, its powerful parallel computing capabilities have led to its widespread application in scientific computing, artificial intelligence, deep learning, physics simulations, and other fields.

[0045] Command Processor (CP): The command processor is the command processing unit in the chip, responsible for processing and executing various instructions or commands to ensure that the various modules inside the chip can operate efficiently and orderly. In this embodiment, the synchronization of the CP layer mainly refers to the synchronization between internal components within the chip or between different block processing clusters. The synchronization information is stored in the memory of the command processor, and the synchronization operator is the command processor. The command processor may include a task data packet buffer, a parsing module, and a segmentation module. The task data packet buffer is used to store and process information sent from the host layer. The parsing module is used to parse the information stored in the task data packet buffer. The segmentation module is used to divide the task information parsed by the parsing module to send the relevant task information to the relevant block processing clusters for execution.

[0046] Compute Unit (CU): In a graphics processing unit (GPU) architecture, a compute unit is the basic unit for executing computational tasks. A workgroup running on a GPU actually executes on a compute unit. A compute unit is the basic unit on a GPU used to execute parallel computing tasks; it contains a certain number of processing elements that can execute multiple threads in parallel. A block processing cluster can include multiple compute units. In this embodiment, synchronization at the CU layer refers to synchronization within the same CU, synchronization between different workgroups within a CU, or synchronization between different kernels, and is achieved through data packets and kernels during the synchronization process. A compute unit can include a workgroup cluster data cache, a synchronization engine, a segmentation module, a task scheduling module, and multiple execution units. The workgroup cluster data cache receives information sent by the command scheduling unit. The synchronization engine parses and synchronizes the information in the workgroup cluster data cache to obtain task information. The segmentation module segments the task information and sends the corresponding task information to the execution units for task execution.

[0047] Streaming Multiprocessors (SMs) are the core computing units of a GPU. They consist of multiple stream processors and related resources, responsible for executing a large number of threads in parallel to achieve efficient graphics rendering and computation tasks. An SM is composed of multiple stream processors (SPs). It also includes shared memory, registers, control units, instruction caches, and other resources. These components work together to support meta-threaded applications. SMs schedule threads in units of warps, with each warp typically containing 32 threads. Threads within the same warp execute the same instructions using Single Instruction Multiple Threading (SIMT) but process different data. This mechanism allows SMs to efficiently handle a large number of parallel tasks, such as rendering multiple pixels in an image. Its core function is parallel computing, primarily used for tasks such as vertex processing and pixel shading in graphics rendering. Simultaneously, with technological advancements, SMs are also widely used in non-graphics fields such as artificial intelligence training and big data analysis, fully leveraging their powerful parallel processing capabilities. SMs are the core modules of a GPU, and multiple SMs constitute the GPU's computing portion. Different GPU models have different numbers of SMs, and the number and performance of SMs directly affect the GPU's computing power and graphics processing speed.

[0048] A Scalar Unit (SMU) is a dedicated hardware module within a graphics processing unit (GPU) used for scalar operations. It can execute basic arithmetic and logical operations on data. Examples include relatively simple basic arithmetic operations such as addition, subtraction, multiplication, and division of elements in two matrices, and exponentiation and logarithmicization of each element in a single matrix, as well as basic logical operations such as logical AND, logical OR, bitwise AND, bitwise OR, and XOR. A Scalar Unit can be a Scalar Arithmetic and Logical Unit (SALU).

[0049] A kernel function is a function defined in GPU programming that executes specifically on the GPU. It serves as the core bridge connecting CPU and GPU computing, describing the specific task logic for GPU parallel processing. Kernel functions are called by the CPU, but actually executed on the GPU, utilizing the GPU's streaming multiprocessors and numerous threads to achieve parallel computation. The kernel function's code is executed simultaneously by hundreds or thousands of threads, each processing different data. For example, when processing images, one thread might be responsible for calculating the color of a single pixel; the kernel function defines the calculation logic for that single pixel, and the GPU automatically schedules a large number of threads to execute this logic in parallel. When a kernel function is started, the thread organization method (such as thread blocks and thread grid dimensions) needs to be specified. The GPU will then allocate threads to different streaming multiprocessors based on these parameters.

[0050] A thread is the smallest unit of execution scheduled by the operating system. It is a control flow within a process and has its own stack, program counter, and register state, but shares the resources of the same process (such as memory, file handles, global variables, etc.).

[0051] In the field of parallel computing, multi-threaded concurrent execution technology is widely used in computing devices such as graphics processing units (GPUs) and artificial intelligence accelerators to improve processing efficiency. These computing devices typically require basic computing components (such as arithmetic logic units) to perform core functions such as control flow management, data scheduling, and auxiliary calculations, and distribute and coordinate computing tasks through control thread bundles.

[0052] In existing technologies, the parallel execution of multiple thread bundles typically relies on a single arithmetic logic unit (ALU). Specifically, when multiple independent thread bundles are scheduled to the same ALU and processed sequentially to perform basic operations, resource contention for the ALU occurs between different thread bundles. This leads to frequent queuing of computational tasks, significantly increasing overall processing latency and reducing the utilization of computing resources.

[0053] Based on this, this disclosure proposes a meta-thread scheduling method, an electronic device, and a computer-readable storage medium, which realizes load balancing among multiple functional units, reduces the latency of multi-thread processing, and enables the computing system to process large-scale parallel computing tasks more efficiently.

[0054] System architecture description applied in the embodiments of this disclosure

[0055] In one embodiment, such as Figure 1 As shown, Figure 1 This is a system architecture diagram of the execution meta-thread scheduling method according to an embodiment of the present disclosure. The system architecture includes, but is not limited to, a computing core 100 and multiple functional units, all of which are connected to the computing core 100 via data.

[0056] Specifically, in a parallel computing system, the computing core 100 can play a core coordinating role through meta-threads. It can call one or more related functional units through meta-threads so that the functional units can perform operations related to their own functions.

[0057] The computing core 100 can call multiple functional units sequentially through meta-threads, or call multiple functional units simultaneously through meta-threads. This disclosure does not specify the order or number of functional units to be called.

[0058] In one embodiment, the computing core 100 is a key component in the GPU responsible for performing parallel computing tasks. It includes multiple execution units 400, register files, shared memory, and other resources, and can process multiple threads simultaneously to achieve efficient parallel computing.

[0059] It is understood that the aforementioned computing core 100 can be a computing unit or a streaming multiprocessor, and this disclosure does not specifically limit it in this regard.

[0060] In one embodiment, the functional unit described above may include a block operation unit. In parallel computing, the block operation unit may be a communication operation unit 210 for performing communication operations, a data copying unit 220 for performing data copying, a matrix operation unit 230 for performing matrix operations, or other types of block operation units. This disclosure does not specifically limit the types of block operation units.

[0061] Specifically, when the functional unit is the communication operation unit 210, the computing core 100 can invoke the communication operation unit 210 through a meta-thread to perform a broadcast operation. It is understood that the aforementioned broadcast operation refers to the operation of copying data from one computing unit and sending it to all other computing units.

[0062] For example, in a GPU, the host can broadcast the convolution kernel parameters to all thread blocks, so that each thread block can use the same convolution kernel for computation.

[0063] Furthermore, when the functional unit is the communication operation unit 210, the computing core 100 can also invoke the communication operation unit 210 through a meta-thread to perform collection operations. It is understood that the aforementioned collection operation refers to the operation of aggregating scattered data from multiple computing units into a single target computing unit in a specific order.

[0064] For example, in a GPU, each thread block computes a sub-block of the image, and the collection operation aggregates the pixel data of all sub-blocks into global memory to reconstruct the complete image.

[0065] Furthermore, when the functional unit is the communication operation unit 210, the computing core 100 can also call the communication operation unit 210 through a meta-thread to perform a reduction operation. It is understood that the reduction operation mentioned above refers to the operation of merging scattered data from multiple computing units into one or a few results through some kind of operation. The operation type can be summation, product, finding the maximum value, or finding the minimum value, etc.

[0066] For example, in a GPU, multiple threads within a thread block each calculate a value, and the maximum value of these multiple values ​​is obtained by reduction and stored in the shared memory within the block.

[0067] Furthermore, when the functional unit is the data copying unit 220, the computing core 100 can invoke the data copying unit 220 through a meta-thread to perform data copying operations. It is understood that, regarding the aforementioned data copying operations, in the GPU, the data copying unit 220 is responsible for efficiently transferring data between different storage areas, reducing the burden on the computing core 100. Its data copying operations mainly revolve around the GPU's internal storage hierarchy and interactions with external devices.

[0068] The types of data copying operations include, but are not limited to, the following: copying within global memory, copying between global memory and shared memory, copying between global memory and registers, copying between constant memory and global memory, data copying between GPU and CPU, data copying of texture memory, and data copying between multiple GPUs.

[0069] It is understood that the aforementioned data copying unit 220 can be either GDMA (GPU Direct Memory Access) or a DMA engine (Direct Memory Access Engine), and this disclosure does not specifically limit it in this regard.

[0070] Furthermore, when the functional unit is the matrix operation unit 230, the computing core 100 can invoke the matrix operation unit 230 through a meta-thread to perform matrix operation operations. For example, the computing core 100 can invoke the matrix operation unit 230 through a meta-thread to perform basic matrix multiplication, i.e., calculate the product of two matrices; or, the computing core 100 can invoke the matrix operation unit 230 through a meta-thread to perform matrix multiplication and addition, i.e., add an accumulation step to the matrix multiplication; or, the computing core 100 can invoke the matrix operation unit 230 through a meta-thread to perform mixed-precision matrix operations, supporting matrix operations of various data precisions to balance performance and accuracy requirements; or, the computing core 100 can invoke the matrix operation unit 230 through a meta-thread to perform batch matrix operations, i.e., perform parallel operations on a set of multiple independent matrices.

[0071] It is understood that the matrix operation unit 230 mentioned above can be either a Tensor Core or a Matrix Core, and this disclosure does not make any specific limitation on it.

[0072] In one embodiment, the functional unit described above may further include a scalar processing unit 300, wherein the scalar processing unit 300 is used to process arithmetic and logical operations on scalar data.

[0073] Specifically, the scalar processing unit 300 is the core component in the computing core 100 responsible for performing arithmetic and logical operations on scalar data. The computing core 100 can call the scalar processing unit 300 through a meta-thread to perform arithmetic and logical operations on scalar data.

[0074] For example, the computing core 100 can call the scalar processing unit 300 through a meta-thread to perform arithmetic operations on numerical values, such as basic addition, subtraction, multiplication, division, increment, decrement, inversion, absolute value, shift operations, etc.; or, the computing core 100 can call the scalar processing unit 300 through a meta-thread to perform logical operations, such as bitwise logical operations and comparison operations; or, the computing core 100 can call the scalar processing unit 300 through a meta-thread to perform other auxiliary operations, such as modulo, address calculation, and flag setting.

[0075] In one embodiment, the functional unit described above may further include an execution unit 400, wherein the execution unit 400 is used to process vector operations.

[0076] Specifically, the execution unit 400 is a hardware component specifically optimized for vector operations. Its core function is to perform parallel processing of vector data, and it can process multiple elements simultaneously in a single operation.

[0077] For example, the computing core 100 can call the execution unit 400 through a meta-thread to perform basic vector arithmetic operations, such as vector addition, vector subtraction, vector multiplication, and vector division; or, the computing core 100 can call the execution unit 400 through a meta-thread to perform vector scalar operations, such as vector addition to a scalar and vector multiplication by a scalar; or, the computing core 100 can call the execution unit 400 through a meta-thread to perform special vector operations, such as vector dot product, extraction of maximum / minimum values ​​of vectors, vector summation / averaging, and vector comparison; or, the computing core 100 can call the execution unit 400 through a meta-thread to perform vector data recombination operations, such as vector shuffling and vector type conversion.

[0078] In one embodiment, the computing core 100 includes a scheduling unit that is communicatively connected to each functional unit. Specifically, this scheduling unit may be a meta-thread instruction scheduler. In parallel computing, the meta-thread instruction scheduler creates meta-threads, and once created, each meta-thread executes a meta-thread program. The meta-thread program consists of a sequence of meta-thread instructions. Further, the meta-thread instruction scheduler fetches, decodes, and dispatches each instruction in the meta-thread instruction sequence to the corresponding functional unit for execution.

[0079] In one embodiment, such as Figure 1 As shown, this illustrates the core coordinating role of meta-threads in parallel computing systems:

[0080] Communication operation management: The meta-thread interacts with the communication operation modules on the left, such as Reduction and Broadcast. These operations are performed for different scopes, such as Collaborative Working Groups (CWG), Sub-Workgroups (SWG), and Grid.

[0081] Scalar arithmetic logic operations: The Scalar Processing Unit 300 (Scalar ALU) is called through the meta-thread to perform arithmetic logic operations on scalar data.

[0082] Invocation of Execution Unit 400: The execution unit 400 is invoked through the meta-thread using an asynchronous request and response mechanism to schedule the execution of computational tasks.

[0083] Matrix operations and data copying: The meta-thread also coordinates matrix multiplication and addition operations and data copying operations, ensuring the transmission of data and the execution of complex operations in the computation process.

[0084] Therefore, by Figure 1 As can be seen, the meta-thread is the scheduling center for various computing and communication operations, enabling different tasks in parallel computing, such as scalar operations, matrix operations, data communication, and execution unit calls, to coordinate efficiently.

[0085] In another embodiment, the communication kernel function, the block processing kernel function, and the element processing kernel function can run in parallel without causing significant resource conflicts.

[0086] Furthermore, in one embodiment, over-allocation of resource-intensive ordinary worker threads can be avoided when demand is insufficient. Resources allocated element-wise, such as vector general-purpose registers, are saved. Metathreads are an efficient block-based processing method, framework, and paradigm suitable for future parallel computing systems.

[0087] In one embodiment, such as Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the relationship between meta-threads, ordinary worker threads, thread bundles, thread blocks, and thread clusters in one embodiment of this disclosure. Compared to the prior art, this schematic diagram adds a meta-thread for management, wherein... Figure 2 It can be seen that a thread cluster includes multiple thread blocks, a thread block includes multiple thread bundles and a meta thread, and a thread bundle includes multiple ordinary worker threads.

[0088] Overall Implementation of the Meta-thread Scheduling Method in this Disclosure

[0089] This disclosure proposes a meta-thread scheduling method, applied to a scheduling unit, which is communicatively connected to multiple functional units; see reference Figure 3 , Figure 3 This is a main flowchart of a meta-thread scheduling method according to an embodiment of the present disclosure; the meta-thread scheduling method includes, but is not limited to, steps S301 to S304.

[0090] Step S301: Obtain the first workload information of the meta-thread scheduling queue and the resident meta-threads of each functional unit;

[0091] Step S302: Determine the target unit from multiple functional units based on the first workload information of the resident meta thread, wherein the target unit is the functional unit with the lowest workload level.

[0092] Step S303: Determine the target meta-thread from the multiple meta-threads to be executed in the meta-thread scheduling queue;

[0093] Step S304: Schedule the target meta thread to the target unit.

[0094] Specifically, in this disclosure, by selecting the functional unit with the lowest workload level as the target unit, load balancing among multiple functional units is achieved. Furthermore, by optimizing the scheduling strategy of the meta-threads, the meta-threads are scheduled to the functional unit with the lowest workload level, thereby reducing the processing latency of the multi-threaded system and enabling the computing system to handle large-scale parallel computing tasks more efficiently.

[0095] In one embodiment, step S301 specifically involves: the scheduling unit obtaining a meta-thread scheduling queue and selecting a meta-thread from the queue for scheduling. Before scheduling, the scheduling unit obtains the first workload information of the resident meta-threads of each functional unit. The resident meta-threads are the meta-threads currently executing or waiting to be executed on the functional unit. The first workload information can be used to describe the workload of the resident meta-threads on the functional unit.

[0096] In one embodiment, step S302 specifically involves the scheduling unit determining a target unit from multiple functional units based on the first workload information of the resident meta-thread, thereby selecting the functional unit with the lowest workload level as the target unit for receiving new meta-threads to achieve load balancing.

[0097] In one embodiment, step S303 specifically involves the scheduling unit selecting one of the multiple pending meta-threads in the meta-thread scheduling queue as the target meta-thread. The target meta-thread is in a ready state and is about to be scheduled to the target unit, while the remaining pending meta-threads have the conditions to execute and need to continue waiting in the meta-thread scheduling queue to be scheduled to a suitable target unit.

[0098] In one embodiment, step S304 specifically involves: the scheduling unit assigning the target meta-thread to the target unit, causing the target unit to begin executing the computational task of the target meta-thread.

[0099] It is understood that the number of pending meta-threads in the meta-thread scheduling queue of this disclosure embodiment is determined by the kernel function written by the user, while the number of functional units in a single computing core is fixed. Typically, the number of pending meta-threads is greater than the number of functional units. For example, the meta-thread scheduling queue contains 6 pending meta-threads, while the computing core contains 3 functional units. When a pending meta-thread is scheduled to a functional unit, it will remain on that functional unit as a resident meta-thread until all computing tasks are completed. Then, the scheduling unit will select the functional unit with the lowest workload level from the 3 functional units as the target unit, and select a ready target meta-thread from the 6 pending meta-threads to allocate to the idle target unit, ensuring a relatively balanced load on each functional unit and improving the utilization of computing resources and system efficiency. It should be understood that the number of pending meta-threads can be set to other numbers according to the user's actual needs. In some computing cores, the number of functional units can also be 16, 32, or 64, and this disclosure embodiment does not limit this.

[0100] In one embodiment, such as Figure 4 As shown, Figure 4 yes Figure 3A flowchart of a sub-step of an embodiment of step S302; the functional unit of the above step embodiment is a scalar processing unit, and the first workload information includes the first preset workload weight of the resident meta-thread of each scalar processing unit. Regarding the determination of the target unit from multiple functional units based on the first workload information of the resident meta-thread in the above step S302, it may include, but is not limited to, steps S401 and S402.

[0101] Step S401: Calculate the first expected workload weight of the scalar processing unit where the resident meta-thread is located based on the first preset workload weight of the resident meta-thread, wherein the first expected workload weight is proportional to the workload level of the scalar processing unit.

[0102] Step S402: Traverse the first expected workload weights of all scalar processing units and determine the scalar processing unit with the smallest first expected workload weight as the target unit.

[0103] In one embodiment, the scheduling unit first obtains a first preset workload weight for the resident metathread of each scalar processing unit. The first preset workload weight represents the actual workload of the resident metathread on the scalar processing unit. Specifically, the smaller the first preset workload weight, the lower the actual workload of the resident metathread. For example, when the first preset workload weight is a small value such as 1, 2, or 3, it indicates that the actual workload of the resident metathread is low. Conversely, the larger the first preset workload weight, the higher the actual workload of the resident metathread. For example, when the first preset workload weight is a large value such as 4, 5, 6, or above, it indicates that the actual workload of the resident metathread is high. Understandably, the compiler initializes a preset workload weight counter for each resident meta-thread based on the kernel function written by the user, which is used to record the first preset workload weight. When the program starts or performs meta-thread scheduling, the scheduling unit can obtain the first preset workload weight of the resident meta-thread from each preset workload weight counter. During program execution, the value of the preset workload weight counter will be dynamically adjusted until the first preset workload weight is 0, at which point the value of the preset workload weight counter of that resident meta-thread is cleared to zero.

[0104] Furthermore, the scheduling unit calculates the first expected workload weight of each scalar processing unit based on the first preset workload weight of the resident meta-thread, wherein the first expected workload weight is proportional to the workload level of the scalar processing unit. Understandably, the magnitude of the first expected workload weight can be used to assess the current workload of the scalar processing unit. A larger first expected workload weight indicates a higher workload level for the scalar processing unit; conversely, a smaller first expected workload weight indicates a lower workload level. For example, the workload level of a scalar processing unit can be divided into two levels: light workload and heavy workload. The first expected workload weight for the light workload level can be set to 1, while the first expected workload weight for the heavy workload level can be set to a larger value of 2, 3, 4, or higher. Alternatively, the workload level of a scalar processing unit can be divided into three levels: light workload, medium workload, and heavy workload. The first expected workload weight for the light workload level can be set to 1, the first expected workload weight for the medium workload level can be set to 2 or 3, and the first expected workload weight for the heavy workload level can be set to a larger value of 4, 5, 6, or higher. Furthermore, the scheduling unit iterates through the first expected workload weights of all scalar processing units and then selects the scalar processing unit with the smallest first expected workload weight as the target unit, thereby ensuring load balancing among multiple scalar processing units and improving the overall system's computing resource utilization.

[0105] It should be noted that before calculating the first expected workload weight of the scalar processing unit where the resident meta-thread resides in step S401, the initial value of the first expected workload weight of each scalar processing unit can be a value initialized by the user when writing the kernel function. For example, at program startup, the compiler initializes an expected workload weight counter for each scalar processing unit based on the kernel function to record the first expected workload weight, and sets the initial value of the first expected workload weight to 0. Then, the scheduling unit can obtain the first expected workload weight from the expected workload weight counter when performing meta-thread scheduling. It should be understood that when a scalar processing unit does not have a resident meta-thread, the corresponding first expected workload weight is 0, and the value of the expected workload weight counter for that scalar processing unit is cleared.

[0106] In another embodiment, such as Figure 5 As shown, Figure 5 yes Figure 3A flowchart of a sub-step of another embodiment of step S302; the first workload information of the above-mentioned step embodiment also includes the first scalar operation count of the resident meta-thread of each scalar processing unit, and the determination of the target unit from multiple functional units based on the first workload information of the resident meta-thread in the above-mentioned step S302 may also include, but is not limited to, steps S501 and S502.

[0107] Step S501: Calculate the first expected number of operations of the scalar processing unit where the resident meta-thread is located based on the first scalar operation count of the resident meta-thread, wherein the first expected number of operations is proportional to the workload level of the scalar processing unit.

[0108] Step S502: Traverse the first expected number of operations for all scalar processing units and determine the scalar processing unit with the fewest first expected number of operations as the target unit.

[0109] In one embodiment, the scheduling unit first obtains the first scalar operation count of the resident metathread of each scalar processing unit. The first scalar operation count represents the actual number of scalar operations remaining for the resident metathread on the scalar processing unit. Specifically, the fewer the first scalar operation counts, the lower the actual workload of the resident metathread. For example, when the first scalar operation count is a small value such as 0, 100, or 200, it indicates that the actual workload of the resident metathread is low. Conversely, the more the first scalar operation counts, the higher the actual workload of the resident metathread. For example, when the first scalar operation count is a large value such as 500, 600, or 700 or higher, it indicates that the actual workload of the resident metathread is high. Understandably, the compiler initializes a scalar operation count counter for each resident meta-thread based on the kernel function written by the user, which is used to record the first scalar operation count. When the program starts or performs meta-thread scheduling, the scheduling unit can obtain the first scalar operation count of each resident meta-thread from the scalar operation count counter. During program execution, the value of the scalar operation count counter will be dynamically adjusted until the first scalar operation count is 0, at which point the value of the scalar operation count counter for that resident meta-thread is cleared to zero.

[0110] Furthermore, the scheduling unit calculates the first expected number of operations for each scalar processing unit based on the first scalar operation count of the resident meta-thread. The first expected number of operations is proportional to the workload level of the scalar processing unit. Understandably, the magnitude of the first expected number of operations can also be used to assess the current workload of the scalar processing unit; that is, the fewer the first expected number of operations, the lower the workload level of the scalar processing unit. For example, smaller values ​​such as 0, 100, or 200 indicate a lower workload level. Conversely, more first expected number of operations indicates a higher workload level; for example, larger values ​​such as 500, 600, or 700 indicate a higher workload level. The scheduling unit then iterates through the first expected number of operations of all scalar processing units and selects the scalar processing unit with the fewest first expected number of operations as the target unit.

[0111] It should be noted that before calculating the first expected number of operations for the scalar processing unit where the resident meta-thread resides in step S501, the initial value of the first expected number of operations for each scalar processing unit can be a value initialized by the user when writing the kernel function. For example, at program startup, the compiler initializes an expected number of operations counter for each scalar processing unit based on the kernel function to record the first expected number of operations, and sets the initial value of the first expected number of operations to 0. Then, the scheduling unit can obtain the first expected number of operations from the expected number of operations counter when performing meta-thread scheduling. When there is no resident meta-thread in a scalar processing unit, the corresponding first expected number of operations is 0, and the value of the expected number of operations counter for that scalar processing unit is cleared.

[0112] In one embodiment, such as Figure 6 As shown, Figure 6 yes Figure 3 A flowchart of a sub-step of one embodiment of step S303; regarding the determination of the target meta-thread from multiple unexecuted meta-threads in the meta-thread scheduling queue in the above step S303, it may include, but is not limited to, steps S601 and S602.

[0113] Step S601: Obtain the second workload information of each meta-thread to be executed based on the meta-thread scheduling queue. The second workload information includes the second preset workload weight of the meta-thread to be executed.

[0114] Step S602: Sort all the pending meta-threads in the meta-thread scheduling queue in descending order of the second preset workload weight of the pending meta-threads, and determine the pending meta-thread with the largest second preset workload weight in the meta-thread scheduling queue as the target meta-thread.

[0115] In one embodiment, the scheduling unit obtains the second workload information of each pending meta-thread from the meta-thread scheduling queue. This second workload information may include a second preset workload weight. It should be noted that the second preset workload weight is a parameter of the pending meta-thread that the user pre-sets based on experience and the number of instructions contained in the meta-thread when writing the kernel function. The compiler then initializes a preset workload weight counter for each pending meta-thread based on the user-written kernel function to record the second preset workload weight. When the program starts or performs meta-thread scheduling, the scheduling unit can obtain the second preset workload weight of the pending meta-thread from each preset workload weight counter. Specifically, the smaller the second preset workload weight, the lower the actual workload of the pending meta-thread. For example, a smaller value such as 1, 2, or 3 indicates a lower actual workload for the pending meta-thread. Conversely, a larger second preset workload weight indicates a higher actual workload for the pending meta-thread. For example, a larger value such as 4, 5, 6, or higher indicates a higher actual workload for the pending meta-thread. Furthermore, the scheduling unit sorts all pending meta-threads in the meta-thread scheduling queue according to their second preset workload weights in descending order, and updates the meta-thread order in the queue. Finally, the scheduling unit selects the meta-thread with the highest second preset workload weight from the queue as the target meta-thread, thus prioritizing the scheduling of meta-threads with larger workloads or higher computational demands, ensuring that critical computing tasks can obtain sufficient computing resources in a timely manner.

[0116] In one embodiment, the meta-thread scheduling queue may contain 5 meta-threads to be executed, namely MT1, MT2, MT3, MT4, and MT5. The second preset workload weights of each meta-thread to be executed are 4, 3, 2, 1, and 5, respectively. That is, the initial meta-thread arrangement order of the meta-thread scheduling queue is: MT1 (4), MT2 (3), MT3 (2), MT4 (1), and MT5 (5). After the scheduling unit sorts the meta-thread scheduling queue according to the second preset workload weight in descending order, the new meta-thread arrangement order is: MT5 (5), MT1 (4), MT2 (3), MT3 (2), and MT4 (1). According to the sorting result, the meta-thread to be executed MT5 has the largest second preset workload weight (5). Therefore, the scheduling unit determines the meta-thread to be executed MT5 as the target meta-thread.

[0117] In another embodiment, the second workload information of the above-described step embodiment also includes the second scalar operation count of the meta-thread to be executed. Regarding the determination of the target meta-thread from the multiple meta-threads to be executed in the meta-thread scheduling queue in step S303, it may also include, but is not limited to, step S701.

[0118] Step S701: Sort all the pending metathreads in the metathread scheduling queue according to the order of the number of second scalar operations of the pending metathreads from most to least, and determine the pending metathread with the most second scalar operations in the metathread scheduling queue as the target metathread.

[0119] In one embodiment, the scheduling unit obtains the second workload information of each pending meta-thread from the meta-thread scheduling queue. This second workload information also includes the second scalar operation count. The compiler then initializes a scalar operation count counter for each pending meta-thread based on user-written kernel functions to record the second scalar operation count. When the program starts or performs meta-thread scheduling, the scheduling unit can obtain the second scalar operation count of each pending meta-thread from the scalar operation count counter. Specifically, the second scalar operation count represents the number of scalar operations included in the pending thread. The fewer the second scalar operation counts, the lower the actual workload of the pending meta-thread. For example, when the second scalar operation count is a small value such as 0, 100, or 200, the actual workload of the pending meta-thread is low. Conversely, the more the second scalar operation counts, the higher the actual workload of the pending meta-thread. For example, when the second scalar operation count is a large value such as 500, 600, or 700 or higher, the actual workload of the pending meta-thread is high. Furthermore, the scheduling unit sorts all pending metathreads in the metathread scheduling queue according to the number of second scalar operations performed on each metathread, from most to least, and updates the metathread order in the queue. Finally, the scheduling unit selects the metathread with the most second scalar operations from the queue as the target metathread, thus prioritizing the scheduling of metathreads with higher workloads or computational demands, thereby improving the utilization of computing resources.

[0120] In one embodiment, the meta-thread scheduling queue may contain 6 meta-threads to be executed, namely MT1, MT2, MT3, MT4, MT5, and MT6. The number of second scalar operations for each meta-thread to be executed is 200, 150, 250, 100, 300, and 400, respectively. That is, the initial meta-thread arrangement order of the meta-thread scheduling queue is: MT1 (200), MT2 (150), MT3 (250), MT4 (100), MT5 (300), and MT6 (400). After the scheduling unit sorts the meta-thread scheduling queue according to the order of the number of second scalar operations from most to least, the new meta-thread arrangement order is obtained as MT6 (400), MT5 (300), MT3 (250), MT1 (200), MT2 (150), and MT4 (100). Based on the updated sorting result, the meta-thread to be executed, MT6, has the most second scalar operations (400). Therefore, the scheduling unit determines the meta-thread to be executed, MT6, as the target meta-thread.

[0121] In one embodiment, the scheduling of the target meta thread to the target unit in step S304 may include, but is not limited to, step S801.

[0122] Step S801: Schedule the target meta-thread to the target unit, and increase the second expected workload weight of the target unit according to the third preset workload weight of the target meta-thread.

[0123] In one embodiment, when scheduling the target meta-thread to the target unit, the scheduling unit increases the second expected workload weight of the target unit based on the target meta-thread's third preset workload weight. That is, the third preset workload weight of the target meta-thread is added to the original second expected workload weight of the target unit, thereby updating the new second expected workload weight of the target unit. Specifically, the compiler can initialize a preset workload weight counter for the target meta-thread based on a user-written kernel function to record the target meta-thread's third preset workload weight, and initialize an expected workload weight counter for the target unit to record the target unit's second expected workload weight. Then, when scheduling the target meta-thread, the scheduling unit obtains the third preset workload weight from the target meta-thread's preset workload counter and adds it to the target unit's expected workload weight counter, increasing the second expected workload weight.

[0124] In another embodiment, the meta-thread scheduling method of this disclosure further includes, but is not limited to, step S901.

[0125] Step S901: After the target unit completes the first preset number of scalar operations, the second expected workload weight of the target unit is reduced based on the first preset value.

[0126] In one embodiment, a second expected workload weight counter can be configured in the scheduling unit to record the second expected workload weight of the target unit. Each time the target unit completes a first preset number of scalar operations, the expected workload weight counter decreases the second expected workload weight of the target unit by a first preset value. It should be noted that the first preset number and the first preset value are set by the user when writing the kernel function, and their specific values ​​can be set according to actual needs; this embodiment does not impose any limitations.

[0127] In one embodiment, the process of scheduling the target meta-thread to the target unit in step S304 may include, but is not limited to, step S1001.

[0128] Step S1001: Schedule the target meta-thread to the target unit, and increase the second expected number of operations of the target unit according to the third scalar operation count of the target meta-thread.

[0129] In one embodiment, when scheduling the target meta-thread to the target unit, the scheduling unit increments the target unit's second expected computation count based on the target meta-thread's third scalar computation count. That is, the third scalar computation count of the target meta-thread is added to the target unit's original second expected computation count, thereby updating the target unit's second expected computation count. Specifically, the compiler can initialize a scalar computation count counter for the target meta-thread based on a user-written kernel function to record the target meta-thread's third scalar computation count, and initialize an expected computation count counter for the target unit to record the target unit's second expected computation count. Then, when scheduling the target meta-thread, the scheduling unit retrieves the third scalar computation count from the target meta-thread's scalar computation count counter and adds it to the target unit's expected computation count counter, thus increasing the second expected computation count.

[0130] In addition, the meta-thread scheduling method of this disclosure also includes, but is not limited to, step S1101.

[0131] Step S1101: After the target unit performs a scalar operation, the second expected number of operations of the target unit is reduced based on the second preset value.

[0132] In one embodiment, a counter for recording the second expected number of operations for the target unit can be configured in the scheduling unit. Each time the target unit performs a scalar operation, the expected number of operations counter is decremented by a second preset value. It should be noted that the second preset value is set by the user when writing the kernel function, and its specific value can be set according to actual needs; this embodiment does not limit its value.

[0133] Based on the meta-thread scheduling method of the above embodiments, various embodiments of the electronic device, computer-readable storage medium, and computer program product of this disclosure are proposed below.

[0134] This disclosure also provides an electronic device 500, including:

[0135] At least one processor, and,

[0136] A memory that is communicatively connected to at least one processor; wherein,

[0137] The memory stores instructions that are executed by at least one processor to cause the at least one processor to perform the method as described in any of the above embodiments of the present disclosure when executing the instructions.

[0138] The following is combined Figure 7 The hardware structure of the electronic device is described in detail. The electronic device 500 includes: a processor 510, a memory 520, an input / output interface 530, a communication interface 540, and a bus 550.

[0139] The processor 510 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this disclosure.

[0140] The memory 520 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 520 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 520 and is called and executed by the processor 510 using the meta-thread scheduling method of the embodiments of this disclosure.

[0141] The input / output interface 530 is used to implement information input and output;

[0142] The communication interface 540 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0143] Bus 550 transmits information between various components of the device (e.g., processor 510, memory 520, input / output interface 530, and communication interface 540);

[0144] The processor 510, memory 520, input / output interface 530 and communication interface 540 are connected to each other within the device via bus 550.

[0145] It is worth noting that since the electronic device 500 of this disclosure is capable of executing the meta-thread scheduling method of any of the above embodiments, the specific implementation and technical effects of the electronic device 500 of this disclosure can be referred to the specific implementation and technical effects of the meta-thread scheduling method of any of the above embodiments.

[0146] Furthermore, one embodiment of this application provides a computer-readable storage medium storing computer-executable instructions for performing the aforementioned meta-thread scheduling method. Exemplarily, the above-described method is executed... Figures 3 to 6 The methods and steps in the text.

[0147] It is worth noting that, since the computer-readable storage medium of this disclosure is capable of executing the meta-thread scheduling method of any of the above embodiments, the specific implementation methods and technical effects of the computer-readable storage medium of this disclosure can be referred to the specific implementation methods and technical effects of the meta-thread scheduling method of any of the above embodiments.

[0148] Furthermore, one embodiment of this application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the aforementioned meta-thread scheduling method. Exemplarily, the above-described method is executed... Figures 3 to 6 The methods and steps in the text.

[0149] It is worth noting that since the computer program product of this disclosure can execute the meta-thread scheduling method of any of the above embodiments, the specific implementation method and technical effect of the computer program product of this disclosure can be referred to the specific implementation method and technical effect of the meta-thread scheduling method of any of the above embodiments.

[0150] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0151] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0152] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0153] It should be understood that in the description of the embodiments of this disclosure, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0154] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0155] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0156] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0157] It should also be understood that the various implementation methods provided in this disclosure can be combined arbitrarily to achieve different technical effects.

[0158] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A meta-thread scheduling method, characterized in that, It is applied to a scheduling unit, which is communicatively connected to multiple functional units; The meta-thread scheduling method includes: Obtain the meta-thread scheduling queue and the first workload information of the resident meta-threads of each functional unit; The target unit is determined from the plurality of functional units based on the first workload information of the resident meta thread, wherein the target unit is the functional unit with the lowest workload level; The target meta-thread is determined from the multiple meta-threads to be executed in the meta-thread scheduling queue; Schedule the target meta-thread to the target unit; The functional unit is a scalar processing unit, and the first workload information includes the first preset workload weight of the resident meta-thread of each scalar processing unit. Determining the target unit from the plurality of functional units based on the first workload information of the resident meta-thread includes: The first expected workload weight of the scalar processing unit where the resident meta-thread is located is calculated based on the first preset workload weight of the resident meta-thread, wherein the first expected workload weight is proportional to the workload level of the scalar processing unit. Iterate through the first expected workload weights of all the scalar processing units and determine the scalar processing unit with the smallest first expected workload weight as the target unit. The step of determining the target meta-thread from the multiple pending meta-threads in the meta-thread scheduling queue includes: The second workload information of each meta-thread to be executed is obtained based on the meta-thread scheduling queue. The second workload information includes the second preset workload weight of the meta-thread to be executed. All the pending meta-threads in the meta-thread scheduling queue are sorted in descending order of their second preset workload weights, and the pending meta-thread with the largest second preset workload weight in the meta-thread scheduling queue is determined as the target meta-thread.

2. The meta-thread scheduling method according to claim 1, characterized in that, The first workload information includes the first scalar operation count of the resident metathread of each scalar processing unit, and the method further includes: The first expected number of operations of the scalar processing unit where the resident meta-thread is located is calculated based on the first scalar operation count of the resident meta-thread, wherein the first expected number of operations is proportional to the workload level of the scalar processing unit; The first expected number of operations is traversed for all the scalar processing units, and the scalar processing unit with the fewest first expected number of operations is determined as the target unit.

3. The meta-thread scheduling method according to claim 1, characterized in that, The second workload information also includes the second scalar operation count of the meta-thread to be executed, and the method further includes: All the pending metathreads in the metathread scheduling queue are sorted in order of the number of second scalar operations performed on the pending metathreads, from most to least, and the pending metathread with the most second scalar operations in the metathread scheduling queue is determined as the target metathread.

4. The meta-thread scheduling method according to claim 1, characterized in that, The step of scheduling the target meta-thread to the target unit includes: The target meta-thread is scheduled to the target unit, and the second expected workload weight of the target unit is increased according to the third preset workload weight of the target meta-thread.

5. The meta-thread scheduling method according to claim 4, characterized in that, The method further includes: After the target unit completes a first preset number of scalar operations, the second expected workload weight of the target unit is reduced based on the first preset value.

6. The meta-thread scheduling method according to claim 2, characterized in that, The step of scheduling the target meta-thread to the target unit includes: The target meta-thread is scheduled to the target unit, and the second expected number of operations of the target unit is increased according to the third scalar operation count of the target meta-thread.

7. The meta-thread scheduling method according to claim 6, characterized in that, The method further includes: After the target unit performs a scalar operation, the second expected number of operations of the target unit is reduced based on a second preset value.

8. An electronic device, characterized in that, The electronic device includes a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for enabling communication between the processor and the memory. The program is executed by the processor to implement the meta-thread scheduling method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the meta-thread scheduling method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or the computer instructions from the computer-readable storage medium and executes the computer program or the computer instructions, causing the computer device to perform the meta-thread scheduling method as described in any one of claims 1 to 7.

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