Noise reduction unit, correction method, noise reduction circuit, and gate drive circuit

Abstract

This application belongs to the field of display driver technology, specifically relating to a noise reduction unit, a correction method, a noise reduction circuit, and a gate driving circuit. The noise reduction unit includes: at least one noise reduction transistor, the control terminal of which is connected to a noise reduction control node, and the first terminal of which is connected to the node being denoised; a pull-down control module connected to the second terminal of the noise reduction transistor, configured to control the second terminal of the noise reduction transistor to be connected to a low-level terminal during the noise reduction phase; and a reverse correction module connected to the noise reduction transistor, configured to apply a reverse correction voltage to the noise reduction transistor during the reverse correction phase to reverse correct the threshold voltage of the noise reduction transistor. This application improves the threshold voltage drift problem caused by forward bias by applying a reverse correction voltage to the noise reduction transistor during the reverse correction phase using the reverse correction module.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, and specifically relates to a noise reduction unit, a correction method, a noise reduction circuit, and a gate driving circuit. Background Technology

[0002] GOA (Gate Driver on Array) is a key circuit for TFT-LCD (Thin-Film Transistor Liquid Crystal Display) to achieve progressive scanning; among them, the noise reduction circuit that performs noise reduction processing on key nodes inside GOA is the core module to ensure the stability of GOA circuit and the reliability of display.

[0003] However, in actual operation, the threshold voltage of each noise reduction transistor in the noise reduction circuit drifts due to prolonged forward bias, which causes the noise at key nodes (such as Q point and G point) to be unable to be effectively reduced, resulting in abnormal GOA output waveform, flickering display screen or horizontal bright lines and other adverse phenomena.

[0004] Therefore, how to improve the threshold voltage drift of noise reduction transistors in noise reduction circuits is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a noise reduction unit, a correction method, a noise reduction circuit, and a gate drive circuit. This application applies a reverse correction voltage to the noise reduction transistor during the reverse correction stage through a reverse correction module to improve the threshold voltage drift problem caused by forward bias.

[0006] In a first aspect, embodiments of this application provide a noise reduction unit, the noise reduction unit comprising: at least one noise reduction transistor, the control terminal of the noise reduction transistor being connected to a noise reduction control node, and a first terminal of the noise reduction transistor being connected to a node to be denoised; a pull-down control module, connected to a second terminal of the noise reduction transistor, configured to control the second terminal of the noise reduction transistor to be connected to a low-level terminal during the noise reduction phase; and a reverse correction module, connected to the noise reduction transistor, configured to apply a reverse correction voltage to the noise reduction transistor during the reverse correction phase to reverse correct the threshold voltage of the noise reduction transistor.

[0007] Optionally, the at least one noise reduction transistor includes a first noise reduction transistor, a second noise reduction transistor, and a third noise reduction transistor. The pull-down control module includes: a first transistor, the control terminal of which is connected to the pull-down control terminal, a first terminal of which is connected to the second terminal of the first noise reduction transistor, and a second terminal of which is connected to the first low-level terminal; a second transistor, the control terminal of which is connected to the control terminal of the first transistor, a first terminal of which is connected to the second terminal of the second noise reduction transistor, and a second terminal of which is connected to the first low-level terminal; and a third transistor, the control terminal of which is connected to the control terminal of the first transistor, a first terminal of which is connected to the second terminal of the third noise reduction transistor, and a second terminal of which is connected to either the first low-level terminal or the second low-level terminal.

[0008] Optionally, the reverse correction module includes: a fourth transistor, the control terminal of the fourth transistor being connected to the first reverse correction terminal, the first terminal of the fourth transistor being connected to the control terminal of the fourth transistor, and the second terminal of the fourth transistor being connected to the second terminal of the first noise reduction transistor, the second terminal of the second noise reduction transistor, and the second terminal of the third noise reduction transistor, respectively.

[0009] Optionally, the reverse correction module includes: a fourth transistor, the control terminal of which is connected to a noise reduction associated node, and a first terminal of which is connected to a second terminal of the first noise reduction transistor, a second terminal of the second noise reduction transistor, and a second terminal of the third noise reduction transistor; a coupling capacitor, the first terminal of which is connected to a second terminal of the fourth transistor; and a fifth transistor, the control terminal of which is connected to the noise reduction control node, the first terminal of which is connected to a second terminal of the coupling capacitor, and the second terminal of which is connected to a control terminal of the fifth transistor.

[0010] Optionally, the at least one noise reduction transistor includes a first noise reduction transistor, a second noise reduction transistor, and a third noise reduction transistor. The pull-down control module includes: a first transistor, the control terminal of which is connected to a first reverse correction terminal, and a first terminal of which is connected to a second terminal of the first noise reduction transistor; a second transistor, the control terminal of which is connected to the control terminal of the first transistor, and a first terminal of which is connected to a second terminal of the second noise reduction transistor; a third transistor, the control terminal of which is connected to the control terminal of the first transistor, and a first terminal of which is connected to a second terminal of the third noise reduction transistor; a fourth transistor, the control terminal of which is connected to a pull-down control terminal, and a first terminal of which is connected to a second terminal of the first transistor, and a second terminal of which is connected to a first low-level terminal; a fifth transistor, the control terminal of which is connected to the control terminal of the fourth transistor, and a first terminal of which is connected to a second terminal of the second transistor, and a second terminal of which is connected to the first low-level terminal; and a sixth transistor, the control terminal of which is connected to the control terminal of the fourth transistor, and a first terminal of which is connected to a second terminal of the third transistor, and a second terminal of which is connected to a second low-level terminal.

[0011] Optionally, the reverse correction module includes: a seventh transistor, the control terminal of which is connected to a second reverse correction terminal, the first terminal of which is connected to the second terminal of the first noise reduction transistor, the second terminal of the second noise reduction transistor, and the second terminal of the third noise reduction transistor, and the second terminal of which is connected to the control terminal of the seventh transistor; and an eighth transistor, the control terminal of which is connected to the control terminal of the seventh transistor, the first terminal of which is connected to the noise reduction control node, and the second terminal of which is connected to the first low-level terminal.

[0012] Optionally, the noise reduction unit further includes a heating module connected to a heating control terminal, configured to heat the at least one noise reduction transistor in response to a heating control signal output from the heating control terminal when the noise reduction unit is in the reverse correction phase.

[0013] Secondly, embodiments of this application provide a correction method applied to a noise reduction unit. The correction method includes: in a noise reduction stage, controlling the second terminal of at least one noise reduction transistor to be connected to a low-level terminal by a pull-down control module, so that the at least one noise reduction transistor performs noise reduction on the noise-reduced node; in a reverse correction stage, applying a reverse correction voltage to the at least one noise reduction transistor by a reverse correction module to reverse correct the threshold voltage of the noise reduction transistor.

[0014] Thirdly, embodiments of this application provide a noise reduction circuit, the noise reduction circuit comprising: a first noise reduction unit, wherein the noise reduction trigger terminal of the first noise reduction unit is connected to a first pull-down control terminal; and a second noise reduction unit, wherein the noise reduction trigger terminal of the second noise reduction unit is connected to a second pull-down control terminal; wherein the first noise reduction unit and the second noise reduction unit alternately operate in a noise reduction stage and a reverse correction stage.

[0015] Fourthly, embodiments of this application provide a gate driving circuit, including N cascaded gate driving modules. The nth-stage gate driving module includes: a pull-up unit, which is connected to the drive output terminal and the stage transmission output terminal of the nith-stage gate driving module, respectively; a pull-down unit, which is connected to the stage transmission output terminal of the (n+j)th-stage gate driving module, and the pull-down unit is also connected to the pull-up unit through a drive control node; an output unit, which is connected to a clock signal terminal and the drive control node, respectively; and a noise reduction circuit, which is connected to the drive control node, the drive output terminal, and the stage transmission output terminal of the current-stage gate driving module, respectively.

[0016] The technical solutions provided in this application have at least the following beneficial effects:

[0017] In the noise reduction stage, this application connects the source of each noise reduction transistor to a low-level terminal through a pull-down control module, so that each noise reduction transistor performs noise reduction tasks for the corresponding noise-reduced node. In the reverse correction stage, the reverse correction module applies a reverse correction voltage to the noise reduction transistor to reverse correct the threshold voltage of the noise reduction transistor, so as to delay or cancel the threshold voltage drift caused by forward bias, and ultimately significantly improve the long-term working stability and reliability of the entire noise reduction unit and GOA circuit. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 The diagram shown is a structural schematic of a gate driving module provided in an embodiment of this application.

[0020] Figure 2 The diagram shown is a schematic of a noise reduction circuit in related technologies.

[0021] Figure 3 The diagram shown is a structural schematic of a noise reduction unit provided in an embodiment of this application.

[0022] Figure 4 The diagram shown is a circuit diagram of the first noise reduction unit provided in the embodiment of this application.

[0023] Figure 5 The image shown is a waveform diagram provided in an embodiment of this application.

[0024] Figure 6 The diagram shown is a circuit diagram of the second noise reduction unit provided in the embodiment of this application.

[0025] Figure 7 The diagram shown is another waveform provided in an embodiment of this application.

[0026] Figure 8 The diagram shown is a circuit diagram of the third noise reduction unit provided in the embodiment of this application.

[0027] Figure 9 The diagram shown is another waveform provided in an embodiment of this application.

[0028] Figure 10 The diagram shown is a layout schematic of a heating module provided in an embodiment of this application.

[0029] Figure 11 The diagram shown is a flowchart of a correction method provided in an embodiment of this application.

[0030] Figure 12 The diagram shown is a circuit diagram of a noise reduction circuit provided in an embodiment of this application.

[0031] Figure 13 The diagram shown is a circuit diagram of another noise reduction circuit provided in an embodiment of this application.

[0032] Figure 14 The diagram shown is a circuit diagram of another noise reduction circuit provided in an embodiment of this application.

[0033] Explanation of reference numerals in the attached figures:

[0034] 100. Noise Reduction Unit; 101. First Noise Reduction Unit; 102. Second Noise Reduction Unit;

[0035] 110. Pull-down control module; 120. Reverse correction module; 130. Heating module;

[0036] M1, First control transistor; M2, Second control transistor; M3, Third control transistor; M4, Fourth control transistor; J1, First noise reduction transistor; J2, Second noise reduction transistor; J3, Third noise reduction transistor; T1, First transistor; T2, Second transistor; T3, Third transistor; T4, Fourth transistor; T5, Fifth transistor; T6, Sixth transistor; T7, Seventh transistor; T8, Eighth transistor; C, Coupling capacitor;

[0037] Q, drive control node; F, stage transmission output terminal; G, drive output terminal; P, noise reduction control node; K, noise reduction association node; LC1, first pull-down control terminal; LC2, second pull-down control terminal; LC3, first reverse correction terminal; LC4, second reverse correction terminal; LC5, heating control terminal; VSS1, first low-level terminal; VSS2, second low-level terminal. Detailed Implementation

[0038] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0039] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0040] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0041] The inventors of this application have discovered that the gate drive circuit includes N cascaded gate drive modules, such as... Figure 1As shown, the nth-level gate driver module mainly includes pull-up units, pull-down units, output units, reset units, and noise reduction circuits. The pull-up and pull-down units generate a Q-point voltage. The pull-up and pull-down units need to obtain multiple stage transmission signals from the upper and lower gate driver modules. The Q-point voltage is the turn-on voltage of the output unit, enabling the output unit to output the gate drive signal and provide the turn-on voltage for the display area. The reset unit is used to avoid the influence between frames. The noise reduction circuit performs noise reduction processing on the signals at each key node. Among them, Qn represents the drive control node of the nth-level gate driver module, Gn represents the drive output terminal of the nth-level gate driver module, Fn represents the stage transmission output terminal of the nth-level gate driver module, CKn represents the clock signal terminal of the nth-level gate driver module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn-3 represents the drive output terminal of the (n-3)th-level gate driver module, Fn-3 represents the stage transmission output terminal of the (n-3)th-level gate driver module, and Fn+4 represents the stage transmission output terminal of the (n+4)th-level gate driver module.

[0042] A normal output from the gate drive module is essential for ensuring proper image display; therefore, the noise reduction circuit plays a crucial role in suppressing signal noise. Figure 2 The diagram shows a schematic of a noise reduction circuit in related technologies. The noise reduction circuit typically uses two noise reduction units: a first noise reduction unit and a second noise reduction unit. These are used alternately by a first pull-down control terminal LC1 and a second pull-down control terminal LC2, respectively, to reduce the aging rate of the devices. Each noise reduction unit includes a noise reduction control unit composed of a first control transistor M1, a second control transistor M2, a third control transistor M3, and a fourth control transistor M4, and a noise reduction execution unit composed of a first noise reduction transistor J1, a second noise reduction transistor J2, and a third noise reduction transistor J3. The main reason for the decrease in noise reduction capability is the long-term drift of the threshold voltage (Vth) of the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3 due to the positive gate-source voltage (Vgs). This results in the inability to suppress noise in the GOA unit, leading to abnormal output.

[0043] To address the issue of threshold voltage drift in noise reduction transistors affecting noise reduction stability, this application provides a noise reduction unit, specifically including the following embodiments:

[0044] Figure 3The diagram shown is a structural schematic of a noise reduction unit 100 provided in an embodiment of this application. The noise reduction unit 100 in this embodiment is applied to a noise reduction circuit in a gate driving circuit, meaning it belongs to any one of the noise reduction units 100 in the noise reduction circuit. The noise reduction unit 100 in this embodiment includes a noise reduction control unit composed of a first control transistor M1, a second control transistor M2, a third control transistor M3, and a fourth control transistor M4. The noise reduction control unit is controlled by the voltage at the noise reduction control terminal and the driving control node Q in the gate driving circuit, controlling the potential at its output terminal, i.e., the noise reduction control node P, so that the noise reduction transistor performs noise reduction processing on the corresponding noise-reduced node according to the potential at the noise reduction control node P. Figure 3 As shown, at least one noise reduction transistor in this embodiment includes a first noise reduction transistor J1, a second noise reduction transistor J2 and a third noise reduction transistor J3, and the noise-reduced node includes a stage transmission output terminal F, a drive control node Q and a drive output terminal G.

[0045] like Figure 3 As shown, the noise reduction unit 100 in this embodiment also includes a pull-down control module 110, which is connected to the second terminal of at least one noise reduction transistor and configured to control the second terminal of at least one noise reduction transistor and the low-level terminal during the noise reduction stage. The low-level terminal in this embodiment can be a first low-level terminal VSS1 and a second low-level terminal VSS2. Specifically, the noise reduction stage is the working stage of the noise reduction unit 100. Under the action of the pull-down control module 110, the second terminal of at least one noise reduction transistor is connected to the first low-level terminal VSS1 and the second low-level terminal VSS2 respectively. For example, the second terminal of the first noise reduction transistor J1 and the second terminal of the second noise reduction transistor J2 are connected to the first low-level terminal VSS1, and the second terminal of the third noise reduction transistor J3 is connected to the second low-level terminal VSS2, thereby providing different discharge paths for the noise reduction transistors during the noise reduction process. Since the voltage values ​​on the first low-level terminal VSS1 and the second low-level terminal VSS2 are different, the voltage values ​​of the low-level terminals can be adjusted respectively to reduce the leakage current of different noise reduction transistors.

[0046] like Figure 3 As shown, the noise reduction unit 100 in this embodiment also includes a reverse correction module 120, which is connected to the noise reduction transistor and is configured to apply a reverse correction voltage to the noise reduction transistor during the reverse correction stage in order to reverse correct the threshold voltage of the noise reduction transistor.

[0047] It should be noted that the reverse correction phase is the non-operating phase of the noise reduction unit 100, also known as the non-noise reduction phase. During this phase, the reverse correction module 120 provides reverse correction voltages to the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3. However, the polarity of the forward bias voltage in this reverse correction phase is opposite to that of the noise reduction transistor J3. For example, the forward bias voltage of the first noise reduction transistor J1 in the noise reduction phase is the noise reduction control node P voltage Vp minus the first low-level terminal VSS1 voltage Vvss1, i.e., the forward bias voltage Vgs = Vp - Vvss1. Therefore, the reverse correction voltage provided by the reverse correction module is Vvss1 - Vp. This reverse correction voltage helps to cancel the first noise reduction transistor. The positive Vth drift of transistors J1, J2, and J3 due to forward bias during long-term noise reduction operation is noted. It should be noted that if all three transistors are connected to the same low-level terminal during the noise reduction stage, their forward biases are identical, and the reverse correction voltage provided by the reverse correction module is also identical, thus completely canceling each other out. However, if the first and second noise reduction transistors are connected to the first low-level terminal VSS1, while the third noise reduction transistor is connected to the second low-level terminal VSS2, although the forward bias voltages differ slightly during the noise reduction stage, the difference is small and can be ignored.

[0048] Therefore, it can be seen that in the noise reduction stage, the source of each noise reduction transistor is connected to a low-level terminal through the pull-down control module, so that each noise reduction transistor performs noise reduction task for the corresponding noise-reduced node; in the reverse correction stage, the reverse correction module applies a reverse correction voltage to the noise reduction transistor to reverse correct the threshold voltage of the noise reduction transistor, so as to delay or cancel the threshold voltage drift caused by forward bias, and ultimately significantly improve the long-term working stability and reliability of the entire noise reduction unit and GOA circuit.

[0049] Figure 4 The diagram shown is a circuit schematic of the first noise reduction unit provided in an embodiment of this application; as shown Figure 4As shown, the pull-down control module 110 of this embodiment includes a first transistor T1, a second transistor T2, and a third transistor T3. Specifically, the control terminal of the first transistor T1 is connected to the pull-down control terminal, the first terminal of the first transistor T1 is connected to the second terminal of the first noise reduction transistor J1, and the second terminal of the first transistor T1 is connected to the first low-level terminal VSS1. The control terminal of the second transistor T2 is connected to the control terminal of the first transistor T1, the first terminal of the second transistor T2 is connected to the second terminal of the second noise reduction transistor J2, and the second terminal of the second transistor T2 is connected to the first low-level terminal VSS1. The control terminal of the third transistor T3 is connected to the control terminal of the first transistor T1, the first terminal of the third transistor T3 is connected to the second terminal of the third noise reduction transistor J3, and the second terminal of the third transistor T3 is connected to either the first low-level terminal VSS1 or the second low-level terminal VSS2.

[0050] It should be noted that a noise reduction circuit includes a first noise reduction unit 101 and a second noise reduction unit 102. The first pull-down control signal output by the first pull-down control terminal LC1 is the noise reduction trigger signal of the first noise reduction unit 101, and the second pull-down control signal output by the second pull-down control terminal LC2 is the noise reduction trigger signal of the second noise reduction unit 102. The potentials output by the first pull-down control terminal LC1 and the second pull-down control terminal LC2 are opposite. In this embodiment, the noise reduction unit can be either the first noise reduction unit or the second noise reduction unit. Here, the first noise reduction unit is taken as an example. The pull-down control terminal is called the first pull-down control terminal LC1, which represents the noise reduction trigger terminal of the working stage of the noise reduction unit 100. That is, when the first pull-down control signal output by the first pull-down control terminal LC1 is high, it indicates that the noise reduction stage has been entered. Figure 5 As shown; at this time, during the high level period of the first pull-down control signal, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on simultaneously, so that the second terminal of the first noise reduction transistor J1 and the second terminal of the second noise reduction transistor J2 are both connected to the first low level terminal VSS1, and the second terminal of the third transistor T3 is connected to the second low level terminal VSS2, thus achieving the purpose of connecting the source of each noise reduction transistor to different low level terminals during the noise reduction stage.

[0051] like Figure 4 As shown, the reverse correction module 120 of this embodiment includes a fourth transistor T4. The control terminal of the fourth transistor T4 is connected to the first reverse correction terminal LC3. The first terminal of the fourth transistor T4 is connected to the control terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 is connected to the second terminal of the first noise reduction transistor J1, the second terminal of the second noise reduction transistor J2 and the second terminal of the third noise reduction transistor J3, respectively.

[0052] In this embodiment, the first reverse correction terminal LC3 is the correction trigger terminal of the noise reduction unit 100. That is, when the first correction signal output by the first reverse correction terminal LC3 is high, it indicates that the noise reduction unit 100 has entered the reverse correction stage. Figure 5 As shown, the reverse correction stage is located during the blanking period of a frame, and the noise reduction stage is located during the scanning period of a frame.

[0053] In this embodiment, during the reverse correction phase, the first pull-down control terminal LC1 outputs a low level, and the first transistor T1, the second transistor T2, and the third transistor T3 are simultaneously turned off. At the same time, the first reverse correction terminal LC3 outputs a high level, turning on the fourth transistor T4, thereby pulling up the potentials of the second terminal (source) of the first noise reduction transistor J1, the second terminal (source) of the second noise reduction transistor J2, and the second terminal (source) of the third noise reduction transistor J3 to a high level (e.g., VGH=VP). At this time, the potential on the noise reduction control node P is pulled down to the first low voltage Vvss1 under the action of the fourth control transistor, thereby making the gate-source voltages Vgs=Vvss1-VGH=Vvss1-Vp of the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3, which is the reverse correction voltage used to reverse bias the noise reduction transistors.

[0054] Figure 6 The diagram shown is a circuit diagram of the second noise reduction unit 100 provided in an embodiment of this application; Figure 6 The noise reduction unit 100 shown is Figure 4 The difference between the noise reduction unit 100 shown lies in the circuit structure of the reverse correction module; specifically as follows: Figure 6 As shown, the reverse correction module includes a fourth transistor T4, a coupling capacitor C, and a fifth transistor T5. The control terminal of the fourth transistor T4 is connected to the noise reduction associated node K, and the first terminal of the fourth transistor T4 is connected to the second terminal of the first noise reduction transistor J1, the second terminal of the second noise reduction transistor J2, and the second terminal of the third noise reduction transistor J3. The first terminal of the coupling capacitor C is connected to the second terminal of the fourth transistor T4. The control terminal of the fifth transistor T5 is connected to the noise reduction control node P, and the first terminal of the fifth transistor T5 is connected to the second terminal of the coupling capacitor C. The second terminal of the fifth transistor T5 is connected to the control terminal of the fifth transistor T5.

[0055] It should be noted that, taking a noise reduction circuit including a first noise reduction unit 101 and a second noise reduction unit 102 as an example, the noise reduction control node P is the control terminal of the noise reduction transistor in the first noise reduction unit 101, and the noise reduction associated node K is the control terminal of the noise reduction transistor in the second noise reduction unit 102. Therefore, the potentials of the noise reduction control node P and the noise reduction associated node K are opposite. The first pull-down control terminal LC1 has the same potential as the noise reduction control node P, and the second pull-down control terminal LC2 has the same potential as the noise reduction associated node K. Figure 7 As shown.

[0056] In this embodiment, during the noise reduction stage, the high-level signal output by the first pull-down control terminal LC1 not only simultaneously turns on the first transistor T1, the second transistor T2, and the third transistor T3, but also simultaneously turns on the first control transistor M1 and the second control transistor M2, setting the potential on the noise reduction control node P to a high level. At this time, since the noise reduction control node P is at a high potential, the fifth transistor T5 is turned on, the noise reduction associated node K is at a low potential, and the fourth transistor T4 is turned off. The high potential on the noise reduction control node P charges the coupling capacitor C through the turned-on fifth transistor T5.

[0057] During the reverse correction phase, the first pull-down control terminal outputs a low-level signal, and the noise reduction control node P is pulled down to a low level through the fourth control transistor M4, while the fifth transistor T5 is turned off. At this time, the noise reduction associated node K is at a high potential, turning on the fourth transistor T4. The voltage in the coupling capacitor C is released through the fourth transistor T4 to the sources of the first noise reduction transistor J1, the second noise reduction transistor J2, and the third noise reduction transistor J3. At this time, the gate-source voltage Vgs of the noise reduction transistor is Vvss1-Vp, which is the reverse correction voltage used to reverse bias the noise reduction transistor.

[0058] Figure 8 The diagram shown is a circuit diagram of the third noise reduction unit 100 provided in an embodiment of this application; Figure 8 The noise reduction unit 100 shown is Figure 4 The noise reduction unit 100 shown differs in that the circuit structures of the pull-down control module and the reverse correction module are different; specifically as follows: Figure 8As shown, the pull-down control module 110 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; the control terminal of the first transistor T1 is connected to the first inverse correction terminal LC3, and the first terminal of the first transistor T1 is connected to the second terminal of the first noise reduction transistor J1; the control terminal of the second transistor T2 is connected to the control terminal of the first transistor T1, and the first terminal of the second transistor T2 is connected to the second terminal of the second noise reduction transistor J2; the control terminal of the third transistor T3 is connected to the control terminal of the first transistor T1, and the first terminal of the third transistor T3 is connected to the second terminal of the third noise reduction transistor J3; the sixth transistor T6... The control terminal of transistor T4 is connected to the pull-down control terminal. The first terminal of transistor T4 is connected to the second terminal of transistor T1, and the second terminal of transistor T4 is connected to the first low-level terminal VSS1. The control terminal of transistor T5 is connected to the control terminal of transistor T4. The first terminal of transistor T5 is connected to the second terminal of transistor T2, and the second terminal of transistor T5 is connected to the first low-level terminal VSS1. The control terminal of transistor T6 is connected to the control terminal of transistor T4. The first terminal of transistor T6 is connected to the second terminal of transistor T3, and the second terminal of transistor T6 is connected to the second low-level terminal VSS2.

[0059] The reverse correction module 120 in this embodiment includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 is connected to the second reverse correction terminal LC4. The first terminal of the seventh transistor T7 is connected to the second terminal of the first noise reduction transistor J1, the second terminal of the second noise reduction transistor J2, and the second terminal of the third noise reduction transistor J3, respectively. The second terminal of the seventh transistor T7 is connected to the control terminal of the seventh transistor T7. The control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7. The first terminal of the eighth transistor T8 is connected to the noise reduction control node P. The second terminal of the eighth transistor T8 is connected to the first low-level terminal VSS1.

[0060] It should be noted that, as Figure 9 As shown, in this embodiment, the pull-down control terminal outputs a high-level signal during the working period of the noise reduction unit (including the noise reduction stage and the reverse correction stage). The first reverse correction terminal LC3 outputs a high level during the noise reduction stage (i.e., the scanning stage) and a low level during the reverse correction stage (i.e., the blanking stage). The potential of the second reverse correction terminal LC4 is opposite to that of the first reverse correction terminal LC3. Here, taking the first noise reduction unit in the noise reduction circuit as an example, its working principle is explained as follows:

[0061] (1) During the noise reduction stage (i.e., the scanning period): Since the first pull-down control terminal LC1 outputs a high-level signal, the first reverse correction terminal LC3 outputs a high-level signal and the second reverse correction terminal LC4 outputs a low-level signal, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on at the same time, and the seventh transistor T7 and the eighth transistor T8 are turned off at the same time. Thus, the second terminals of the first noise reduction transistor J1, the second noise reduction transistor J2 and the third noise reduction transistor J3 are respectively connected to the low-level terminal, thereby realizing the noise reduction processing of the drive output terminal, the drive control node and the stage transmission output terminal.

[0062] (2) During the reverse correction phase (i.e. blanking period): Since the first pull-down control terminal LC1 still outputs a high-level signal, the first reverse correction terminal LC3 outputs a low-level signal, and the second reverse correction terminal LC4 outputs a high-level signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned off, thereby disconnecting the source of the noise reduction transistor from the low-level terminal; at the same time, due to the high-level signal output by the second reverse correction terminal LC4, the seventh transistor T7 and the eighth transistor T8 are turned on simultaneously, so that the potential of the noise reduction control node P is pulled down to the low potential Vvss1 through the conducting eighth transistor T8, and the source of the noise reduction transistor is pulled up to the high potential (VGH=Vp) through the conducting seventh transistor T7. At this time, the gate-source voltage Vgs of the noise reduction transistor is Vvss1-Vp, which is the reverse correction voltage used to reverse bias the noise reduction transistor.

[0063] In one embodiment, the noise reduction unit 100 further includes a heating module 130 connected to the heating control terminal LC5, configured to heat at least one noise reduction transistor in response to a heating control signal output on the heating control terminal LC5 when the noise reduction unit 100 is in the reverse correction phase. That is, while the reverse correction module 120 performs reverse correction on at least one noise reduction transistor, the heating module 130 heats at least one noise reduction transistor, increasing the electron mobility of a-Si, increasing Ion, and promoting a rapid increase in reverse Vgs. This can quickly delay or offset the threshold voltage drift caused by the forward Vgs.

[0064] In this embodiment, the heating module 130 is a metal trace layer, which at least partially overlaps with the gate trace of at least one noise reduction transistor in its layout. Specifically, the gate traces of all noise reduction transistors are typically spaced apart on the same metal layer; however, the metal trace layer of the heating module 130 can be directly above or directly below the gate trace, as specifically designed as follows: Figure 10As shown; simultaneously, the metal trace, which serves as the heating control terminal LC5, is electrically connected to the metal trace layer. By applying voltage to the heating control terminal LC5, the metal trace layer heats up, thereby achieving the function of heating the noise reduction transistor; in addition, when the product is in a high-temperature environment, the transistor's IV curve will shift to the right. In this embodiment, the reverse Vgs time is greater than the forward Vgs time, the electron mobility of a-Si is greater, and Ion is greater, which promotes the rapid increase of reverse Vgs. This can effectively promote the transistor's IV curve to return to positive, so that the noise of the GOA unit can be effectively suppressed, resulting in better output performance.

[0065] Figure 11 The diagram shown is a flowchart illustrating a correction method provided in an embodiment of this application; as follows: Figure 9 As shown, the correction method of this embodiment is applied to the noise reduction unit shown in the above embodiment, and specifically includes the following steps:

[0066] Step S100: In the noise reduction stage, the second terminal of at least one noise reduction transistor is connected to the low-level terminal by the pull-down control module, so that the at least one noise reduction transistor performs noise reduction on the node to be denoised.

[0067] Step S200: In the reverse correction stage, the pull-down control module is turned off, and a reverse correction voltage is applied to the at least one noise reduction transistor through the reverse correction module to reverse correct the threshold voltage of the noise reduction transistor.

[0068] It should be noted that the working principle of the correction method in this embodiment is the same as that of the noise reduction unit described above, and will not be repeated here.

[0069] Figure 12 The diagram shown is a circuit diagram of a noise reduction circuit provided in an embodiment of this application. Figure 13 The diagram shown is a circuit diagram of another noise reduction circuit provided in an embodiment of this application. Figure 14 The diagram shown is a circuit diagram of another noise reduction circuit provided in an embodiment of this application; as follows: Figure 12 , Figure 13 and Figure 14 As shown, the noise reduction circuit of this embodiment includes: a first noise reduction unit 101, which is configured as the noise reduction unit 100 shown in the above embodiment, and the noise reduction trigger terminal of the first noise reduction unit 101 is connected to the first pull-down control terminal LC1.

[0070] The noise reduction circuit in this embodiment also includes a second noise reduction unit 102, which is configured as the noise reduction unit 100 shown in the above embodiment. The noise reduction trigger terminal of the second noise reduction unit 102 is connected to the second pull-down control terminal LC2. The first noise reduction unit 101 and the second noise reduction unit 102 work alternately in the noise reduction stage and the reverse correction stage.

[0071] In one embodiment, this application provides a gate driving circuit including N cascaded gate driving modules. The nth-stage gate driving module includes a pull-up unit, a pull-down unit, an output unit, and a noise reduction circuit. The pull-up unit is connected to the drive output terminal and the stage transmission output terminal of the ni-th-stage gate driving module, respectively. The pull-down unit is connected to the stage transmission output terminal of the (n+j)th-stage gate driving module and is also connected to the pull-up unit through a drive control node. The output unit is connected to a clock signal terminal and a drive control node, respectively. The noise reduction circuit is connected to the drive control node, drive output terminal, and stage transmission output terminal of the current-stage gate driving module, respectively.

[0072] It should be noted that the specific structure of the gate driving module provided in this embodiment is as follows: Figure 1 As shown above, the working principle of the gate drive module was explained using i=3 and j=4 as an example, and will not be repeated here.

[0073] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0074] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0075] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A noise reduction unit, characterized in that, The noise reduction unit includes: At least one noise reduction transistor, wherein the control terminal of the noise reduction transistor is connected to a noise reduction control node, and the first terminal of the noise reduction transistor is connected to the node to be denoised; wherein the at least one noise reduction transistor includes a first noise reduction transistor, a second noise reduction transistor, and a third noise reduction transistor; A pull-down control module, connected to the second terminal of the noise reduction transistor, is configured to control the second terminal of the noise reduction transistor to be connected to a low-level terminal during the noise reduction phase. A reverse correction module, connected to the noise reduction transistor, is configured to apply a reverse correction voltage to the noise reduction transistor during the reverse correction phase to reverse correct the threshold voltage of the noise reduction transistor. The reverse correction module includes: A fourth transistor, the control terminal of which is connected to a noise reduction associated node, and the first terminal of which is connected to the second terminal of the first noise reduction transistor, the second terminal of the second noise reduction transistor, and the second terminal of the third noise reduction transistor; wherein, the potential of the noise reduction associated node is opposite to that of the noise reduction control node; A coupling capacitor, wherein the first terminal of the coupling capacitor is connected to the second terminal of the fourth transistor; The fifth transistor has its control terminal connected to the noise reduction control node, its first terminal connected to the second terminal of the coupling capacitor, and its second terminal connected to the control terminal of the fifth transistor.

2. The noise reduction unit according to claim 1, characterized in that, The drop-down control module includes: The first transistor has a control terminal connected to a pull-down control terminal, a first terminal of the first transistor connected to a second terminal of the first noise reduction transistor, and a second terminal of the first transistor connected to a first low-level terminal. The second transistor has a control terminal connected to the control terminal of the first transistor, a first terminal of the second transistor connected to the second terminal of the second noise reduction transistor, and a second terminal of the second transistor connected to the first low-level terminal. The third transistor has its control terminal connected to the control terminal of the first transistor, its first terminal connected to the second terminal of the third noise reduction transistor, and its second terminal connected to either the first low-level terminal or the second low-level terminal.

3. A noise reduction unit, characterized in that, The noise reduction unit includes: At least one noise reduction transistor, wherein the control terminal of the noise reduction transistor is connected to a noise reduction control node, and the first terminal of the noise reduction transistor is connected to the node to be denoised; wherein the at least one noise reduction transistor includes a first noise reduction transistor, a second noise reduction transistor, and a third noise reduction transistor; A pull-down control module, connected to the second terminal of the noise reduction transistor, is configured to control the second terminal of the noise reduction transistor to be connected to a low-level terminal during the noise reduction phase. A reverse correction module, connected to the noise reduction transistor, is configured to apply a reverse correction voltage to the noise reduction transistor during the reverse correction phase to reverse correct the threshold voltage of the noise reduction transistor. The reverse correction module includes: The seventh transistor has its control terminal connected to the second reverse correction terminal, its first terminal connected to the second terminal of the first noise reduction transistor, the second terminal of the second noise reduction transistor, and the second terminal of the third noise reduction transistor, and its second terminal connected to the control terminal of the seventh transistor. The eighth transistor has its control terminal connected to the control terminal of the seventh transistor, its first terminal connected to the noise reduction control node, and its second terminal connected to the first low-level terminal.

4. The noise reduction unit according to claim 3, characterized in that, The drop-down control module includes: The first transistor has a control terminal connected to a first inverse correction terminal, and a first terminal of the first transistor is connected to a second terminal of the first noise reduction transistor. The second transistor has its control terminal connected to the control terminal of the first transistor, and its first terminal is connected to the second terminal of the second noise reduction transistor. The third transistor has its control terminal connected to the control terminal of the first transistor, and its first terminal connected to the second terminal of the third noise reduction transistor. The fourth transistor has its control terminal connected to the pull-down control terminal, its first terminal connected to the second terminal of the first transistor, and its second terminal connected to the first low-level terminal. The fifth transistor has its control terminal connected to the control terminal of the fourth transistor, its first terminal connected to the second terminal of the second transistor, and its second terminal connected to the first low-level terminal. The sixth transistor has its control terminal connected to the control terminal of the fourth transistor, its first terminal connected to the second terminal of the third transistor, and its second terminal connected to the second low-level terminal.

5. The noise reduction unit according to any one of claims 1-4, characterized in that, The noise reduction unit also includes: A heating module, connected to a heating control terminal, is configured to heat the at least one noise reduction transistor in response to a heating control signal output from the heating control terminal when the noise reduction unit is in the reverse correction phase.

6. A correction method, characterized in that, The correction method, applied to the noise reduction unit according to any one of claims 1-5, comprises: During the noise reduction stage, the pull-down control module controls the second terminal of at least one noise reduction transistor to be connected to the low-level terminal, so that the at least one noise reduction transistor performs noise reduction on the node to be denoised. During the reverse correction phase, the pull-down control module is turned off, and a reverse correction voltage is applied to the at least one noise reduction transistor through the reverse correction module to reverse correct the threshold voltage of the noise reduction transistor.

7. A noise reduction circuit, characterized in that, The noise reduction circuit includes: The first noise reduction unit is configured as the noise reduction unit according to any one of claims 1-5, wherein the noise reduction trigger terminal of the first noise reduction unit is connected to the first pull-down control terminal. The second noise reduction unit is configured as the noise reduction unit according to any one of claims 1-5, wherein the noise reduction trigger terminal of the second noise reduction unit is connected to the second pull-down control terminal; The first noise reduction unit and the second noise reduction unit work alternately in the noise reduction stage and the reverse correction stage.

8. A gate driving circuit, comprising N cascaded gate driving modules, characterized in that, The nth-stage gate drive module includes: Pull-up unit, the pull-up unit is connected to the drive output terminal of the ni-th gate drive module and the stage transmission output terminal of the ni-th gate drive module respectively; A pull-down unit is connected to the stage transmission output terminal of the (n+j)th stage gate drive module, and the pull-down unit is also connected to the pull-up unit through a drive control node; An output unit, wherein the output unit is connected to both the clock signal terminal and the drive control node; The noise reduction circuit of claim 7 is connected to the drive control node, drive output terminal and stage transmission output terminal of the current stage gate drive module, respectively.

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