Two-step adc circuit, module based on flash architecture optimization

Abstract

The present application relates to the technical field of CMOS image sensor design, and in particular to a two-step ADC circuit and module based on Flash architecture optimization. The present application provides a two-step ADC circuit based on Flash architecture optimization, which comprises a data input unit, a comparator unit, a Flash-ADC unit, a voltage lifting unit, an SS-ADC unit, and a result output unit. The present application combines SS ADC and Flash ADC to form a two-step ADC, and further splits the quantization of the Flash-ADC unit, so that the number of comparators is reduced from 7 to 4 while keeping the quantization time unchanged, effectively reducing the circuit area.

Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor design technology, and more specifically, to: 1. a two-step ADC circuit based on Flash architecture optimization; 2. a two-step ADC module based on Flash architecture optimization. Background Technology

[0002] A typical CMOS image sensor includes a pixel array, readout circuitry, and driver circuitry. The analog-to-digital converter (ADC), acting as a bridge between natural signals and a digital processor, is a crucial part of the readout circuitry. ADCs can be categorized into three types based on their integration level: pixel-level, column-level, and chip-level. Column-level ADCs offer advantages such as high speed and low power consumption, making them the most widely used type in CMOS image sensors.

[0003] Common column-level ADC architectures include: single-slope ADC (SS ADC), successive approximation ADC (SAR ADC), and cyclic ADC. Among them, SS ADC is widely used due to its simple circuit structure and good cell consistency. However, SS ADC suffers from the drawback that its readout speed increases exponentially with the increase of bit depth. To ensure quantization speed, the inventors attempted to choose Flash ADC, which has the advantage of extremely fast quantization speed. However, existing Flash ADC circuits have a large number of comparators (generally at least 7), resulting in a large circuit area and limiting its application in CMOS image sensors. Summary of the Invention

[0004] Therefore, it is necessary to address the issue of excessive circuit area caused by the large number of comparators in existing Flash ADCs by providing a two-step ADC circuit and module optimized based on Flash architecture.

[0005] This invention is achieved using the following technical solution:

[0006] In a first aspect, the present invention provides a two-step ADC circuit based on Flash architecture optimization, which is used to perform 11-bit quantization on two columns of pixel signals Vpixel1~Vpixel2 to obtain two corresponding quantization results D1[10:0]~D2[10:0].

[0007] The two-step ADC circuit based on Flash architecture optimization includes: a data input section, a comparator section, a Flash-ADC section, a voltage boost section, an SS-ADC section, and a result output section.

[0008] The data input unit samples Vpixel1 and Vpixel2 to the comparator unit in a preset order.

[0009] The comparator section includes four comparators, Comp1 to Comp4. During serial coarse quantization of the lower three bits, Comp1 to Comp4 generate two 4-bit thermometer codes sequentially. During parallel coarse quantization of the fourth bit, Comp1 and Comp3 generate two control signals, Vref-control1 and Vref-control2, respectively. During parallel quantization of the higher seven bits, Comp1 to Comp4 generate four intersecting signals, Ramp1 and Ramp4, respectively.

[0010] The Flash-ADC works in conjunction with the comparator unit to perform serial coarse quantization of the lower 3 bits and obtain the shared voltage net_cap.

[0011] The voltage boosting section is used to: directly output net_cap as two boosted voltages Vout1~Vout2 during parallel coarse quantization of the 4th bit; and to boost net_cap in conjunction with the ramp signal Vramp1 to output Vout1 and boost net_cap in conjunction with the ramp signal Vramp2 to output Vout2 during parallel high 7-bit quantization.

[0012] The SS-ADC section provides Vramp1~Vramp2 to the voltage boost section to cooperate with the comparator section in performing parallel high 7-bit quantization.

[0013] The output section is used to: convert the two consecutive 4-digit thermometer codes into D1[2:0] and D2[2:0] respectively; set Vref-control1 and Vref-control2 as D1[3] and D2[3] respectively; obtain D1[4] and D1[10:5] based on Ramp1~Ramp2; and obtain D2[4] and D2[10:5] based on Ramp3~Ramp4.

[0014] This implementation of a two-step ADC circuit based on a Flash architecture optimized according to the method or process of an embodiment of the present disclosure.

[0015] Secondly, the present invention discloses a two-step ADC module based on Flash architecture optimization, which adopts the layout of the two-step ADC circuit based on Flash architecture optimization as disclosed in the first aspect.

[0016] This implementation of a two-step ADC module based on a Flash architecture optimized according to the method or process of an embodiment of this disclosure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. This invention combines SS ADC and Flash ADC to form a two-step ADC, and further decomposes the quantization of the Flash-ADC section to reduce the number of comparators from 7 to 4 while keeping the quantization time unchanged, effectively reducing the circuit area.

[0019] 2. The Flash-ADC section and SS-ADC section of the present invention adopt the same global quantization method, which greatly saves area overhead; and when performing coarse quantization of the lower 3 bits, the present invention uses four comparators shared by two adjacent columns to compress serial quantization into two columns, thereby speeding up the overall quantization speed.

[0020] 3. This invention utilizes the advantage of equal voltage division in the resistor series of the Flash-ADC section to further divide the minimum voltage change required for coarse quantization of the lower 3 bits, and with the addition of a point judgment mechanism, reduces the number of comparators required to work from 4 to 2, effectively reducing power consumption.

[0021] 4. This invention adds an extended ramp to the SS-ADC section to extend the upper negative ramp signal to increase the fine quantization range, and introduces an error calibration mechanism to correct the error caused by the voltage intersecting at the extended section, thus ensuring the correctness of the quantization results. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 The overall structure diagram of the two-step ADC circuit based on Flash architecture optimization provided by the present invention;

[0024] Figure 2 for Figure 1 Circuit diagram of the data input section;

[0025] Figure 3 for Figure 1 Circuit diagram of the comparator section;

[0026] Figure 4 for Figure 3 Circuit diagram of Comp1 or Comp3;

[0027] Figure 5 for Figure 3 Circuit diagram of Comp2 or Comp4;

[0028] Figure 6 for Figure 3Circuit diagram of the Flash-ADC section;

[0029] Figure 7 for Figure 3 Circuit diagram of the medium voltage boost section;

[0030] Figure 8 for Figure 3 Partial circuit diagram of the SS-ADC section;

[0031] Figure 9 for Figure 3 Another part of the circuit diagram of the SS-ADC section;

[0032] Figure 10 for Figure 3 Circuit diagram of the result output section. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] Example 1

[0037] See Figure 1 , Figure 1 The overall structure diagram of a two-step ADC circuit based on Flash architecture optimization provided by the present invention is shown. It belongs to the column-level ADC and is used to perform 11-bit quantization on two column pixel signals Vpixel1~Vpixel2 to obtain two corresponding quantization results D1[10:0]~D2[10:0].

[0038] First, it should be noted that the 11-bit quantization process includes:

[0039] S1, perform serial coarse quantization of the lower 3 bits — that is: first perform coarse quantization of the lower 3 bits of Vpixel1, and then perform coarse quantization of the lower 3 bits of Vpixel2.

[0040] S2, perform parallel 4th bit coarse quantization - that is: synchronously perform 4th bit coarse quantization on Vpixel1 and Vpixel2;

[0041] S3 performs parallel high-7-bit quantization—that is, synchronously performs high-7-bit coarse quantization on Vpixel1 and Vpixel2. This high-7-bit quantization includes: coarse quantization at the 5th bit and fine quantization at the 6th bit.

[0042] It should be noted that in the high 7 rows of quantization in a single row, the 5th bit coarse quantization and the high 6th bit fine quantization are also performed simultaneously.

[0043] Therefore, in chronological order, the 11-bit quantization process of Vpixel1~Vpixel2 can be divided into 4 stages Y1~Y4:

[0044] Y1 means: coarse quantization of the lower 3 bits of Vpixel1;

[0045] Y2 means: coarse quantization of the lower 3 bits of Vpixel2;

[0046] Y3 means: synchronously perform 4th-bit coarse quantization on Vpixel1 and Vpixel2;

[0047] Y4 means: synchronously perform high 7-bit coarse quantization on Vpixel1 and Vpixel2.

[0048] Second, we will introduce the circuit structure of a two-step ADC circuit optimized based on Flash architecture—which integrates Flash ADC and SS ADC. For example... Figure 1 As shown, the two-step ADC circuit based on the Flash architecture optimization can be divided according to its function, and may include: a data input section, a comparator section, a Flash-ADC section, a voltage boost section, an SS-ADC section, and a result output section; it may also include: an error calibration section.

[0049] The following will explain each point in detail:

[0050] (a) The data input section is used to sample Vpixel1 and Vpixel2 to the comparator section in a preset order.

[0051] The preset order is as follows: Vpixel1 is sampled separately at Y1, Vpixel2 is sampled separately at Y2, and sampling is shared at Y3 and Y4.

[0052] See Figure 2 The data input section can be designed to include: 2 pixel switches Sp1~Sp2, 2 ground switches SS1~SS2, 2 reference switches SV1~SV2, 2 sampling capacitors SC1~SC2, and 3 switching switches switch1~switch3.

[0053] The specific circuit connections are as follows:

[0054] The upper plate of SC1 is connected to Vpixel1 via Sp1, and the lower plate is connected to ground VSS via SS1 and to a fixed voltage Va via SV1; the upper plate of SC2 is connected to Vpixel2 via Sp2, and the lower plate is connected to VSS via SS2 and to Va via SV2; the first end of switch1 is connected to the upper plate of SC1, and the second end is connected to the first end of switch3 and is used to output the input signal Vin1; the first end of switch2 is connected to the upper plate of SC2, and the second end is connected to the second end of switch3 and is used to output the input signal Vin2.

[0055] Therefore, to achieve the above-mentioned preset order, we have:

[0056] At Y1: Sp1 and SS1 are on, SV1 is off, Sp2, SS2 and SV2 are off, switch1 and switch3 are on, and switch2 is off; at this time, Vpixel1 is directly output as Vin1 and Vin2, that is, Vin1=Vin2=Vpixel1.

[0057] At Y2: Sp2 and SS2 are on, SV2 is off, Sp1, SS1, and SV1 are off, switch2 and switch3 are on, and switch1 is off; at this time, Vpixel2 is directly output as Vin1 and Vin2, that is, Vin1=Vin2=Vpixel2.

[0058] During Y3 and Y4: switch1 and switch2 are connected, and switch3 is disconnected; at this time, Vin1 and Vin2 are not connected, and sampling sharing is performed.

[0059] It should be noted that SV1 is controlled by the control signal Vref-control1 to switch on and off; SV2 is controlled by the control signal Vref-control2 to switch on and off.

[0060] Specifically, when Vref-control1=1, SV1 is on; when Vref-control1=0, SV1 is off; when Vref-control2=1, SV2 is on; when Vref-control2=0, SV2 is off.

[0061] (ii) The comparator is used to switch between different inputs at different stages to perform the corresponding quantization operation.

[0062] See Figure 3 The price comparison unit can be designed to include: 4 comparators Comp1~Comp4; it can also include: switch array one, which includes: 4 column one switches SX1~SX4 and 4 column two switches SY1~SY4, used to control the input of Comp1~Comp4.

[0063] The specific circuit connections are as follows:

[0064] The positive input terminal of Comp1 is connected to the voltage divider potential V8 through SX1 and the boost voltage Vout1 through SX2. The negative input terminal is connected to Vin1. Output terminal one is used to output the thermometer code Q1, output terminal two is used to output the crossover signal Ramp1, and output terminal three is used to output Vref-control1.

[0065] The positive input terminal of Comp2 is connected to the voltage divider level SW1 via SX3 and the boost voltage Vout2 via SX4. The negative input terminal is connected to Vin1. Output terminal one is used to output the thermometer code Q2, and output terminal two is used to output the crossover signal Ramp2.

[0066] The positive input terminal of Comp3 is connected to the voltage divider level SW3 via SY1 and to Vout1 via SY2. The negative input terminal is connected to Vin2. Output terminal one is used to output the thermometer code Q3, output terminal two is used to output the crossover signal Ramp3, and output terminal three is used to output Vref-control2.

[0067] The positive input terminal of Comp4 is connected to the voltage divider level SW2 via SY3 and to Vout2 via SY4. The negative input terminal is connected to Vin2. Output terminal one is used to output the thermometer code Q4, and output terminal two is used to output the crossover signal Ramp4.

[0068] See Figure 4 For Comp1 and Comp3, their structures are the same, both including: 2 amplifiers A1~A2, 1 latch_A, 2 buffers buffer1~buffer2, 1 output buffer Output_buffer1, 2 D flip-flops DFF1~DFF2, and 1 XOR gate.

[0069] Input terminal 1 of A1 serves as the positive input of the entire comparator, and input terminal 2 serves as the negative input. Output terminal 1 is connected to input terminal 1 of A2, and output terminal 2 is connected to input terminal 2 of A2. Output terminal 1 of A2 is connected to input terminal 1 of latch_A, and output terminal 2 is connected to input terminal 2 of latch_A. Output terminal 1 of latch_A is connected to the input of buffer1, and output terminal 2 is connected to the input of buffer2. The output of buffer1 is connected to the input of DFF1 and input terminal 1 of Output_buffer1, and the output of DFF1 serves as the second output of the entire comparator. The output of buffer2 is connected to the input of DFF2 and input terminal 2 of Output_buffer1, and the output of Output_buffer1 serves as the first output of the entire comparator. Input terminal 1 of XOR is connected to the power supply VDD, input terminal 2 is connected to the output of DFF2, and the output terminal serves as the third output of the entire comparator.

[0070] See Figure 5 For Comp2 and Comp4, their structures are the same, both including: 2 amplifiers A3~A4, 1 latch_B, 2 buffers buffer3~buffer4, 1 output buffer Output_buffer2, and 1 D flip-flop DFF3.

[0071] Input terminal 1 of A3 serves as the positive input of the entire comparator, and input terminal 2 serves as the negative input. Output terminal 1 is connected to input terminal 1 of A4, and output terminal 2 is connected to input terminal 2 of A4. Output terminal 1 of A4 is connected to input terminal 1 of latch_B, and output terminal 2 is connected to input terminal 2 of latch_B. Output terminal 1 of latch_B is connected to the input of buffer3, and output terminal 2 is connected to the input of buffer4. The output of buffer3 is connected to the input of DFF3 and input terminal 1 of Output_buffer2, and the output of DFF3 serves as output terminal 2 of the entire comparator. The output of buffer4 is connected to input terminal 2 of Output_buffer2, and the output of Output_buffer2 serves as output terminal 1 of the entire comparator.

[0072] Therefore, to achieve the corresponding quantification, we have:

[0073] When Y1 and Y2 are active, SX1 is on and SX2 is off. The inputs to Comp1 are Vin1 and V8, and the output is Q1. When SX3 is on and SX4 is off, the inputs to Comp2 are Vin1 and SW1, and the output is Q2. When SY1 is on and SY2 is off, the inputs to Comp3 are Vin2 and SW3, and the output is Q3. When SY3 is on and SY4 is off, the inputs to Comp4 are Vin2 and SW2, and the output is Q4. Q1 to Q4 form a 4-digit thermometer code.

[0074] In other words, during the serial coarse quantization of the lower 3 bits, Comp1~Comp4 generate two 4-bit thermometer codes sequentially. It should be noted that since Vin1~Vin2 of Y1 (with a value of Vpixel1) and Vin1~Vin2 of Y2 (with a value of Vpixel2) have different value sources, the 4-bit thermometer codes of Y1 and Y2 may have different values.

[0075] At Y3, SX1 is disconnected and SX2 is connected. The inputs of Comp1 are Vin1 and Vout1, and the output is Vref-control1. SY1 is disconnected and SY2 is connected. The inputs of Comp3 are Vin2 and Vout2, and the output is Vref-control2. Comp2 and Comp4 are not working.

[0076] In other words, during the parallel coarse quantization of the 4th bit, Comp1 and Comp3 generate two control signals Vref-control1 to Vref-control2 respectively.

[0077] At Y4, SX1 is disconnected and SX2 is connected. The inputs of Comp1 are Vin1 and Vout1, and the output is Ramp1. SX3 is disconnected and SX4 is connected. The inputs of Comp2 are Vin1 and Vout2, and the output is Ramp2. SY1 is disconnected and SY2 is connected. The inputs of Comp3 are Vin2 and Vout1, and the output is Ramp3. SY3 is disconnected and SY4 is connected. The inputs of Comp4 are Vin2 and Vout2, and the output is Ramp4.

[0078] In other words, during parallel high 7-bit quantization, Comp1~Comp4 generate four intersecting signals Ramp1~Ramp4 respectively.

[0079] (iii) The Flash-ADC section is used to: cooperate with the comparator section to perform serial coarse quantization of the lower 3 bits and obtain the shared voltage net_cap.

[0080] See Figure 6The Flash-ADC section is designed with reference to the Flash ADC and may include: a resistor array, a second switch array, a third switch array, and a decoder.

[0081] The input terminal of the decoder is connected to the output terminal of Comp1~Comp4, and the output terminal is used to output 8 control levels Control1~Control8. That is to say, the decoder is used to generate 8 control levels Control1~Control8 based on the 4-bit thermometer code.

[0082] The resistor array consists of 16 resistors R1~R1 connected in series. 16 The end of R1 furthest from R2 is connected to the array voltage Vlow; R 16 Stay away from R 15 One end is connected to the array voltage Vhigh; R i With R i+1 A voltage divider potential V is formed between them i , i∈[1,15]. It should be noted that R1~R 16 The resistance values ​​are the same, so that an evenly distributed voltage is formed between Vhigh and Vlow.

[0083] Switch array two is used to include: 3 switches A1~A3 listed above, 3 switches B1~B3 listed below; V2 is connected to V14 through B1 and A1 connected in series; SW1 is formed between B1 and A1; V4 is connected to V12 through B2 and A2 connected in series; SW2 is formed between B2 and A2; V6 is connected to V10 through B3 and A3 connected in series; SW3 is formed between B3 and A3.

[0084] It should be noted that A1~A3 and B1~B3 are switched on and off by Q1. Specifically, when Q1=1, A1~A3 are on and B1~B3 are off; when Q1=0, A1~A3 are off and B1~B3 are on.

[0085] Switch array three includes: eight toggle switches S1~S8; the first terminal of S1 is connected to V1, the first terminal of S2 is connected to V3, the first terminal of S3 is connected to V5, the first terminal of S4 is connected to V7, the first terminal of S5 is connected to V9, and the first terminal of S6 is connected to V... 11 The first end of S7 is connected to V. 13 The first end of S8 is connected to V. 15 The second ends of S1 to S8 are connected together and used to output net_cap.

[0086] It is important to note that S j Subject to Control j Control is used to switch on and off; j∈[1,8]. Specifically, Controlj When =1, S j On; Control j When =0, S j disconnect.

[0087] (iv) The voltage boosting unit is used to provide corresponding boosted voltages in Y3 and Y4. Specifically, in Y3, the voltage boosting unit directly outputs net_cap as two boosted voltages Vout1~Vout2; in Y4, the voltage boosting unit boosts net_cap in conjunction with the positive ramp signal Vramp1 to output Vout1, and boosts net_cap in conjunction with the negative ramp signal Vramp2 to output Vout2.

[0088] See Figure 7 The voltage boosting section can be designed to include: two input switches Sq1~Sq2, two grounding switches SD1~SD2, two boosting switches SU1~SU2, and two sampling capacitors HC1~HC2.

[0089] The upper plate of HC1 is used to output Vout1; the upper plate of HC1 is connected to net_cap through Sq1, and the lower plate is connected to ground VSS through SD1 and to Vramp1 through SU1; the upper plate of HC2 is used to output Vout2; the upper plate of HC2 is connected to net_cap through Sq2, and the lower plate is connected to ground VSS through SD2 and to Vramp2 through SU2.

[0090] Therefore, to achieve the corresponding voltage output, we have:

[0091] At Y3, Sq1 and Sq2, SD1 and SD2 are turned on, and SU1 and SU2 are turned off.

[0092] At Y4, Sq1, Sq2, SD1, and SD2 are disconnected, while SU1 and SU2 are connected.

[0093] (v) The SS-ADC section is used to provide Vramp1~Vramp2 to the voltage boost section to cooperate with the comparator section to perform parallel high 7-bit quantization.

[0094] See Figure 8 The SS-ADC section is designed with reference to the SS ADC and may include: a differential ramp generation section and a counting section; it may also include: a negative ramp extension section and a positive ramp extension section.

[0095] The differential ramp generator is a 7-bit current-steering ADC used to provide the basic ramp segments for positive and negative ramp signals. The differential ramp generator includes: a current source array, a differential switch array, and two resistors RV1~RV2. The first terminal of RV1 is used to output Vramp1; the first terminal of RV2 is used to output Vramp2; the second terminal of RV1 is grounded to VSS. The current source array includes: 64 differential current sources I1~I... connected in parallel. 64 The differential switch array includes: 64 switches Se1~Se 64 64 switches Sf1~Sf 64 ;I k The output terminal is connected to Se k Connect the first end of RV1, via Sf k Connect the first end of RV2; k∈[1,64].

[0096] Where I1 represents the unit specification i0; I2~I 64 They have the same specifications, and their size is 4i0.

[0097] It should be noted that Se k 、Sf k Form the k-th group of switches, and Se k 、Sf k They do not open simultaneously. The clock signal CLK is used to control Se based on a combination of binary encoding and thermometer code encoding. k 、Sf k The switching is performed. Specifically, the highest bit of CLK is binary-encoded to perform differential control on the first group of switches (i.e., Se1, Sf1); the other bits of CLK are thermometer-coded to control the remaining 63 groups of switches (i.e., Se2, Sf2, Se3, Sf3, ..., Se...). 64 、Sf 64 Differential control is performed.

[0098] The counting unit is used for synchronous counting in conjunction with the differential switch array during parallel high 7-bit quantization. See also... Figure 9 The counting section includes: one counter Counter1, one OR gate, and three AND gates AND1~AND3. Input 1 of OR is connected to the clock signal CLK, input 2 is connected to the start signal RUN, and the output is connected to the control terminal of Counter1. Counter1 is a 7-bit counter used to output 7-bit count values ​​D0~D6. Input 1 of AND1 is connected to D0, input 2 to D1, input 3 to D2, and the output is connected to input 1 of AND3. Input 1 of AND2 is connected to D3, input 2 to D4, input 3 to D5, and the output is connected to input 2 of AND3. The input of AND3 is used to output RUN.

[0099] Considering the possibility that the Vin1~Vin2 values ​​may be too small, a negative slope extension section can be added to extend Vramp1 (i.e., the extended slope section that provides the positive slope signal) and a positive slope extension section can be added to extend Vramp2 (i.e., the extended slope section that provides the negative slope signal).

[0100] like Figure 8 As shown, the negative ramp extension includes: three NMOS current sources N1~N3 and six switches SN1~SN6; the output of N1 is connected to the first terminal of RV1 via SN1 and to the first terminal of RV2 via SN2; the output of N2 is connected to the first terminal of RV1 via SN3 and to the first terminal of RV2 via SN4; the output of N3 is connected to the first terminal of RV1 via SN4 and to the first terminal of RV2 via SN5. The specifications of N1~N3 are i0, 2i0, and 4i0, respectively.

[0101] The positive ramp extension section includes: three PMOS current sources P1~P3 and six switches SP1~SP6; the output of P1 is connected to the first terminal of RV1 via SP1 and to the first terminal of RV2 via SP2; the output of P2 is connected to the first terminal of RV1 via SP3 and to the first terminal of RV2 via SP4; the output of P3 is connected to the first terminal of RV1 via SP4 and to the first terminal of RV2 via SP5. The specifications of P1~P3 are i0, 2i0, and 4i0, respectively.

[0102] Therefore, if upper and lower ramp extensions are added, the counting unit is also used to control SN1~SN6 and SP1~SP6. (See also...) Figure 9 The counting unit may also include: a counter Counter2; Counter2 is a 3-bit counter, with control terminal 1 connected to CLK, control terminal 2 connected to RUN, and output terminal used to output 3-bit count values ​​X0~X2.

[0103] It should be noted that SN1~SN2 and SP1~SP2 are controlled by the count value X0 for switching; specifically, when X0=1, SN1 and SP1 are on, and SN2 and SP2 are off; when X0=0, SN2 and SP2 are on, and SN1 and SP1 are off. SN3~SN4 and SP3~SP4 are controlled by the count value X1 for switching; specifically, when X1=1, SN3 and SP3 are on, and SN4 and SP4 are off; when X1=0, SN4 and SP4 are on, and SN3 and SP3 are off. SN5~SN6 and SP5~SP6 are controlled by X2 for switching; specifically, when X2=1, SN5 and SP5 are on, and SN6 and SP6 are off; when X2=1, SN6 and SP6 are on, and SN5 and SP5 are off.

[0104] (vi) The result output section is used to: obtain the corresponding quantization bit values ​​based on the output of the price comparison unit at different stages:

[0105] ① Convert the two consecutive 4-digit thermometer codes into D1[2:0] and D2[2:0] respectively;

[0106] ②. Vref-control1 and Vref-control2 are designated as D1[3] and D2[3], respectively;

[0107] ③ Based on Ramp1~Ramp2, we get D1[4] and D1[10:5]; based on Ramp3~Ramp4, we get D2[4] and D2[10:5].

[0108] Among them, the detailed process of ③ above is as follows: based on Ramp1 and Ramp2, two switching levels out1~out2 are generated to control the counting output of the SS-ADC section to obtain D1[10:5], and out1 is used as D1[4]; based on Ramp3 and Ramp4, two switching levels out3~out4 are generated to control the counting output of the SS-ADC section to obtain D2[10:5], and out2 is used as D2[4].

[0109] It should be noted that when out1=1 and out2=0, it means that Vin1 and Vout1 intersect, but Vin1 and Vout2 do not intersect; when out1=0 and out2=1, it means that Vin1 and Vout1 do not intersect, but Vin1 and Vout2 intersect; when out3=1 and out4=0, it means that Vin2 and Vout1 intersect, but Vin2 and Vout2 do not intersect; when out3=0 and out4=1, it means that Vin2 and Vout1 do not intersect, but Vin2 and Vout2 intersect.

[0110] If upper and negative ramp extensions are added, Vin1 and Vin2 may intersect with the extended ramp segments, resulting in an extension intersection. Specifically, until Counter1 is full (i.e., D0~D6 are all 1), out1~out4 remain 0. Then Counter2 starts timing and controls the negative and positive ramp extensions via X0~X2 to extend the corresponding ramp signals until out1 or out2 shows a 1, and out3 or out4 shows a 1. This indicates a potential error in the high 4 bits of quantization, requiring error calibration.

[0111] So, see Figure 10Based on the above logic, the output section can be designed to include: 1 encoder, 2 fine quantization toggling circuits ffj_circuit1~ffj_circuit2, 2 two-to-one selectors MUX1~MUX2, and 10 latches Latch1~Latch10; it can also include: an error calibrator (not shown).

[0112] The input terminals of the Encoder are used to input Q1~Q4 respectively, and are used to: convert the two 4-bit thermometer codes into 3-bit code values ​​to obtain D1[2:0] and D2[2:0] respectively; Latch1 is connected to the output terminal of the Encoder and is used to latch and output D1[2:0]; Latch2 is connected to the output terminal of the Encoder and is used to latch and output D2[2:0].

[0113] Latch3 is connected to Vref-control1 and is used to latch and output D1[3]; Latch4 is connected to Vref-control2 and is used to latch and output D2[3].

[0114] The two input terminals of ffj_circuit1 are used to input Ramp1 and Ramp2 respectively, and the two output terminals are used to output two transition levels out1 and out2 respectively; Latch5 is connected to out1 and is used to latch and output D1[4]; the two input terminals of ffj_circuit2 are used to input Ramp3 and Ramp4 respectively, and the two output terminals are used to output two transition levels out3 and out4 respectively; Latch6 is connected to out3 and is used to latch and output D2[4].

[0115] The input terminals of Latch7~Latch8 are connected to the output terminal of Counter1 to latch the count value of Counter1; out1 is connected to the control terminal of Latch7; out2 is connected to the control terminal of Latch8; out3 is connected to the control terminal of Latch9; out4 is connected to the control terminal of Latch10; the control terminal of MUX1 is connected to out1, input terminal 1 is connected to the output terminal of Latch7, input terminal 2 is connected to the output terminal of Latch8, and the output terminal is used to output D1[10:5]; the control terminal of MUX2 is connected to out3, input terminal 1 is connected to the output terminal of Latch9, input terminal 2 is connected to the output terminal of Latch10, and the output terminal is used to output D2[10:5].

[0116] Specifically, when out1=1 and out2=0, Latch7 stops latching the counter value of Counter1, and MUX1 outputs the value latched in Latch7 and uses it as D1[10:5].

[0117] When out1=0 and out2=1, Latch8 stops latching the counter value of Counter1, and MUX1 outputs the value latched in Latch8 and uses it as D1[10:5].

[0118] When out3=1 and out4=0, Latch9 stops latching the counter value of Counter1, and MUX2 outputs the value latched in Latch9 and uses it as D2[10:5].

[0119] When out3=0 and out4=1, Latch10 stops latching the counter value of Counter1, and MUX2 outputs the value latched in Latch10 and uses it as D2[10:5].

[0120] In other words, MUX1~MUX2 only output the values ​​in the latches that are stopped from being latched.

[0121] The error calibrator performs error calibration on D1[3:0] and D2[3:0] according to the following logic;

[0122] If D g [3]=1、D g [4]=1, then D g [3] Calibration is 0; g∈{1,2};

[0123] If D g [3]=1、D g [4]=0, then D g [2:0] minus 1;

[0124] If D g [3]=0、D g [4]=0, then D g [3] Calibrate to 1;

[0125] If D g [3]=0、D g [4]=1, then D g [2:0] plus 1.

[0126] Therefore, the two-step ADC circuit based on the above-described structure and optimized Flash architecture operates as follows:

[0127] Y1: The data input section samples Vpixel1 separately, so that Vpixel1 is directly output as Vin1 and Vin2.

[0128] Comp1 first compares Vin1 with V8 to obtain Q1. Specifically, if Vin1 is greater than V8, Q1 is 1, A1~A3 are turned on and B1~B3 are turned off, making SW1=V14, SW2=V12, and SW3=V10; if Vin1 is less than V8, Q1 is 0, B1~B3 are turned on and A1~A3 are turned off, making SW1=V2, SW2=V4, and SW3=V6. Next, Comp2 compares Vin1 with SW1 to obtain Q2; Comp3 compares Vin2 with SW3 to obtain Q3; and Comp4 then compares Vin2 with SW2 to obtain Q4. In this way, Q1~Q4 of Y1 form the first four-digit thermometer code value.

[0129] The first four-digit thermometer code value is converted by the decoder into Control1~Control8 to control the switching of S1~S8. V1, V3, ..., V 15 These intermediate potentials share charge based on the conduction status of S1~S8, forming a net_cap. When Sq1 and SD1 are on and SU1 is off, the net_cap of Y1 is not only stored in HC1 but also output as Vout1.

[0130] The first four-digit thermometer code value is converted into D1[2:0] by the Encoder.

[0131] Y2: The data input section samples Vpixel2 separately, so that Vpixel2 is directly output as Vin1 and Vin2.

[0132] Similar to Y1:

[0133] Comp1 first compares Vin1 with V8 to obtain Q1. Specifically, if Vin1 is greater than V8, Q1 is 1, A1~A3 are turned on and B1~B3 are turned off, making SW1=V14, SW2=V12, and SW3=V10; if Vin1 is less than V8, Q1 is 0, B1~B3 are turned on and A1~A3 are turned off, making SW1=V2, SW2=V4, and SW3=V6. Next, Comp2 compares Vin1 with SW1 to obtain Q2; Comp3 compares Vin2 with SW3 to obtain Q3; and Comp4 then compares Vin2 with SW2 to obtain Q4. In this way, Q1~Q4 of Y2 form the second four-digit thermometer code value.

[0134] The second four-digit thermometer code value is converted by the decoder into Control1~Control8 to control the on / off states of S1~S8. V1, V3, ..., V 15These intermediate potentials share charge based on the conduction status of S1~S8, forming a net_cap. When Sq2 and SD2 are on and SU2 is off, the net_cap of Y2 is not only stored in HC2 but also output as Vout2.

[0135] The second four-digit thermometer code value is converted into D2[2:0] by the Encoder.

[0136] Y3: The data input unit will share the sampling of Vpixel1 and Vpixel2.

[0137] Comp2 and Comp4 are not working; only Comp1 and Comp3 are working.

[0138] Comp1 compares Vin1 with Vout1 to obtain Vref-control1. Specifically, if Vin1 is greater than Vout1, then Vref-control1 is 0, SV1 is off, and the voltage of the lower plate of SC1 remains unchanged; if Vin1 is less than Vout1, then Vref-control1 is 1, SV1 is on, and the lower plate of SC1 is connected to Va to raise Vin1. Vref-control1 is used as D1[3].

[0139] Comp3 compares Vin2 with Vout1 to obtain Vref-control2. Specifically, if Vin2 is greater than Vout1, then Vref-control2 is 0, SV2 is off, and the voltage of the lower plate of SC2 remains unchanged; if Vin2 is less than Vout1, then Vref-control2 is 1, SV2 is on, and the lower plate of SC2 is connected to Va to raise Vin2. Vref-control2 is used as D2[3].

[0140] Y4: The data input section maintains sampling sharing between Vpixel1 and Vpixel2.

[0141] The differential ramp generator produces Vramp1 and Vramp2; Counter1 starts counting synchronously.

[0142] When SU1 is turned on, HC1, in conjunction with Vramp1, raises the net_cap of Y1 stored therein to output Vout1; when SU2 is turned on, HC2, in conjunction with Vramp2, raises the net_cap of Y2 stored therein to output Vout2.

[0143] Comp1 compares Vin1 with Vout1 to obtain Ramp1; Comp2 compares Vin1 with Vout2 to obtain Ramp2; Comp3 compares Vin2 with Vout1 to obtain Ramp3; Comp4 compares Vin2 with Vout2 to obtain Ramp4.

[0144] ffj_circuit1 detects Ramp1 and Ramp2 to obtain out1 and out2; ffj_circuit2 detects Ramp3 and Ramp4 to obtain out3 and out4.

[0145] If the intersection is normal (i.e., out1 or out2 shows 1 and out3 or out4 shows 1 when Counter1 is not full), it means that Vin1 and Vin2 did not extend the ramp segment to intersect. MUX1~MUX2 will output the values ​​in the latches that stopped latching and use them as D1[10:5] and D2[10:5] respectively. In this case, the quantization is correct and no correction is needed.

[0146] If an extended intersection occurs, D1[3:0] and D2[3:0] will be further calibrated according to the above description, while other bits remain unchanged.

[0147] Example 2

[0148] This embodiment 2 discloses a two-step ADC module based on Flash architecture optimization, which adopts the layout of the two-step ADC circuit based on Flash architecture optimization as disclosed in embodiment 1. The modular packaging makes it easier to promote and apply the aforementioned circuit.

[0149] The two-step ADC module based on Flash architecture optimization includes: a data input module (corresponding to the data input section), a comparator module (corresponding to the comparator section), a Flash-ADC module (corresponding to the Flash-ADC section), a voltage boost module (corresponding to the voltage boost section), an SS-ADC module (corresponding to the SS-ADC section), and a result output module (corresponding to the result output section). The specific circuit layout is shown in Example 1 and will not be repeated here.

[0150] This embodiment 2 also discloses a CMOS image sensor, which adopts the above-mentioned two-step ADC module based on Flash architecture optimization.

[0151] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0152] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A two-step ADC circuit based on Flash architecture optimization, characterized in that, It is used to perform 11-bit quantization on two columns of pixel signals Vpixel1~Vpixel2 to obtain two corresponding quantization results D1[10:0]~D2[10:0]; It includes: The data input section samples Vpixel1 and Vpixel2 to the comparator section in a preset order; the data input section outputs two input signals Vin1~Vin2; the data input section includes: two pixel switches Sp1~Sp2, two ground switches SS1~SS2, two reference switches SV1~SV2, two sampling capacitors SC1~SC2, and three switching switches switch1~switch3; The upper plate of SC1 is connected to Vpixel1 via Sp1, and the lower plate is connected to ground VSS via SS1 and to a fixed voltage Va via SV1; the upper plate of SC2 is connected to Vpixel2 via Sp2, and the lower plate is connected to VSS via SS2 and to Va via SV2; the first terminal of switch1 is connected to the upper plate of SC1, and the second terminal is connected to the first terminal of switch3, and is used to output the input signal Vin1; the first terminal of switch2 is connected to the upper plate of SC2, and the second terminal is connected to the second terminal of switch3, and is used to output the input signal Vin2; SV1 is switched by Vref-control1; SV2 is switched by Vref-control2. Specifically, when performing coarse quantization of the lower 3 bits of Vpixel1: Sp1 and SS1 are turned on, SV1 is turned off, Sp2, SS2 and SV2 are turned off, switch1 and switch3 are turned on, and switch2 is turned off; When performing coarse quantization of the lower 3 bits of Vpixel2: Sp2 and SS2 are turned on, SV2 is turned off, Sp1, SS1, and SV1 are turned off, switch2 and switch3 are turned on, and switch1 is turned off; During parallel coarse quantization of the 4th bit and parallel high 7-bit quantization: switch1 and switch2 are turned on, switch3 is turned off; the comparator section includes: 4 comparators Comp1~Comp4, and switch array one; switch array one includes: 4 column-1 switches SX1~SX4, and 4 column-2 switches SY1~SY4; the positive input of Comp1 is connected to the voltage divider potential V8 through SX1, and to Vout1 through SX2, the negative input is connected to Vin1, output terminal one is used to output Q1, output terminal two is used to output Ramp1, and output terminal three is used to output Vref-control1; the positive input of Comp2 is connected to SX3 Connect voltage divider SW1 to Vout2 via SX4, connect the negative input to Vin1, output terminal 1 is used to output Q2, and output terminal 2 is used to output Ramp2; Connect voltage divider SW3 to Comp3 via SY1, connect the positive input to Vout1 via SY2, connect the negative input to Vin2, output terminal 1 is used to output Q3, output terminal 2 is used to output Ramp3, and output terminal 3 is used to output Vref-control2; Connect voltage divider SW2 to Comp4 via SY3, connect the positive input to Vout2 via SY4, connect the negative input to Vin2, output terminal 1 is used to output Q4, and output terminal 2 is used to output Ramp4; During serial coarse quantization of the lower 3 bits: the data input section samples Vpixel1 and Vpixel2 separately; SX1 is turned on and SX2 is turned off, the input of Comp1 is Vin1 and V8, and the output is Q1; SX3 is turned on and SX4 is turned off, the input of Comp2 is Vin1 and SW1, and the output is Q2; SY1 is turned on and SY2 is turned off, the input of Comp3 is Vin2 and SW3, and the output is Q3; SY3 is turned on and SY4 is turned off, the input of Comp4 is Vin2 and SW2, and the output is Q4; Q1~Q4 form a 4-bit thermometer code; Comp1~Comp4 generate two 4-bit thermometer codes successively; During the parallel coarse quantization of the 4th bit: the data input section shares the sampling of Vpixel1 and Vpixel2; SX1 is disconnected and SX2 is connected, the input of Comp1 is Vin1 and Vout1, and the output is Vref-control1; SY1 is disconnected and SY2 is connected, the input of Comp3 is Vin2 and Vout2, and the output is Vref-control2; Comp2 and Comp4 are not working; Comp1 and Comp3 generate two control signals Vref-control1 to Vref-control2 respectively. During parallel high 7-bit quantization, the data input section samples and shares Vpixel1 and Vpixel2; SX1 is off and SX2 is on, the input of Comp1 is Vin1 and Vout1, and the output is Ramp1; SX3 is off and SX4 is on, the input of Comp2 is Vin1 and Vout2, and the output is Ramp2; SY1 is off and SY2 is on, the input of Comp3 is Vin2 and Vout1, and the output is Ramp3; SY3 is off and SY4 is on, the input of Comp4 is Vin2 and Vout2, and the output is Ramp4; Comp1~Comp4 generate four intersecting signals Ramp1~Ramp4 respectively; the Flash-ADC section works in conjunction with the comparator section to perform serial low 3-bit coarse quantization and obtain the shared voltage net_cap; The voltage boosting section is used to: directly output net_cap as two boosted voltages Vout1~Vout2 during parallel coarse quantization of the 4th bit; and during parallel high 7-bit quantization, boost net_cap in combination with the positive ramp signal Vramp1 to output Vout1, and boost net_cap in combination with the negative ramp signal Vramp2 to output Vout2. The SS-ADC section provides Vramp1~Vramp2 to the voltage boost section to cooperate with the comparator section in performing parallel high 7-bit quantization; and The output section is used to: convert the two consecutive 4-digit thermometer codes into D1[2:0] and D2[2:0] respectively; use Vref-control1 and Vref-control2 as D1[3] and D2[3] respectively; obtain D1[4] and D1[10:5] based on Ramp1~Ramp2; and obtain D2[4] and D2[10:5] based on Ramp3~Ramp4.

2. The two-step ADC circuit based on Flash architecture optimization according to claim 1, characterized in that, The 11-bit quantization process includes: S1, performing serial coarse quantization of the lower 3 bits; S1 includes: first performing coarse quantization on the lower 3 bits of Vpixel1, and then performing coarse quantization on the lower 3 bits of Vpixel2. S2 performs parallel coarse quantization of the 4th bit; S2 includes: synchronously performing 4th-bit coarse quantization on Vpixel1 and Vpixel2; S3 performs parallel high-7-bit quantization; S3 includes: synchronously performing high 7-bit coarse quantization on Vpixel1 and Vpixel2; the high 7-bit quantization includes: the 5th bit coarse quantization and the high 6th bit fine quantization.

3. The two-step ADC circuit based on Flash architecture optimization according to claim 2, characterized in that, Comp1 and Comp3 have the same structure, both including: 2 amplifiers A1~A2, 1 latch_A, 2 buffers buffer1~buffer2, 1 output buffer Output_buffer1, 2 D flip-flops DFF1~DFF2, and 1 XOR gate; Input terminal 1 of A1 serves as the positive input of the entire comparator, and input terminal 2 serves as the negative input. Output terminal 1 is connected to input terminal 1 of A2, and output terminal 2 is connected to input terminal 2 of A2. Output terminal 1 of A2 is connected to input terminal 1 of latch_A, and output terminal 2 is connected to input terminal 2 of latch_A. Output terminal 1 of latch_A is connected to the input of buffer1, and output terminal 2 is connected to the input of buffer2. The output of buffer1 is connected to the input of DFF1 and input terminal 1 of Output_buffer1, and the output of DFF1 serves as the second output of the entire comparator. The output of buffer2 is connected to the input of DFF2 and input terminal 2 of Output_buffer1, and the output of Output_buffer1 serves as the first output of the entire comparator. Input terminal 1 of XOR is connected to the power supply VDD, input terminal 2 is connected to the output of DFF2, and the output terminal serves as the third output of the entire comparator. Comp2 and Comp4 have the same structure, both including: 2 amplifiers A3~A4, 1 latch_B, 2 buffers buffer3~buffer4, 1 output buffer Output_buffer2, and 1 D flip-flop DFF3; Input terminal 1 of A3 serves as the positive input of the entire comparator, and input terminal 2 serves as the negative input. Output terminal 1 is connected to input terminal 1 of A4, and output terminal 2 is connected to input terminal 2 of A4. Output terminal 1 of A4 is connected to input terminal 1 of latch_B, and output terminal 2 is connected to input terminal 2 of latch_B. Output terminal 1 of latch_B is connected to the input of buffer3, and output terminal 2 is connected to the input of buffer4. The output of buffer3 is connected to the input of DFF3 and input terminal 1 of Output_buffer2, and the output of DFF3 serves as output terminal 2 of the entire comparator. The output of buffer4 is connected to input terminal 2 of Output_buffer2, and the output of Output_buffer2 serves as output terminal 1 of the entire comparator.

4. The two-step ADC circuit based on Flash architecture optimization according to claim 2, characterized in that, The Flash-ADC section includes: a resistor array, a second switch array, a third switch array, and a decoder. The decoder is used to generate eight control levels, Control1 to Control8, based on a 4-bit thermometer code. The eight control levels, Control1 to Control8, are generated based on the first four-bit thermometer code value when performing coarse quantization of the lower three bits of Vpixel1, and based on the second four-bit thermometer code value when performing coarse quantization of the lower three bits of Vpixel2. The resistor array consists of 16 resistors R1~R1 connected in series. 16 The end of R1 furthest from R2 is connected to the array voltage Vlow; R 16 Stay away from R 15 One end is connected to the array voltage Vhigh; R i With R i+1 A voltage divider potential V is formed between them i , i∈[1,15]; Switch array two includes: three switches A1~A3 listed above, and three switches B1~B3 listed below; V2 is connected to V14 via B1 and A1 connected in series; SW1 is formed between B1 and A1; V4 is connected to V12 via B2 and A2 connected in series; SW2 is formed between B2 and A2; V6 is connected to V10 via B3 and A3 connected in series; SW3 is formed between B3 and A3; wherein, A1~A3 and B1~B3 are switched by Q1. Switch array three includes: eight toggle switches S1~S8; the first terminal of S1 is connected to V1, the first terminal of S2 is connected to V3, the first terminal of S3 is connected to V5, the first terminal of S4 is connected to V7, the first terminal of S5 is connected to V9, and the first terminal of S6 is connected to V... 11 The first end of S7 is connected to V. 13 The first end of S8 is connected to V. 15 The second ends of S1~S8 are connected together for outputting net_cap; where S j Subject to Control j Control the switching on and off; j∈[1,8].

5. The two-step ADC circuit based on Flash architecture optimization according to claim 4, characterized in that, The voltage boosting section includes: two input switches Sq1~Sq2, two grounding switches SD1~SD2, two boosting switches SU1~SU2, and two sampling capacitors HC1~HC2; The upper plate of HC1 is used to output Vout1; the upper plate of HC1 is connected to net_cap through Sq1, and the lower plate is connected to ground VSS through SD1 and to Vramp1 through SU1; the upper plate of HC2 is used to output Vout2; the upper plate of HC2 is connected to net_cap through Sq2, and the lower plate is connected to ground VSS through SD2 and to Vramp2 through SU2. When performing coarse quantization of the lower 3 bits of Vpixel1, Sq1 and SD1 are turned on, SU1 is turned off, and net_cap, which performs coarse quantization of the lower 3 bits of Vpixel1, is not only stored in HC1, but also output as Vout1. When performing coarse quantization of the lower 3 bits of Vpixel2, Sq2 and SD2 are turned on, SU2 is turned off, and net_cap, which performs coarse quantization of the lower 3 bits of Vpixel2, is not only stored in HC2, but also output as Vout2. During the parallel coarse quantization of the 4th bit, Sq1, Sq2, SD1, and SD2 are turned on, while SU1 and SU2 are turned off. During parallel high 7-bit quantization, Sq1, Sq2, SD1, and SD2 are disconnected, while SU1 and SU2 are turned on.

6. The two-step ADC circuit based on Flash architecture optimization according to claim 2, characterized in that, The SS-ADC section includes: a differential ramp generation section and a counting section; The differential ramp generator includes: a current source array, a differential switch array, and two resistors RV1~RV2; the first terminal of RV1 is used to output Vramp1; the first terminal of RV2 is used to output Vramp2; the second terminal of RV1 is grounded to VSS; the current source array includes: 64 differential current sources I1~I in parallel. 64 The differential switch array includes: 64 switches Se1~Se 64 64 switches Sf1~Sf 64 ;I k The output terminal is connected to Se k Connect the first end of RV1, via Sf k Connect the first end of RV2; k∈[1,64]; The counting unit is used for synchronous counting in conjunction with the differential switch array during parallel high 7-bit quantization. The counting unit includes: one counter (Counter1), one OR gate (OR), and three AND gates (AND1~AND3). Input one of OR is connected to the clock signal CLK, input two is connected to the start signal RUN, and the output is connected to the control terminal of Counter1. Counter1 is a 7-bit counter used to output 7-bit count values ​​D0~D6. Input one of AND1 is connected to D0, input two is connected to D1, input three is connected to D2, and the output is connected to input one of AND3. Input one of AND2 is connected to D3, input two is connected to D4, input three is connected to D5, and the output is connected to input two of AND3. The input of AND3 is used to output RUN. Among them, CLK controls Se based on a combination of binary encoding and thermometer code encoding. k 、Sf k Turn on / off.

7. The two-step ADC circuit based on Flash architecture optimization according to claim 6, characterized in that, The output section includes: 1 encoder, 2 fine-tuning toggle circuits ffj_circuit1~ffj_circuit2, 2 2-to-1 multiplexers MUX1~MUX2, and 10 latches Latch1~Latch10; The input terminals of the Encoder are used to input Q1~Q4, which are used to: convert two 4-bit thermometer codes into 3-bit code values ​​to obtain D1[2:0] and D2[2:0] respectively; Latch1 is connected to the output terminal of the Encoder and is used to latch and output D1[2:0]; Latch2 is connected to the output terminal of the Encoder and is used to latch and output D2[2:0]; Latch3 is connected to Vref-control1 and is used to latch and output D1[3]; Latch4 is connected to Vref-control2 and is used to latch and output D2[3]; The two input terminals of ffj_circuit1 are used to input Ramp1 and Ramp2 respectively, and the two output terminals are used to output two transition levels out1 and out2 respectively; Latch5 is connected to out1 and is used to latch and output D1[4]; The two input terminals of ffj_circuit2 are used to input Ramp3 and Ramp4 respectively, and the two output terminals are used to output two transition levels out3 and out4 respectively; Latch6 is connected to out3 and is used to latch and output D2[4]; The input terminals of Latch7~Latch8 are connected to the output terminal of Counter1 to latch the count value of Counter1; out1 is connected to the control terminal of Latch7; out2 is connected to the control terminal of Latch8; out3 is connected to the control terminal of Latch9; out4 is connected to the control terminal of Latch10; the control terminal of MUX1 is connected to out1, input terminal 1 is connected to the output terminal of Latch7, input terminal 2 is connected to the output terminal of Latch8, and the output terminal is used to output D1[10:5]; the control terminal of MUX2 is connected to out3, input terminal 1 is connected to the output terminal of Latch9, input terminal 2 is connected to the output terminal of Latch10, and the output terminal is used to output D2[10:5]; When out1=1 and out2=0, Latch7 stops latching the counter value of Counter1, and MUX1 outputs the value latched in Latch7 and uses it as D1[10:5]. When out1=0 and out2=1, Latch8 stops latching the counter value of Counter1, and MUX1 outputs the value latched in Latch8 and uses it as D1[10:5]. When out3=1 and out4=0, Latch9 stops latching the counter value of Counter1, and MUX2 outputs the value latched in Latch9 and uses it as D2[10:5]. When out3=0 and out4=1, Latch10 stops latching the counter value of Counter1, and MUX2 outputs the value latched in Latch10 and uses it as D2[10:5].

8. The two-step ADC circuit based on Flash architecture optimization according to claim 7, characterized in that, The differential slope generation section also includes: the negative slope extension section, the positive slope extension section, The negative ramp extension section is used to extend Vramp1, and includes: 3 NMOS current sources N1~N3 and 6 switches SN1~SN6; the output terminal of N1 is connected to the first terminal of RV1 through SN1 and to the first terminal of RV2 through SN2; the output terminal of N2 is connected to the first terminal of RV1 through SN3 and to the first terminal of RV2 through SN4; the output terminal of N3 is connected to the first terminal of RV1 through SN5 and to the first terminal of RV2 through SN6. The positive ramp extension section is used to extend Vramp2, and includes: 3 PMOS current sources P1~P3 and 6 switches SP1~SP6; the output terminal of P1 is connected to the first terminal of RV1 through SP1 and to the first terminal of RV2 through SP2; the output terminal of P2 is connected to the first terminal of RV1 through SP3 and to the first terminal of RV2 through SP4; the output terminal of P3 is connected to the first terminal of RV1 through SP5 and to the first terminal of RV2 through SP6. The counter also includes: a counter Counter2; Counter2 is a 3-bit counter, with control terminal 1 connected to CLK, control terminal 2 connected to RUN, and output terminal used to output 3-bit count values ​​X0~X2; among which, SN1~SN2 and SP1~SP2 are controlled by X0 to switch on and off; SN3~SN4 and SP3~SP4 are controlled by X1 to switch on and off; SN5~SN6 and SP5~SP6 are controlled by X2 to switch on and off. The output section also includes an error calibrator, which is used to calibrate the errors of D1[3:0] and D2[3:0] when extended intersection occurs; Where, if D g [3]=1、D g [4]=1, then D g [3] Calibration is 0; g∈{1,2}; If D g [3]=1、D g [4]=0, then D g [2:0] minus 1; If D g [3]=0、D g [4]=0, then D g [3] Calibrate to 1; If D g [3]=0、D g [4]=1, then D g [2:0] plus 1.

9. A two-step ADC module based on Flash architecture optimization, characterized in that, It adopts the layout of a two-step ADC circuit based on Flash architecture optimization as described in any one of claims 1-8.

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