Radio frequency chip, low-noise amplifier, radio frequency front-end module and electronic equipment

Abstract

The invention discloses a radio frequency chip, a low-noise amplifier, a radio frequency front-end module and electronic equipment, the radio frequency chip comprises a device area, a metal layer and a connecting structure, the device area is provided with a plurality of function transistors, and the metal layer is stacked on the device area. The connecting structure is connected between the device region and the metal layer, and the connecting structure is used for connecting the first electrode, the second electrode and the third electrode of the function transistor to the first port, the second port and the third port in the metal layer respectively. Wherein at least one of the first port, the second port and the third port connected with the at least one functional transistor is not connected into a circuit of the radio frequency chip. Therefore, only the connection position and the connection mode of the connection wire in the metal layer need to be adjusted, and the functional transistor in the device area does not need to be rearranged, so that the chip design of the radio frequency chip is more flexible, and the application scene of the radio frequency chip is enriched.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and more specifically, to a radio frequency chip, a low-noise amplifier, a radio frequency front-end module, and electronic equipment. Background Technology

[0002] Currently, radio frequency (RF) front-end modules are widely used in wireless communication, the Internet of Things (IoT), smart homes, and other fields. They can include devices such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers to achieve the task of receiving and transmitting RF signals.

[0003] In existing RF front-end modules, the RF chips inside suffer from the problem of limited application scenarios. Summary of the Invention

[0004] This application provides an RF chip, a low-noise amplifier, an RF front-end module, and an electronic device.

[0005] According to a first aspect of this application, an embodiment of this application provides a radio frequency (RF) chip, which includes a device region, a metal layer, and a connection structure. The device region has a plurality of functional transistors, each having a first electrode, a second electrode, and a third electrode. The metal layer is stacked on the device region. The connection structure connects the device region and the metal layer, and is configured to connect the first electrode of each functional transistor to a first port in the metal layer, connect the second electrode of each functional transistor to a second port in the metal layer, and connect the third electrode of each functional transistor to a third port in the metal layer. At least one of the first, second, and third ports to which at least one functional transistor is connected is not connected to the circuitry of the RF chip.

[0006] This application provides a radio frequency (RF) chip, which includes a device region, a metal layer, and connection structures. Because this application pre-configures multiple functional transistors in the device region of the RF chip and reserves corresponding connection ports (i.e., a first port, a second port, and a third port) in the metal layer, it allows for the selective integration of some functional transistors into the RF chip's circuitry, while leaving others unconnected, by modifying the metal layer according to the actual circuit architecture of the RF chip.

[0007] In this scenario, only the connection positions and methods of the interconnect traces in the metal layer need to be adjusted, without requiring a relocation of the functional transistors in the device region. This makes the design of the RF chip more flexible, enriching its application scenarios. Furthermore, since no adjustments to the device region are required, this application can also save on RF chip design costs and shorten the RF chip development cycle.

[0008] According to a second aspect of this application, embodiments of this application also provide a radio frequency (RF) chip, which includes a device region, a metal layer, and a connection structure. The device region has a plurality of functional transistors, and the metal layer is stacked on the device region. The connection structure connects the device region and the metal layer; the connection structure is configured to connect the plurality of functional transistors to connection ports in the metal layer; wherein at least one connection port to which a functional transistor is connected is not connected to the circuitry of the RF chip.

[0009] This application also provides a radio frequency (RF) chip, which includes a device region, a metal layer, and a connection structure. Because this application pre-configures multiple functional transistors in the device region of the RF chip and reserves connection ports corresponding to the functional transistors in the metal layer, it allows for the selective connection of some functional transistors to the RF chip's circuitry, while leaving others unconnected, by modifying the metal layer according to the actual circuit architecture of the RF chip.

[0010] In this configuration, only the connection positions and methods of the interconnect traces in the metal layer need to be adjusted; there is no need to rearrange the functional transistors in the device area. This makes the design of the RF chip more flexible, thus expanding its application scenarios. Furthermore, since no adjustments to the device area are required, this embodiment can also save on RF chip design costs and shorten the RF chip development cycle.

[0011] According to a third aspect of this application, embodiments of this application also provide a radio frequency (RF) chip, which includes a device region, multiple metal layers, multiple components, and a connection structure. The multiple metal layers are sequentially stacked on the device region, and include a first metal layer and a third metal layer. The first metal layer is the metal layer with the largest distance from the device region among the multiple metal layers, and the third metal layer is located between the first metal layer and the device region. At least one of the multiple components is disposed in the device region and the third metal layer. The connection structure connects the multiple components and the first metal layer, and the connection structure is configured to connect the multiple components to a connection port in the first metal layer; wherein the connection port to which at least one component is connected is not connected to the circuitry of the RF chip.

[0012] This application also provides a radio frequency (RF) chip, which includes a device region, multiple metal layers, multiple components, and connection structures. Because this application reserves connection ports for multiple components in the first metal layer of the RF chip, it allows for selective integration of some components into the RF chip's circuitry, while leaving others unintegrated, based on the actual circuit architecture of the RF chip, by modifying the metal layer. In this case, only the connection positions and methods of the wiring in the first metal layer need to be adjusted, making the RF chip design more flexible and enriching its application scenarios.

[0013] Furthermore, since the first metal layer is the top metal layer of the RF chip, placing the connection ports on the first metal layer makes it easier to modify the layout of the connection traces on the first metal layer. It's easy to understand that because the connection ports are located on the first metal layer, the metal connection structures on other metal layers (other metal layers between the first metal layer and the device area) do not need to be modified or adjusted, which can reduce the design difficulty and cost of the RF chip.

[0014] According to a fourth aspect of this application, embodiments of this application also provide a low-noise amplifier, which includes a device region, multiple metal layers, and a connection structure. The device region has multiple functional transistors, each having a first terminal, a second terminal, and a third terminal. The functional transistors are used to amplify radio frequency signals. Multiple metal layers are sequentially stacked on the device region, including a first metal layer, which is the metal layer with the largest distance from the device region among the multiple metal layers. A connection structure connects the device region and the first metal layer, and the connection structure is configured to: connect the first terminal of the functional transistor to a first port in the first metal layer; connect the second terminal of the functional transistor to a second port in the first metal layer; and connect the third terminal of the functional transistor to a third port in the first metal layer. At least one of the first, second, and third ports to which at least one functional transistor is connected is not connected to the circuitry of the low-noise amplifier.

[0015] This application also provides a low-noise amplifier, which includes a device region, multiple metal layers, and connection structures. Because this application pre-configures multiple functional transistors in the device region of the low-noise amplifier and reserves connection ports (i.e., first port, second port, and third port) corresponding to the functional transistors in the first metal layer, it allows for the selective connection of some functional transistors to the low-noise amplifier circuit, while leaving others unconnected, by modifying the metal layers according to the actual circuit architecture of the low-noise amplifier.

[0016] In this configuration, only the connection positions and methods of the interconnect traces in the first metal layer need to be adjusted, without requiring a relocation of the functional transistors in the device region. This makes the chip design of the low-noise amplifier more flexible, enriching its application scenarios. Furthermore, since no adjustments to the device region are required, this embodiment can also save on the design cost of the low-noise amplifier and shorten its development cycle.

[0017] Furthermore, since the first metal layer is the top metal layer of the low-noise amplifier, placing the connection ports corresponding to the functional transistors on the first metal layer makes it easier to modify the layout of the connection traces on the first metal layer. It is easy to understand that because the connection ports are located on the first metal layer, the metal connection structures on other metal layers (other metal layers between the first metal layer and the device area) do not need to be modified or adjusted, which can reduce the design difficulty and cost of the low-noise amplifier.

[0018] According to a fifth aspect of this application, embodiments of this application also provide a radio frequency front-end module, which includes the low-noise amplifier described above.

[0019] According to a sixth aspect of this application, embodiments of this application also provide an electronic device, which includes the radio frequency chip described above; or, includes the low noise amplifier described above; or, includes the radio frequency front-end module described above. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of the radio frequency chip provided in the embodiments of this application.

[0022] Figure 2 yes Figure 1 The diagram shows a cross-sectional view of the RF chip.

[0023] Figure 3 yes Figure 1 The diagram shows the arrangement of multiple functional transistors in the radio frequency chip.

[0024] Figure 4 yes Figure 1 The diagram shows the structure of the functional transistor in the radio frequency chip.

[0025] Figure 5 yes Figure 1The diagram shows another cross-sectional structure of the radio frequency chip.

[0026] Figure 6 yes Figure 1 The circuit structure diagram corresponding to the radio frequency chip is shown.

[0027] Figure 7 This is another structural schematic diagram of the radio frequency chip provided in the embodiments of this application.

[0028] Figure 8 yes Figure 7 The diagram shows a cross-sectional view of the RF chip.

[0029] Figure 9 This is a schematic diagram of the structure of the low-noise amplifier provided in the embodiments of this application.

[0030] Figure 10 This is a structural block diagram of the electronic device provided in the embodiments of this application. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0032] This application provides an embodiment of a radio frequency (RF) chip 100, which is an integrated circuit chip used to process radio frequency signals. Exemplarily, the RF chip 100 may be a power amplifier chip, a low-noise amplifier chip, an RF switch chip, etc., and this embodiment does not impose specific limitations.

[0033] Please see Figure 1 and Figure 2 The radio frequency chip 100 may include a device region 20, a metal layer 30, and a connection structure 40. The device region 20 is provided with a plurality of functional transistors 210, each having a first electrode, a second electrode, and a third electrode (not shown in the figure). The metal layer 30 is stacked on the device region 20.

[0034] The connection structure 40 is connected between the device region 20 and the metal layer 30. The connection structure 40 is configured to connect the first terminal of the functional transistor 210 to the first port 301 in the metal layer 30, connect the second terminal of the functional transistor 210 to the second port 302 in the metal layer 30, and connect the third terminal of the functional transistor 210 to the third port 303 in the metal layer 30.

[0035] For example, the connection structure 40 may include a metal via, which can be connected between the device region 20 and the metal layer 30 to connect the XX terminal of the functional transistor 210 to the XX port. Further, the connection structure 40 may also include a metal trace, wherein one end of the metal via can be connected to the XX terminal of the functional transistor 210, and the other end of the metal via can be connected to a metal bump disposed on the metal layer 30. The metal trace connects the metal bump and the XX port; that is, the XX terminal of the functional transistor 210 can be connected to the XX port sequentially through the metal via and the metal trace. Furthermore, the number of metal vias and metal traces can both be multiple, making the implementation of the connection structure 40 more flexible.

[0036] It should be noted that "connecting the XX terminal of the functional transistor 210 to the XX port in the metal layer 30" can be achieved by directly connecting the two through structures such as metal vias or metal traces. Alternatively, they can be indirectly connected; for example, other components, such as capacitors, can be connected between them.

[0037] Specifically, at least one of the first port 301, the second port 302, and the third port 303 to which at least one functional transistor 210 is connected is not connected to the circuitry of the radio frequency chip 100. For example, in... Figure 1 In the present embodiment, the first port 301, the second port 302, and the third port 303 connected to the rightmost functional transistor 210 of the RF chip 100 are not connected to the circuit of the RF chip 100. In other possible embodiments, the first port 301 and the second port 302 connected to the rightmost functional transistor 210 of the RF chip 100 are not connected to the circuit of the RF chip 100, or the first port 301 and the third port 303 connected to the leftmost functional transistor 210 of the RF chip 100 are not connected to the circuit of the RF chip 100.

[0038] Here, "not connected" means that at least one port has no electrical connection to the circuit architecture of the RF chip 100. In other words, when the RF chip 100 is operating normally, if at least one port of the functional transistor 210 is not connected to the circuit of the RF chip 100, it means that the functional transistor 210 is in an "idle state" and cannot work. That is to say, in some scenarios, the presence of this functional transistor 210 is redundant for the circuit architecture of the RF chip 100. Of course, in other scenarios, all ports of the functional transistor 210 can be connected to the circuit of the RF chip 100, and for the circuit architecture of the RF chip 100, the functional transistor 210 is in a working state.

[0039] In some possible embodiments, at least one of the first port 301, the second port 302, and the third port 303 to which at least one functional transistor 210 is connected is not connected to all the circuits included in the RF chip 100. It is easy to understand that the same RF chip 100 can contain multiple functionally independent circuits. Taking a low-noise amplifier chip as an example, the RF chip 100 can integrate two or more independent low-noise amplifier circuits for power amplification of RF signals in different bands. In this case, the fact that at least one functional transistor 210 is not connected to all the circuits included in the RF chip 100 means that regardless of whether any circuit in the RF chip 100 is in operation, the RF signal will not pass through the functional transistor 210 in the circuit not connected to the RF chip 100. This functional transistor 210 is completely "idle" and does not perform any device function (e.g., power amplification of the RF signal, turning on or off a signal branch, etc.).

[0040] Therefore, in this embodiment of the application, a plurality of functional transistors 210 are pre-set in the device area 20 of the RF chip 100, and connection ports corresponding to the functional transistors 210 (i.e., the first port 301, the second port 302 and the third port 303) are reserved in the metal layer 30. This allows some functional transistors 210 to be selectively connected to the circuit of the RF chip 100 and others not connected to the circuit of the RF chip 100 by modifying the metal layer 30 according to the actual circuit architecture of the RF chip 100.

[0041] In this configuration, only the connection positions and methods of the interconnecting traces in the metal layer 30 need to be adjusted, without requiring a redesign of the functional transistors 210 in the device region 20. This makes the chip design of the RF chip 100 more flexible, enriching its application scenarios. Furthermore, since no adjustments to the device region 20 are required, this embodiment can also save on the design cost of the RF chip 100 and shorten its development cycle.

[0042] Here, taking the RF chip 100 as a low-noise amplifier chip as an example, in related technologies, if it is necessary to adjust the signal gain of the low-noise amplifier chip, since the chip structure of the low-noise amplifier chip is fixed, it is necessary to add or reduce the number of parallel functional transistors 210 in the device area 20, and simultaneously modify the connection method of the connection traces in the metal layer 30, resulting in a long development cycle for the RF chip 100.

[0043] In this embodiment, since multiple connection ports corresponding to functional transistors 210 are reserved in the metal layer 30, the number of parallel functional transistors 210 connected to the low noise amplifier chip can be flexibly adjusted according to the gain requirements of the low noise amplifier chip, without the need to rearrange the device area 20, which can shorten the development cycle of the RF chip 100 and save the design cost of the RF chip 100.

[0044] The specific implementation of the radio frequency chip 100 is described below.

[0045] In this embodiment, device region 20 refers to the area in the radio frequency chip 100 used for laying out active devices (e.g., functional transistors 210). Exemplarily, device region 20 can be grown on a substrate material (e.g., silicon substrate, sapphire substrate, etc.) using epitaxial growth techniques to grow a semiconductor thin film. For example, a gallium arsenide (GaAs) thin film can be grown on a silicon substrate. The structure of the active region is then formed using photolithography and etching techniques, and specific impurity atoms (such as boron, phosphorus, etc.) are doped into the active region through ion implantation or diffusion processes to form a P-type or N-type semiconductor region. Finally, the first, second, and third electrodes corresponding to the functional transistor 210 are fabricated.

[0046] As an example, the functional transistor 210 can be a field-effect transistor (FET). The first terminal can be the gate of the FET, the second terminal can be the source of the FET, and the third terminal can be the drain of the FET. For example, the functional transistor 210 can be a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), etc., and this example is not limited to any particular type.

[0047] As another example, the functional transistor 210 can be a bipolar transistor. The first terminal can be the base of the bipolar transistor, the second terminal can be the emitter of the bipolar transistor, and the third terminal can be the collector of the bipolar transistor. For example, the functional transistor 210 can be a heterojunction bipolar transistor (HBT), etc., but this example is not limiting.

[0048] Specifically, the functional transistor 210 will be used as an example of a field-effect transistor (MOS transistor) in the following description.

[0049] It should be noted that this embodiment does not limit the role of the functional transistor 210 in the RF chip 100. For example, the functional transistor 210 can be a power transistor that amplifies the RF signal. In this case, the first terminal of the functional transistor 210 is used to input the RF signal, the second terminal of the functional transistor 210 is grounded, and the third terminal of the functional transistor 210 is used to output the RF signal. Alternatively, the functional transistor 210 can be a switching transistor that turns a signal branch on or off. In this case, the second and third terminals of the functional transistor 210 are connected in series in the signal branch, and the first terminal of the functional transistor 210 is used to receive a control signal, which controls the functional transistor 210 to be in a conducting or off state.

[0050] Furthermore, in some possible embodiments, all functional transistors 210 on device region 20 can be connected to connection ports in metal layer 30 via connection structure 40. In other possible embodiments, some functional transistors 210 on device region 20 can be connected to connection ports in metal layer 30 via connection structure 40, while other functional transistors 210 are not connected to connection ports in metal layer 30, but are directly connected on device region 20.

[0051] In this embodiment, there are multiple functional transistors 210, which can be arranged at intervals in the device region 20. Specifically, the number of functional transistors 210 can be greater than or equal to 2, for example, the number of functional transistors 210 can be 2, 3, 5, 8, 10, 15, 20, etc. Of course, the multiple functional transistors 210 can be arranged in an M*N array at intervals in the device region 20. This embodiment does not limit the arrangement of the multiple functional transistors 210.

[0052] Please refer to it again. Figure 1 The spacing d between two adjacent functional transistors 210 can be greater than or equal to 5 μm. As an example, the spacing d can be greater than or equal to 5 μm and less than 10 μm; as another example, the spacing d can be greater than or equal to 10 μm and less than 20 μm. Exemplarily, the spacing d can be 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, etc., and this embodiment does not impose a specific limitation.

[0053] Since the spacing d between two adjacent functional transistors 210 can be greater than or equal to 5um, it provides good heat dissipation performance when both adjacent functional transistors 210 are in operation, thus ensuring that the functional transistors 210 can work normally.

[0054] It should be noted that the functional transistor 210 not connected to the RF chip 100 in this embodiment is different from the dummy transistor that serves a circuit protection function in related technologies. On one hand, the functional transistor 210 not connected to the RF chip 100 is connected to a port disposed in the metal layer 30 via the connection structure 40; on the other hand, the functional transistor 210 not connected to the RF chip 100 and the functional transistor 210 connected to the RF chip 100 are also spaced apart, and the distance between them is greater than or equal to 5µm.

[0055] For the virtual transistor, it is not connected to the port in the metal layer 30, and the virtual transistor is arranged "closely" to the transistor arrangement, with the distance between them being almost zero. Therefore, in this embodiment, the functional transistor 210 not connected to the RF chip 100 and the virtual transistor are different in both the arrangement and connection of the transistors.

[0056] It should be emphasized that the functional transistors 210 not connected to the RF chip 100 in this embodiment serve a "pre-set" function. If the RF chip 100 needs to connect more functional transistors 210 in the subsequent process, the pre-set functional transistors 210 can be directly connected to the circuit of the RF chip 100 by modifying the metal layer 30, so as to shorten the development cycle of the RF chip 100.

[0057] In this embodiment, the plurality of functional transistors 210 may include a first functional transistor 2110 and a second functional transistor 2120. The first functional transistor 2110 is not connected to the circuitry of the RF chip 100, while the second functional transistor 2120 is connected to the circuitry of the RF chip 100. That is, at least one of the first port 301, the second port 302, and the third port 303 connected to the first functional transistor 2110 is not connected to the circuitry of the RF chip 100. All of the first port 301, the second port 302, and the third port 303 connected to the second functional transistor 2120 are connected to the circuitry of the RF chip 100. It should be noted that the number of first functional transistors 2110 in this embodiment can be one or more; similarly, the number of second functional transistors 2120 can be one or more.

[0058] As an example, the first functional transistors 2110 are all located on one side of the transistor array formed by the plurality of second functional transistors 2120. Here, the first functional transistors 2110 are denoted as A, and the second functional transistors 2120 are denoted as B. The plurality of functional transistors 210 can be arranged in the pattern of "AABBBBB" or "BBBBBAA".

[0059] As another example, multiple first functional transistors 2110 are located on both sides of the transistor array formed by multiple second functional transistors 2120, and the multiple functional transistors 210 can be arranged in an "AABBBBBA" pattern.

[0060] As another example, when the number of the first functional transistor 2110 and the second functional transistor 2120 is approximately the same, "approximately the same" means that the difference between them can be 0, 1, 2, etc. In this case, the first functional transistor 2110 and the second functional transistor 2120 can be arranged alternately, and the multiple functional transistors 210 can be arranged in a "ABABABA" or "ABABABAB" or "BABABABAB" pattern.

[0061] It is easy to see that in the various arrangement examples given above, for any two adjacent second functional transistors 2120, they are either directly spaced apart, or each is spaced apart by a first functional transistor 2110. In this case, the spacing between any two adjacent second functional transistors 2120 can be approximately the same. Therefore, when the RF chip 100 is in operation, the heat dissipation of the multiple second functional transistors 2120 is uniformly distributed, preventing damage to some second functional transistors 2120 due to uneven heat dissipation, thus ensuring the normal operation of the RF chip 100.

[0062] Please see Figure 3 The functional transistor 210 has a specified direction X, which is the extension direction of the straight line containing the source and drain of the functional transistor 210. Figure 3 In region (a), the designated direction X1 of the first functional transistor 2110 is the same as the designated direction X2 of the second functional transistor 2120. Multiple functional transistors 210 are arranged in parallel to save layout space in device region 20, making the layout of RF chip 100 more compact.

[0063] exist Figure 3In region (b), the angle between the designated direction X1 of the first functional transistor 2110 and the designated direction X2 of the second functional transistor 2120 is an acute or right angle, allowing for more flexible arrangement of multiple functional transistors 210 on the device region 20, thereby reducing the layout difficulty of the RF chip 100. For example, the angle between the two can be greater than or equal to 15 degrees and less than or equal to 90 degrees. As one example, the angle between the two can be greater than or equal to 15 degrees and less than 45 degrees; as another example, the angle between the two can be greater than or equal to 45 degrees and less than 60 degrees; as yet another example, the angle between the two can be greater than or equal to 60 degrees and less than or equal to 90 degrees. Exemplarily, the angle between the two can be 15 degrees, 20 degrees, 26 degrees, 30 degrees, 45 degrees, 50 degrees, 60 degrees, 75 degrees, 82 degrees, 90 degrees, etc., and this embodiment does not impose specific limitations.

[0064] It's important to note here that, for virtual transistors, they are arranged "closely" to the transistors, with a parallel relationship between them. Figure 3 In region (b), the functional transistors 210 not connected to the RF chip 100 and the functional transistors 210 connected to the RF chip 100 can be arranged at a certain angle, which means that the arrangement of the transistors is different between the functional transistors 210 not connected to the RF chip 100 and the virtual transistors in this embodiment.

[0065] Please see Figure 4 The functional transistor 210 may include a first comb member 2101 and a second comb member 2102, which are spaced apart. The first comb member 2101 is used to connect one of the source and the drain, and the second comb member 2102 is used to connect the other of the source and the drain. Specifically, the first comb member 2101 and the second comb member 2102 respectively serve to shunt the current flowing through the functional transistor 210, so as to ensure that the functional transistor 210 can operate in high-current scenarios.

[0066] Specifically, the first comb member 2101 and the second comb member 2102 may each include a plurality of comb electrodes 2103. The plurality of comb electrodes 2103 included in the first comb member 2101 and the plurality of comb electrodes 2103 included in the second comb member 2102 are arranged alternately in a first preset direction P, and the plurality of comb electrodes 2103 included in the same comb member are connected to each other.

[0067] In this embodiment, the number of comb electrodes 2103 included in the same comb member is greater than or equal to 5. That is, the number of comb electrodes 2103 included in the first comb member 2101 is greater than or equal to 5, and the number of comb electrodes 2103 included in the second comb member 2102 is greater than or equal to 5. As an example, the number of comb electrodes 2103 can be greater than or equal to 5 and less than 10; as another example, the number of comb electrodes 2103 can be greater than or equal to 10 and less than or equal to 20. Exemplarily, the number of comb electrodes 2103 can be 5, 8, 10, 12, 15, 18, 20, etc., and this embodiment does not impose a specific limitation.

[0068] It should be noted that, for virtual transistors, the size of a virtual transistor is usually small, and the number of its comb electrodes 2103 is usually less than 5, for example, the number can be equal to 3, 4, etc. However, in this application, the number of comb electrodes 2103 of the functional transistor 210 not connected to the RF chip 100 is greater than or equal to 5, which indicates that, in terms of transistor device structure, the functional transistor 210 not connected to the RF chip 100 in this embodiment is also different from the virtual transistor.

[0069] In some possible embodiments, the multiple functional transistors 210 have the same element size, making the arrangement of the multiple functional transistors 210 on the device region 20 more uniform and compact. Here, "element size" is the product of the width of the comb-finger electrode 2103 and the number of comb-finger electrodes 2103. Specifically, "width of the comb-finger electrode" refers to the dimension of a single comb-finger electrode 2103 in the second predetermined direction Q, that is, Figure 4 In the dimension D, "number of comb electrodes 2103" refers to the number of comb electrodes 2103 included in a single comb element. The second preset direction Q intersects the first preset direction P. In some possible examples, the second preset direction Q and the first preset direction P are perpendicular. For example, if the width of the comb electrode 2103 is 0.1 mm and the number of comb electrodes 2103 is 10, then the element size of the functional transistor 210 is 0.1 mm * 10 = 1.0 mm.

[0070] In some other possible embodiments, at least some of the functional transistors 210 have different element sizes. For example, at least one first functional transistor 2110 and at least one second functional transistor 2120 have different element sizes. Since the amplification gain of the functional transistors 210 differs depending on their element sizes, when the RF chip 100 is a low-noise amplifier chip, functional transistors 210 with different element sizes can be selected and connected to the circuit of the RF chip 100 by modifying the metal layer 30, according to the gain requirements of the low-noise amplifier chip. This makes the chip design of the RF chip 100 more flexible and enriches its application scenarios.

[0071] Please refer to it again. Figure 2 A metal layer 30 is stacked on the device area 20 and is used to provide metal traces, passive components (e.g., primary and secondary traces of transformers or baluns, capacitors, inductors, resistors, etc.). In addition, the metal layer 30 is also used to provide connection ports (e.g., first port 301, second port 302, and third port 303, etc.). Specifically, the metal layer 30 can be a copper layer, an aluminum-copper alloy (AlCu) layer, etc., and this embodiment does not impose specific limitations.

[0072] As an example, the number of metal layers 30 can be one, so that the overall wiring layout of the RF chip 100 is simpler and more compact.

[0073] As another example, such as Figure 2 As shown, there can be multiple metal layers 30, which are stacked sequentially on the device region 20 to make the overall wiring layout of the RF chip 100 more flexible. Specifically, the number of metal layers 30 can be 2, 3, 4, 5, etc., and this embodiment does not impose a specific limitation.

[0074] Furthermore, when there are multiple metal layers 30, an insulating dielectric layer 32 is provided between two adjacent metal layers 30. On one hand, the insulating dielectric layer 32 can provide mechanical support for the different metal layers 30, ensuring the stability of the entire chip structure and providing electrical isolation. On the other hand, the insulating dielectric layer 32 can be used to set metal vias to connect passive devices located on different metal layers 30, ensuring normal transmission of radio frequency signals. Specifically, the insulating dielectric layer 32 can be a silicon-based organic material (SiCOH) layer, a silicon dioxide (SiO2) layer, etc., and this embodiment does not impose specific limitations.

[0075] In some possible embodiments, the first port 301, the second port 302, and the third port 303 are all located in the same metal layer 30. In this case, if it is necessary to add or reduce the number of functional transistors 210 in the RF chip 100, only the layout of the connection traces of a single metal layer 30 (i.e., the first metal layer 310) needs to be modified, which can reduce the design difficulty and cost of the RF chip 100.

[0076] As an example, the plurality of metal layers 30 may include a first metal layer 310, which is the metal layer 30 with the largest distance from the device region 20 among the plurality of metal layers 30. Figure 2 In the example shown, the first port 301, the second port 302, and the third port 303 ( Figure 2 (Not shown in the image) are all located in the first metal layer 310. Since the first metal layer 310 is the top metal layer of the RF chip 100, it is basically exposed on the outer surface of the RF chip 100 before the RF chip 100 is packaged. Setting the first port 301, the second port 302 and the third port 303 in the first metal layer 310 makes it easier to modify the layout of the connection traces of the metal layer 30.

[0077] It is easy to understand that since the first port 301, the second port 302 and the third port 303 are located on the first metal layer 310, the metal connection structure located on other metal layers 30 (other metal layers located between the first metal layer 310 and the device region 20) does not need to be modified or adjusted, which can further reduce the design difficulty and cost of the RF chip 100.

[0078] As another example, the multiple metal layers 30 may include a second metal layer 320, which is the metal layer 30 adjacent to the device region 20 among the multiple metal layers 30. That is, the second metal layer 320 is the metal layer 30 with the smallest distance from the device region 20 among the multiple metal layers 30. The first port 301, the second port 302, and the third port 303 are all located in the second metal layer 320. Therefore, if it is necessary to add or reduce the number of functional transistors 210 in the RF chip 100, it is necessary to modify the layout of the connection traces of multiple metal layers 30 at the same time. This makes the adjustment of the overall trace layout of the RF chip 100 more flexible and avoids the difficulty of adjustment when adjusting the layout of the connection traces of a single metal layer 30.

[0079] Of course, in other possible examples, the first port 301, the second port 302 and the third port 303 may all be located in other metal layers 30 between the first metal layer 310 and the second metal layer 320.

[0080] In some other possible embodiments, at least two of the first port 301, the second port 302, and the third port 303 can be located in different metal layers 30, allowing for more flexible layout of the connection ports. In this case, if it is necessary to add or reduce the number of functional transistors 210 in the RF chip 100, the layout of the connection traces in the metal layers 30 where the first port 301, the second port 302, and the third port 303 are located must be modified simultaneously.

[0081] Specifically, this embodiment does not limit the location of the first port 301, the second port 302, and the third port 303.

[0082] In this embodiment, the connection structure 40 is connected between the device region 20 and the metal layer 30. Here, "connection structure 40" should be understood as an overall structure that connects multiple functional transistors 210 to multiple connection ports in the metal layer 30. Specifically, the connection structure 40 is configured to connect the first terminal of each functional transistor 210 to a first port 301 in the metal layer 30, connect the second terminal of each functional transistor 210 to a second port 302 in the metal layer 30, and connect the third terminal of each functional transistor 210 to a third port 303 in the metal layer 30.

[0083] Please refer to it again. Figure 2 The connection structure 40 may include a first connection structure 410, a second connection structure 420, and a third connection structure. Figure 2 (Not shown in the diagram). The first connection structure 410 is configured to connect the first terminal of the functional transistor 210 to the first port 301 in the metal layer 30; the second connection structure 420 is configured to connect the second terminal of the functional transistor 210 to the second port 302 in the metal layer 30; and the third connection structure is configured to connect the third terminal of the functional transistor 210 to the third port 303 in the metal layer 30. Figure 2 (Not shown in the image).

[0084] In this embodiment, the first connection structure 410, the second connection structure 420, and the third connection structure are independent of each other in terms of hardware structure, so as to connect the first, second, and third poles of the functional transistor 210 to the first port 301, the second port 302, and the third port 303 in the metal layer 30 one by one, thereby avoiding signal leakage.

[0085] In some possible embodiments, the first connection structure 410 may include a first metal via (not shown in the figure), through which the first electrode of the functional transistor 210 is connected to a first port 301 in the metal layer 30. Specifically, the first metal via may be located in and penetrate the insulating dielectric layer 32 between the device region 20 and the metal layer 30. Exemplarily, the first electrode of the functional transistor 210 may be directly connected to the first port 301 through the first metal via.

[0086] In some possible embodiments, the first connection structure 410 may include at least one first metal via and at least one first metal trace (neither shown in the figure), and the first electrode of the functional transistor 210 is connected to the first port 301 through at least one first metal via and at least one first metal trace. Therefore, the presence of the first metal trace allows for greater flexibility in the position of the first port 301 on the metal layer 30, enabling flexible adjustment of the layout of the first port 301 on the metal layer 30. Exemplarily, the first electrode of the functional transistor 210 may be connected to the first port 301 sequentially through the first metal via and the first metal trace. Specifically, the number of first metal vias may be one or more, and the number of first metal traces may be one or more.

[0087] As an example, the first terminal of the functional transistor 210 is connected to a first metal block of the metal layer 30 through at least one first metal via, and the first metal block is connected to the first port 301 through at least one first metal trace. Here, "metal block" refers to a bump structure located in the metal layer 30, which can serve as a metal connection.

[0088] Specifically, there can be multiple first metal vias, each located in a different insulating dielectric layer 32. These first metal vias in different insulating dielectric layers 32 can be directly connected, or they can be connected via connection traces on an intermediate metal layer to connect the first electrode of the functional transistor 210 to the first metal block. There can also be multiple first metal traces, which are sequentially connected to connect the first metal block to the first port 301, making the connection between the first metal block and the first port 301 more flexible. For example, the first electrode of the functional transistor 210 can be connected to the first port 301 sequentially via a first metal via, a connection trace, and both a first metal via and a first metal trace.

[0089] As another example, there can be multiple first metal vias, each located in a different insulating dielectric layer 32. These first metal vias in different insulating dielectric layers 32 are connected by a first metal trace located on an intermediate metal layer to connect the first electrode of the functional transistor 210 to the first port 301. Exemplarily, the first electrode of the functional transistor 210 can be connected to the first port 301 sequentially via a first metal via, a first metal trace, and another first metal via. Specifically, this embodiment does not limit the specific implementation of the first connection structure 410.

[0090] In some possible embodiments, the second connection structure 420 may include a second metal via (not shown in the figure), through which the second terminal of the functional transistor 210 is connected to the second port 302 in the metal layer 30. Specifically, the second metal via may be located in and penetrate the insulating dielectric layer 32 between the device region 20 and the metal layer 30. Exemplarily, the second terminal of the functional transistor 210 may be directly connected to the second port 302 through the second metal via.

[0091] In other possible embodiments, the second connection structure 420 may include at least one second metal via and at least one second metal trace (neither shown in the figure), and the second electrode of the functional transistor 210 is connected to the second port 302 through at least one second metal via and at least one second metal trace. Therefore, the presence of the second metal trace allows for greater flexibility in the position of the second port 302 on the metal layer 30, enabling flexible adjustment of the layout of the second port 302 on the metal layer 30. Exemplarily, the second electrode of the functional transistor 210 may be connected to the second port 302 sequentially through the second metal via and the second metal trace. Specifically, the number of second metal vias may be one or more, and the number of second metal traces may be one or more.

[0092] As an example, the second terminal of the functional transistor 210 is connected to the second metal block of the metal layer 30 through at least one second metal via, and the second metal block is connected to the second port 302 through at least one second metal trace.

[0093] Specifically, there can be multiple second metal vias, each located in a different insulating dielectric layer 32. These second metal vias in different insulating dielectric layers 32 can be directly connected, or they can be connected via connection traces on an intermediate metal layer to connect the second electrode of the functional transistor 210 to the second metal block. There can also be multiple second metal traces, which are sequentially connected to connect the second metal block to the second port 302, making the connection between the second metal block and the second port 302 more flexible. For example, the second electrode of the functional transistor 210 can be connected to the second port 302 sequentially via a second metal via, a connection trace, and another second metal via and another second metal trace.

[0094] In another example, there can be multiple second metal vias, each located in a different insulating dielectric layer 32. These second metal vias in different insulating dielectric layers 32 are connected by a second metal trace located on an intermediate metal layer to connect the second terminal of the functional transistor 210 to the second port 302. Exemplarily, the second terminal of the functional transistor 210 can be connected to the second port 302 sequentially via a second metal via, a second metal trace, and another second metal via. Specifically, this embodiment does not limit the specific implementation of the second connection structure 420.

[0095] In some possible embodiments, the third connection structure may include a third metal via (not shown in the figure), through which the third electrode of the functional transistor 210 is connected to the third port 303 in the metal layer 30. In other possible embodiments, the third connection structure may include at least one third metal via and at least one third metal trace (both not shown in the figure), through which the third electrode of the functional transistor 210 is connected to the third port 303. As an example, the third electrode of the functional transistor 210 is connected to a third metal block of the metal layer 30 through at least one third metal via, and the third metal block is connected to the third port 303 through at least one third metal trace. Specifically, the number of third metal vias and the number of third metal traces may be one or more.

[0096] It should be noted here that, Figure 2 At the cross-sectional angle shown, the third electrode of functional transistor 210 is blocked, therefore... Figure 2 The corresponding third connection structure and third port 303 cannot be shown in the document. Specifically, for the implementation of the third connection structure, please refer to the relevant descriptions of the first connection structure 410 or the second connection structure 420 in the specification above, which will not be elaborated on here.

[0097] The specific connection method of the first functional transistor 2110 and the second functional transistor 2120 is described below.

[0098] Please refer to it again. Figure 1 At least two ports of the first functional transistor 2110, namely the first port 301, the second port 302, and the third port 303, are connected to the same first functional transistor 2110. That is, at least two connection ports of the first functional transistor 2110 are short-circuited to prevent malfunctions caused by accidental connection to the RF chip 100, thus ensuring the normal operation of the RF chip 100. Specifically... Figure 1 In the first functional transistor 2110, the first port 301 and the second port 302 are connected.

[0099] As an example, the RF chip 100 may have a ground port 101. The ground port 101 can be understood as a part of the RF chip 100 used to connect to ground (GND). Ground (GND) is used to provide a stable voltage reference point, for example, 0V. Specifically, at least two of the first port 301, the second port 302, and the third port 303, which are connected to the same first functional transistor 2110, are connected to the ground port 101 to prevent the RF signal from leaking from the connection port of the first functional transistor 2110, thereby ensuring the normal operation of the RF chip 100.

[0100] exist Figure 1 In the illustrated embodiment, the first port 301 and the second port 302 of the first functional transistor 2110 are connected to the ground port 101. In other possible embodiments, the first port 301, the second port 302, and the third port 303 of the first functional transistor 2110 can all be connected to the ground port 101 to ensure the normal operation of the RF chip 100.

[0101] Of course, in other possible embodiments, the first port 301, the second port 302 and the third port 303 connected to the same first functional transistor 2110 can be in an "idle state", that is, any one of the first port 301, the second port 302 and the third port 303 is in a disconnected state to avoid introducing parasitic capacitance to the RF chip 100.

[0102] In this embodiment, the second functional transistor 2120 can be a power transistor that amplifies the power of the radio frequency signal. The gate of the second functional transistor 2120 is connected to the first port 301 in the first metal layer 310, the source of the second functional transistor 2120 is connected to the second port 302 in the first metal layer 310, and the drain of the second functional transistor 2120 is connected to the third port 303 in the first metal layer 310.

[0103] As an example, the RF chip 100 has a ground port 101 located on the first metal layer 310, and the second port 302 of the second functional transistor 2120 is connected to the ground port 101. For example, when both the second port 302 and the ground port 101 are located on the first metal layer 310, the second port 302 can be connected to the ground port 101 through a ground trace 3130 located on the first metal layer 310 to ground the source of the second functional transistor 2120.

[0104] In some possible embodiments, the RF chip 100 may further include a first inductor (not shown in the figure), at least a portion of which is located on the first metal layer 310. The second port 302 to which the second functional transistor 2120 is connected is connected to one end of the first inductor, and the other end of the first inductor is connected to a ground port 101, so that the source of the second functional transistor 2120 is grounded through the first inductor, thereby improving the Q value and stability of the circuit.

[0105] For example, when the second port 302 to which the second functional transistor 2120 is connected is located in an intermediate metal layer, a portion of the structure of the first inductor can be located in the first metal layer 310 and connected to the ground port 101; another portion of the structure of the first inductor can be located in the same intermediate metal layer as the second port 302 and connected to the second port 302. Furthermore, first inductors located in different metal layers 30 can be connected through metal vias between the intermediate metal layer and the first metal layer 310, making the layout of the first inductor more flexible.

[0106] As an example, the first metal layer 310 may also include a signal trace 3110 for transmitting radio frequency signals. The third port 303 to which the second functional transistor 2120 is connected is connected to the signal trace 3110 so that the radio frequency signal output from the drain of the second functional transistor 2120 can be transmitted through the signal trace 3110 located in the first metal layer 310.

[0107] It should be noted that, since the first metal layer 310 is the top metal layer 30 of the RF chip 100, its thickness is much greater than that of the other metal layers 30 located between the first metal layer 310 and the device region 20 (e.g., Figure 2The thickness of the second metal layer 320 in the first metal layer 310 is as follows. Exemplarily, the thickness of the first metal layer 310 can be greater than or equal to 2.5 μm, for example, the thickness of the first metal layer 310 can be 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.2 μm, 4.5 μm, 4.6 μm, 4.8 μm, 5.2 μm, 5.5 μm, 6 μm, etc. The thickness of other metal layers 30 can be less than or equal to 1 μm, for example, the thickness of other metal layers 30 can be 1 μm, 0.85 μm, 0.72 μm, 0.6 μm, 0.53 μm, 0.4 μm, 0.32 μm, 0.21 μm, 0.16 μm, etc. In some possible examples, the first metal layer 310 can be a redistribution layer (RDL), which is typically an aluminum layer, and its thickness can be greater than or equal to 1.4 μm, for example, 1.4 μm, 1.8 μm, 2 μm, etc.

[0108] In some possible embodiments, the radio frequency chip 100 includes at least three metal layers disposed from top to bottom. The first metal layer 310 disposed at the top may be a redistribution layer (RDL), and at least one of the second and third metal layers disposed below the first metal layer 310 (RDL layer) may be a thick metal layer. The thickness of the second metal layer (thick metal layer 1) and / or the third metal layer (thick metal layer 2) is greater than the thickness of the other metal layers below it.

[0109] Therefore, in this embodiment, the third port 303 connected to the second functional transistor 2120 and the signal trace 3110 are both located on the first metal layer 310. On the one hand, this can improve the connection convenience between the third port 303 and the signal trace 3110 and reduce the difficulty of the trace layout; on the other hand, since the first metal layer 310 has a large thickness, it can ensure the transmission efficiency of radio frequency signals and reduce signal transmission loss.

[0110] As an example, the RF chip 100 may further include a second inductor (not shown in the figure), located on the first metal layer 310. The first port 301 to which the second functional transistor 2120 is connected is connected to the second inductor to connect the gate of the second functional transistor 2120 to the second inductor. The second inductor can adjust the impedance matching of the circuit, reduce RF signal reflection, and thus improve the stability of the circuit.

[0111] In some possible embodiments, the first port 301 to which the second inductor and the second functional transistor 2120 are connected can both be located on the first metal layer 310 to improve the connection convenience between the first port 301 and the second inductor and reduce the difficulty of wiring layout.

[0112] In some other possible embodiments, when the first port 301 to which the second functional transistor 2120 is connected is located in an intermediate metal layer, a portion of the structure of the second inductor can be located in the first metal layer 310; another portion of the structure of the second inductor can be located in the same intermediate metal layer as the first port 301 and connected to the first port 301. Furthermore, second inductors located in different metal layers 30 can be connected through metal vias between the intermediate metal layer and the first metal layer 310, making the layout of the second inductor more flexible.

[0113] As an example, the plurality of metal layers 30 may further include a third metal layer 330, which is located between the first metal layer 310 and the device region 20. The RF chip 100 may also include a capacitor 3120, one of the plates of which is located on the third metal layer 330. See also... Figure 5 There are two third metal layers 330, and the two plates of capacitor 3120 are located in the two third metal layers 330 respectively.

[0114] Of course, in other possible embodiments, there may be only one third metal layer 330, located between the second metal layer 320 and the first metal layer 310. In this case, one of the plates of the capacitor 3120 is located on the third metal layer 330, and the other plate of the capacitor 3120 is located on the second metal layer 320.

[0115] Specifically, the first port 301 connected to the second functional transistor 2120 is connected to the capacitor 3120. In this case, the capacitor 3120 can be understood as part of the first connection structure 410, that is, the gate of the second functional transistor 2120 is connected to the first port 301 through the capacitor 3120. Figure 2 In the example shown, the gate of the second functional transistor 2120 can be connected to one of the plates of the capacitor 3120 through a first metal via, and the other plate of the capacitor 3120 can be connected to the first port 301 through another first metal via, thereby connecting the gate of the second functional transistor 2120 to the capacitor 3120. The capacitor 3120 can be used for filtering and decoupling to stabilize the gate voltage of the second functional transistor 2120.

[0116] Furthermore, in this embodiment, capacitor 3120 and second functional transistor 2120 are pre-connected together so that capacitor 3120 and second functional transistor 2120 can be integrated into the circuit of RF chip 100 as a whole, which can reduce the design difficulty and cost of RF chip 100.

[0117] In some possible embodiments, the first ports 301 connected to the multiple functional transistors 210 are all different; that is, the multiple first ports 301 connected to the multiple functional transistors 210 are independent of each other. Specifically in Figure 1 In this configuration, multiple first ports 301 connected to multiple second functional transistors 2120 are connected and configured as input radio frequency signals.

[0118] As an example, the multiple first ports 301 connected to the multiple functional transistors 210 can all be located on the first metal layer 310. The first metal layer 310 may also include a signal input trace 3120 and a signal input port 102, wherein the signal input port 102 is used to input radio frequency signals. The signal input port 102 and the multiple first ports 301 are connected through the signal input trace 3120. Since the thickness of the first metal layer 310 is much greater than the thickness of the other metal layers 30 located between the first metal layer 310 and the device region 20, the transmission efficiency of the radio frequency signal can be guaranteed and the signal transmission loss can be reduced.

[0119] In some other possible embodiments, at least two functional transistors 210 are connected to the same first port 301. For example, the gates of at least two functional transistors 210 can be connected in the device region 20 and connected to the same first port 301 by sharing a first connection structure 410. In this case, the number of first connection structures 410 and first ports 301 can be reduced, making the overall structure of the RF chip 100 more compact and saving layout space of the RF chip 100.

[0120] It is easy to understand that regardless of whether the number of functional transistors 210 connected in parallel is increased or decreased, there will always be some functional transistors 210 that are fixedly connected in the circuit architecture of the RF chip 100. Therefore, there is no need to reserve corresponding connection ports for these functional transistors 210, in order to save layout space in the RF chip 100.

[0121] In some possible embodiments, the second ports 302 connected to the plurality of functional transistors 210 are all different; that is, the plurality of second ports 302 connected to the plurality of functional transistors 210 are independent of each other. Specifically in Figure 1 In the middle, multiple second ports 302 connected to multiple second functional transistors 2120 are connected to each other and grounded.

[0122] As an example, the multiple second ports 302 connected to the multiple functional transistors 210 may all be located on the first metal layer 310. The first metal layer 310 may also include a ground trace 3130 and a ground port 101, and the ground port 101 and the multiple second ports 302 are connected through the ground trace 3130.

[0123] As another example, the RF chip 100 may also include a first inductor (not shown), at least a portion of which is located on the first metal layer 310. Multiple second ports 302 to which multiple second functional transistors 2120 are connected are interconnected and connected to one end of the first inductor, while the other end of the first inductor is grounded. Specifically, the ground trace 3130 can be considered as a portion of the first inductor near one end, used to connect the multiple second ports 302, with the other end of the first inductor connected to the ground port 101.

[0124] In some other possible embodiments, at least two functional transistors 210 are connected to the same second port 302. For example, the sources of at least two functional transistors 210 can be connected in the device region 20 and connected to the same second port 302 by sharing a second connection structure 420. In this case, the number of second connection structures 420 and second ports 302 can be reduced, making the overall structure of the RF chip 100 more compact and saving layout space of the RF chip 100.

[0125] In some possible embodiments, the third ports 303 connected to the multiple functional transistors 210 are all different; that is, the multiple third ports 303 connected to the multiple functional transistors 210 are independent of each other. Specifically in Figure 1 In this configuration, multiple third ports 303 connected to multiple second-function transistors 2120 are connected together and configured to output radio frequency signals.

[0126] As an example, the multiple third ports 303 connected to the multiple functional transistors 210 may all be located in the first metal layer 310. The first metal layer 310 may also include signal traces 3110, and the multiple third ports 303 are respectively connected to the signal traces 3110.

[0127] In some other possible embodiments, at least two functional transistors 210 are connected to the same third port 303. For example, the drains of at least two functional transistors 210 can be connected in device region 20 and connected to the same third port 303 by sharing a third connection structure. In this case, the number of third connection structures and third ports 303 can be reduced, making the overall structure of the RF chip 100 more compact and saving layout space of the RF chip 100.

[0128] Please see Figure 1 and Figure 6The multiple functional transistors 210 may also include a third functional transistor 2130, which is connected to the circuit of the RF chip 100. The third functional transistor 2130 may also be a power transistor for amplifying the RF signal. The gate of the third functional transistor 2130 is connected to the first port 301 in the first metal layer 310, the source of the third functional transistor 2130 is connected to the second port 302 in the first metal layer 310, and the drain of the third functional transistor 2130 is connected to the third port 303 in the first metal layer 310.

[0129] Specifically, multiple first ports 301 connected to the multiple second functional transistors 2120 are interconnected and configured as input radio frequency signals. Multiple second ports 302 connected to the multiple second functional transistors 2120 are interconnected and used for grounding. Multiple third ports 303 connected to the multiple second functional transistors 2120 are interconnected and connected to the second port 302 connected to the third functional transistor 2130. The first port 301 connected to the third functional transistor 2130 is configured as an input bias voltage signal, and the third port 303 connected to the third functional transistor 2130 is configured as an output radio frequency signal.

[0130] As an example, the first metal layer 310 may further include a first voltage port 103, which provides a bias voltage signal Vb to ensure that the third functional transistor 2130 operates in the linear region. The amplitude of the bias voltage signal can be greater than or equal to 0.9V and less than or equal to 2V; for example, the amplitude of the bias voltage signal can be 0.9V, 1.2V, 1.5V, 1.8V, 2V, etc. Specifically, the first port 301 to which the third functional transistor 2130 is connected can be connected to the first voltage port 103 via a metal trace located on the first metal layer 310.

[0131] As an example, the first metal layer 310 may also include a signal output port 104 for outputting a power-amplified radio frequency signal. Specifically, the third port 303 to which the third functional transistor 2130 is connected can be connected to the signal output port 104 via a metal trace located on the first metal layer 310.

[0132] In some possible embodiments, the RF chip 100 further includes a power supply port 105 disposed on the first metal layer 310, which is used to provide a power supply voltage VDD. The amplitude of the power supply voltage VDD can be greater than or equal to 1V and less than or equal to 5V; for example, the amplitude of the power supply voltage VDD can be 1V, 1.1V, 1.2V, 1.8V, 2.2V, 2.5V, 2.8V, 3V, 3.3V, 4.2V, 4.5V, 5V, etc. The RF chip 100 may also include a third inductor 106. The third port 303 connected to the third functional transistor 2130 is connected to one end of the third inductor 106, and the other end of the third inductor 106 is connected to the power supply port 105. Specifically, at least a portion of the third inductor 106 can be disposed on the first metal layer 310 to serve as impedance matching and high-frequency noise filtering.

[0133] It should be noted that, in the process of adjusting the connection position and connection method of the connecting traces in the metal layer 30 to add or reduce the number of parallel functional transistors 210, the trace length of any one or more of the first inductor, second inductor and third inductor 106 can be adjusted at the same time, thereby flexibly adjusting the inductance values ​​of the first inductor, second inductor and third inductor 106, making the chip design of the RF chip 100 more flexible and enriching the application scenarios of the RF chip 100.

[0134] In addition, to facilitate the reader's understanding, in Figure 1 The layout of the first functional transistor 2110, the third functional transistor 2130, and the multiple second functional transistors 2120 in the device area 20 is only schematic and should not be directly interpreted as their actual layout in the device area 20.

[0135] Please see Figure 7 The metal layer 30 may be provided with multiple passive devices 50. Each passive device 50 has a first terminal and a second terminal, which should be understood as the two connection terminals of the passive device 50. Specifically, the passive device 50 may be a resistor, capacitor, inductor, etc.

[0136] In this embodiment, the connection structure 40 is further configured to connect the first end of the passive device 50 to the fourth port 304 in the metal layer 30, and the second end of the passive device 50 to the fifth port 305 in the metal layer 30. At least one of the fourth port 304 and the fifth port 305 to which at least one passive device 50 is connected is not connected to the circuitry of the radio frequency chip 100.

[0137] Therefore, in this embodiment, multiple passive devices 50 are pre-configured in the metal layer 30 of the RF chip 100, and connection ports corresponding to the passive devices 50 (i.e., the fourth port 304 and the fifth port 305) are reserved in the metal layer 30. This allows for the selective connection of some passive devices 50 to the circuit of the RF chip 100, while leaving others unconnected, by modifying the metal layer 30 according to the actual circuit architecture of the RF chip 100. Taking a resistor as an example, the resistance values ​​of the multiple resistors can be different. Resistors with target resistance values ​​can be selectively connected to the circuit of the RF chip 100 according to the circuit requirements, making the chip design of the RF chip 100 more flexible and enriching its application scenarios.

[0138] Specifically, the connection structure 40 may include a fourth connection structure and a fifth connection structure (not shown in the figure). The fourth connection structure is configured to connect the first end of the passive device 50 to the fourth port 304 in the metal layer 30; the fifth connection structure is configured to connect the second end of the passive device 50 to the fifth port 305 in the metal layer 30. For details on the implementation of the fourth and fifth connection structures, please refer to the descriptions of the first connection structure 410 or the second connection structure 420 above in the specification; further details will not be provided here.

[0139] As an example, the fourth port 304 and the fifth port 305 are both located in the same metal layer 30, for example, in the first metal layer 310. As another example, the fourth port 304 and the fifth port 305 may be located in different metal layers 30.

[0140] As one example, the multiple passive devices 50 are connected to different fourth ports 304. As another example, at least two passive devices 50 are connected to the same fourth port 304.

[0141] As one example, the multiple passive devices 50 are connected to different fifth ports 305. As another example, at least two passive devices 50 are connected to the same fifth port 305.

[0142] Specifically, this embodiment does not limit the configuration method of the fourth port 304 and the fifth port 305.

[0143] Please see Figure 8There are multiple metal layers 30, which are stacked sequentially on the device region 20. The multiple metal layers 30 may include a first metal layer 310 and a third metal layer 330. The first metal layer 310 is the metal layer 30 with the largest distance from the device region 20. The third metal layer 330 is located between the first metal layer 310 and the device region 20. Multiple passive devices 50 are disposed on the third metal layer 330. For example, a passive device 50 may be a resistor disposed on one of the third metal layers 330; or a passive device 50 may be a capacitor with its two plates disposed on two different third metal layers 330.

[0144] Specifically, the connection structure 40 is also connected between the third metal layer 330 and the first metal layer 310, and the connection structure 40 is also configured to: connect the first end of the passive device 50 to the fourth port 304 in the first metal layer 310; and connect the second end of the passive device 50 to the fifth port 305 in the first metal layer 310.

[0145] Since both the fourth port 304 and the fifth port 305 in this embodiment are located on the first metal layer 310, and the first metal layer 310 is the top metal layer of the RF chip 100, in this case, if it is necessary to add or reduce the number of passive devices 50 in the RF chip 100, or to adjust the series-parallel relationship of the passive devices 50, only the layout of the connection traces of a single metal layer 30 (i.e., the first metal layer 310) needs to be modified, which can reduce the design difficulty and cost of the RF chip 100.

[0146] Please refer to it again. Figure 7 The multiple passive devices 50 may include a first resistor 510 and a second resistor 520. The first resistor 510 is not connected to the circuit of the RF chip 100, while the second resistor 520 is connected to the circuit of the RF chip 100. The resistance values ​​of at least one first resistor 510 and at least one second resistor 520 are different. Therefore, according to the circuit requirements of the RF chip 100, resistors with target resistance values ​​can be selectively connected to the circuit of the RF chip 100 by modifying the metal layer 30, making the chip design of the RF chip 100 more flexible and enriching its application scenarios.

[0147] Specifically, the first resistor 510 and the second resistor 520 can be located in the same third metal layer 330 or in different third metal layers 330. In this embodiment, the location of the first resistor 510 and the second resistor 520 is not limited.

[0148] As an example, the fourth port 304 and the fifth port 305, which are connected to the same first resistor 510, are connected to short-circuit the first resistor 510 to prevent malfunctions caused by accidental connection to the RF chip 100, thus ensuring the normal operation of the RF chip 100. Specifically, the RF chip 100 may have a ground port 101, and the fourth port 304 and the fifth port 305, which are connected to the same first resistor 510, are both connected to the ground port 101 to prevent RF signals from leaking from the connection ports of the first resistor 510, thus ensuring the normal operation of the RF chip 100.

[0149] Of course, in other possible embodiments, the fourth port 304 and the fifth port 305 connected to the same first resistor 510 can be in an "unused state", that is, the fourth port 304 and the fifth port 305 are both in an open state.

[0150] exist Figure 7 In the illustrated embodiment, the second resistor 520 may include a first voltage divider resistor 5210 and a second voltage divider resistor 5220. The fourth port 304 connected to the first voltage divider resistor 5210 is used to input the supply voltage VDD. For example, the fourth port 304 connected to the first voltage divider resistor 5210 may be connected to the power supply port 105. The fifth port 305 connected to the first voltage divider resistor 5210 is connected to the fourth port 304 connected to the second voltage divider resistor 5220 to form a voltage divider port (not shown in the figure). The fifth port 305 connected to the second voltage divider resistor 5220 is grounded. For example, the fifth port 305 connected to the second voltage divider resistor 5220 may be connected to the ground port 101. The port (i.e., the first port 301) connected to the input electrode (i.e., the gate) of the second functional transistor 2120 is connected to the voltage divider port.

[0151] In this embodiment, the first voltage divider resistor 5210 and the second voltage divider resistor 5220 divide the supply voltage VDD to form a bias voltage, which is then output to the gate of the functional transistor 2120. Therefore, different values ​​of the second resistor 520 can be selected to be connected to the circuit of the RF chip 100 to adjust the resistance values ​​of the first voltage divider resistor 5210 and the second voltage divider resistor 5220, thereby adjusting the amplitude of the bias voltage and enriching the application scenarios of the RF chip 100.

[0152] It should be noted that the first voltage divider resistor 5210 can be a single resistor or a resistor unit formed by connecting multiple second resistors 520 in series or parallel; the second voltage divider resistor 5220 can be a single resistor or a resistor unit formed by connecting multiple second resistors 520 in series or parallel, and this embodiment does not impose specific limitations. Furthermore, for the reader's convenience, in Figure 7The layout of the first resistor 510 and the multiple second resistors 520 is only schematic and should not be directly interpreted as their actual layout in the metal layer 30.

[0153] This application provides an embodiment of a radio frequency (RF) chip 100, which may include a device region 20, a metal layer 30, and a connection structure 40. The device region 20 is provided with a plurality of functional transistors 210, each having a first terminal, a second terminal, and a third terminal. The metal layer 30 is stacked on the device region 20. The connection structure 40 connects the device region 20 and the metal layer 30. The connection structure 40 is configured to connect the first terminal of each functional transistor 210 to a first port 301 in the metal layer 30, connect the second terminal of each functional transistor 210 to a second port 302 in the metal layer 30, and connect the third terminal of each functional transistor 210 to a third port 303 in the metal layer 30.

[0154] Specifically, at least one of the first port 301, the second port 302, and the third port 303 to which at least one functional transistor 210 is connected is not connected to the circuitry of the radio frequency chip 100. For example, in... Figure 1 In the circuit of the RF chip 100, the first port 301, the second port 302, and the third port 303 connected to the functional transistor 210 located on the far right of the RF chip 100 are not connected to the circuit of the RF chip 100.

[0155] Therefore, in this embodiment of the application, a plurality of functional transistors 210 are pre-set in the device area 20 of the RF chip 100, and connection ports corresponding to the functional transistors 210 (i.e., the first port 301, the second port 302 and the third port 303) are reserved in the metal layer 30. This allows some functional transistors 210 to be selectively connected to the circuit of the RF chip 100 and others not connected to the circuit of the RF chip 100 by modifying the metal layer 30 according to the actual circuit architecture of the RF chip 100.

[0156] In this configuration, only the connection positions and methods of the interconnecting traces in the metal layer 30 need to be adjusted, without requiring a redesign of the functional transistors 210 in the device region 20. This makes the chip design of the RF chip 100 more flexible, enriching its application scenarios. Furthermore, since no adjustments to the device region 20 are required, this embodiment can also save on the design cost of the RF chip 100 and shorten its development cycle.

[0157] Please refer to it again. Figure 1 and Figure 2This application also provides an RF chip 100, which may include a device region 20, a metal layer 30, and a connection structure 40. The device region 20 has a plurality of functional transistors 210, and the metal layer 30 is stacked on the device region 20. The connection structure 40 connects the device region 20 and the metal layer 30, and is configured to connect the plurality of functional transistors 210 to connection ports 300 in the metal layer 30. At least one connection port 300 to which a functional transistor 210 is connected is not connected to the circuitry of the RF chip 100.

[0158] Therefore, in this embodiment of the application, a plurality of functional transistors 210 are pre-set in the device area 20 of the RF chip 100, and connection ports 300 corresponding to the functional transistors 210 are reserved in the metal layer 30. This allows for the selective connection of some functional transistors 210 to the circuit of the RF chip 100 by modifying the metal layer 30 according to the actual circuit architecture of the RF chip 100, while other functional transistors 210 are not connected to the circuit of the RF chip 100.

[0159] In this configuration, only the connection positions and methods of the interconnecting traces in the metal layer 30 need to be adjusted, without requiring a redesign of the functional transistors 210 in the device region 20. This makes the chip design of the RF chip 100 more flexible, enriching its application scenarios. Furthermore, since no adjustments to the device region 20 are required, this embodiment can also save on the design cost of the RF chip 100 and shorten its development cycle.

[0160] In some possible embodiments, the connection port 300 to which at least one functional transistor 210 is connected is not connected to all the circuits included in the radio frequency chip 100. Specifically, the connection port 300 to which at least one functional transistor 210 is connected may include the first port 301, the second port 302 and the third port 303 in the above embodiments.

[0161] In some possible embodiments, there are multiple metal layers 30, which are sequentially stacked on the device region 20. Among these, the multiple metal layers 30 include a first metal layer 310, which is the metal layer 30 with the largest distance from the device region 20. A connection structure 40 is connected between the device region 20 and the first metal layer 310; the connection structure 40 is configured to connect multiple functional transistors 210 to connection ports in the first metal layer 310.

[0162] In some possible embodiments, the plurality of metal layers 30 further includes a third metal layer 330, which is located between the first metal layer 310 and the device region 20; the third metal layer 330 is provided with a plurality of passive devices 50. A connection structure 40 is also connected between the third metal layer 330 and the first metal layer 310; the connection structure 40 is further configured to connect the plurality of passive devices 50 to a connection port 300 in the first metal layer 310, wherein at least one passive device is connected to a connection port 300 that is not connected to the circuitry of the RF chip 100. Specifically, the connection port 300 to which at least one passive device is connected may include the fourth port 304 and the fifth port 305 in the embodiments described above.

[0163] Specifically, the details and implementation methods of the device region 20, metal layer 30, connection structure 40, and passive device 50 can be found in the detailed descriptions in the embodiments above, and will not be repeated here. Where there is no conflict, other technical features and related technical solutions in the embodiments above can be incorporated into this embodiment; however, to save space, they will not be elaborated upon here.

[0164] Please refer to it again. Figure 2 and Figure 7 This application also provides an RF chip 100, which may include a device region 20, multiple metal layers 30, multiple components 60, and a connection structure 40. The multiple metal layers 30 are stacked sequentially on the device region 20, and include a first metal layer 310 and a third metal layer 330. The first metal layer 310 is the metal layer 30 with the largest distance from the device region 20, and the third metal layer 330 is located between the first metal layer 310 and the device region 20. At least one of the multiple components 60 is disposed in the device region 20 and the third metal layer 330. The connection structure 40 connects the multiple components 60 and the first metal layer 310, and is configured to connect the multiple components 60 to a connection port 300 in the first metal layer 310; wherein at least one component 60 is connected to a connection port 300 that is not connected to the circuitry of the RF chip 100.

[0165] Therefore, in this embodiment of the application, multiple connection ports 300 corresponding to components 60 are reserved in the first metal layer 310 of the RF chip 100. This allows for the selective connection of some components 60 to the circuit of the RF chip 100, while leaving others unconnected, based on the actual circuit architecture of the RF chip 100. In this case, only the connection positions and connection methods of the wiring in the first metal layer 310 need to be adjusted, making the chip design of the RF chip 100 more flexible and enriching the application scenarios of the RF chip 100.

[0166] Furthermore, since the first metal layer 310 is the top metal layer of the RF chip 100, placing the connection port 300 on the first metal layer 310 makes it easier to modify the layout of the connection traces on the first metal layer 310. It is easy to understand that because the connection port 300 is located on the first metal layer 310, the metal connection structures on other metal layers 30 (other metal layers between the first metal layer 310 and the device region 20) do not need to be modified or adjusted, which can reduce the design difficulty and cost of the RF chip 100.

[0167] In some possible embodiments, component 60 may include a plurality of functional transistors 210 disposed in device region 20. Connection structure 40 is configured to connect the plurality of functional transistors 210 to connection ports 300 in the first metal layer 310, wherein at least one functional transistor 210 is connected to a connection port 300 that is not connected to the circuitry of the RF chip 100. Specifically, the connection port 300 to which at least one functional transistor 210 is connected may include a first port 301, a second port 302, and a third port 303 as described in the previous embodiments.

[0168] In some possible embodiments, component 60 may include a plurality of passive components 50 disposed on a third metal layer 330. Connection structure 40 is configured to connect the plurality of passive components 50 to connection ports 300 in the first metal layer 310, wherein at least one passive component 50 is connected to a connection port 300 that is not connected to the circuitry of the RF chip 100. Specifically, the connection port 300 to which at least one passive component is connected may include the fourth port 304 and the fifth port 305 as described in the previous embodiments.

[0169] Specifically, the details and implementation methods of the device region 20, metal layer 30, connection structure 40, functional transistor 210, and passive device 50 can be found in the detailed descriptions in the embodiments above, and will not be repeated here. Where there is no conflict, other technical features and related technical solutions in the embodiments above can be incorporated into this embodiment; however, to save space, they will not be elaborated upon here.

[0170] This application also provides a low-noise amplifier 700, which amplifies weak radio frequency signals and reduces noise introduction to improve the signal-to-noise ratio of the radio frequency front-end module. Please refer to... Figure 2 and Figure 9 The low-noise amplifier 700 may include a device region 20, multiple metal layers 30, and a connection structure 40. The device region 20 is provided with multiple functional transistors 210, each having a first terminal, a second terminal, and a third terminal. The functional transistors 210 are used to amplify the power of radio frequency signals.

[0171] Multiple metal layers 30 are sequentially stacked on the device region 20. The multiple metal layers 30 may include a first metal layer 310, which is the metal layer 30 with the largest distance from the device region 20 among the multiple metal layers 30. A connection structure 40 is connected between the device region 20 and the first metal layer 310. The connection structure 40 is configured to: connect the first terminal of the functional transistor 210 to a first port 301 in the first metal layer 310; connect the second terminal of the functional transistor 210 to a second port 302 in the first metal layer 310; and connect the third terminal of the functional transistor 210 to a third port 303 in the first metal layer 310. At least one of the first port 301, second port 302, and third port 303 to which at least one functional transistor 210 is connected is not connected to the circuitry of the low-noise amplifier.

[0172] Therefore, in this embodiment of the application, a plurality of functional transistors 210 are pre-set in the device area 20 of the low noise amplifier 700, and connection ports corresponding to the functional transistors 210 (i.e., the first port 301, the second port 302 and the third port 303) are reserved in the first metal layer 310. This allows for the subsequent selective connection of some functional transistors 210 to the circuit of the low noise amplifier 700 by modifying the metal layer 30 according to the actual circuit architecture of the low noise amplifier 700, while other functional transistors 210 are not connected to the circuit of the low noise amplifier 700.

[0173] In this configuration, only the connection positions and methods of the interconnecting traces in the first metal layer 310 need to be adjusted, without requiring a redesign of the functional transistors 210 in the device region 20. This makes the chip design of the low-noise amplifier 700 more flexible, enriching its application scenarios. Furthermore, since no adjustments to the device region 20 are required, this embodiment can also save on the design cost of the low-noise amplifier 700 and shorten its development cycle.

[0174] Furthermore, since the first metal layer 310 is the top metal layer of the low-noise amplifier 700, placing the connection port corresponding to the functional transistor 210 on the first metal layer 310 makes it easier to modify the layout of the connection traces on the first metal layer 310. It is easy to understand that because the connection port is located on the first metal layer 310, the metal connection structures on other metal layers 30 (other metal layers between the first metal layer 310 and the device region 20) do not need to be modified or adjusted, which can reduce the design difficulty and cost of the low-noise amplifier 700.

[0175] In some possible embodiments, the plurality of functional transistors 210 may include a first functional transistor 2110, which is not connected in the circuitry of the low-noise amplifier 700. At least two of the first port 301, second port 302, and third port 303 connected to the same first functional transistor 2110 are connected.

[0176] In some possible embodiments, the low-noise amplifier 700 is provided with a ground port 101, and at least two of the first port 301, the second port 302 and the third port 303, which are connected to the same first functional transistor 2110, are connected to the ground port 101.

[0177] In some possible embodiments, the first port 301 to which the multiple functional transistors 210 are connected is different.

[0178] In some possible embodiments, the second ports 302 to which the multiple functional transistors 210 are connected are different.

[0179] In some possible embodiments, the third port 303 to which the multiple functional transistors 210 are connected is different.

[0180] In some possible embodiments, the functional transistor 210 is a field-effect transistor (FET), with its first, second, and third terminals being the gate, source, and drain, respectively. Multiple functional transistors 210 may include second functional transistors 2120 connected to the circuitry of the low-noise amplifier 700; wherein multiple first ports 301 connected to the multiple second functional transistors 2120 are interconnected and configured as input radio frequency (RF) signals. Multiple second ports 302 connected to the multiple second functional transistors 2120 are interconnected and grounded. Multiple third ports 303 connected to the multiple second functional transistors 2120 are interconnected and configured as output radio frequency (RF) signals.

[0181] In some possible embodiments, the plurality of metal layers 30 may further include a third metal layer 330 located between the first metal layer 310 and the device region 20. The third metal layer 330 is provided with a plurality of passive devices 50, each having a first end and a second end. A connection structure 40 is also connected between the third metal layer 330 and the first metal layer 310. The connection structure 40 is further configured to connect the first end of the passive device 50 to a fourth port 304 in the first metal layer 310 and to connect the second end of the passive device 50 to a fifth port 305 in the first metal layer 310. At least one of the fourth port 304 and the fifth port 305 to which at least one passive device 50 is connected is not connected to the circuitry of the low-noise amplifier 700.

[0182] Specifically, the details and implementation methods of the device region 20, metal layer 30, connection structure 40, functional transistor 210, and passive device 50 can be found in the detailed descriptions in the embodiments above, and will not be repeated here. Where there is no conflict, other technical features and related technical solutions in the embodiments above can be incorporated into this embodiment; however, to save space, they will not be elaborated upon here.

[0183] Please see Figure 10 This application also provides a radio frequency (RF) front-end module 800 and an electronic device 900 configured with the RF front-end module 800. The RF front-end module 800 is a component that integrates two or more discrete devices such as RF switches, low-noise amplifiers, filters, duplexers, and power amplifiers into an independent module, thereby improving integration and hardware performance, and miniaturizing the size. Specifically, the RF front-end module 800 may include the aforementioned low-noise amplifier 700.

[0184] The electronic device 900 can be a 4G or 5G communication device such as a smartphone, tablet, or smartwatch. Specifically, the electronic device 900 may include the radio frequency front-end module 800 in the above embodiments to realize the reception and transmission of radio frequency signals. In other possible embodiments, the electronic device 900 may also include the radio frequency chip 100 or the low noise amplifier 700 in the above embodiments.

[0185] Furthermore, with the development of 5G technology, the requirements for the performance of radio frequency front-end modules are becoming increasingly stringent. The technical solution of this application can be applied to 5G radio frequency front-end modules to improve the communication performance of 5G communication equipment.

[0186] In this application specification, certain terms are used to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. The specification and claims do not distinguish components based on differences in name, but rather on differences in function. The term "comprising" throughout the specification and claims is an open-ended term and should be interpreted as "including but not limited to"; "generally" means that those skilled in the art can solve the technical problem within a certain margin of error and basically achieve the technical effect.

[0187] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inside", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the purpose of simplifying the description of this application and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0188] In this application, unless otherwise expressly specified or limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or merely surface contact. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0189] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0190] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0191] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A radio frequency chip, characterized in that, include: The device area contains multiple functional transistors; The functional transistor has a first electrode, a second electrode, and a third electrode; A metal layer is stacked on the device region; as well as A connection structure is provided between the device region and the metal layer; the connection structure is configured to connect the first terminal of the functional transistor to a first port in the metal layer, the second terminal of the functional transistor to a second port in the metal layer, and the third terminal of the functional transistor to a third port in the metal layer. Wherein, at least one of the first port, second port and third port to which at least one of the functional transistors is connected is not connected to the circuit of the radio frequency chip.

2. The radio frequency chip according to claim 1, characterized in that, At least one of the first, second, and third ports to which at least one of the functional transistors is connected is not connected to all the circuits included in the radio frequency chip.

3. The radio frequency chip according to claim 1, characterized in that, The connection structure includes a first connection structure, a second connection structure, and a third connection structure; The first connection structure is configured to connect the first electrode of the functional transistor to a first port in the metal layer; The second connection structure is configured to connect the second terminal of the functional transistor to a second port in the metal layer; The third connection structure is configured to connect the third terminal of the functional transistor to a third port in the metal layer.

4. The radio frequency chip according to claim 3, characterized in that, The first connection structure includes a first metal via, through which the first terminal of the functional transistor is connected to a first port in the metal layer; and / or The second connection structure includes a second metal via, through which the second terminal of the functional transistor is connected to a second port in the metal layer; or / and The third connection structure includes a third metal via, through which the third terminal of the functional transistor is connected to a third port in the metal layer.

5. The radio frequency chip according to claim 3, characterized in that, The first connection structure includes at least one first metal via and at least one first metal trace, and the first electrode of the functional transistor is connected to the first port through at least one first metal via and at least one first metal trace; or / and The second connection structure includes at least one second metal via and at least one second metal trace, and the second terminal of the functional transistor is connected to the second port through at least one second metal via and at least one second metal trace; or / and The third connection structure includes at least one third metal via and at least one third metal trace, and the third terminal of the functional transistor is connected to the third port through at least one of the third metal vias and at least one of the third metal traces.

6. The radio frequency chip according to claim 5, characterized in that, The first electrode of the functional transistor is connected to the first metal block of the metal layer through at least one first metal via, and the first metal block is connected to the first port through at least one first metal trace. or / and The second terminal of the functional transistor is connected to the second metal block of the metal layer through at least one second metal via, and the second metal block is connected to the second port through at least one second metal trace. or / and The third terminal of the functional transistor is connected to the third metal block of the metal layer through at least one of the third metal vias, and the third metal block is connected to the third port through at least one of the third metal traces.

7. The radio frequency chip according to claim 1, characterized in that, The plurality of said functional transistors include a first functional transistor, which is not connected in the circuitry of the radio frequency chip; Among them, at least two of the first port, second port and third port connected to the same first functional transistor are connected.

8. The radio frequency chip according to claim 7, characterized in that, The radio frequency chip has a ground port, and at least two of the first port, second port and third port connected to the same first functional transistor are connected to the ground port.

9. The radio frequency chip according to claim 1, characterized in that, The spacing between two adjacent functional transistors is greater than or equal to 5 μm.

10. The radio frequency chip according to claim 1, characterized in that, The functional transistor is a field-effect transistor, and the first terminal, the second terminal, and the third terminal are the gate, the source, and the drain of the field-effect transistor, respectively; wherein, the functional transistor has a specified direction, which is the extension direction of the straight line containing the source and drain of the functional transistor; The plurality of functional transistors include a first functional transistor and a second functional transistor, wherein the first functional transistor is not connected to the circuit of the radio frequency chip, and the second functional transistor is connected to the circuit of the radio frequency chip; wherein the angle between the specified direction of the first functional transistor and the specified direction of the second functional transistor is an acute angle or a right angle.

11. The radio frequency chip according to claim 1, characterized in that, The functional transistor includes a plurality of comb-finger electrodes, the number of which is greater than or equal to 5.

12. The radio frequency chip according to any one of claims 1 to 11, characterized in that, The number of metal layers is multiple, and the multiple metal layers are stacked sequentially in the device region; The first port, the second port, and the third port are all located in the same metal layer.

13. The radio frequency chip according to claim 12, characterized in that, The plurality of metal layers include a first metal layer, which is the metal layer with the largest distance from the device region among the plurality of metal layers; the first port, the second port and the third port are all located in the first metal layer.

14. The radio frequency chip according to claim 12, characterized in that, The plurality of metal layers includes a second metal layer, which is the metal layer adjacent to the device region among the plurality of metal layers; the first port, the second port and the third port are all located in the second metal layer.

15. The radio frequency chip according to any one of claims 1 to 11, characterized in that, The plurality of functional transistors include a first functional transistor and a second functional transistor, wherein the first functional transistor is not connected to the circuit of the radio frequency chip, and the second functional transistor is connected to the circuit of the radio frequency chip; Wherein, the element size of at least one of the first functional transistors and the element size of at least one of the second functional transistors are different; the functional transistors include a plurality of comb-finger electrodes, and the element size is the product between the width of the comb-finger electrode and the number of the comb-finger electrodes.

16. The radio frequency chip according to any one of claims 1 to 11, characterized in that, The plurality of said functional transistors include a second functional transistor connected in the circuit of the radio frequency chip; the second functional transistor is a field-effect transistor, and the second and third terminals of the second functional transistor are the source and drain, respectively; The number of metal layers is multiple, and the multiple metal layers are stacked sequentially on the device region; wherein, the multiple metal layers include a first metal layer, which is the metal layer with the largest distance from the device region among the multiple metal layers; The source of the second functional transistor is connected to a second port in the first metal layer, and the drain of the second functional transistor is connected to a third port in the first metal layer.

17. The radio frequency chip according to claim 16, characterized in that, The radio frequency chip has a ground port located on the first metal layer; the second port of the second functional transistor is connected to the ground port; or The radio frequency chip further includes a first inductor, at least a portion of which is located in the first metal layer; the second port to which the second functional transistor is connected is connected to the first inductor.

18. The radio frequency chip according to claim 16, characterized in that, The first metal layer includes signal traces for transmitting radio frequency signals; The third port to which the second functional transistor is connected is connected to the signal trace.

19. The radio frequency chip according to claim 16, characterized in that, The radio frequency chip also includes a second inductor, which is located in the first metal layer; The first electrode of the second functional transistor is the gate, the gate of the second functional transistor is connected to the first port in the first metal layer, and the first port to which the second functional transistor is connected is connected to the second inductor.

20. The radio frequency chip according to claim 16, characterized in that, The plurality of metal layers further include a third metal layer located between the first metal layer and the device region; the radio frequency chip further includes a capacitor, one of the capacitor's plates being located in the third metal layer; The first electrode of the second functional transistor is the gate, the gate of the second functional transistor is connected to the first port in the third metal layer, and the first port to which the second functional transistor is connected is connected to the capacitor.

21. The radio frequency chip according to any one of claims 1 to 11, characterized in that, The first ports connected to the plurality of said functional transistors are all different; and / or The second ports connected to the plurality of said functional transistors are all different; and / or The third ports connected to the multiple functional transistors are all different.

22. The radio frequency chip according to claim 21, characterized in that, The functional transistor is a field-effect transistor, and the first terminal, the second terminal, and the third terminal are the gate, the source, and the drain of the field-effect transistor, respectively. The plurality of functional transistors include second functional transistors connected to the circuitry of the radio frequency chip; wherein the plurality of first ports to which the plurality of second functional transistors are connected are interconnected and configured to input radio frequency signals; The multiple second ports connected to the multiple second functional transistors are interconnected and grounded; The plurality of third ports to which the plurality of second functional transistors are connected are connected and configured to output the radio frequency signal.

23. The radio frequency chip according to any one of claims 1 to 11, characterized in that, At least two of the functional transistors are connected to the same first port; or / and At least two of the functional transistors are connected to the same second port; or / and At least two of the functional transistors are connected to the same third port.

24. The radio frequency chip according to any one of claims 1 to 11, characterized in that, The metal layer is provided with a plurality of passive devices, each passive device having a first end and a second end; The connection structure is further configured to connect the first end of the passive device to the fourth port in the metal layer, and the second end of the passive device to the fifth port in the metal layer; Wherein, at least one of the fourth and fifth ports connected to at least one of the passive devices is not connected to the circuit of the radio frequency chip.

25. The radio frequency chip according to claim 24, characterized in that, There are multiple metal layers, and the multiple metal layers are stacked sequentially on the device region; The plurality of metal layers include a first metal layer and a third metal layer, wherein the first metal layer is the metal layer with the largest distance from the device region among the plurality of metal layers, and the third metal layer is located between the first metal layer and the device region; the plurality of passive devices are disposed on the third metal layer; The connection structure is also connected between the third metal layer and the first metal layer; the connection structure is also configured to: connect the first end of the passive device to the fourth port in the first metal layer; and connect the second end of the passive device to the fifth port in the first metal layer.

26. The radio frequency chip according to claim 24, characterized in that, The passive devices include a first resistor and a second resistor, wherein the first resistor is not connected to the circuit of the radio frequency chip, and the second resistor is connected to the circuit of the radio frequency chip. Wherein, the resistance value of at least one of the first resistors and the resistance value of at least one of the second resistors are not the same.

27. The radio frequency chip according to claim 24, characterized in that, The plurality of said functional transistors include a second functional transistor, and the plurality of said passive devices include a second resistor, wherein the second functional transistor and the second resistor are connected in the circuit of the radio frequency chip; The second resistor includes a first voltage divider resistor and a second voltage divider resistor. The fourth port connected to the first voltage divider resistor is used to input the power supply voltage. The fifth port connected to the first voltage divider resistor is connected to the fourth port connected to the second voltage divider resistor to form a voltage divider port. The fifth port connected to the second voltage divider resistor is grounded. The port connected to the input terminal of the second functional transistor is connected to the voltage divider port.

28. The radio frequency chip according to any one of claims 1 to 11, characterized in that, The functional transistor is a field-effect transistor, and the first terminal, the second terminal, and the third terminal are the gate, the source, and the drain of the field-effect transistor, respectively. The plurality of functional transistors include a second functional transistor and a third functional transistor, the second functional transistor and the third functional transistor being connected to the circuit of the radio frequency chip; wherein, the plurality of first ports connected to the plurality of second functional transistors are connected to each other and configured to input radio frequency signals; The multiple second ports to which the multiple second functional transistors are connected are connected and used for grounding; The plurality of third ports to which the plurality of second functional transistors are connected are connected to each other, and the third functional transistors are connected to the second ports; The first port connected to the third functional transistor is configured as an input bias voltage signal, and the third port connected to the third functional transistor is configured as an output radio frequency signal.

29. The radio frequency chip according to claim 28, characterized in that, The radio frequency chip also includes a first inductor; The multiple second ports connected to the multiple second functional transistors are connected to one end of the first inductor; the other end of the first inductor is grounded.

30. The radio frequency chip according to claim 28, characterized in that, The radio frequency chip is provided with a power supply port, and the radio frequency chip also includes a third inductor; The third port connected to the third functional transistor is connected to one end of the third inductor, and the other end of the third inductor is connected to the power supply port.

31. A radio frequency chip, characterized in that, include: The device area contains multiple functional transistors; A metal layer is stacked on the device region, and A connection structure is provided between the device region and the metal layer; the connection structure is configured to connect a plurality of the functional transistors to a connection port in the metal layer; wherein at least one of the functional transistors is connected to a connection port that is not connected to the circuitry of the radio frequency chip.

32. The radio frequency chip according to claim 31, characterized in that, At least one of the connection ports connected to the functional transistor is not connected to all the circuits included in the radio frequency chip.

33. The radio frequency chip according to claim 31, characterized in that, The number of metal layers is multiple, and the multiple metal layers are stacked sequentially on the device region; wherein, the multiple metal layers include a first metal layer, which is the metal layer with the largest distance from the device region among the multiple metal layers; The connection structure connects the device region and the first metal layer; the connection structure is configured to connect a plurality of the functional transistors to a connection port in the first metal layer.

34. The radio frequency chip according to claim 33, characterized in that, The plurality of metal layers further include a third metal layer located between the first metal layer and the device region; the third metal layer is provided with a plurality of passive devices; The connection structure is also connected between the third metal layer and the first metal layer; the connection structure is also configured to connect a plurality of the passive devices to a connection port in the first metal layer; wherein at least one of the passive devices is connected to a connection port that is not connected to the circuit of the radio frequency chip.

35. A radio frequency chip, characterized in that, include: Device area; Multiple metal layers are stacked sequentially in the device region; The plurality of metal layers include a first metal layer and a third metal layer, wherein the first metal layer is the metal layer with the largest distance from the device region among the plurality of metal layers, and the third metal layer is located between the first metal layer and the device region; Multiple components are disposed in at least one of the device area and the third metal layer; as well as A connection structure is provided between the plurality of said components and the first metal layer; the connection structure is configured to connect the plurality of said components to a connection port in the first metal layer; wherein at least one of said components is connected to a connection port that is not connected to the circuitry of the radio frequency chip.

36. The radio frequency chip according to claim 35, characterized in that, The component includes a plurality of functional transistors disposed in the device region; the connection structure is configured to connect the plurality of functional transistors to connection ports in the first metal layer; wherein, at least one connection port to which a functional transistor is connected is not connected to the circuitry of the RF chip; or / and The components include multiple passive devices disposed on the third metal layer; the connection structure is configured to connect the multiple passive devices to a connection port in the first metal layer; wherein, at least one of the passive devices is connected to a connection port that is not connected to the circuit of the radio frequency chip.

37. A low-noise amplifier, characterized in that, include: The device area contains multiple functional transistors; The functional transistor has a first terminal, a second terminal, and a third terminal; wherein, the functional transistor is used to amplify the power of radio frequency signals; Multiple metal layers are sequentially stacked on the device region; the multiple metal layers include a first metal layer, which is the metal layer with the largest distance from the device region among the multiple metal layers; and A connection structure is provided between the device region and the first metal layer; the connection structure is configured to connect a first terminal of the functional transistor to a first port in the first metal layer, a second terminal of the functional transistor to a second port in the first metal layer, and a third terminal of the functional transistor to a third port in the first metal layer. Wherein, at least one of the first port, second port and third port to which at least one of the functional transistors is connected is not connected to the circuit of the low-noise amplifier.

38. The low-noise amplifier according to claim 37, characterized in that, The plurality of said functional transistors include a first functional transistor, which is not connected in the circuitry of the low-noise amplifier; Among them, at least two of the first port, second port and third port connected to the same first functional transistor are connected.

39. The low-noise amplifier according to claim 38, characterized in that, The low-noise amplifier has a ground port, and at least two of the first port, second port, and third port connected to the same first functional transistor are connected to the ground port.

40. The low-noise amplifier according to any one of claims 37 to 39, characterized in that, The first ports connected to the plurality of said functional transistors are all different; and / or The second ports connected to the plurality of said functional transistors are all different; and / or The third ports connected to the multiple functional transistors are all different.

41. The low-noise amplifier according to claim 40, characterized in that, The functional transistor is a field-effect transistor, and the first terminal, the second terminal, and the third terminal are the gate, the source, and the drain of the field-effect transistor, respectively. The plurality of said functional transistors include second functional transistors connected in the circuit of the low-noise amplifier; wherein the plurality of first ports to which the plurality of second functional transistors are connected are connected and configured to input radio frequency signals; The multiple second ports connected to the multiple second functional transistors are interconnected and grounded; The plurality of third ports to which the plurality of second functional transistors are connected are connected and configured to output the radio frequency signal.

42. The low-noise amplifier according to any one of claims 37 to 39, characterized in that, The plurality of metal layers further include a third metal layer, the third metal layer being located between the first metal layer and the device region; the third metal layer is provided with a plurality of passive devices, the passive devices having a first terminal and a second terminal; The connection structure is also connected between the third metal layer and the first metal layer; the connection structure is also configured to: connect a first end of the passive device to a fourth port in the first metal layer; and connect a second end of the passive device to a fifth port in the first metal layer; Wherein, at least one of the fourth and fifth ports to which at least one of the passive devices is connected is not connected to the circuit of the low-noise amplifier.

43. A radio frequency front-end module, characterized in that, include: The low-noise amplifier as described in any one of claims 37 to 42.

44. An electronic device, characterized in that, include: The radio frequency chip as described in any one of claims 1 to 36; or, The low-noise amplifier as described in any one of claims 37 to 42; or, The radio frequency front-end module as described in claim 43.

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