Shallow trench isolation structure and its manufacturing method
By adjusting the formation rate of the isolation layer by gradually increasing the carrier charge concentration within the isolation trench, the problem of void defects in high aspect ratio shallow trench isolation structures is solved, thereby improving the yield of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-26
AI Technical Summary
In the manufacturing process of semiconductor devices, the problems of filling voids and hole defects caused by chemical vapor deposition in shallow trench isolation structures with high aspect ratios are difficult to solve.
By irradiating the isolation trench with a treatment beam, the formation rate of the isolation layer is adjusted to gradually increase the carrier charge concentration, ensuring that the isolation layer forms first at the bottom of the isolation trench and reducing void defects.
It effectively reduces or avoids void defects within the isolation layer, thereby improving the yield of semiconductor devices.
Smart Images
Figure CN121548288B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a shallow trench isolation structure and its manufacturing method. Background Technology
[0002] As the feature size of semiconductor devices decreases, the isolation area between semiconductor devices also shrinks. When a high aspect ratio structure is set in the isolation area, the shrinkage of the isolation area will increase the probability of filling void defects in the high aspect ratio structure.
[0003] For example, for high aspect ratio structures of non-metallic materials, such as shallow trench isolation structures (STI HARP) prepared by low-temperature high aspect ratio process, when using chemical vapor deposition (CVD), the deposition rate at the opening of the shallow trench isolation structure is higher than the deposition rate at the bottom of the isolation trench. This makes it easy to complete the sealing quickly without completely filling the isolation trench, resulting in filling voids in the isolation trench and forming pores in the filling layer within the isolation trench. Summary of the Invention
[0004] Therefore, it is necessary to provide a shallow trench isolation structure and its manufacturing method to reduce or even avoid the probability of holes appearing in the isolation layer of the shallow trench isolation structure.
[0005] This application provides a method for manufacturing a shallow trench isolation structure, including:
[0006] A substrate is provided in which an isolation trench is formed, a dielectric layer is formed on the sidewalls of the isolation trench, and the bottom of the isolation trench is exposed;
[0007] A processing beam is irradiated into the isolation trench along a direction perpendicular to the isolation trench, so as to form carrier charges in the substrate surrounding the isolation trench, and the concentration of the carrier charges gradually increases along the direction near the bottom of the isolation trench.
[0008] An isolation layer is formed within the isolation trench to form a shallow trench isolation structure including the isolation trench and the isolation layer; wherein the formation rate of the isolation layer is positively correlated with the concentration of the charge carriers.
[0009] In one embodiment, during the process of irradiating the isolation trench with a processing beam, the incident angle of the processing beam entering the isolation trench is adjusted so that the portion of the adjusted processing beam that hits the bottom of the isolation trench is larger than the portion of the processing beam that hits the sidewall of the isolation trench.
[0010] In one embodiment, an ellipsometer is used to adjust the incident angle of the processed beam that enters the isolation trench.
[0011] In one embodiment, the wavelength range of the processed light beam includes 640nm to 780nm.
[0012] In one embodiment, the process of forming an isolation layer within the isolation trench includes:
[0013] The isolation layer is formed in the isolation trench using a thermal oxidation growth process.
[0014] In one embodiment, the substrate is made of a non-metallic silicon material.
[0015] In one embodiment, the dielectric layer is formed on the inner wall of the isolation trench using a deposition process or a thermal oxidation growth process, and the material of the dielectric layer includes silicon oxide.
[0016] In one embodiment, a plasma dry etching process is used to remove part of the dielectric layer, and the thickness of the remaining dielectric layer gradually increases in the direction away from the bottom of the isolation trench.
[0017] In one embodiment, the aspect ratio of the isolation trench ranges from 6 to 20.
[0018] Accordingly, this application also provides a shallow trench isolation structure, which is manufactured using the shallow trench isolation structure manufacturing method described above.
[0019] An unexpected effect of this application is that by irradiating the isolation trench in the substrate with a processing beam, charge carriers are formed in the substrate surrounding the isolation trench, and the concentration of the charge carriers gradually increases along the direction near the bottom of the isolation trench. By forming an isolation layer in the isolation trench, a shallow trench isolation structure including the isolation trench and the isolation layer is formed, and the formation rate of the isolation layer is positively correlated with the concentration of the charge carriers, so as to avoid premature sealing of the isolation layer at the top of the isolation trench, thereby reducing or even avoiding the probability of forming void defects in the isolation layer. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of the structure corresponding to the trench formation step in a semiconductor device manufacturing method in a related technology.
[0022] Figure 2 This is a schematic diagram of the structure corresponding to the step of forming a first dielectric layer on the inner wall of a trench in a semiconductor device manufacturing method in a related technology.
[0023] Figure 3 This is a schematic diagram of the structure corresponding to the step of forming a second dielectric layer in a trench in a semiconductor device manufacturing method in a related technology.
[0024] Figure 4 A flowchart illustrating a method for manufacturing a shallow trench isolation structure according to one embodiment of this application.
[0025] Figure 5 This is a schematic diagram of the structure corresponding to the step of providing a substrate and forming an isolation trench in the substrate in the manufacturing method of a shallow trench isolation structure provided in one embodiment of this application.
[0026] Figure 6 This is a schematic diagram of the structure corresponding to the step of forming a medium layer on the inner wall of the isolation trench in the manufacturing method of the shallow trench isolation structure provided in one embodiment of this application.
[0027] Figure 7 This is a schematic diagram of the structure corresponding to the step of removing part of the dielectric layer in the manufacturing method of the shallow trench isolation structure provided in one embodiment of this application.
[0028] Figure 8 This is a schematic diagram of the structure corresponding to the step of irradiating a processing beam into the isolation trench in the manufacturing method of a shallow trench isolation structure provided in one embodiment of this application.
[0029] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming carrier charges in the substrate surrounding the isolation trench in the manufacturing method of the shallow trench isolation structure provided in one embodiment of this application.
[0030] Figure 10 This is a schematic diagram of the structure corresponding to the step of adjusting the incident angle of the processing beam using an ellipsometer in the manufacturing method of the shallow trench isolation structure provided in one embodiment of this application.
[0031] Figure 11 This is a schematic diagram of the structure corresponding to the step of forming an isolation layer in the isolation trench in the manufacturing method of the shallow trench isolation structure provided in one embodiment of this application.
[0032] The reference numerals in the figures include: 100-substrate; 101-trench; 102-silicon oxide layer; 103-silicon nitride layer; 110-first dielectric layer; 111-second dielectric layer; 112-hole defect; 200-substrate; 201-isolation trench; 202-oxide layer; 203-hard mask layer; 210-dielectric layer; 220-isolation layer. Detailed Implementation
[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0038] Figures 1 to 3 This is a schematic diagram of a portion of the steps in a semiconductor device manufacturing method in a related technology. The following section combines... Figures 1 to 3 This section describes part of the manufacturing process of the Shallow Trench Isolation High Aspect Ratio Process (STI HARP) fabricated using a low-temperature, high aspect ratio process.
[0039] First, refer to Figure 1 A substrate 100 is provided, and a trench 101 is formed within the substrate 100. Exemplarily, the formation process of the trench 101 includes: forming a silicon oxide layer 102 and a silicon nitride layer 103 on the substrate 100, and performing an etching process to form a trench 101 that penetrates the silicon nitride layer 103 and the silicon oxide layer 102 and extends into the substrate 100. Optionally, the material of the substrate 100 includes silicon or other non-metallic materials. Optionally, a dry etching process is used for the etching process.
[0040] Next, refer to Figure 2 A first dielectric layer 110 is formed on the inner wall of the trench 101. Optionally, the first dielectric layer 110 is formed by any one of the following processes: thermal oxidation, furnace tube oxidation, or deposition, and the material of the first dielectric layer 110 includes silicon oxide.
[0041] Then refer to Figure 3 A second dielectric layer 111 is formed on the first dielectric layer 110 within the trench 101, and the second dielectric layer 111 at least fills the trench 101. Optionally, the second dielectric layer 111 is formed using a chemical vapor deposition (CVD) process, and the material of the second dielectric layer 111 includes silicon oxide, silicon nitride, or other materials with insulating properties.
[0042] However, please continue reading Figure 3 When the trench 101 is a trench with a high aspect ratio (i.e., the aspect ratio of the trench 101 is greater than or equal to 6), during the formation of the second medium layer 111, the medium deposition rate at the opening of the trench 101 is higher than the medium deposition rate at the bottom of the trench 101. This can easily lead to the trench 101 being sealed before it is completely filled, resulting in the formation of a void defect 112 in the second medium layer 111.
[0043] Based on this, this application provides a shallow trench isolation structure and its manufacturing method to reduce or even avoid the probability of holes appearing in the isolation layer of the shallow trench isolation structure.
[0044] Figure 4 A flowchart illustrating a method for manufacturing a shallow trench isolation structure according to one embodiment of this application. See also... Figure 4 One embodiment of this application provides a method for manufacturing a shallow trench isolation structure, which includes the following steps S01 to S03.
[0045] Step S01: Provide a substrate in which an isolation trench is formed, a dielectric layer is formed on the sidewalls of the isolation trench, and the bottom of the isolation trench is exposed.
[0046] Step S02: Irradiate the isolation trench with a processing beam along the direction perpendicular to the isolation trench, so as to form carrier charges in the substrate around the isolation trench, and the concentration of carrier charges gradually increases along the direction near the bottom of the isolation trench.
[0047] It should be noted that, since a dielectric layer is formed on the sidewall of the isolation trench in step S01 and the bottom of the isolation trench is exposed, the bottom of the isolation trench is more likely to absorb the processing beam because it is not blocked during the process of irradiating the isolation trench with the processing beam. However, the sidewall of the isolation trench is more difficult to absorb the processing beam due to the blocking effect of the dielectric layer. As a result, the charge concentration of the carriers around the bottom of the isolation trench is higher than that around the sidewall of the isolation trench.
[0048] Step S03: An isolation layer is formed in the isolation trench to form a shallow trench isolation structure including the isolation trench and the isolation layer; wherein the formation rate of the isolation layer is positively correlated with the concentration of the charge carrier.
[0049] It should be noted that, since the formation rate of the isolation layer is positively correlated with the concentration of charge carriers, and the charge carrier concentration around the bottom of the isolation trench in step S02 is higher than that around the sidewalls of the isolation trench, the isolation layer at the bottom of the isolation trench forms relatively quickly, the isolation layer at the sidewalls of the isolation trench forms at a slower rate, and the isolation layer at the top opening of the isolation trench forms relatively slowly. This reduces or avoids the probability of the isolation layer being sealed prematurely at the top opening, thereby reducing or even avoiding the probability of forming voids in the isolation layer.
[0050] The method for manufacturing a shallow trench isolation structure as described above involves irradiating an isolation trench in a substrate with a processing beam to generate charge carriers in the substrate surrounding the isolation trench, with the concentration of the charge carriers gradually increasing towards the bottom of the isolation trench. An isolation layer is formed within the isolation trench to create a shallow trench isolation structure comprising the isolation trench and the isolation layer. The formation rate of the isolation layer is positively correlated with the concentration of the charge carriers, thereby preventing premature sealing of the isolation layer at the top of the isolation trench and reducing or even eliminating the probability of forming voids or defects within the isolation layer.
[0051] Figures 5 to 10 This is a schematic diagram of some steps in the manufacturing method of a shallow trench isolation structure provided in one embodiment of this application. The following is in conjunction with... Figures 5 to 10 This paper details the manufacturing method of shallow trench isolation structures.
[0052] See Figures 5 to 7 In one embodiment, a substrate 200 is provided, in which an isolation trench 201 is formed. A dielectric layer 210 is formed on the sidewalls of the isolation trench 201, and the bottom of the isolation trench 201 is exposed. Optionally, the substrate 200 is made of a non-metallic silicon material; the oxide layer 202 is made of silicon oxide; and the hard mask layer 203 is made of silicon nitride. Optionally, the aspect ratio of the isolation trench 201 ranges from 6 to 20.
[0053] For example, the process of forming the isolation trench 201 and the dielectric layer 210 includes: First, referring to Figure 5A substrate 200 is provided, on which an oxide layer 202 is formed, and a hard mask layer 203 is formed on the oxide layer 202. Next, the hard mask layer 203, the oxide layer 202, and the substrate 200 are etched to form an isolation trench 201 that penetrates the hard mask layer 203 and the oxide layer 202 and extends into the substrate 200. Then, refer to... Figure 6 A medium layer 210 is formed on the inner wall of the isolation trench 201; then, refer to Figure 7 Remove part of the medium layer 210 to expose the bottom of the isolation trench 201.
[0054] In one embodiment, a dielectric layer is formed on the inner wall of the isolation trench using a deposition process or a thermal oxidation growth process, and the dielectric layer is made of silicon oxide. Optionally, a plasma dry etching process is used to remove part of the dielectric layer, and the thickness of the remaining dielectric layer gradually increases in the direction away from the bottom of the isolation trench, so that the light transmittance of the dielectric layer gradually decreases in the direction away from the bottom of the isolation trench.
[0055] See Figure 8 and Figure 9 In one embodiment, a processing beam is irradiated into the isolation trench 201 in a direction perpendicular to the isolation trench 201, so that carrier charges are formed in the substrate 200 surrounding the isolation trench 201, and the concentration of carrier charges gradually increases in the direction near the bottom of the isolation trench 201.
[0056] In one embodiment, the processing beam is a visible light beam of a specific wavelength. During the irradiation of the isolation trench with the processing beam, the beam enters the substrate and generates a photoelectric reaction, thereby generating a certain number of electron-hole pairs within the substrate surrounding the isolation trench. When the substrate is made of non-metallic silicon material, it more readily absorbs longer wavelengths of visible light. Therefore, the substrate exhibits the best absorption effect when the processing beam is red light, in which case the wavelength range of the processing beam includes 640 nm to 780 nm.
[0057] In one embodiment, during the irradiation of the processing beam into the isolation trench, the incident angle of the processing beam entering the isolation trench can be adjusted so that the portion of the adjusted processing beam pointing towards the bottom of the isolation trench is larger than the portion pointing towards the sidewalls of the isolation trench. This adjusts the carrier charge distribution within the substrate, ensuring that the carrier charge concentration gradually increases along the direction near the bottom of the isolation trench. Optionally, an ellipsometer is used to adjust the incident angle of the processing beam entering the isolation trench.
[0058] For example, the process of adjusting the incident angle of the processing beam into the isolation trench using an ellipsometer includes: first, adjusting the incident angle of the processing beam to a first incident angle using the angle adjustment device in the ellipsometer; then, with the angles of the polarizer and analyzer fixed, adjusting the incident angle of the processing beam to a second incident angle, so that the processing beam is perpendicularly incident into the bottom of the isolation trench, thereby minimizing the reflection loss of the processing beam and promoting the photoelectric absorption effect of the substrate, activating the portion of the substrate located at the bottom of the isolation trench and increasing the number of charge carriers; subsequently, refer to... Figure 10 The sidewall of the isolation trench 201 is divided into four equal parts of the same height along the depth direction of the isolation trench 201 (i.e., Figure 10 The processing beam (P1~P4) is continuously adjusted so that it sequentially illuminates four parts of the sidewall of the isolation trench 201 (i.e., the processing beam passes through parts P4, P3, P2 and P1 in sequence from the bottom of the isolation trench). Finally, when the processing beam approaches the top corner of the isolation trench 201, the light source of the processing beam is turned off to reduce or avoid the generation of charge carriers at the top corner of the isolation trench due to illumination.
[0059] Continue reading Figure 10 In one embodiment, during the process of irradiating the sidewall of the isolation trench 201 with a processing beam, the incident angle α of the processing beam continuously decreases. For example, the incident angle α is 80° when the processing beam irradiates part P4, 60° when it irradiates part P3, 40° when it irradiates part P2, and 20° when it irradiates part P1. In other embodiments of this application, the specific value of the incident angle of the processing beam can be adjusted according to the actual size of the isolation trench, and this application does not impose any limitations on this.
[0060] It should be noted that when the processing beam illuminates the bottom of the isolation trench, the reflectivity of the processing beam is relatively low. Therefore, the number of charge carriers near the bottom of the isolation trench in the substrate is relatively the highest. As the processing beam illuminates the sidewalls of the isolation trench from bottom to top, the reflectivity of the processing beam increases with the decrease in the incident angle, causing the beam to be reflected back into the air. This reduces the light energy absorbed by the substrate near the sidewalls of the isolation trench along the direction of exit from the trench, and gradually decreases the number of active charge carriers in the substrate near the sidewalls along the same direction. Simultaneously, since the processing beam does not illuminate the top corner of the isolation trench, the number of charge carriers near the top corner of the isolation trench in the substrate is relatively the lowest.
[0061] It should be noted that when the thickness of the dielectric layer gradually increases in the direction away from the bottom of the isolation trench, the light transmittance of the dielectric layer gradually decreases in the same direction. In this case, it is not necessary to adjust the incident angle of the processing beam; directly directing the processing beam perpendicularly into the isolation trench can ensure a gradual increase in carrier charge concentration in the direction near the bottom of the isolation trench, thereby adjusting the formation rate of the dielectric layer subsequently formed within the isolation trench. Furthermore, if the incident angle of the processing beam is adjusted using an ellipsometer in conjunction with the gradual increase in the thickness of the dielectric layer in the direction away from the bottom of the isolation trench, the adjustment effect on the carrier concentration distribution can be further optimized.
[0062] In other embodiments of this application, the concentration distribution of charge carriers can also be adjusted by adjusting parameters such as the wavelength of the processing beam, the incident angle, and the duration of irradiation at different locations. Alternatively, the concentration distribution of charge carriers can be adjusted by forming a barrier layer with different transmittance or other means, so as to adjust the generation rate of the dielectric layer subsequently formed in the isolation trench. This application does not limit this.
[0063] Next, refer to Figure 11 In one embodiment, an isolation layer 220 is formed within the isolation trench 201 to form a shallow trench isolation structure including the isolation trench 201 and the isolation layer 220; wherein the formation rate of the isolation layer 220 is positively correlated with the concentration of carrier charge. Optionally, the isolation layer 220 is formed using either a thermal oxidation growth process or a deposition process, and the isolation layer 220 at least fills the isolation trench 201. Optionally, the material of the isolation layer 220 includes silicon dioxide.
[0064] For example, when the material of the isolation layer includes silicon dioxide, the specific process of forming the isolation layer includes: Si(OC2H5)4+O2→SiO2+CO2+H2O, that is, silicon dioxide is generated by reacting tetraethyl orthosilicate (TEOS) with oxygen. During the formation of the isolation layer, the concentration distribution of charge carriers in the substrate will have a certain influence on the formation rate of the isolation layer.
[0065] It should be noted that, since the carrier charge concentration gradually increases along the direction near the bottom of the isolation trench in the aforementioned steps, the carrier charge concentration distribution is as follows: the carrier charge concentration is relatively high at the bottom of the isolation trench, followed by the concentration near the sidewalls of the isolation trench, while the carrier charge concentration is relatively low at the top opening of the isolation trench. Furthermore, it should be emphasized that, because the substrates on both sides of the isolation trench are covered with oxide layers and hard mask layers, the top corners of the isolation trench are not illuminated by the processing beam, thus no carrier charge is generated or the concentration of generated carrier charge is relatively minimal.
[0066] Since the formation rate of the isolation layer is positively correlated with the concentration of charge carriers, given the charge carrier concentration distribution described above, the isolation layer at the bottom of the isolation trench forms relatively quickly, followed by the isolation layer at the sidewalls of the isolation trench, and the isolation layer at the top opening of the isolation trench forms relatively slowly. This reduces or avoids the probability of the isolation layer being prematurely sealed at the top opening, thereby reducing or even avoiding the probability of forming void defects within the isolation layer, which in turn helps to improve the yield of semiconductor devices.
[0067] In one embodiment, after forming an isolation layer within the isolation trench, the method for manufacturing the shallow trench isolation structure further includes: planarizing the isolation layer so that the remaining isolation layer just fills the isolation trench. Optionally, a chemical mechanical polishing (CMP) process is used to planarize the isolation layer to facilitate subsequent processes.
[0068] Accordingly, one embodiment of this application also provides a shallow trench isolation structure, manufactured using the shallow trench isolation structure manufacturing method described above. In other embodiments of this application, other semiconductor structures with the same or similar structures can also be manufactured using the shallow trench isolation structure manufacturing method described above, in order to reduce or even avoid the probability of void defects in the isolation layer or other film layers, thereby helping to improve product performance and yield.
[0069] An unexpected effect of this application is that by irradiating the isolation trench in the substrate with a processing beam, charge carriers are formed in the substrate surrounding the isolation trench, and the concentration of the charge carriers gradually increases along the direction near the bottom of the isolation trench. By forming an isolation layer in the isolation trench, a shallow trench isolation structure including the isolation trench and the isolation layer is formed, and the formation rate of the isolation layer is positively correlated with the concentration of the charge carriers, so as to avoid premature sealing of the isolation layer at the top of the isolation trench, thereby reducing or even avoiding the probability of forming void defects in the isolation layer.
[0070] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0072] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of manufacturing a shallow trench isolation structure, characterized by, include: A substrate is provided in which an isolation trench is formed, a dielectric layer is formed on the sidewalls of the isolation trench, and the bottom of the isolation trench is exposed; A processing beam is irradiated into the isolation trench along a direction perpendicular to the isolation trench, so as to form carrier charges in the substrate surrounding the isolation trench, and the concentration of the carrier charges gradually increases along the direction near the bottom of the isolation trench. An isolation layer is formed within the isolation trench to form a shallow trench isolation structure including the isolation trench and the isolation layer; wherein the formation rate of the isolation layer is positively correlated with the concentration of the charge carriers.
2. The manufacturing method of the shallow trench isolation structure according to claim 1, characterized in that, During the process of irradiating the isolation trench with a processing beam, the incident angle of the processing beam entering the isolation trench is adjusted so that the portion of the adjusted processing beam that hits the bottom of the isolation trench is greater than the portion of the processing beam that hits the sidewall of the isolation trench.
3. The manufacturing method of the shallow trench isolation structure according to claim 2, characterized in that, An ellipsometer is used to adjust the incident angle of the processed beam that enters the isolation trench.
4. The manufacturing method of the shallow trench isolation structure according to claim 1, characterized in that, The wavelength of the processed beam is in the range of 640nm to 780nm.
5. The manufacturing method of the shallow trench isolation structure according to claim 1, characterized in that, The process of forming an isolation layer within the isolation trench includes: The isolation layer is formed in the isolation trench using a thermal oxidation growth process.
6. The method for manufacturing the shallow trench isolation structure according to claim 5, characterized in that, The substrate is made of non-metallic silicon.
7. The method for manufacturing the shallow trench isolation structure according to claim 1, characterized in that, The dielectric layer is formed on the inner wall of the isolation trench using a deposition process or a thermal oxidation growth process, and the material of the dielectric layer includes silicon oxide.
8. The method for manufacturing the shallow trench isolation structure according to claim 1, characterized in that, A portion of the dielectric layer is removed using a plasma dry etching process, and the thickness of the remaining dielectric layer gradually increases in the direction away from the bottom of the isolation trench.
9. The method for manufacturing the shallow trench isolation structure according to claim 1, characterized in that, The aspect ratio of the isolation trench is in the range of 6 to 20.
10. A shallow trench isolation structure, characterized in that, It is manufactured using the manufacturing method of the shallow trench isolation structure as described in any one of claims 1 to 9.