Driving method of display panel, pixel driving circuit and display panel

Abstract

The embodiment of the invention discloses a driving method of a display panel, a pixel driving circuit and the display panel. According to the driving method of the display panel, at least one picture updating period comprises a data writing stage, a data holding stage and a data compensation stage; the at least one data compensation stage is located before the at least one data writing stage; in the data compensation stage, a grid scanning signal is provided for the pixel driving circuit, compensation data voltage is written in, in the data writing stage, the grid scanning signal is provided for the pixel driving circuit, target data voltage is written in, and the compensation data voltage is smaller than the target data voltage. And in the data holding stage, the data voltage is not written into the pixel driving circuit. According to the embodiment of the invention, the problem of picture flicker caused by a transistor hysteresis effect is solved, the target brightness is ensured to be reached as soon as possible when the picture is switched, and the picture brightness difference in the same picture updating period is reduced, so that the picture display quality and effect are improved.

Description

[0001] This application is a divisional application of application number 202011125984.8, filed on October 20, 2020, entitled "A driving method and display device for a display panel". Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a driving method for a display panel, a pixel driving circuit, and a display panel. Background Technology

[0003] In an Organic Light-Emitting Diode (OLED) display, the pixel circuitry achieves display functionality by controlling the driving current flowing through the OLED via a driving transistor. The magnitude of this driving current is related to characteristic parameters of the driving transistor, including the threshold voltage.

[0004] In existing OLED displays, when displaying two different images, the brightness of the images changes slowly during the switching process due to the difference in brightness. This brightness change takes a long time and is easily noticeable to the human eye, resulting in screen flicker and poor display quality. This has become an urgent problem to be solved in order to improve the quality of OLED displays. Summary of the Invention

[0005] This invention provides a driving method for a display panel, a pixel driving circuit, and a display panel, which can compensate for the instability of the electrical performance of transistors when switching display images, reduce brightness differences and change time, enable the display image to reach the target brightness faster, and solve the problem of screen flicker caused by transistor hysteresis.

[0006] In a first aspect, embodiments of the present invention provide a driving method for a display panel, including multiple screen update cycles, at least one of the screen update cycles including a data writing phase, a data holding phase, and a data compensation phase;

[0007] At least one of the data compensation stages is located before at least one of the data writing stages; in the data compensation stage, a gate scan signal is provided to the pixel driving circuit and a compensation data voltage is written;

[0008] During the data writing stage, a gate scan signal is provided to the pixel driving circuit and a target data voltage is written, wherein the compensation data voltage is less than the target data voltage;

[0009] During the data holding phase, no data voltage is written to the pixel driving circuit.

[0010] Secondly, embodiments of the present invention also provide a pixel driving circuit, wherein the pixel circuit includes a data writing stage, a data holding stage and a data compensation stage in at least one frame update cycle;

[0011] At least one of the data compensation stages is located before at least one of the data writing stages;

[0012] During the data compensation phase, the pixel driving circuit receives the gate scan signal and is written with the compensation data voltage;

[0013] During the data writing phase, the pixel driving circuit receives the gate scan signal and is written with the target data voltage;

[0014] The compensated data voltage is less than the target data voltage.

[0015] Thirdly, embodiments of the present invention also provide a display panel including the above-described pixel driving circuit.

[0016] The display panel driving method, pixel driving circuit, and display panel provided in this invention include multiple screen update cycles during the display driving process. At least one of the screen update cycles includes a data writing stage, a data holding stage, and a data compensation stage. The data compensation stage is positioned before the data writing stage. In the data compensation stage, a gate scan signal is provided to the pixel driving circuit and a compensation data voltage is written, which is less than a target data voltage. In the data writing stage, a gate scan signal is provided to the pixel driving circuit and the target data voltage is written. In the data holding stage, no data voltage is written to the pixel driving circuit. This enables the display panel to perform a data compensation process in at least one screen update cycle, thereby improving the display brightness of the display panel during the data compensation process. This invention can solve the problem of screen flicker caused by the hysteresis effect of transistors, compensate for the defects of unstable transistor electrical performance, ensure that the screen reaches the target brightness of the current screen update cycle as quickly as possible during switching, reduce the screen brightness difference within the same screen update cycle, and thus improve the screen display quality and effect. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the brightness changes of the OLED display panel provided by the inventor during the research process;

[0018] Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0019] Figure 3 yes Figure 2 The diagram shows the structure of the pixel driving circuit in the display device.

[0020] Figure 4 This is a timing diagram of a driving method for a display panel provided in an embodiment of the present invention;

[0021] Figure 5 and Figure 6 These are timing diagrams for two other display panel driving methods provided in embodiments of the present invention;

[0022] Figure 7 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention;

[0023] Figure 8 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention;

[0024] Figure 9 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention;

[0025] Figure 10 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention;

[0026] Figure 11 This is a timing diagram of the data compensation stage provided in an embodiment of the present invention;

[0027] Figure 12 This is a timing diagram of the data writing stage provided in an embodiment of the present invention;

[0028] Figure 13 This is a timing diagram of the data retention phase provided in an embodiment of the present invention;

[0029] Figure 14 This is a schematic diagram of the structure of a display panel pixel driving circuit provided in an embodiment of the present invention;

[0030] Figure 15 This is a timing diagram of a data writing stage provided in an embodiment of the present invention;

[0031] Figure 16 This is a schematic diagram of the structure of a display panel pixel driving circuit provided in an embodiment of the present invention;

[0032] Figure 17 This is a timing diagram of another data writing stage provided in an embodiment of the present invention;

[0033] Figure 18 This is a schematic diagram of the structure of a display panel pixel driving circuit provided in an embodiment of the present invention;

[0034] Figure 19 This is a timing diagram of another data writing stage provided in an embodiment of the present invention. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0037] Figure 1 This is a schematic diagram of the brightness changes of an OLED display panel provided by the inventor during the research process. (For reference) Figure 1 For example, taking a display panel with a refresh rate of 1 Hz as an example, the inventors discovered through research that during the driving process of an OLED display panel, when switching from a black state to a display screen of a certain brightness, if multiple data refresh frames are set, the pixel driving circuit can achieve multi-frame driving display by repeatedly writing data voltage. During this process, the hysteresis effect of the driving transistor in the pixel driving circuit gradually weakens, and the electrical performance gradually stabilizes. As shown in the figure, the first 4 seconds (the first four frames) represent the process of repeatedly refreshing and writing data voltage. During this process, the electrical performance of the transistor gradually stabilizes, and the brightness of the display panel screen gradually increases, finally reaching the target brightness in the 4th second. It should be noted that during the data refresh writing process in the first 4 seconds, the data voltage written to the pixel driving circuit is the same, and it is the theoretical data voltage Vdata0 corresponding to the target brightness of the screen update cycle. However, although the written data voltage is the same, due to the hysteresis effect of the driving transistor itself, in the earlier refresh frames, the actual brightness of the screen differs significantly from the target brightness, which the human eye can perceive and form the display effect. To address the above problems, this invention provides a driving method for a display panel.

[0038] Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Figure 3 yes Figure 2 The diagram shows the structure of the pixel driving circuit in the display device. Figure 4 This is a timing diagram of a display panel driving method provided in an embodiment of the present invention. First, refer to... Figure 2 This invention describes the display device to which the display panel driving method provided in this embodiment applies. The display device specifically includes a display panel 100, a scanning driving unit 200, and a data writing unit 300. The display panel 100 includes a plurality of pixel units 110. The pixel units 110 are generally arranged in an array along the row and column directions. The pixel units 110 may include at least three colors: red, green, and blue. Through the color matching of the three primary colors (red, green, and blue), a full-color display can be achieved.

[0039] Continue to refer to Figure 2 and Figure 3 Specifically, the light-emitting process of each pixel unit 110 is essentially implemented by the pixel driving circuit corresponding to each pixel unit 110 in the display panel 100. The following example demonstrates this. Figure 3 Taking the 7T1C pixel driving circuit shown as an example, the driving process of this pixel driving circuit will be briefly introduced.

[0040] It is understandable that, in addition to the pixel unit 110, the display panel also includes multiple gate scan lines 120 and multiple data signal lines 130. The pixel driving circuit is electrically connected to the gate scan lines 120 and the data signal lines 130, respectively. The pixel driving circuit receives the gate scan signal provided by the scan driving unit 200 through the gate scan line 120, and also receives the data voltage signal provided by the data writing unit 300 through the data signal line 130. Based on the gate scan signal and the data voltage signal, the pixel driving circuit drives the pixel unit 110 to emit light. Figure 3 In the 7T1C pixel driving circuit shown, the gate scan line 120 is electrically connected to the first scan signal terminal S1. The first scan signal terminal S1 can provide a gate scan signal to the gate of the driving transistor T of the pixel driving circuit, thereby controlling the switching of the pixel driving circuit. The data signal line 130 is electrically connected to the data signal terminal Vdata. The data signal terminal Vdata can write data voltage into the storage capacitor Cst, thereby driving the light-emitting diode, i.e., the pixel unit 110, to emit light through the driving transistor T.

[0041] Of course, such as Figure 3 The 7T1C pixel driving circuit shown is only one example of an embodiment of the present invention. The display panel driving method provided by the embodiment of the present invention is also applicable to other pixel driving circuits, which will not be described here.

[0042] The display panel driving method provided in this invention mainly improves the timing of the display panel during the screen update cycle. It can be understood that the display panel's driving process includes multiple screen update cycles, with each cycle displaying one image. Microscopically, the image displayed by the display panel is essentially the process of multiple pixel units emitting light. Macroscopically, multiple pixel units, through the combination of color and brightness, can achieve the display of an image. One screen update cycle of the display panel is essentially the process of all its pixel units being driven and illuminated by their corresponding pixel driving circuits. In other words, during one screen update cycle of the display panel, each pixel driving circuit on the display panel is refreshed once. During the refresh process, the pixel driving circuit drives the pixel unit 110 to emit light once through the gate scan signal and data voltage signal provided by the gate scan line 120 and data signal line 130, respectively, which is the data writing stage. When the pixel driving circuit drives the pixel unit 110 to emit light only through the gate scan signal provided by the gate scan line 120 without writing the data voltage signal, this is the data holding stage.

[0043] The inventors discovered through research that when a display panel needs to display dynamic images, it may need to refresh 60 frames per second. However, when the displayed image is static for a period of time, taking a single pixel unit as an example, that pixel unit may only need to maintain the same brightness for one second or several consecutive seconds, so there is no need to continuously write data within that one second. For example, compared to high-frequency driving where data is written to every frame out of 60 frames per second, the display panel provided in this invention includes low-frequency driving, where, for example, only a portion of the 60 frames per second do not require data writing. That is, in this embodiment, for each pixel unit and pixel driving circuit, a single frame update cycle of the display panel includes one data writing phase and multiple data holding phases.

[0044] It is understood that in some optional embodiments of this application, the display panel may include both low-frequency drive and high-frequency drive, and the two driving methods can be selected according to the needs of the screen.

[0045] It is understood that the low-frequency drive mentioned in this application does not refer to all signal lines being low-frequency driven. Optionally, the low-frequency driven signal in this application mainly refers to the emission control signal Emit. The effective pulse of the emission control signal Emit causes the pixel driving circuit to control the light-emitting element 60 to emit light. It is understood that the driving process of the pixel driving circuit requires the cooperation of multiple scan signals and control signals, and signals on other signal lines in the pixel driving circuit can also be driven using low frequency. Specifically, such as... Figure 4As shown, the display panel refreshing 60 frames per second essentially means that the pixel driving circuit corresponding to each pixel unit on the display panel receives 60 effective pulses of the emission control signal Emit within 1 second, and the pixel unit emits light 60 times within 1 second. It can be understood that the emission process of a pixel unit is not only controlled by the emission control signal Emit, but the process of the corresponding pixel driving circuit driving the pixel unit to emit light once can include a data voltage writing period and an emission period. The data voltage writing period is the preparation process of writing data voltage into the storage capacitor, while the emission period is the process of emission directly controlled by the emission control signal Emit. In other words, a frame update cycle as described in this application can include at least one data writing stage, at least one holding stage, and at least one data compensation stage. Each of the data writing stage, data holding stage, and data compensation stage corresponds to at least one emission process of the pixel driving circuit.

[0046] The following is a detailed description of the driving method for the display panel provided in the embodiments of the present invention. In the driving method for the display panel provided in the embodiments of the present invention, the display panel includes multiple screen update cycles during the driving display process. At least one screen update cycle can be set to include a data writing stage, a data holding stage, and a data compensation stage; the data compensation stage is located before the data writing stage.

[0047] In this context, the display panel typically updates multiple frames during display, and the brightness of each frame varies. The frame update cycle refers to the process of updating and displaying a specific frame within a certain time period. Each frame update cycle can be configured to include multiple stages, such as a data compensation stage, a data writing stage, or a data holding stage. Each stage can drive the display panel to display a frame. For example, the frame corresponding to the current frame update cycle can be driven to display in the first few stages, and the display of that frame can be maintained in later stages. For instance, taking a frame update cycle duration of 1 second and the refresh rate of the display panel's Emit control signal as 60 Hz, the display panel maintains the same frame display within 1 second, but in essence, it can refresh 60 identical frames. That is, the 1-second frame update cycle can be divided into 60 stages, each stage lasting 1 / 60 of a second. Of course, in this embodiment of the invention, the duration of each stage in the frame update cycle can be set differently according to actual needs, and this is not limited here.

[0048] The screen update cycle in the driving method provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 2-4Specifically, in the driving method of the display panel, optionally, in the data compensation stage A, a gate scan signal is provided to the pixel unit 110 and a compensation data voltage is written, the compensation data voltage being less than the target data voltage; the target data voltage is the theoretical data voltage corresponding to the target brightness of the current screen update cycle.

[0049] In this embodiment of the invention, the driving process of the display panel is essentially a process of synchronously or sequentially driving multiple pixel units on it. Generally, when the display panel displays an image, each pixel unit 110 needs to be written with a corresponding data voltage to drive the pixel unit to emit light at a corresponding brightness, thereby realizing the display of the entire display panel. Therefore, for each pixel unit 110 in the display panel, when writing the data voltage, the corresponding pixel unit 110 needs to be turned on sequentially through the gate scan signal provided by the gate scan line 120, and the data voltage signal needs to be written through the data signal line 130.

[0050] In other words, a data writing phase actually involves sequentially writing data to multiple pixel units in coordination with the scan lines. For ease of explanation, this embodiment uses a single pixel unit as an example. The data compensation phase and data holding phase are similar and will not be described in detail here.

[0051] refer to Figure 4The data compensation process involves multiple data compensation stages, A. This stage essentially involves writing compensation data voltage to the pixel units. After writing the compensation data voltage, the pixel units are driven to display. However, the brightness of the pixel units or display panel is affected by the hysteresis effect of the driving transistors in the pixel driving circuit. Therefore, the brightness of the pixel units or display panel is not actually consistent with the theoretically corresponding brightness of the compensation data voltage. For OLED display panels, the brightness of a pixel unit is positively correlated with the current flowing through the driving transistors in the pixel driving circuit, while the current flowing through the driving transistors is inversely proportional to the data voltage written to the pixel unit. Based on this, in this embodiment of the invention, the written compensation data voltage is set to be less than the target data voltage during the data compensation stage. Theoretically, the brightness of the pixel units or display panel should be greater than the target brightness of the current screen update cycle. However, due to the hysteresis effect of the driving transistors in the pixel driving circuit, the compensation data voltage at this time does not make the brightness of the pixel units greater than the target brightness of the current screen update cycle. Instead, it compensates for the pixel units whose brightness could not reach the expected level due to the hysteresis effect, and may even make the brightness of the pixel units exactly equal to the target brightness. In other words, during this data compensation phase, a higher actual screen brightness can be achieved by writing a smaller compensation data voltage. Furthermore, because the screen brightness is higher during the compensation phase, it is closer to the target brightness, and the time to reach the target brightness can be shortened to some extent. Therefore, during this screen update cycle, the difference in brightness change is relatively small before reaching the target brightness, the brightness buffer time is shortened, and the target brightness can be reached more quickly, ensuring the display effect of the image.

[0052] Optionally, during the data writing stage, a gate scan signal is provided to the pixel unit 110 and a target data voltage is written.

[0053] refer to Figure 4 In the data writing stage B, within the same screen update cycle, this stage must be set after the data compensation stage A. As described in the data compensation stage, through the data compensation process, the electrical performance of the driving transistors in the pixel driving circuit tends to stabilize, and the threshold reaches its theoretical value. Therefore, this stage can perform data writing and drive the display according to the pixel driving circuit with stable electrical performance. In this stage, the theoretical data voltage corresponding to the target brightness of the current screen update cycle is written into the pixel unit. Through the normal driving of the pixel driving circuit, the pixel unit or display panel displays at the target brightness.

[0054] Understandably, the target data voltage in this stage can be a data voltage value within a certain range. For the display panel, its target brightness can actually be a brightness value within the allowable error range, and the corresponding theoretical data voltage can also be a data voltage value within the allowable range. After the data voltage within this allowable range is written, the brightness of the displayed image reaches the expected brightness range.

[0055] Optionally, during the data holding phase, no data voltage is written to the pixel unit. Specifically, a gate scan signal is provided to the pixel unit 110, but no data voltage signal is written. (See reference...) Figure 4 The data holding stage C is essentially a picture holding stage. The data voltage in this stage remains consistent with the previous stage. In the pixel driving circuit, the storage capacitor in the data holding stage stores the data voltage of the previous stage, meaning the gate potential of the driving transistor maintains the data voltage of the previous stage. Therefore, when driving light emission in this data holding stage, there is no need to rewrite the data voltage, and its brightness is theoretically the same as the previous stage. Therefore, it can be understood that in this embodiment, the data holding stage should be set after the data writing stage or the data compensation stage. The data voltage written in the data writing stage or the data compensation stage can be stored in the capacitor of the pixel driving circuit, and there is no need to rewrite the data voltage in the data holding stage. During the pixel unit refresh display process, it is only necessary to provide a light emission control signal to turn on and drive the pixel unit, enabling the display panel to maintain the picture. It should be noted that, as... Figure 4 As shown, the data voltage corresponding to the data holding phase C is not the written data voltage, but only a reference value used to compare the compensation data voltage Vdata written in the data compensation phase A with the target data voltage Vdata0 written in the data writing phase B. For example, in the data holding phase, the switch controlling the data signal input of the pixel driving circuit is turned off, and no data signal is input to the pixel driving circuit regardless of the signal on the data signal line; for example... Figure 3 During the data holding phase, the second transistor M2 (which will be described in detail later) in the pixel driving circuit is in the off state.

[0056] The display panel driving method provided in this invention includes multiple screen update cycles during the display driving process. At least one screen update cycle includes a data writing phase, a data holding phase, and a data compensation phase. The data compensation phase is positioned before the data writing phase. In the data compensation phase, a gate scan signal is provided to the pixel unit, and a compensation data voltage is written. The compensation data voltage is less than the target data voltage, which is the theoretical data voltage corresponding to the target brightness of the current screen update cycle. In the data writing phase, a gate scan signal is provided to the pixel unit, and the target data voltage is written. In the data holding phase, no data voltage is written to the pixel unit. This enables the display panel to perform a data compensation process in at least one screen update cycle, thereby rapidly improving the display brightness of the display panel during the data compensation process. This invention can solve the screen flicker problem caused by the hysteresis effect of transistors, compensate for the instability of transistor electrical performance, ensure that the screen reaches the target brightness of the current screen update cycle as quickly as possible during switching, reduce the screen brightness difference within the same screen update cycle, and thus improve the screen display quality and effect. Furthermore, by making the compensation data voltage less than the target data voltage, the frequency of data signal input can be further reduced, thus lowering power consumption.

[0057] It is important to note that, such as Figure 4 Three data compensation stages A, one data writing stage B, and multiple data holding stages C are provided as an example, but the number of each stage is not limited here. It is understood that within the same screen update cycle, the number of data compensation stages needs to be set based on the specific hysteresis effect of the driving transistors in the pixel driving circuit of the display panel, and also based on the effect of the compensation data actually written during the data compensation stages. Specifically, within the same screen update cycle, more than one and less than five data compensation stages can be set before the data writing stage, while one data writing stage can be set simultaneously. On the one hand, using a certain number of data compensation stages can effectively compensate for the brightness of the screen, effectively increasing the screen display brightness before reaching the target brightness, and allowing the threshold of the driving transistor to stabilize as quickly as possible; on the other hand, using fewer data writing stages can reduce the data writing process of the display panel, thereby reducing the driving frequency of the display panel and thus reducing the power consumption of the display panel. Those skilled in the art can set the number of data compensation stages within the same screen update cycle according to the actual compensation effect of the panel. Figure 5 and Figure 6 These are timing diagrams of two other display panel driving methods provided in the embodiments of the present invention, for comparison. Figures 4-6For example, for a display panel with a frame update cycle of 1 second and a drive frequency of 60 Hz for the Emit control signal in the display panel, one to three data compensation stages A, i.e., one to three data compensation frames, can be set in the same frame update cycle. Immediately following the data compensation stage, a data writing stage B, i.e., one data writing frame, is set. All stages after the data writing stage are set as data holding stages C, i.e., multiple data holding frames.

[0058] Furthermore, it should be noted that the data writing phase is essentially a crucial stage for the display panel to display images, determining the display brightness of pixel units throughout the entire image update cycle. As provided in the above embodiment, the image update cycle includes a data compensation phase and a data holding phase in addition to the data writing phase. The inclusion of a data holding phase reduces the number of data writing phases, primarily for lowering the driving frequency and panel power consumption. Simultaneously, in this embodiment, the addition of a data compensation phase before the data writing phase aims to improve the buffering process of panel brightness within an image update cycle. Those skilled in the art will understand that, throughout the entire driving process of the display panel, i.e., multiple image update cycles, in addition to including the data compensation and data holding phases in at least one image update cycle, other image update cycles may not include these phases. In this case, at least one image update cycle may only include the data writing phase, driven in a high-frequency driving mode; naturally, as analyzed below, this image update cycle is the high-frequency driving image update cycle described in this application, and the frequency of the image update cycle increases accordingly.

[0059] For example, if the frequency of the frame update cycle in a high-frequency drive is 60Hz, there are 60 frames per second, and each frame is a data writing phase with a data writing phase frequency of 60Hz. Therefore, the frame update cycle frequency is also 60Hz. However, in the embodiments provided in this application, when using a low-frequency drive, although one frame update cycle still includes 60 frames, i.e., 60 phases (i.e., the total number of data writing phases, data holding phases, and data compensation phases in one frame update cycle is 60), the target data voltage can be written only once. In this case, the frequency of the data writing phase is reduced, equivalent to 1Hz, and the frame update cycle frequency is equivalent to 1Hz.

[0060] Furthermore, it should be noted that although the screen display during the data holding phase may change in the embodiments of this application, the time period simply including the data holding phase is not considered an independent screen update cycle. Only the complete cycle including the data writing phase, the data holding phase, and the data compensation phase is considered a screen update cycle under the low-frequency drive condition described in this application.

[0061] Furthermore, unless otherwise specified, the frame update cycle mentioned below refers to the frame update cycle under low-frequency drive.

[0062] Furthermore, the inventors discovered that while the pixel driving circuit's driving transistors exhibit a hysteresis effect during actual screen switching in a display panel, the degree of this hysteresis is related to the displayed image. Specifically, the hysteresis effect significantly impacts the period when the brightness of the current screen update cycle is greater than that of the previous screen update cycle. At this time, for the pixel unit and the pixel driving circuit, a lower data voltage signal needs to be written to the pixel driving circuit to generate a higher driving current during the light-emitting process, thereby driving the light-emitting diode to emit light at a higher brightness. However, due to the hysteresis effect of the driving transistors, in the earlier data writing stages of the current screen update cycle, the threshold voltage Vth of the driving transistors deviates significantly, resulting in a smaller driving current and inability to drive properly. The brightness of the pixel unit at this time will be lower than the target brightness, leading to unsatisfactory screen brightness and poor display quality in the current screen update cycle.

[0063] Accordingly, optionally, in the display panel driving method provided in this embodiment of the invention, the multiple screen update cycles include at least one first screen update cycle and at least one second screen update cycle; the brightness of the first screen update cycle is greater than the brightness of its preceding screen update cycle, and the first screen update cycle includes the data writing phase, the data holding phase, and the data compensation phase; the brightness of the second screen update cycle is less than or equal to the brightness of its preceding screen update cycle, and the first screen update cycle includes the data writing phase and the data holding phase. In other words, when the brightness of the current screen update cycle is greater than the brightness of the preceding screen update cycle, the current screen update cycle includes the data compensation phase, the data writing phase, and the data holding phase; when the brightness of the current screen update cycle is less than or equal to the brightness of the preceding screen update cycle, the current screen update cycle includes the data writing phase and the data holding phase.

[0064] In this scenario, when the brightness of the first screen update cycle is greater than that of the previous screen update cycle, the brightness of the display panel switches. Due to the hysteresis effect of the driving transistor, the actual brightness is lower than the target brightness when writing data at the target voltage. Therefore, in addition to the data writing and data holding phases, a data compensation phase is also included in the first screen update cycle. Through data compensation, higher brightness can be obtained in the data compensation phase, resulting in a significant increase in brightness during the screen switching process and faster attainment of the target brightness. When the brightness of the second screen update cycle is less than or equal to that of the previous screen update cycle, the second screen update cycle only includes the data writing and data holding phases, and the data compensation phase is not required. Conversely, when the display screen switches from high brightness to low brightness, i.e., in the adjacent nth and (n+1)th screen update cycles, the nth screen update cycle is a high-brightness screen, and the (n+1)th screen update cycle is a low-brightness screen. In the nth screen update cycle, the driving current of the pixel driving circuit is larger, and the gate-source voltage of the driving transistor is larger. When it's the (n+1)th frame update cycle, the driving current of the pixel driving circuit decreases, and the gate-source voltage of the driving transistor decreases. That is, the gate-source voltage of the driving transistor shows a downward trend. At this time, the current of the driving transistor decreases, and the threshold voltage Vth of the driving transistor will not shift significantly. The electrical performance of the driving transistor is relatively stable, so there is no need for data compensation.

[0065] This embodiment allows for targeted brightness compensation for each frame update cycle of the display panel, ensuring that the actual brightness of the display panel meets the target brightness requirements in each frame update cycle, thereby improving the display effect and preventing flickering. Simultaneously, selectively adding a data compensation phase in specific frame update cycles reduces the number of times the data writing unit writes data signals in other frame update cycles, thus lowering the overall power consumption of the display panel.

[0066] This invention provides various implementation methods for setting the compensation data voltage value during the data compensation phase of the image update cycle. (Continue to refer to...) Figure 4 Optionally, the same screen update cycle includes multiple data compensation stages A, which include a first data compensation stage A1 and a second data compensation stage A2. The first data compensation stage A1 is before the second data compensation stage A2; the compensation data voltage written in the second data compensation stage A2 is greater than the compensation data voltage written in the first data compensation stage A1.

[0067] like Figure 4As shown, at this point, the first data compensation stage A1 precedes the second data compensation stage A2, and the corresponding compensation data voltages Vdata1 < Vdata2 for these two stages. It can be understood that as the data compensation stages progress, the electrical performance of the driving transistors in the pixel driving circuit gradually stabilizes, and the impact of transistor threshold drift on display brightness decreases. Therefore, by setting the compensation data voltage of the second data compensation stage to be less than that of the first data compensation stage, it can be ensured that the actual brightness of the image does not exceed the target brightness of the current image update cycle, thus guaranteeing a stable and gradual change in brightness.

[0068] Optional, continue to refer to Figure 4 The same screen update cycle includes multiple data compensation stages A, which are arranged sequentially in chronological order; the compensation data voltage Vdata written in these multiple data compensation stages A increases sequentially. For example... Figure 4 As can be seen from the brightness of the data compensation stage displayed in the image, by setting the compensation data voltage written for each of the multiple data compensation stages to increase sequentially, the theoretical corresponding screen display brightness gradually decreases, while the actual brightness gradually increases with data compensation. Eventually, the compensation voltage increases to the target data voltage, and the screen brightness also increases to the target brightness corresponding to the current screen update cycle.

[0069] Of course, considering that the actual impact of the hysteresis effect of the driving transistor needs to be determined by simulation or experiment, when setting multiple data compensation stages, the compensation data voltage corresponding to individual local data compensation stages may also decrease. While ensuring that the compensation data voltage of multiple data compensation stages generally shows an increasing trend, the increase of the compensation data voltage corresponding to any two adjacent data compensation stages can be disregarded.

[0070] Optionally, in another embodiment of the present invention, the same screen update cycle may be set to include multiple data compensation stages, including a third data compensation stage and a fourth data compensation stage, wherein the third data compensation stage precedes the fourth data compensation stage; the compensation data voltage written in the fourth data compensation stage is equal to the compensation data voltage written in the third data compensation stage. Figure 7 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention. Refer to the following... Figure 7 The compensation data voltage in the data compensation stage of this embodiment will be described in detail. First, the same screen update cycle includes a data compensation stage A, a data writing stage B, and a data holding stage C, with the data compensation stage A preceding the data writing stage B.

[0071] by Figure 7Taking the third data compensation stage A3 and the fourth data compensation stage A4 as examples, the third data compensation stage A3 is located before the fourth data compensation stage A4, and the corresponding compensation data voltages Vdata3 = Vdata4 for these two stages. Wherein, by Figure 4 As shown in the embodiment, with each data compensation stage, the electrical performance of the driving transistor in the pixel driving circuit gradually stabilizes. By setting the compensation data voltage corresponding to each of the multiple data compensation stages to increase sequentially, the theoretical corresponding screen brightness gradually decreases, while the actual brightness gradually increases with data compensation. Ultimately, the compensation voltage increases to the target data voltage, and the screen brightness also increases to the target brightness corresponding to the current screen update cycle. Based on this, those skilled in the art can reasonably set the voltage value of the data compensation voltage written in the data compensation stage to achieve the same compensation data voltage written in multiple data compensation stages before the data writing stage, that is, setting Vdata3 to be equal to Vdata4. Figure 7 As can be seen from the brightness of the data compensation stage displayed in the image, on the basis of ensuring that the voltage value of the data compensation voltage is less than the target data voltage, that is, on the basis of ensuring that the brightness corresponding to the data compensation voltage is higher than the target brightness, the voltage values ​​of the data compensation voltages Vdata3 and Vdata4 can be reasonably increased to reduce the theoretically corresponding brightness. This ensures that after the electrical performance of the driving transistor is stable, the brightness of the data compensation stage will not exceed or significantly exceed the target brightness, thus ensuring the stable change of brightness during the data compensation stage and avoiding screen flicker.

[0072] like Figure 7 In the third data compensation stage A3 and the fourth data compensation stage A4 shown, since the written compensation data voltage is the same, the data writing unit does not need to change the output value of the compensation data voltage during the writing process of the compensation data voltage in these two data compensation stages. This can reduce the complexity of the output data voltage of the data writing unit, reduce the amount of calculation of the data writing unit, and thus reduce the power consumption of the data writing unit to a certain extent.

[0073] Optionally, at least one data holding stage can be provided between the third data compensation stage and the fourth data compensation stage. The data holding stage C is used to display the data according to the data voltage written in the previous data writing stage B or data compensation stage C. When at least one data holding stage C is provided between the third data compensation stage A3 and the fourth data compensation stage A4, the data holding stage C can maintain the brightness-preserving display of the image from the third data compensation stage A3. At this time, the driving transistor of the pixel driving circuit maintains the same external state in this data holding stage C as in the third data compensation stage A3, i.e., the gate-source voltage remains consistent. Therefore, this data holding stage C can not only compensate for the brightness of the pixel unit or display panel, but also reduce the offset of the threshold voltage Vth of the driving transistor, making the electrical performance of the driving transistor more stable. Furthermore, since the data holding stage C does not require writing the data compensation voltage, the number of data writes by the data writing unit is reduced, thereby further reducing power consumption.

[0074] In some optional embodiments of this application, various examples are provided regarding the relationship between the compensation data voltages of multiple data compensation stages within the same screen update cycle. Optionally, when the same screen update cycle includes multiple data compensation stages, the compensation data voltages written for the multiple data compensation stages can be set to form an arithmetic sequence, a geometric sequence, or an exponential sequence.

[0075] For compensation data voltages that follow an arithmetic, geometric, or exponential sequence, the theoretically corresponding brightness in each data compensation stage also follows the same arithmetic, geometric, or exponential sequence. Simultaneously, due to data compensation, the hysteresis effect of the driving transistor gradually weakens, thus the theoretical brightness in each data compensation stage can be set with a decreasing trend. Since the compensation data voltage can be set to increase, the theoretically corresponding brightness can decrease, ultimately ensuring that the compensation data voltage reaches the target data voltage while the electrical performance of the driving transistor stabilizes, and the display panel brightness reaches the target brightness.

[0076] Furthermore, based on this, the specific value of the compensation data voltage needs to be reasonably set to effectively buffer the hysteresis effect of the driving transistor and improve the brightness of the compensation stage. Specifically, the first data compensation stage among multiple data compensation stages in the same frame update cycle can be taken as the initial data compensation stage, and the compensation data voltage written in the initial data compensation stage can be set as Vdata = Vdata0 × L1 / L2; where L2 is the target brightness of the frame update cycle, Vdata0 is the target data voltage corresponding to the target brightness of the frame update cycle, and L1 is the actual brightness when the target data voltage is written to the pixel unit in the initial data compensation stage.

[0077] Understandably, during the initial data compensation stage, when the target data voltage is written to the pixel unit, the brightness of the pixel unit or display panel will not reach the target brightness corresponding to the target data voltage due to the hysteresis effect of the driving transistor. That is, brightness L1 will be significantly lower than the target brightness. From another perspective, brightness L1 essentially records the degree of hysteresis effect of the driving transistor. Since brightness and data voltage are negatively correlated, the ratio of brightness L1 to the target brightness L2 is essentially equal to the ratio of the target data voltage Vdata0 to the theoretical data voltage value Vdata1 of L1. Using this ratio as the ratio of the compensation data voltage Vdata written in the initial data compensation stage to the target data voltage Vdata0, we can obtain Vdata = Vdata0. 2 / Vdata1. Therefore, it can be understood that by writing the compensation data voltage Vdata during the initial data compensation stage, the theoretical brightness during the data compensation stage can be greater than the target brightness. This reduces the hysteresis effect from lowering the screen brightness while simultaneously providing targeted compensation for the brightness impact caused by the hysteresis effect of the driving transistor.

[0078] Optionally, the first data compensation stage in multiple data compensation stages of the same frame update cycle is the initial data compensation stage; the compensation data voltage Vdata = KVdata' written in the initial data compensation stage; where Vdata' is the theoretical data voltage corresponding to the target brightness of the previous frame update cycle, 0 < K < 1.

[0079] As described in the above embodiments, the prerequisite for adding a data compensation stage in the frame update cycle is that the brightness of the previous frame update cycle is lower than the brightness of the current frame update cycle. Based on this, to ensure that the data compensation process in the current frame update cycle is based on the brightness of the previous frame update cycle, the compensation data voltage written in the initial data compensation stage can be set to be proportional to the data voltage of the previous frame update cycle. The specific value of the coefficient K needs to be determined based on the actual compensation effect of Vdata. Those skilled in the art can obtain this relationship through experimentation and simulation; no further limitations are imposed here.

[0080] In addition, the same screen update cycle includes N data compensation stages. The data voltage corresponding to the nth data compensation stage can be set as Vdata_n = Vdata0 - (N-n+1)*x, where Vdata0 is the target data voltage corresponding to the target brightness of the current screen update cycle, n and N are both positive integers, 1≤n≤N, and x = 0.5V~2V.

[0081] At this point, the compensation data voltages corresponding to the N data compensation stages essentially form an arithmetic sequence, with a common difference of x. Setting the range of the common difference x to 0.5V to 2V ensures that the compensation data voltage values ​​change slowly during the data compensation stages. Furthermore, according to... Figure 3 As shown in the timing diagram, after providing arithmetic and increasing compensation data voltages, the brightness of the display panel can not only gradually increase, but also maintain a high level of brightness in the initial data compensation stage. This makes the brightness of the screen throughout the entire screen update cycle closer to the target display brightness, effectively avoiding screen flicker.

[0082] Figure 8 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention, referred to... Figure 8 In another embodiment of the present invention, taking a single screen update cycle comprising multiple data compensation stages A as an example, the single screen update cycle sequentially includes the 1st to the Nth data compensation stages A. The difference in compensation data voltage written between the a-th data compensation stage A and the (a+1)-th data compensation stage A can be set to ΔX1; the difference in compensation data voltage written between the b-th data compensation stage A and the (b+1)-th data compensation stage A can be set to ΔX2; wherein ΔX1 > ΔX2, a and b are both positive integers greater than 0, and a+1 ≤ b. Wherein, a, a+1, b, and b+1 are all not greater than N.

[0083] The relationship between the a-th data compensation stage A and the (a+1)-th data compensation stage A is that the (a+1)-th data compensation stage is adjacent to the a-th data compensation stage and follows the a-th data compensation stage. The (a+1)-th data compensation stage being adjacent to the a-th data compensation stage means that there are no other data compensation stages between the a-th and (a+1)-th data compensation stages, but at least one data holding stage can be set. The data holding stage is used to display the data voltage written in the previous data writing stage or data compensation stage; in this case, the display screen of the a-th data compensation stage can be maintained. Furthermore, the compensation data voltage value written in the (a+1)-th and a-th data compensation stages is a gradually changing compensation data voltage value; in these two data compensation stages, the compensation data voltage gradually increases. Similarly, the relationship between the b-th and b+1-th data compensation stages is that the (b+1)-th data compensation stage is adjacent to the b-th data compensation stage and follows the b-th data compensation stage. Furthermore, taking a single frame update cycle comprising N data compensation stages as an example, where a+1≤N and b+1≤N, the compensation data voltage written in each stage not only shows an increasing trend, but the difference between two adjacent compensation data voltages also becomes smaller and smaller. In other words, the brightness difference theoretically corresponding to the compensation data voltage becomes smaller and smaller, and gets closer and closer to the target brightness.

[0084] The inventors discovered that over time, the drift of the threshold voltage of the driving transistor approaches stability, and the change in electrical performance becomes more gradual. In this embodiment of the invention, by setting a compensation data voltage with increasingly smaller differences provided during the data compensation stage, the change trend becomes more gradual. This matches the decreasing hysteresis effect of the driving transistor and the decreasing change in the threshold voltage Vth of the driving transistor, making the brightness compensation gradually smaller and closer to the normal state, thus achieving normal driving display. This not only avoids insufficient brightness compensation during the initial data compensation, resulting in a smaller actual brightness increase, but also prevents excessive compensation in later data stages, causing the actual brightness to exceed the target brightness.

[0085] Furthermore, considering the actual data compensation duration, the proportion of the data compensation phase in a single screen update cycle should have a certain upper limit to ensure that it does not affect the normal screen display. Specifically, the proportion of the data compensation phase can be appropriately reduced according to the degree of hysteresis effect of the driving transistor. In this embodiment of the invention, the same screen update cycle can be configured to include N data compensation phases, M data holding phases, and P data writing phases; wherein N / (N+M+P)≤1 / 6, and N, M, and P are all integers greater than or equal to 1.

[0086] At this point, for a drive process with a frame update cycle of 1 second and a drive frequency of 60 Hz, the data compensation phase should account for less than or equal to 10 frames. Clearly, the proportion of the data compensation phase at this time will not affect the duration of displaying the image at the target brightness. For the human eye, the perceived image brightness differs less from the target brightness, resulting in more accurate image display and better display quality.

[0087] As shown in the image update cycle above, the data compensation phase is located before the data writing phase, while the data retention phase is located after the data writing phase. This is only one embodiment of the present invention. For the actual driving process, the embodiments of the present invention also provide various implementation methods for the positions of the data compensation phase and the data retention phase.

[0088] Optionally, the same screen update cycle includes N data compensation stages, M data holding stages, and P data writing stages; where N, M, and P are all integers greater than or equal to 1; and the interval between any two adjacent data compensation stages can be set to n data holding stages, where 0 ≤ n ≤ M.

[0089] The data holding phase is used to display the data voltage written in the previous data writing or data compensation phase, thereby maintaining the display image from the previous data writing or data compensation phase. It can be understood that setting an interval of at least one data holding phase between two adjacent data compensation phases delays the refresh of the image displayed in that data compensation phase. During the display process at the compensated brightness, the electrical performance of the driving transistor can gradually stabilize, thus achieving brightness compensation. Specifically, when there is no interval of 0 data holding phases between any two data compensation phases, this is a scheme where the data compensation phases are concentrated before the data writing phase, which will not be elaborated upon here. Figure 9 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention, referred to... Figure 9 When the interval between any two data compensation stages A is greater than zero data holding stages C, due to the limited number of data holding stages, a maximum of M data holding stages can be set between two adjacent data compensation stages. Furthermore, considering that the brightness of the display panel is lower than the target brightness during the data compensation stage, the number of data holding stages between two adjacent data compensation stages can be reasonably set to ensure that the overall brightness of the entire screen update cycle is closer to the target brightness. Moreover, at least some data holding stages should be set after the data writing stage. In this case, the screen display at the target brightness achieved during the data writing stage can be delayed and displayed during the data holding stage, thus making the entire screen update cycle display closer to the target brightness. For schemes where all data holding stages are set after the data writing stage, due to the long period of data holding without data voltage writing, the data voltage signal written during the data writing stage stored in the pixel driving circuit will be lost. Alternatively, due to signal crosstalk and other reasons, the data voltage that actually causes the driving transistor to work and generate driving current during the data holding stage may be inaccurate or uncontrollable, resulting in a difference between the actual display screen during the data holding stage and the display screen during the data writing stage. In this embodiment, by interleaving a data hold phase between the data compensation phases, or between the data compensation phase and the data write phase, the uncontrollable nature of holding the image for a long time during a large number of continuous data hold phases can be avoided, ensuring that the display brightness of the entire image update cycle is closer to the target brightness with relative accuracy. Furthermore, the data compensation phase and the data write phase can be more evenly distributed throughout the entire image update cycle, reducing the pressure of intensive data writing voltage in the early stages of the image update cycle.

[0090] Specifically, in this embodiment of the invention, the same screen update cycle can be configured to include multiple data compensation stages and multiple data retention stages; at least two data compensation stages are separated by at least one data retention stage. Based on this, this embodiment of the invention provides specific solutions regarding the number and location of the data retention stages between data compensation stages.

[0091] Among them, continue to refer to Figure 9 Optionally, the same number of data hold stages can be set between any two adjacent data compensation stages. In this case, the brightness compensated in each data compensation stage can achieve the same degree of delayed refresh, meaning the image can be displayed at the compensated brightness, thus ensuring that the electrical performance of the driving transistor gradually stabilizes during this process. Moreover, since a data hold stage is added after the data compensation stage, the data hold stage can compensate for brightness without writing data voltage to the pixel unit, thereby saving the number of times compensation data voltage is written and reducing the power consumption of the display panel.

[0092] Figure 10 This is a timing diagram of another display panel driving method provided in an embodiment of the present invention, compared with... Figure 9 and Figure 10 The similarities between this embodiment and the above embodiments will not be repeated. In this embodiment, the number of data holding stages C between two adjacent data compensation stages A in the same screen update cycle can also be set to increase progressively. In this embodiment, through gradual data compensation writing, the electrical performance of the driving transistor tends to stabilize in the later data compensation stages of multiple data compensation stages, at which point the screen brightness of the display panel tends to approach the target brightness. Taking a screen update cycle including multiple data compensation stages, with the same screen update cycle including the 1st to the Nth data compensation stages in sequence as an example, that is, the difference between the actual brightness of the pixel unit and the target brightness in the ath data compensation stage is greater than the difference between the actual brightness of the pixel unit and the target brightness in the (a+1)th data compensation stage. This embodiment further reduces the number of data holding stages between the ath and a-1th data compensation stages, which can avoid too many data holding stages holding a screen with a large difference from the target brightness, and allows more data holding stages to be set in the stages where the electrical performance of the driving transistor gradually stabilizes, so that the screen of the entire screen update cycle is closer to the target display brightness. Furthermore, as the data compensation stage progresses, the drift trend of the threshold voltage Vth of the driving transistor slows down. To accommodate this slowing trend, the number of data compensation stages in the later stages of a frame update cycle can be appropriately reduced, and the arrangement density does not need to be very dense. At this time, the number of data writes by the data writing unit can be appropriately reduced, thereby reducing the power consumption of the display device.

[0093] Furthermore, as mentioned above, since the brightness of the display panel is lower than the target brightness during the data compensation stage, in order to ensure that the overall brightness of the entire screen update cycle is closer to the target brightness, the positions of the data compensation stage and the data writing stage in the entire screen update cycle can be reasonably set. This allows the brightness of the data compensation stage to be effectively compensated, quickly reaching the target brightness, and also ensures that the target brightness achieved during the data writing stage is maintained throughout the screen update cycle, achieving a higher time percentage. Based on this, in this embodiment of the invention, the same screen update cycle can be set to include N data compensation stages, M data holding stages, and P data writing stages; where N, M, and P are all integers greater than or equal to 1; any data compensation stage includes M*a% / N data holding stages, where 30% ≤ a% ≤ 50%, and M*a% is an integer greater than or equal to 1, and M*a% / N is an integer greater than or equal to 1.

[0094] Here, M*a% of the data holding stages are essentially the number of data holding stages preceding the data writing stages. In other words, M*a% is evenly divided according to the number N of data compensation stages, and then distributed after each data compensation stage. At this point, a data holding stage exists after each data compensation stage, and the brightness compensated in each data compensation stage can be refreshed with a delay. Simultaneously, the remaining data holding stages can also be evenly distributed among the P data writing stages, arranging them after each data writing stage, thus delaying the refresh of the image in each data writing stage.

[0095] Of course, in the same screen update cycle, only one data writing stage can usually be set. Therefore, except for the data holding stage set before the data writing stage, the other data holding stages can simultaneously maintain the display of the target brightness screen of the one data writing stage.

[0096] It should be noted that when a% is set relatively small, there are fewer data hold stages after each data compensation stage, and the compensated brightness cannot be maintained. Conversely, when a% is set relatively large, the target brightness image is maintained for a longer period during the data writing stage, resulting in a smaller difference between the overall brightness and the maintained brightness throughout the entire image update cycle. Another point to note is that while a large a% setting results in a smaller difference between the overall brightness and the maintained brightness, setting too many data hold stages to maintain the target brightness image during the data writing stage can cause leakage current in the driving transistors of the pixel driving circuit. This can lead to a decrease in the maintained image brightness after multiple data hold stages, thus resulting in a difference from the target brightness. Based on these reasons, the a% ratio can be set within the range of 30% to 50%, and the specific value of a% can be adjusted based on the actual brightness compensation situation and the overall brightness throughout the entire image update cycle.

[0097] This embodiment allows for several advantages. First, by adding a data holding phase after the data compensation phase, the data holding phase can compensate for brightness without writing compensation data voltage to the pixel units, thus reducing the number of compensation data voltage writes and lowering the power consumption of the display panel. Second, the data compensation phase and the data writing phase can be appropriately distributed in the early to mid-stages of the screen update cycle, reducing the pressure of intensive data voltage writes required in the early stages of the screen update cycle. Third, setting a relatively small number of data holding phases after the data writing phase can prevent the uncontrollable image from being held for too long, ensuring that the display brightness of the entire screen update cycle is closer to the target brightness. Fourth, a relatively small number of data holding phases ensures that the brightness of the held image is closer to the brightness of the image during the data writing phase.

[0098] Furthermore, the driving method for the display panel provided in this embodiment of the invention also involves the design of a specific pixel driving circuit structure in the display panel. First, in the display panel, a pixel driving circuit is provided for each pixel unit, meaning the display panel includes multiple pixel driving circuits corresponding one-to-one with each pixel unit. Specifically, the pixel driving circuit may include a first pixel driving circuit and a second pixel driving circuit. The driving transistor of the first pixel driving circuit is a silicon-based transistor, and the driving transistor of the second pixel driving circuit is an oxide semiconductor transistor. In the same frame update cycle, the proportion of data compensation stages in the first pixel driving circuit can be set to be different from the proportion of data compensation stages in the second pixel driving circuit.

[0099] It is understandable that silicon-based transistors and oxide semiconductor transistors differ in their electrical performance and hysteresis effects due to their structural differences. Therefore, for pixel driving circuits containing different driving transistors, the proportion of data compensation stages needs to be set differently during the display driving process. This allows for differentiated data compensation for pixel driving circuits with different driving transistors, ensuring that the corresponding pixel units reach the target brightness as quickly as possible, thus resulting in more uniform screen brightness throughout the entire image update cycle. Generally, compared to oxide semiconductor transistors, silicon-based transistors have poorer hysteresis characteristics. Therefore, when performing data compensation, the proportion of data compensation stages can be set slightly higher to improve the degree of brightness compensation.

[0100] Similarly, for transistors made from the same material, their electrical performance will vary significantly due to differences in transistor type, and the hysteresis effect will also differ. Based on this, in the following cases, the display panel includes multiple pixel driving circuits corresponding one-to-one with each pixel unit. Each pixel driving circuit includes driving transistors; the driving transistors include N-type silicon-based transistors and P-type silicon-based transistors; the pixel driving circuit includes a third pixel driving circuit and a fourth pixel driving circuit, the third pixel driving circuit including N-type silicon-based transistors, and the fourth pixel driving circuit including P-type silicon-based transistors; the proportion of data compensation stages in the third pixel driving circuit can be set to be different from the proportion of data compensation stages in the fourth pixel driving circuit within the same frame update cycle.

[0101] At this point, by performing differentiated data compensation for pixel driving circuits containing different types of driving transistors, it can be ensured that the corresponding pixel units reach the target brightness as soon as possible, thereby making the image brightness more uniform throughout the entire image update cycle.

[0102] Furthermore, it can be set that in the same frame update cycle, the number of data compensation stages of the third pixel driving circuit accounts for X, and the number of data compensation stages of the fourth pixel driving circuit accounts for Y, where X≥Y.

[0103] Taking low-temperature polycrystalline silicon transistors (LTS) as an example, N-type silicon transistors exhibit a more pronounced hysteresis effect. Therefore, more data compensation stages can be set during the image update cycle to improve brightness compensation. P-type silicon transistors, on the other hand, have relatively better electrical performance and a less pronounced hysteresis effect, allowing for a smaller number of data compensation stages during the image update cycle.

[0104] In another embodiment of the present invention, the display panel includes a plurality of pixel driving circuits corresponding one-to-one with the pixel units, and the pixel driving circuit includes driving transistors; the driving transistors include N-type silicon transistors. For a pixel driving circuit including N-type silicon transistors, in a frame update cycle, the number of data compensation stage, data holding stage and data writing stage satisfies: N / (N+M+P)≤1 / 6.

[0105] In another embodiment of the present invention, the display panel includes a plurality of pixel driving circuits corresponding one-to-one with the pixel units, and the pixel driving circuit includes driving transistors; the driving transistors include P-type silicon transistors. For a pixel driving circuit including P-type silicon transistors, in a frame update cycle, the number of data compensation stage, data holding stage and data writing stage satisfies: N / (N+M+P)≤1 / 12.

[0106] Similarly, N-type silicon transistors have poorer electrical performance and a more pronounced hysteresis effect. Therefore, more data compensation stages can be set in the frame update cycle to improve the brightness compensation effect. For P-type silicon transistors, the hysteresis effect is relatively less pronounced, and fewer data compensation stages can be set in the frame update cycle. Taking a frame update cycle of 1 second and a driving frequency of 60 Hz as an example, one frame update cycle includes 60 frames. For an N-type silicon transistor pixel driving circuit, the data compensation stage can be set to include 10 frames, and for a P-type silicon transistor pixel driving circuit, the data compensation stage can be set to include 5 frames.

[0107] Based on the type of driving transistors in different pixel driving circuits, the above methods can increase the proportion of driving transistors in the data compensation stage, or set a specific proportion, for driving transistors with more severe hysteresis effects. This can improve the degree of data compensation in the data compensation stage, so that each pixel unit in the display panel can receive appropriate brightness compensation in the same frame update cycle. This can avoid differences in brightness between pixel units due to different degrees of hysteresis effects, making the brightness of pixel units more accurate and ensuring the brightness uniformity of the display panel.

[0108] Furthermore, the embodiments of the present invention also discuss and design the degree of data compensation in different screen update cycles. Specifically, any two adjacent screen update cycles include a first screen update cycle and a second screen update cycle; the first screen update cycle includes N1 data compensation stages, M1 data holding stages, and P1 data writing stages; the second screen update cycle includes N2 data compensation stages, M2 data holding stages, and P2 data writing stages; the first screen update cycle and the second screen update cycle can be set to satisfy: N1+M1+P1<N2+M2+P2, N1<N2.

[0109] Where N1+M1+P1 represents the total number of stages in the first screen update cycle, and N2+M2+P2 represents the total number of stages in the second screen update cycle. When N1+M1+P1 < N2+M2+P2, it indicates that the total number of stages in the second screen update cycle is larger. Clearly, when the first and second screen update cycles include the same number of data compensation stages, the data compensation stages in the first screen update cycle have a higher time proportion. From the perspective of compensation time proportion alone, the degree of data compensation in the first screen update cycle is higher than that in the second screen update cycle. To ensure that each screen update cycle in the same display panel performs the same degree of brightness compensation, making the brightness compensation more uniform, the number of data compensation stages N2 in the second screen update cycle can be set to be greater than the number of data compensation stages N1 in the first screen update cycle. Furthermore, in the actual screen update process of the display panel, the number of data compensation stages in the first and second screen update cycles can be set to satisfy N1 / (N1+M1+P1) = N1 / (N2+M2+P2).

[0110] Optional, P1 = P2 = 1.

[0111] Further research by the inventors revealed that different colored pixel units, due to their varying luminous efficiency, require different driving currents for the same target brightness during actual display driving, meaning the required data voltage for writing also differs. Based on this, in another embodiment of the invention, the display panel includes a first color pixel unit and a second color pixel unit, and under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit is lower than the theoretical data voltage corresponding to the second color pixel unit.

[0112] Optionally, the voltage difference of the compensation data corresponding to two adjacent data compensation stages of the first color pixel unit can be set to be greater than the voltage difference of the compensation data corresponding to two adjacent data compensation stages of the second color pixel unit.

[0113] Alternatively, the compensation data voltage corresponding to the initial data compensation stage of the first color pixel is less than the compensation data voltage corresponding to the initial data compensation stage of the second color pixel.

[0114] Alternatively, the number of data compensation stages for the first color pixel is greater than the number of data compensation stages for the second color pixel.

[0115] It is understood that in a display panel, the luminous efficiency of a first color pixel unit is lower than that of a second color pixel unit. For example, the first color pixel unit could be a blue pixel unit, and the second color pixel unit could be a red or green pixel unit. At the same target brightness, the driving current of the blue pixel unit needs to be higher than that of the red or green pixel unit. Therefore, it is understood that the initial compensation data voltage of the blue pixel unit should be smaller; a smaller initial compensation data voltage corresponds to a higher theoretical brightness, thereby enabling the blue pixel unit to reach the target brightness more quickly.

[0116] On the other hand, it can be understood that the current change of the blue pixel unit is relatively large. In order to stimulate the threshold voltage of the blue pixel unit driving transistor to stabilize quickly, the difference in the compensation data voltage of the blue pixel unit can be increased to match the current change trend of the blue pixel unit. This allows the brightness of the blue pixel unit to change rapidly, synchronously reaching the same target brightness as pixel units of other colors. Based on this, optionally, the decreasing rate of the compensation data voltage difference between two adjacent data compensation stages of the first color pixel unit can be set to be greater than the decreasing rate of the compensation data voltage difference between two adjacent data compensation stages of the second color unit, so that the changing trend of the compensation data voltage of the blue pixel unit is steeper.

[0117] On the other hand, the data compensation stage can be understood as primarily responsible for providing a compensation data voltage lower than the target data voltage, i.e., a higher theoretical brightness, thereby improving the hysteresis of the driving transistor threshold voltage. Therefore, for blue pixel units, setting more data compensation stages can result in a better improvement in the hysteresis reduction of the driving transistor threshold voltage for blue pixel units, leading to faster stabilization of the driving transistor threshold voltage for blue pixel units. Optionally, when the sum of the data sequence of other stages before the blue pixel data writing stage equals the sum of the data sequence of other frames before the second color pixel data writing stage, the number of data compensation frames for the blue pixel unit can be set to be more than the number of data compensation stages for the second color pixel.

[0118] In some optional embodiments of this application, the similarities with the above embodiments will not be repeated. The difference lies in the following: to simplify the data compensation algorithm for different color pixel units, the compensation data voltage written during the data compensation stage is quantitatively calculated. This embodiment of the invention also sets up an arithmetic sequence relationship to quantify the magnitude relationship of the compensation data voltage written by different color pixel units in multiple data compensation stages. Specifically, during the data compensation stage, the compensation data voltages written by the first color pixel unit and the second color pixel unit in multiple data compensation stages are both in the form of an arithmetic sequence, specifically the first arithmetic sequence and the second arithmetic sequence, respectively. The common difference of the first arithmetic sequence is d1, the number of terms is N1, and the first term is a1; the common difference of the second arithmetic sequence is d2, the number of terms is N2, and the first term is a2. Furthermore, the first and second arithmetic sequences can be configured to satisfy: a1 = a2, d1 = d2, N1 < N2; or, a1 = a2, d1 < d2, N1 = N2; or, a1 < a2, d1 = d2, N1 = N2.

[0119] Understandably, because the theoretical brightness during the data compensation stage is greater than the target brightness, the compensated data voltage is less than the target data voltage. Therefore, the first and second arithmetic sequences corresponding to the first and second color pixel units are essentially increasing arithmetic sequences. Moreover, since the theoretical data voltage of the first color pixel unit will be less than the theoretical data voltage of the second color pixel unit under the same target brightness, the last term of the first arithmetic sequence is less than the last term of the second arithmetic sequence.

[0120] Based on this, to ensure that the compensation data voltages in the two arithmetic sequences synchronously reach the compensation data voltage of the last term, thus guaranteeing the uniformity of brightness on the display panel, the first term and tolerance can be set to be equal, i.e., a1 = a2, d1 = d2. The number of terms in the first arithmetic sequence can be set to be less than the number of terms in the second arithmetic sequence, i.e., N1 < N2. In other words, when other conditions are equal, the number of data compensation stages N1 for the first color pixel can be set to be less than the number of data compensation stages N2 for the second color pixel. That is, in terms of the number of compensation stages, the data compensation degree of the first color pixel unit is lower. Since the target data voltage of the first color pixel unit is lower than that of the second color pixel unit, the first color pixel unit does not need much data compensation, while the second color pixel unit needs more. At this time, the first and second color pixel units can also synchronously reach the corresponding target data voltage and obtain the same target brightness.

[0121] Of course, in this embodiment, the first term and the number of terms can also be set to be equal, i.e., a1 = a2, N1 = N2, and the common difference of the first arithmetic sequence can be set to be less than the common difference of the second arithmetic sequence, i.e., d1 < d2. In other words, when other conditions are equal, the compensation data voltage difference d1 between two adjacent data compensation stages of the first color pixel unit can be set to be less than the compensation data voltage difference d2 between two adjacent data compensation stages of the second color pixel unit. That is, for the first color pixel unit, the compensation data voltage in its data compensation stage can increase faster. Since the target data voltage of the first color pixel unit is lower than that of the second color pixel unit, it can be ensured that the first color pixel unit and the second color pixel unit reach the corresponding target data voltage synchronously and obtain the same target brightness synchronously.

[0122] Similarly, in this embodiment, the tolerance and number of terms can be set to be equal, i.e., d1 = d2, N1 = N2, and the first term of the first arithmetic sequence can be set to be less than the first term of the second arithmetic sequence, i.e., a1 < a2. In other words, when other conditions are equal, the compensation data voltage a1 corresponding to the initial data compensation stage of the first color pixel can be set to be less than the compensation data voltage a2 corresponding to the initial data compensation stage of the second color pixel. That is, for the first color pixel unit, its initial compensation data voltage value in the data compensation stage is smaller. Since the target data voltage of the first color pixel unit is lower than the target data voltage of the second color pixel unit, setting the initial compensation data voltage value to be smaller can ensure that the first color pixel unit and the second color pixel unit reach the corresponding target data voltage synchronously and obtain the same target brightness synchronously.

[0123] It should be noted that using an arithmetic sequence to quantify the magnitude relationship of the compensation data voltages for different color pixel units presupposes that the compensation data voltages are set as an arithmetic sequence, and that specific conditions remain consistent within this arithmetic sequence. Only when these specific conditions remain the same can specific parameters within the arithmetic sequence of compensation data voltages for different color pixel units exhibit a certain magnitude relationship. It is understood that in other embodiments of the present invention, the compensation data voltages for different color pixel units may also satisfy other magnitude relationships, thereby adaptively adjusting and compensating for the hysteresis effect of the driving transistors of the corresponding color pixel units, ensuring the stability of the driving transistors and the uniformity of the display. This will not be elaborated upon further here.

[0124] Based on the same inventive concept, embodiments of the present invention also provide a display device. (Continue to refer to...) Figure 2The display device includes: a display panel 100, which includes a plurality of pixel units 110, and the display panel 100 includes a plurality of screen update cycles, at least one of which includes a data writing phase, a data compensation phase, and a data holding phase; the data compensation phase is located before the data writing phase; a scan driving unit 200, which provides a gate scan signal to each pixel unit respectively during the data writing phase and the data compensation phase; a data writing unit 300, which provides a gate scan signal to the pixel unit and writes a target data voltage during the data writing phase, the target data voltage being the theoretical data voltage corresponding to the target brightness of the current screen update cycle; and is also used to provide a gate scan signal to the pixel unit and write a compensation data voltage during the data compensation phase, the compensation data voltage being less than the target data voltage.

[0125] The display device is not limited to mobile phones, tablets, and wearable products; it can also be computers, televisions, advertising screens, etc., without limitation. During the display driving process, the display panel 100 generally needs to update the image to present a continuous display. Multiple image update cycles can be set during the display driving process, with each cycle corresponding to displaying an image of a certain brightness. In the display device of this embodiment, at least one image update cycle includes a data writing stage, a data compensation stage, and a data holding stage. The data compensation stage is essentially the process of writing compensation data voltage to the pixel unit. After writing the compensation data voltage, the pixel unit is driven to display. However, the brightness of the pixel unit or display panel is affected by the hysteresis effect of the driving transistor in the pixel driving circuit. In this case, the brightness of the pixel unit or display panel is not actually consistent with the brightness theoretically corresponding to the compensation data voltage. Those skilled in the art will understand that for OLED display panels, the brightness of the pixel unit is positively correlated with the current flowing through the driving transistor in the pixel driving circuit, while the current flowing through the driving transistor is inversely proportional to the data voltage written to the pixel unit. Based on this, in this embodiment of the invention, during the data compensation stage, the written compensation data voltage is set to be less than the target data voltage. Theoretically, the brightness of the pixel unit or display panel will be greater than the target brightness of the current screen update cycle. Furthermore, although the driving transistors of the pixel driving circuit also exhibit hysteresis, writing a data voltage according to the higher screen brightness can improve the actual brightness of the display panel. In other words, during this data compensation stage, a higher screen brightness can be achieved by writing a smaller compensation data voltage. Moreover, since the screen brightness is higher during the compensation stage, it is closer to the target brightness, and the time to reach the target brightness can be shortened to some extent. Therefore, during this screen update cycle, the difference in brightness change is relatively small before reaching the target brightness, the brightness buffer time is shortened, and the target brightness can be reached more quickly, ensuring the display effect of the screen.

[0126] The data writing phase refers to the process of writing the theoretical data voltage corresponding to the target brightness of the current screen update cycle into the pixel unit. Since the data writing phase must be set after the data compensation phase, the electrical performance of the driving transistors in the pixel driving circuit tends to stabilize through the data compensation process, and the threshold reaches the theoretical value. At this point, the data writing phase can realize the normal driving of the pixel driving circuit, and the pixel unit or display panel displays at the target brightness. The data holding phase essentially displays using the target data voltage written in the data writing phase, or it can also display using the compensation data voltage written in the data compensation phase. Therefore, this data holding phase should be set after the data writing or data compensation phase. The data voltage written in the data writing or data compensation phase can be stored in the capacitor of the pixel driving circuit, and there is no need to rewrite the data voltage in this data holding phase. During the pixel unit refresh display process, it is only necessary to provide a light emission control signal to turn on and drive the pixel unit, so that the display panel can maintain the image.

[0127] The display device provided in this invention includes a display panel, a scanning driving unit, and a data writing unit. The display panel includes multiple pixel units, and the display driving process of the display panel includes multiple screen update cycles. At least one screen update cycle includes a data writing stage, a data holding stage, and a data compensation stage; and the data compensation stage is located before the data writing stage. The scanning driving unit provides a gate scanning signal to each pixel unit during the data writing and data compensation stages. The data writing unit provides a gate scanning signal to the pixel unit and writes a target data voltage during the data writing stage. The target data voltage is the theoretical data voltage corresponding to the target brightness of the current screen update cycle. It also provides a gate scanning signal to the pixel unit and writes a compensation data voltage during the data compensation stage. The compensation data voltage is less than the target data voltage. This enables the display panel to perform a data compensation process in at least one screen update cycle, thereby improving the display brightness of the display panel during the data compensation process. This invention can solve the problem of screen flicker caused by the hysteresis effect of transistors, compensate for the defects of unstable transistor electrical performance, ensure that the screen reaches the target brightness of the current screen update cycle as quickly as possible during switching, reduce the screen brightness difference within the same screen update cycle, and thus improve the screen display quality and effect.

[0128] The display device provided above includes a plurality of pixel driving circuits corresponding one-to-one with each pixel unit in its display panel. The driving process of the display panel is essentially the process of driving each pixel driving circuit. Embodiments of the present invention also provide various pixel driving circuits. In the above-described display panel and its driving method, the specific process for the same frame update cycle can include a data compensation stage, a data writing stage, and a data holding stage, which will be described in detail below. First, each data compensation stage, data writing stage, and data holding stage in the same frame update cycle is actually equivalent to the driving process of one frame of the display panel. In the corresponding frame driving process, for each pixel unit and pixel driving circuit on the display panel, the driving process of that frame includes multiple driving periods. Figure 11 This is a timing diagram of the data compensation stage provided in an embodiment of the present invention. Figure 12 This is a timing diagram of the data writing stage provided in an embodiment of the present invention. Figure 13 This is a timing diagram of the data retention phase provided in an embodiment of the present invention, for reference. Figures 11-13 Specifically, the data compensation phase includes at least a compensation data voltage writing period b1 and an emission period c; the data writing phase includes at least a target data voltage writing period b2 and an emission period c; and the data retention phase includes at least an emission period c.

[0129] The following explanation will use the data writing stage as an example to illustrate the target data voltage writing period and the emission period. (Continue reading...) Figure 3 The pixel driving circuit includes: a driving transistor T, a data writing module 20, an emissive control module (51 and 52), and a threshold compensation module 30; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor is connected to the second node N2, and the second terminal T2 of the driving transistor is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2; the threshold compensation module 30 is electrically connected between the first node N1 and the third node N3; the data writing module 20 is used to provide the data signal input from the data signal terminal Vdata to the driving transistor T; the threshold compensation module 30 is used to compensate the threshold voltage Vth of the driving transistor T to the first node N1; the emissive control module (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light-emitting element 60, and the emissive control module (51 and 52) is used to control whether the driving current flows through the light-emitting element 60.

[0130] Specifically, the pixel driving circuit further includes an initialization module 10, a reset module 70, and a storage capacitor Cst. The initialization module 10 is electrically connected between the initialization signal terminal Vref and the first node N1. The initialization module 10 is used to provide an initialization signal of the initialization signal terminal Vref to the first node N1 during the initialization phase. The reset module 70 is electrically connected between the first scan signal terminal S1 and the anode of the light-emitting element 60. The reset module 70 is used to provide a reset signal to the anode of the light-emitting element 60 during the reset phase. The gate G of the driving transistor T and the first plate a of the storage capacitor Cst are electrically connected to the first node N1. The second plate b of the storage capacitor Cst is electrically connected to the power supply signal terminal PVDD.

[0131] The following is for reference. Figure 3 and Figure 12 The specific driving timing of this pixel driving circuit is described below:

[0132] During initialization phase a, initialization module 10 is turned on and provides an initialization signal to the first node N1 at the initialization signal terminal Vref, so as to initialize the signal stored in the storage capacitor Cst and the gate G of the driving transistor T. This phase is actually a process of resetting the storage capacitor Cst and the gate G of the driving transistor T, which is used to eliminate the data voltage signal present in the storage capacitor Cst and the gate G of the driving transistor T when the previous frame was displayed. Thus, in each driving process of each light-emitting element 60, it is reset before driving light, ensuring the uniformity of the light emission control of each light-emitting element 60 and ensuring the uniformity of the light emission brightness.

[0133] During the target data voltage writing period b2, both the data writing module 20 and the threshold compensation module 30 are turned on. The data voltage signal at the data signal terminal Vdata is sequentially written to the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30. This causes the gate voltage of the driving transistor T to gradually increase until the voltage difference between the gate voltage of the driving transistor T and the voltage at the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, at which point the driving transistor T is turned off.

[0134] In this process, the data voltage signal Vdata at the data signal terminal, under the control of the data writing module 20, charges the first plate a of the storage capacitor Cst through the driving transistor T, ensuring that the first node N1 reaches a preset potential value that has been compensated for by a threshold. At this time, the voltage V1 of the first node N1 is Vd = |Vth|, where Vd is the data voltage at the data signal terminal and Vth is the threshold voltage of the driving transistor.

[0135] During the light-emitting period c, the light-emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light-emitting element 60, which emits light in response to the driving current.

[0136] The light-emitting control module may include a first light-emitting control module 51 and a second light-emitting control module 52. The first light-emitting control module 51 is electrically connected between the power signal terminal and the first terminal T1 of the driving transistor T. The second light-emitting control module 52 is electrically connected between the second terminal T2 of the driving transistor T and the first terminal of the light-emitting element 60. The second terminal of the light-emitting element 60 may be electrically connected to the low-level signal terminal PVEE so that when the first light-emitting control module 51 and the second light-emitting control module 52 are turned on during the light-emitting period, a current loop can be formed to drive the light-emitting element 60 to emit light.

[0137] It should be noted that the embodiments of the present invention do not specifically limit the specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module. Provided that the threshold voltage compensation function of the driving transistor can be achieved, each module of the pixel driving circuit can be designed according to actual needs. For ease of understanding, the specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module in the embodiments of the present invention are illustrated below. The initialization module 10 may include a first transistor M1, the gate of which is electrically connected to the first scan signal terminal S1. During initialization period a, the first scan signal controls the first transistor M1 to be turned on, at which time the initialization signal terminal Vref initializes the potential of the first node N1 through the first transistor M1; during non-initialization period, the first scan signal controls the first transistor M1 to be turned off. The data writing module 20 includes a second transistor M2, and the threshold compensation module 30 includes a third transistor M3. The gates of both the second transistor M2 and the third transistor M3 are electrically connected to the second scan signal terminal S2. During the target data voltage writing period b2, the second scan signal S2 controls the second transistor M2 and the third transistor M3 to turn on. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30. During the non-data writing period, the second scan signal S2 controls the second transistor M2 and the third transistor M3 to turn off. In the light emission control module, the first light emission control module 51 may include a fourth transistor M4, and the second light emission control module 52 may include a fifth transistor M5. The gates of the fourth transistor M4 and the fifth transistor M5 are both electrically connected to the light emission control signal terminal Emit. During the light emission period, the light emission control signal controls the fourth transistor M4 and the fifth transistor M5 to turn on. At this time, the power supply signal terminal PVDD, the fourth transistor M4, the driving transistor T, the fifth transistor M5, and the light emission element 60 form a conduction channel. The driving transistor T generates a driving current to drive the light emission element 60 to emit light. During the non-light emission period, the light emission control signal controls the fourth transistor M4 and the fifth transistor M5 to turn off. It should be noted that the transistors and driving transistors in the above modules can be N-type transistors or P-type transistors, and the embodiments of the present invention do not impose any restrictions.

[0138] The pixel driving circuit described above is essentially a 7T1C pixel driving circuit, and its driving process essentially includes an initialization period (a), a data writing period (b), and an emission period (c). It can be understood that in the data writing stage, data compensation stage, and data holding stage of this embodiment of the invention, the switching on and off of each stage can be achieved by changing the data voltage value input to the data signal terminal. Specifically, refer to... Figure 11 and Figure 12By adjusting the data signal from the target data voltage to the compensation data voltage, the data writing period b can be adjusted to the compensation data voltage writing period b1 during the data compensation phase. Simultaneously, refer to... Figure 13 By controlling the relevant control signals, the initialization module 10, the data writing module 20 and the threshold compensation module 30 can all be turned off, while the light emission control modules (51 and 52) are turned on. This enables the initialization period a and the data writing period b to be turned off during the data holding phase, while the light emission element 60 is driven to emit light under the control of the light emission control signal Emit, thus entering the light emission period c.

[0139] It should be noted that, in the embodiments of the present invention, the gate potential of the driving transistor T can be initialized by the initialization module 10 during the data holding stage, or the gate potential of the driving transistor T can be left uninitialized, so that the gate of the driving transistor T holds the data voltage stored in the previous stage, such as the data writing stage, and the light-emitting element 60 is driven to emit light with the data voltage.

[0140] This invention provides another implementation for a pixel driving circuit in a display panel. In this alternative pixel driving circuit, a bias adjustment module is further included. The driving transistor in the pixel driving circuit exhibits threshold drift, which affects the overall characteristics of the driving transistor and consequently the uniformity of the display. To address this, the bias adjustment module added in this invention biases the driving transistor, thereby reducing threshold drift and restoring the threshold to a normal level. This ensures normal driving of the pixel driving circuit, allowing the pixel units and the display panel to display according to the target brightness, thus guaranteeing display quality. Specifically, the pixel driving circuit includes: a driving transistor, a data writing module, a light emission control module, a threshold compensation module, and a bias adjustment module.

[0141] The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node; the data writing module is electrically connected between the data signal terminal and the second node, and the data writing module is used to provide the data signal input to the data signal terminal of the driving transistor; the light emission control module and the driving transistor are electrically connected between the power supply signal terminal and the light emission element, and the light emission control module is used to control whether the driving current flows through the light emission element.

[0142] The threshold compensation module is electrically connected between the first node and the third node; the threshold compensation module is used to detect and self-compensate the deviation of the threshold voltage of the driving transistor; the bias adjustment module is electrically connected between the threshold bias adjustment signal terminal and the second node or between the threshold bias adjustment signal terminal and the third node; the control terminal of the bias adjustment module is connected to the first control signal terminal, and the bias adjustment module is used to control the voltage bias of the driving transistor under the control of the first control signal input at the first control signal terminal and the threshold bias adjustment signal input at the threshold bias adjustment signal terminal.

[0143] Furthermore, the pixel driving circuit also includes an initialization module, which is electrically connected between the initialization signal terminal and the first node; the initialization module is used to provide the initialization signal input to the initialization signal terminal to the first node.

[0144] It is understood that in this embodiment of the invention, by setting a bias adjustment module in the pixel driving circuit and cooperating with setting a data compensation stage in the screen update cycle, the bias signal provided by the bias adjustment module can be used to reverse conduct the driving transistor, thereby reducing the drift of the threshold voltage of the driving transistor during forward conduction, making the threshold voltage of the driving transistor more stable, and ensuring the driving accuracy of the driving transistor. At the same time, by using the data compensation stage to increase the theoretical brightness of the pixel unit, it can be ensured that the screen reaches the target brightness of the current screen update cycle as soon as possible when switching, making the driving circuit of the pixel driving circuit more accurate in driving the brightness of the light-emitting element. That is, this embodiment of the invention can avoid brightness distortion caused by the hysteresis effect and threshold offset of the driving transistor, ensuring the accuracy and uniformity of the screen display on the display panel, and improving the screen display effect. Furthermore, by setting a period for the bias adjustment module to work in the data compensation stage in this embodiment, the work of the data compensation stage can be assisted, especially when a screen update cycle includes multiple data compensation stages with different compensation data voltages, it can avoid the impact of different data compensation voltages on the driving transistor.

[0145] The following is a detailed description of several pixel driving circuits including bias adjustment modules provided in the embodiments of the present invention. Figure 14 This is a schematic diagram of the structure of a display panel pixel driving circuit provided in an embodiment of the present invention. Figure 15 This is a timing diagram of another data writing stage provided in an embodiment of the present invention. First, refer to... Figure 14The pixel driving circuit includes: a driving transistor T, a data writing module 20, an emissive control module (51 and 52), a threshold compensation module 30, and a bias adjustment module 40; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor T is connected to the second node N2, and the second terminal T2 of the driving transistor T is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2, and the data writing module 20 is used to provide the data signal input from the data signal terminal Vdata to the driving transistor T;

[0146] The light-emitting control modules (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light-emitting element 60. The light-emitting control modules (51 and 52) are used to control whether the driving current flows through the light-emitting element 60. The threshold compensation module 30 is electrically connected between the first node N1 and the third node N3. The threshold compensation module 30 is used to detect and self-compensate the deviation of the threshold voltage Vth of the driving transistor T.

[0147] The bias adjustment module 40 is electrically connected between the threshold bias adjustment signal terminal Vobs and the third node N3; the control terminal of the bias adjustment module 40 is connected to the first control signal terminal s1-p. The bias adjustment module 40 is used to control the voltage bias of the driving transistor T under the control of the first control signal input at the first control signal terminal s1-p and the threshold bias adjustment signal input at the threshold bias adjustment signal terminal Vobs.

[0148] Optionally, in such Figure 14 In the pixel driving circuit shown, in order to simplify its pixel driving circuit structure and improve the area utilization of the array substrate in the display panel, the driving transistor T can be set to a P-type transistor; and the threshold compensation module 30 and the bias adjustment module 40 are multiplexed as an initialization module for resetting the first node N1.

[0149] For the pixel driving circuit described above, its data writing stage and data compensation stage further include a first threshold bias period and / or a second threshold bias period; in the data writing stage, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light emission period; in the data compensation stage, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light emission period.

[0150] The following section also uses the data writing phase as an example to introduce the specific driver timing. (Refer to...) Figure 15 The details are as follows:

[0151] During the first threshold bias period d1, the bias adjustment module 40 is turned on, and the bias adjustment signal terminal Vobs inputs the threshold bias adjustment signal Vobs to the third node N3. By properly setting the signal value of Vobs to the third node N3, and based on the Vdata+Vth held by the first node N1 in the previous frame, Vdata+Vth < Vobs can be made, thus turning on the driving transistor T and writing the Vobs signal to the second node N2, making the potential of the second node N2 lower than the potential of the first node N1. In another scenario, the driving transistor T can be understood as essentially a capacitor. Writing the threshold bias adjustment signal Vobs to the third node N3 can adaptively adjust the potential of the second node N2, making the potential of the second node N2 lower than the potential of the first node N1. For the driving transistor, its voltage at the first node N1 is lower than the voltage at the second node N2, thus enabling the driving transistor T to conduct in reverse, i.e., achieving reverse bias. At this time, the threshold voltage drift of the driving transistor T is reduced, thereby ensuring normal light emission in subsequent light emission periods.

[0152] During initialization period a, the threshold compensation module 30 and the bias adjustment module 40 are multiplexed as the initialization module. At this time, both the threshold compensation module 30 and the bias adjustment module 40 are turned on. The bias adjustment signal terminal Vobs is multiplexed as the initialization signal terminal Vini, and the initialization signal is written to the first node N1. At this time, Vobs / Vini is a low level signal.

[0153] During the target data voltage writing period b2, both the data writing module 20 and the threshold compensation module 30 are turned on. The data voltage signal at the data signal terminal Vdata is sequentially written to the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30. This causes the gate voltage of the driving transistor T to gradually increase until the voltage difference between the gate voltage of the driving transistor T and the voltage at the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, at which point the driving transistor T is turned off.

[0154] During the second threshold bias period d2, the bias adjustment module 40 is also turned on, and the bias adjustment signal terminal Vobs inputs the threshold bias adjustment signal Vobs to the third node N3. By properly setting the signal value of Vobs, the voltage of the third node N3 can be made greater than the voltage of the first node N1, thus turning on the driving transistor T and writing the Vobs signal to the second node N2, making the potential of the second node N2 lower than the potential of the first node N1. In another scenario, the driving transistor T can be understood as essentially a capacitor. Writing the threshold bias adjustment signal Vobs to the third node N3 can adaptively adjust the potential of the second node N2, making the potential of the second node N2 lower than the potential of the first node N1. At this time, for the driving transistor, the potential of the first node N1 is less than the potential of the second node N2, thus causing the driving transistor T to conduct in reverse phase, that is, to achieve reverse bias, thereby reducing the threshold voltage drift of the driving transistor T and ensuring normal light emission in subsequent light emission periods.

[0155] During the light-emitting period c, the light-emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light-emitting element 60, which emits light in response to the driving current.

[0156] It should be noted that the embodiments of the present invention do not specifically limit the structure of the initialization module, data writing module, threshold compensation module, and light emission control module. Provided that the threshold voltage compensation function of the driving transistor can be achieved, each module of the pixel driving circuit can be designed according to actual needs. For ease of understanding, the specific structures of the initialization module, data writing module, threshold compensation module, bias adjustment module, and light emission control module in the embodiments of the present invention are illustrated below. Specifically, the bias adjustment module 40 may include a fifth transistor M5. The gate of the fifth transistor M5 is electrically connected to the second scan signal terminal s2-p1. During the first threshold bias period d1 and the second threshold bias period d2, the second scan signal terminal s2-p1 controls the bias adjustment module 40 to conduct. At this time, the threshold bias adjustment signal Vobs is input to the second node N3, making the potential of the first node N1 lower than the potential of the second node N2, thereby achieving the inverse conduction of the driving transistor M3. The threshold compensation module 30 and the bias adjustment module 40 are multiplexed as an initialization module. The threshold compensation module 30 can be configured as a fourth transistor M4, specifically an N-type transistor. The gate of the fourth transistor M4 is electrically connected to the third scan signal terminal sn. During initialization period a, the second scan signal terminal s2-p1 and the third scan signal terminal sn respectively control the bias adjustment module 40 and the threshold compensation module 30 to conduct, thereby writing a low-level initialization signal Vini to the first node N1. The data writing module 20 includes a second transistor M2, the gate of which is electrically connected to the first scan signal terminal s1-p. During the target data voltage writing period b2, the first scan signal s1-p controls the second transistor M2 to conduct, and the third scan signal sn controls the fourth transistor M4 to conduct. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30. The light-emitting control module may include a first transistor M1 and a sixth transistor M6, the gates of which are electrically connected to the light-emitting control signal terminal Emit. During the light-emitting period c, the light-emitting control signal Emit controls the first transistor M1 and the sixth transistor M6 to conduct. At this time, the power supply signal terminal PVDD, the first transistor M1, the driving transistor T, the sixth transistor M6, and the light-emitting element 60 form a conduction channel. The driving transistor T generates a driving current to drive the light-emitting element 60 to emit light.

[0157] Similarly, as above Figure 14The provided pixel driving circuit's driving process essentially includes an initialization period a, a data writing period b, and an emission period c. It is understood that in the data writing, data compensation, and data holding stages of this embodiment, the data voltage value input to the data signal terminal can be changed to adjust the data writing period b to the compensation data voltage writing period b1 during the data compensation stage. Simultaneously, by controlling related control signals, both the data writing module 20 and the threshold compensation module 30 are turned off, while the emission control modules (51 and 52) are turned on. This allows the initialization period a and the data writing period b to be turned off during the data holding stage, while the image is displayed using the emission period c throughout the entire data holding stage. Furthermore, in addition to setting the first threshold bias period d1 and the second threshold bias period d2 in the data writing stage, the same first threshold bias period d1 and the second threshold bias period d2 can also be set in the data compensation stage; no limitation is imposed here.

[0158] Figure 16 This is a schematic diagram of the structure of a display panel pixel driving circuit provided in an embodiment of the present invention. Figure 17 This is a timing diagram of another data writing stage provided in an embodiment of the present invention, referred to... Figure 16 The pixel driving circuit includes: a driving transistor T, a data writing module 20, an emissive control module (51 and 52), a threshold compensation module 30, and a bias adjustment module 40; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor T is connected to the second node N2, and the second terminal T2 of the driving transistor T is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2, and the data writing module 20 is used to provide the data signal input from the data signal terminal Vdata to the driving transistor T;

[0159] The light-emitting control modules (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light-emitting element 60. The light-emitting control modules (51 and 52) are used to control whether the driving current flows through the light-emitting element 60. The threshold compensation module 30 is electrically connected between the first node N1 and the third node N3. The threshold compensation module 30 is used to detect and self-compensate the deviation of the threshold voltage Vth of the driving transistor T.

[0160] The bias adjustment module 40 is electrically connected between the threshold bias adjustment signal terminal Vobs and the third node N3; the control terminal of the bias adjustment module 40 is connected to the second control signal terminal s2-p1. The bias adjustment module 40 is used to control the voltage bias of the driving transistor T under the control of the second control signal input at the second control signal terminal s2-p1 and the threshold bias adjustment signal input at the threshold bias adjustment signal terminal Vobs.

[0161] Alternatively, the driving transistor T can be set to an N-type transistor; and the threshold compensation module 30 and the bias adjustment module 40 can be reused as an initialization module for resetting the first node N1.

[0162] Furthermore, the NMOS driving transistor can be configured as a dual-gate transistor. This dual-gate transistor includes a first gate and a second gate. The first gate serves as the control terminal of the driving transistor, used to receive data signals, while the second gate connects to the threshold voltage feedback unit. Specifically, the first gate can be the bottom gate of the dual-gate transistor, and the second gate can be the top gate. By using multiple gate structures, the cutoff current of the driving transistor can be reduced, and the transistor's withstand voltage can be increased to improve reliability. Alternatively, even when the transistor operates in the saturation region, the drain-source voltage fluctuates, but the drain-source current does not fluctuate significantly, thus enabling the driving transistor to achieve flat characteristics. Furthermore, by connecting the second gate to the threshold voltage feedback unit, the threshold voltage feedback information provided by the unit can be used to adjust the operating state of the driving transistor and compensate for threshold voltage drift caused by transistor aging. Simultaneously, the threshold voltage feedback unit can also compensate for differences in the mobility of the driving transistor, solving the problem of uneven light emission brightness of the light-emitting element caused by threshold voltage drift and mobility differences, further improving the uniformity of the display panel.

[0163] For example Figure 16 The pixel driving circuit shown can also be configured to include a first threshold bias period and / or a second threshold bias period in its data writing phase and data compensation phase. In the data writing phase, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light emission period. In the data compensation phase, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light emission period.

[0164] The following section also uses the data writing phase as an example to introduce the specific driver timing. (Refer to...) Figure 17 The details are as follows:

[0165] During the first threshold bias period d1, the bias adjustment module 40 is turned on, and simultaneously, the bias adjustment signal terminal Vobs inputs the threshold bias adjustment signal Vobs to the third node N3. By properly setting the signal value of Vobs, the voltage of the third node N3 can be made less than the voltage of the first node N1, thereby enabling the driving transistor T to conduct in reverse, i.e., achieving reverse bias. It should be noted that during the light emission period of the previous frame, the storage capacitor Cst holds the Vdata signal, and the potential of the first node N1 is Vdata + Vth. By properly setting Vobs < Vdata + Vth, the driving transistor T can be turned on in reverse. At this time, the threshold voltage drift of the driving transistor T is reduced, thus ensuring normal light emission in subsequent light emission periods.

[0166] During initialization period a, the threshold compensation module 30 and the bias adjustment module 40 are multiplexed as the initialization module. At this time, both the threshold compensation module 30 and the bias adjustment module 40 are turned on. The bias adjustment signal terminal Vobs is multiplexed as the initialization signal terminal Vini, and the initialization signal is written to the first node N1. At this time, Vobs / Vini is a high-level signal.

[0167] During the target data voltage writing period b2, both the data writing module 20 and the threshold compensation module 30 are turned on. The data voltage signal at the data signal terminal Vdata is sequentially written to the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30. This causes the gate voltage of the driving transistor T to gradually increase until the voltage difference between the gate voltage of the driving transistor T and the voltage at the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, at which point the driving transistor T is turned off.

[0168] During the light-emitting period c, the light-emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light-emitting element 60, which emits light in response to the driving current.

[0169] For ease of understanding, similarly, here we will refer to... Figure 16The specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module in the pixel driving circuit are illustrated. The bias adjustment module 40 may include a seventh transistor M7, whose gate is electrically connected to the second scan signal terminal s2-p1. During the first threshold bias period d1, the second scan signal terminal s2-p1 controls the bias adjustment module 40 to conduct, at which time the threshold bias adjustment signal Vobs is input to the third node N3, thereby achieving the inverted conduction of the driving transistor M3. The threshold compensation module 30 and the bias adjustment module 40 are multiplexed as an initialization module. The threshold compensation module 30 may be configured as a fourth transistor M4, specifically an N-type transistor, whose gate is electrically connected to the third scan signal terminal sn. During the initialization period a, the second scan signal terminal s2-p and the third scan signal terminal sn respectively control the bias adjustment module 40 and the threshold compensation module 30 to conduct, thereby writing a high-level initialization signal Vini to the first node N1. The data writing module 20 includes a second transistor M2, whose gate is electrically connected to the first scan signal terminal s1-p. During the target data voltage writing period b2, the first scan signal s1-p controls the second transistor M2 to turn on, and the third scan signal sn controls the fourth transistor M4 to turn on. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30. The light emission control module may include a first transistor M1 and a fifth transistor M5, whose gates are both electrically connected to the light emission control signal terminal Emit. During the light emission period c, the light emission control signal Emit controls the first transistor M1 and the fifth transistor M5 to turn on. At this time, the power supply signal terminal PVDD, the first transistor M1, the driving transistor T, the fifth transistor M5, and the light emission element 60 form a conduction channel. The driving transistor T generates a driving current to drive the light emission element 60 to emit light.

[0170] Similarly, as above Figure 16The provided pixel driving circuit's driving process essentially includes an initialization period a, a data writing period b, and an emission period c. It is understood that in the data writing, data compensation, and data holding stages of this embodiment, the data voltage value input to the data signal terminal can be changed to adjust the data writing period b to the compensation data voltage writing period b1 during the data compensation stage. Simultaneously, by controlling related control signals, both the data writing module 20 and the threshold compensation module 30 are turned off, while the emission control modules (51 and 52) are turned on. This allows the initialization period a and the data writing period b to be turned off during the data holding stage, while the image is displayed using the emission period c throughout the entire data holding stage. Furthermore, in addition to setting the first threshold bias period d1 and the second threshold bias period d2 in the data writing stage, the same first threshold bias period d1 and the second threshold bias period d2 can also be set in the data compensation stage; no limitation is imposed here.

[0171] Figure 18 This is a schematic diagram of the structure of a display panel pixel driving circuit provided in an embodiment of the present invention. Figure 19 This is a timing diagram of another data writing stage provided in an embodiment of the present invention, referred to... Figure 18 The pixel driving circuit includes: a driving transistor T, a data writing module 20, an emissive control module (51 and 52), a threshold compensation module 30, and a bias adjustment module 40; the control terminal G of the driving transistor T is connected to the first node N1, the first terminal T1 of the driving transistor T is connected to the second node N2, and the second terminal T2 of the driving transistor T is connected to the third node N3; the data writing module 20 is electrically connected between the data signal terminal Vdata and the second node N2, and the data writing module 20 is used to provide the data signal input from the data signal terminal Vdata to the driving transistor T;

[0172] The light-emitting control modules (51 and 52) and the driving transistor T are electrically connected between the power signal terminal PVDD and the light-emitting element 60. The light-emitting control modules (51 and 52) are used to control whether the driving current flows through the light-emitting element 60. The threshold compensation module 30 is electrically connected between the first node N1 and the third node N3. The threshold compensation module 30 is used to detect and self-compensate the deviation of the threshold voltage Vth of the driving transistor T.

[0173] The bias adjustment module 40 is electrically connected between the threshold bias adjustment signal terminal Vobs and the second node N2; the control terminal of the bias adjustment module 40 is connected to the first control signal terminal s1-p. The bias adjustment module 40 is used to control the voltage bias of the driving transistor T under the control of the first control signal input at the first control signal terminal s1-p and the threshold bias adjustment signal input at the threshold bias adjustment signal terminal Vobs.

[0174] Optionally, the driving transistor T can be configured as an N-type transistor; the data writing module 20 can be multiplexed as the bias adjustment module 40, and the data signal terminal Vdata can be multiplexed as the threshold bias adjustment signal terminal Vobs; the data writing module 20 is also used to provide the threshold bias adjustment signal Vobs input from the data signal terminal Vdata to the second node N2. Furthermore, the first light-emitting control module 51 and the threshold compensation module 30 in the light-emitting control module can be multiplexed as an initialization module, and the power signal terminal PVDD can be multiplexed as the initialization signal terminal.

[0175] For the pixel driving circuit described above, its data writing stage and data compensation stage may also include a first threshold bias period and / or a second threshold bias period; in the data writing stage, the first threshold bias period is located before the target data voltage writing period, and the second threshold bias period is located between the target data voltage writing period and the light emission period; in the data compensation stage, the first threshold bias period is located before the compensation data voltage writing period, and the second threshold bias period is located between the compensation data voltage writing period and the light emission period.

[0176] The following section also uses the data writing phase as an example to introduce the specific driver timing. (Refer to...) Figure 19 The details are as follows:

[0177] During the first threshold bias period d1, the bias adjustment module 40 is turned on, and simultaneously, the bias adjustment signal terminal Vobs inputs the threshold bias adjustment signal Vobs to the second node N2. It should be noted that in this pixel driving circuit, the input threshold bias adjustment signal Vobs at this time is actually the data signal Vdata' written by the pixel driving circuit located before the current pixel driving circuit on the display panel. Clearly, by writing the data signal Vdata' to the second node N2, the voltage of the second node N2 is actually less than the voltage of the first node N1, driving the transistor T to turn on. The Vobs signal is then written to the third node N3, thus the voltage of the third node N3 is less than the voltage of the first node N1, driving the transistor to achieve inverted conduction, i.e., reverse bias. At this time, the threshold voltage drift of the driving transistor T is reduced, thereby ensuring normal light emission in subsequent light emission periods.

[0178] During initialization period a, the first light emission control module 51 and the threshold compensation module 30 are multiplexed as the initialization module, and the power signal terminal PVDD is multiplexed as the initialization signal terminal. At this time, the first light emission control module 51 and the threshold compensation module 30 are turned on, and the power signal terminal PVDD writes the initialization signal to the first node N1, that is, writes a high-level signal to the first node N1 to achieve initialization.

[0179] During the target data voltage writing period b2, both the data writing module 20 and the threshold compensation module 30 are turned on. The data voltage signal at the data signal terminal Vdata is sequentially written to the first node N1, i.e., the first plate a of the storage capacitor Cst and the gate G of the driving transistor T, through the data writing module 20, the driving transistor T and the threshold compensation module 30. This causes the gate voltage of the driving transistor T to gradually increase until the voltage difference between the gate voltage of the driving transistor T and the voltage at the first terminal T1 of the driving transistor T is equal to the threshold voltage of the driving transistor T, at which point the driving transistor T is turned off.

[0180] During the light-emitting period c, the light-emitting control modules (51 and 52) are turned on, and the driving current generated by the driving transistor T flows into the light-emitting element 60, which emits light in response to the driving current.

[0181] Similarly, for ease of understanding, the following is used here: Figure 18 The specific structures of the initialization module, data writing module, threshold compensation module, and light emission control module in the pixel driving circuit are illustrated. The data writing module 20 includes a second transistor M2, whose gate is electrically connected to the first scan signal terminal s1-p. The data writing module 20 is multiplexed as a bias adjustment module 40. During the first threshold bias period d1, the first scan signal terminal s1-p controls the bias adjustment module 40 to conduct. At this time, the threshold bias adjustment signal Vobs, i.e., Vdata', is input to the third node N3, thereby achieving the inverted conduction of the driving transistor M3.

[0182] The threshold compensation module 30 and the first light emission control module 51 in the light emission control module are multiplexed as an initialization module. The threshold compensation module 30 can be configured as a fourth transistor M4, specifically an N-type transistor, with its gate electrically connected to the third scan signal terminal sn. The first light emission control module 51 can specifically be a first transistor M1, with its gate electrically connected to the first light emission control signal Emit1. During initialization period a, the third scan signal terminal sn and the first light emission control signal Emit1 are turned on by the fourth transistor M4 and the first transistor M1, respectively, thereby writing a high-level initialization signal Vini (essentially PVDD) to the first node N1.

[0183] During the target data voltage writing period b2, the first scan signal s1-p controls the second transistor M2 to turn on, and the third scan signal sn controls the fourth transistor M4 to turn on. At this time, the data signal terminal Vdata writes the threshold-compensated data voltage signal to the first node N1 through the second transistor M2, the driving transistor T, and the threshold compensation module 30.

[0184] The second light-emitting control module 52 in the light-emitting control module may include a fifth transistor M5, the gate of which is electrically connected to the second light-emitting control signal terminal Emit2. During the light-emitting period c, the first light-emitting control signal Emit1 and the second light-emitting control signal Emit2 control the first transistor M1 and the fifth transistor M5 to be turned on. At this time, the power supply signal terminal PVDD, the first transistor M1, the driving transistor T, the fifth transistor M5, and the light-emitting element 60 form a conduction channel, and the driving transistor T generates a driving current to drive the light-emitting element 60 to emit light.

[0185] Similarly, as above Figure 18 The provided pixel driving circuit's driving process essentially includes an initialization period a, a data writing period b, and an emission period c. It is understood that in the data writing, data compensation, and data holding stages of this embodiment, the data voltage value input to the data signal terminal can be changed to adjust the data writing period b to the compensation data voltage writing period b1 during the data compensation stage. Simultaneously, by controlling related control signals, both the data writing module 20 and the threshold compensation module 30 are turned off, while the emission control modules (51 and 52) are turned on. This allows the initialization period a and the data writing period b to be turned off during the data holding stage, while the image is displayed using the emission period c throughout the entire data holding stage. Furthermore, in addition to setting the first threshold bias period d1 and the second threshold bias period d2 in the data writing stage, the same first threshold bias period d1 and the second threshold bias period d2 can also be set in the data compensation stage; no limitation is imposed here.

[0186] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A driving method for a display panel, characterized in that, It includes multiple screen update cycles, and at least one of the screen update cycles includes a data writing phase, a data holding phase, and a data compensation phase; At least one of the data compensation stages is located before at least one of the data writing stages; During the data compensation stage, a gate scan signal is provided to the pixel driving circuit and a compensation data voltage is written. During the data writing stage, a gate scan signal is provided to the pixel driving circuit and a target data voltage is written, wherein the compensation data voltage is less than the target data voltage; During the data holding phase, no data voltage is written to the pixel driving circuit.

2. The driving method for the display panel according to claim 1, characterized in that, The same screen update cycle includes multiple data compensation stages, including a first data compensation stage and a second data compensation stage, wherein the first data compensation stage precedes the second data compensation stage; and the compensation data voltage written in the second data compensation stage is greater than the compensation data voltage written in the first data compensation stage.

3. The driving method for the display panel according to claim 1, characterized in that, The same screen update cycle includes multiple data compensation stages, including a third data compensation stage and a fourth data compensation stage, wherein the third data compensation stage precedes the fourth data compensation stage; the compensation data voltage written in the fourth data compensation stage is equal to the compensation data voltage written in the third data compensation stage.

4. The driving method for a display panel according to claim 1, characterized in that, The plurality of screen update cycles include at least one first screen update cycle and at least one second screen update cycle; The brightness of the first frame update cycle is greater than the brightness of the previous frame update cycle. The first frame update cycle includes the data writing phase, the data holding phase, and the data compensation phase. The brightness of the second frame update cycle is less than or equal to the brightness of the previous frame update cycle, and the first frame update cycle includes the data writing phase and the data holding phase.

5. The driving method for a display panel according to claim 1, characterized in that, The same screen update cycle includes multiple data compensation stages; the compensation data voltages written for the multiple data compensation stages are in the form of an arithmetic sequence, a geometric sequence, or an exponential sequence.

6. The driving method for a display panel according to claim 1, characterized in that, The same screen update cycle includes N data compensation stages, M data holding stages, and P data writing stages; Where N / (N+M+P)≤1 / 6, and N, M and P are all integers greater than or equal to 1.

7. The driving method for a display panel according to claim 1, characterized in that, The same screen update cycle includes multiple data compensation stages. The difference between the compensation data voltage written in the a-th data compensation stage and the (a+1)-th data compensation stage is ΔX1; the difference between the compensation data voltage written in the b-th data compensation stage and the (b+1)-th data compensation stage is ΔX2. Where △X1>△X2, a and b are both positive integers greater than 0, and a+1≤b.

8. The driving method for a display panel according to claim 1, characterized in that, The data retention phase is an interval between the data compensation phase and the data writing phase in the same screen update cycle. And / or, the same screen update cycle includes multiple data compensation phases, with at least one data hold phase spaced between at least two of the data compensation phases.

9. The driving method for a display panel according to claim 8, characterized in that, The same number of data holding stages may be spaced between any two adjacent data compensation stages; or, the data compensation stage and the data writing stage may be spaced at least two times apart.

10. The driving method for a display panel according to claim 1, characterized in that, The target data voltage is the theoretical data voltage corresponding to the target brightness in the current frame update cycle.

11. The driving method for a display panel according to claim 1, characterized in that, The same screen update cycle includes N data compensation stages, M data holding stages, and P data writing stages; Where N, M, and P are all integers greater than or equal to 1; The interval between any two adjacent data compensation stages is n data holding stages, where 0 ≤ n ≤ M.

12. The driving method for a display panel according to claim 11, characterized in that, Between any two adjacent data compensation stages, there are M*a% / N data retention stages, where 30% ≤ a% ≤ 50%, and M*a% is an integer greater than or equal to 1, and M*a% / N is an integer greater than or equal to 1.

13. The driving method for a display panel according to claim 11, characterized in that, The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit. The driving transistor of the first pixel driving circuit is a silicon-based transistor, and the driving transistor of the second pixel driving circuit is an oxide semiconductor transistor. In the same frame update cycle, the proportion of data compensation stages in the first pixel driving circuit is different from the proportion of data compensation stages in the second pixel driving circuit.

14. The driving method for a display panel according to claim 11, characterized in that, The pixel driving circuit includes a driving transistor; The driving transistor includes an N-type silicon-based transistor, and the number of the data compensation stage, the data holding stage and the data writing stage satisfies: N / (N+M+P)≤1 / 6; Alternatively, the driving transistor may include a P-type silicon-based transistor, and the number of the data compensation stage, the data holding stage, and the data writing stage shall satisfy: N / (N+M+P)≤1 / 12.

15. The driving method for a display panel according to claim 11, characterized in that, The pixel driving circuit includes driving transistors; the driving transistors include N-type silicon-based transistors and P-type silicon-based transistors. The pixel driving circuit includes a third pixel driving circuit and a fourth pixel driving circuit. The third pixel driving circuit includes the N-type silicon transistor, and the fourth pixel driving circuit includes the P-type silicon transistor. In the same frame update cycle, the proportion of data compensation stages in the third pixel driving circuit is different from that in the fourth pixel driving circuit.

16. The driving method for a display panel according to claim 11, characterized in that, Any two adjacent screen update cycles include a first screen update cycle and a second screen update cycle; the first screen update cycle includes N1 data compensation stages, M1 data holding stages, and P1 data writing stages; the second screen update cycle includes N2 data compensation stages, M2 data holding stages, and P2 data writing stages; The first screen update cycle and the second screen update cycle satisfy: N1+M1+P1<N2+M2+P2, N1<N2.

17. The driving method for a display panel according to claim 5, characterized in that, The display panel includes a first color pixel unit and a second color pixel unit, and under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit is less than the theoretical data voltage corresponding to the second color pixel unit. During the data compensation stage, the compensation data voltages written by the first color pixel unit and the second color pixel unit in the multiple data compensation stages are all in an arithmetic sequence, and are respectively the first arithmetic sequence and the second arithmetic sequence; the common difference of the first arithmetic sequence is d1, the number of terms is N1, and the first term is a1; the common difference of the second arithmetic sequence is d2, the number of terms is N2, and the first term is a2; the first arithmetic sequence and the second arithmetic sequence satisfy: a1=a2, d1=d2, N1<N2; or, a1=a2, d1<d2, N1=N2; or, a1<a2, d1=d2, N1=N2.

18. The driving method for a display panel according to claim 1, characterized in that, The display panel includes a first color pixel unit and a second color pixel unit, and under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit is less than the theoretical data voltage corresponding to the second color pixel unit. The voltage difference of the compensation data corresponding to the two adjacent data compensation stages of the first color pixel unit is greater than the voltage difference of the compensation data corresponding to the two adjacent data compensation stages of the second color pixel unit. Alternatively, the compensation data voltage corresponding to the initial data compensation stage of the first color pixel is less than the compensation data voltage corresponding to the initial data compensation stage of the second color pixel. Alternatively, the number of data compensation stages for the first color pixel is greater than the number of data compensation stages for the second color pixel.

19. The driving method for a display panel according to claim 1, characterized in that, The data writing phase includes at least a target data voltage writing period and a light emission period; The data compensation phase includes at least a data compensation voltage writing period and a light emission period; The data retention phase includes at least the luminescence period.

20. The driving method for a display panel according to claim 19, characterized in that, The data writing phase and the data compensation phase further include a first threshold bias period and / or a second threshold bias period; During the data writing phase, the first threshold bias period is located before the target data voltage writing period, or the second threshold bias period is located between the target data voltage writing period and the light emission period; During the data compensation phase, the first threshold bias period is located before the compensation data voltage writing period, or the second threshold bias period is located between the compensation data voltage writing period and the light emission period.

21. A pixel driving circuit, characterized in that, The pixel driving circuit includes a data writing phase, a data holding phase, and a data compensation phase in at least one frame update cycle; At least one of the data compensation stages is located before at least one of the data writing stages; During the data compensation phase, the pixel driving circuit receives the gate scan signal and is written with the compensation data voltage; During the data writing phase, the pixel driving circuit receives the gate scan signal and is written with the target data voltage; The compensated data voltage is less than the target data voltage.

22. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes a driving transistor, a data writing module, a light emission control module, a threshold compensation module, and a bias adjustment module. The data writing module is used to provide data signals to the driving transistor; The light-emitting control module is electrically connected to the driving transistor between the power signal terminal and the light-emitting element, and is used to control whether the driving current flows through the light-emitting element. The threshold compensation module is electrically connected between the first node and the third node and is used to detect and self-compensate the deviation of the threshold voltage of the driving transistor. The control terminal of the driving transistor is electrically connected to the first node, the first terminal of the driving transistor is electrically connected to the second node, and the second terminal of the driving transistor is electrically connected to the third node; the driving transistor is used to generate driving current. The bias adjustment module is electrically connected between the threshold bias adjustment signal terminal and the third node, or electrically connected between the threshold bias adjustment signal terminal and the second node, for providing the signal from the bias adjustment signal terminal to the third node to adjust the bias state of the driving transistor.

23. The pixel driving circuit according to claim 21, characterized in that, The plurality of screen update cycles include at least one first screen update cycle and at least one second screen update cycle; The brightness of the first frame update cycle is greater than the brightness of the previous frame update cycle. The first frame update cycle includes the data writing phase, the data holding phase, and the data compensation phase. The brightness of the second frame update cycle is less than or equal to the brightness of the previous frame update cycle, and the first frame update cycle includes the data writing phase and the data holding phase.

24. The pixel driving circuit according to claim 21, characterized in that, The same screen update cycle includes multiple data compensation stages, including a first data compensation stage and a second data compensation stage, wherein the first data compensation stage precedes the second data compensation stage; and the compensation data voltage written in the second data compensation stage is greater than the compensation data voltage written in the first data compensation stage.

25. The pixel driving circuit according to claim 21, characterized in that, The same screen update cycle includes multiple data compensation stages, including a third data compensation stage and a fourth data compensation stage, wherein the third data compensation stage precedes the fourth data compensation stage; the compensation data voltage written in the fourth data compensation stage is equal to the compensation data voltage written in the third data compensation stage.

26. The pixel driving circuit according to claim 21, characterized in that, The same screen update cycle includes N data compensation stages, M data holding stages, and P data writing stages; Where N / (N+M+P)≤1 / 6, and N, M and P are all integers greater than or equal to 1.

27. The pixel driving circuit according to claim 21, characterized in that, The same screen update cycle includes multiple data compensation stages. The difference between the compensation data voltage written in the a-th data compensation stage and the (a+1)-th data compensation stage is ΔX1; the difference between the compensation data voltage written in the b-th data compensation stage and the (b+1)-th data compensation stage is ΔX2. Where △X1>△X2, a and b are both positive integers greater than 0, and a+1≤b.

28. The pixel driving circuit according to claim 21, characterized in that, The data retention phase is an interval between the data compensation phase and the data writing phase in the same screen update cycle. And / or, the same screen update cycle includes multiple data compensation phases, with at least one data hold phase spaced between at least two of the data compensation phases.

29. The pixel driving circuit according to claim 28, characterized in that, The same number of data holding stages are spaced between any two adjacent data compensation stages; Alternatively, at least two data retention phases may be spaced between the data compensation phase and the data writing phase.

30. The pixel driving circuit according to claim 21, characterized in that, The same screen update cycle includes N data compensation stages, M data holding stages, and P data writing stages; Where N, M, and P are all integers greater than or equal to 1; The interval between any two adjacent data compensation stages is n data holding stages, where 0 ≤ n ≤ M.

31. The pixel driving circuit according to claim 30, characterized in that, Between any two adjacent data compensation stages, there are M*a% / N data retention stages, where 30% ≤ a% ≤ 50%, and M*a% is an integer greater than or equal to 1, and M*a% / N is an integer greater than or equal to 1.

32. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes a first pixel driving circuit, wherein the driving transistor of the first pixel driving circuit is a silicon-based transistor.

33. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes a second pixel driving circuit, wherein the driving transistor of the second pixel driving circuit is an oxide semiconductor transistor.

34. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes a driving transistor; The driving transistor includes an N-type silicon-based transistor, and the number of the data compensation stage, the data holding stage, and the data writing stage satisfies: N / (N+M+P)≤1 / 6. Alternatively, the driving transistor may include a P-type silicon-based transistor, and the number of the data compensation stage, the data holding stage, and the data writing stage shall satisfy: N / (N+M+P)≤1 / 12.

35. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes driving transistors; the driving transistors include N-type silicon-based transistors and P-type silicon-based transistors. The pixel driving circuit includes a third pixel driving circuit and a fourth pixel driving circuit. The third pixel driving circuit includes the N-type silicon transistor, and the fourth pixel driving circuit includes the P-type silicon transistor. In the same frame update cycle, the proportion of data compensation stages in the third pixel driving circuit is different from that in the fourth pixel driving circuit.

36. The pixel driving circuit according to claim 21, characterized in that, Any two adjacent screen update cycles include a first screen update cycle and a second screen update cycle; the first screen update cycle includes N1 data compensation stages, M1 data holding stages, and P1 data writing stages; the second screen update cycle includes N2 data compensation stages, M2 data holding stages, and P2 data writing stages; The first screen update cycle and the second screen update cycle satisfy: N1+M1+P1<N2+M2+P2, N1<N2.

37. The pixel driving circuit according to claim 21, characterized in that, Under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit corresponding to the pixel driving circuit is less than the theoretical data voltage corresponding to the second color pixel unit corresponding to the other pixel driving circuit. During the data compensation stage, the compensation data voltages written by the first color pixel unit and the second color pixel unit in the multiple data compensation stages are all in an arithmetic sequence, and are respectively the first arithmetic sequence and the second arithmetic sequence; the common difference of the first arithmetic sequence is d1, the number of terms is N1, and the first term is a1; the common difference of the second arithmetic sequence is d2, the number of terms is N2, and the first term is a2; the first arithmetic sequence and the second arithmetic sequence satisfy: a1=a2, d1=d2, N1<N2; or, a1=a2, d1<d2, N1=N2; or, a1<a2, d1=d2, N1=N2.

38. The pixel driving circuit according to claim 21, characterized in that, Under the same target brightness, the theoretical data voltage corresponding to the first color pixel unit corresponding to the pixel driving circuit is less than the theoretical data voltage corresponding to the second color pixel unit corresponding to the other pixel driving circuit. The voltage difference of the compensation data corresponding to the two adjacent data compensation stages of the first color pixel unit is greater than the voltage difference of the compensation data corresponding to the two adjacent data compensation stages of the second color pixel unit. Alternatively, the compensation data voltage corresponding to the initial data compensation stage of the first color pixel is less than the compensation data voltage corresponding to the initial data compensation stage of the second color pixel. Alternatively, the number of data compensation stages for the first color pixel is greater than the number of data compensation stages for the second color pixel.

39. The pixel driving circuit according to claim 21, characterized in that, The data writing phase includes at least a target data voltage writing period and a light emission period; The data compensation phase includes at least a data compensation voltage writing period and a light emission period; The data retention phase includes at least the luminescence period.

40. The pixel driving circuit according to claim 39, characterized in that, The data writing phase and the data compensation phase further include a first threshold bias period and / or a second threshold bias period; During the data writing phase, the first threshold bias period is located before the target data voltage writing period, or the second threshold bias period is located between the target data voltage writing period and the light emission period; During the data compensation phase, the first threshold bias period is located before the compensation data voltage writing period, or the second threshold bias period is located between the compensation data voltage writing period and the light emission period.

41. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit also includes a driving transistor and a bias adjustment module. The bias adjustment module is electrically connected to either the first terminal or the second terminal of the driving transistor.

42. The pixel driving circuit according to claim 41, characterized in that, The control terminal of the bias adjustment module is electrically connected to the second control signal terminal, and is used to provide the signal of the bias adjustment signal terminal to the first terminal or the second terminal of the driving transistor under the control of the signal of the second control signal terminal.

43. The pixel driving circuit according to claim 41, characterized in that, The pixel driving circuit also includes a data writing module; The data writing module is electrically connected to either the first terminal of the driving transistor or the second terminal of the driving transistor.

44. The pixel driving circuit according to claim 41, characterized in that, The bias adjustment module is reused as the data writing module; The bias adjustment module is used to provide the signal of the bias adjustment signal terminal to the driving transistor to adjust the bias state of the driving transistor. The data writing module is used to provide data signals to the driving transistor.

45. The pixel driving circuit according to claim 21, characterized in that, A scan driving unit is used to provide gate scan signals to the pixel driving circuit during the data writing phase and the data compensation phase, respectively. A data writing unit is used to write the target data voltage to the pixel driving circuit during the data writing phase; It is also used to write the compensation data voltage to the pixel driving circuit during the data compensation stage.

46. ​​The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes a pixel driving circuit, which includes: The module includes a driving transistor, a data writing module, a light emission control module, and a threshold compensation module. The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node. The data writing module is electrically connected between the data signal terminal and the second node; the threshold compensation module is electrically connected between the first node and the third node; the data writing module is used to provide the data signal input from the data signal terminal to the driving transistor; The threshold compensation module is used to compensate the threshold voltage of the driving transistor to the first node; The light-emitting control module and the driving transistor are electrically connected between the power signal terminal and the light-emitting element. The light-emitting control module is used to control whether the driving current flows through the light-emitting element.

47. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes: The module includes a driving transistor, a data writing module, a light emission control module, a threshold compensation module, and a bias adjustment module. The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node. The data writing module is electrically connected between the data signal terminal and the second node, and the data writing module is used to provide the data signal input from the data signal terminal to the driving transistor. The light-emitting control module and the driving transistor are electrically connected between the power signal terminal and the light-emitting element. The light-emitting control module is used to control whether the driving current flows through the light-emitting element. The threshold compensation module is electrically connected between the first node and the third node; the threshold compensation module is used to detect and self-compensate the deviation of the threshold voltage of the driving transistor. The bias adjustment module is electrically connected between the threshold bias adjustment signal terminal and the second node or between the threshold bias adjustment signal terminal and the third node; the control terminal of the bias adjustment module is connected to the first control signal terminal, and the bias adjustment module is used to control the voltage bias of the driving transistor under the control of the first control signal input at the first control signal terminal and the threshold bias adjustment signal input at the threshold bias adjustment signal terminal.

48. The pixel driving circuit according to claim 47, characterized in that, The driving transistor is an N-type transistor; The threshold compensation module and the bias adjustment module are reused as an initialization module for resetting the first node.

49. The pixel driving circuit according to claim 47, characterized in that, The driving transistor is an N-type transistor; The data writing module is reused as the bias adjustment module, and the data signal terminal is reused as the threshold bias adjustment signal terminal; The data writing module is also used to provide the second node with the threshold bias adjustment signal input from the data signal terminal.

50. The pixel driving circuit according to claim 47, characterized in that, The driving transistor is a P-type transistor; The threshold compensation module and the bias adjustment module are reused as an initialization module for resetting the first node.

51. The pixel driving circuit according to claim 21, characterized in that, The target data voltage is the theoretical data voltage corresponding to the target brightness in the current frame update cycle.

52. The pixel driving circuit according to claim 21, characterized in that, During the data holding phase, no data voltage is written to the pixel driving circuit.

53. The pixel driving circuit according to claim 21, characterized in that, The screen update cycle includes at least the data writing phase and the data holding phase; The brightness of the current screen update cycle is greater than that of the previous screen update cycle, and the previous screen update cycle includes the data writing phase, the data holding phase, and the data compensation phase.

54. The pixel driving circuit according to claim 21, characterized in that, The pixel driving circuit includes: Driver transistor, data writing module, bias adjustment module; The control terminal of the driving transistor is connected to the first node, the first terminal of the driving transistor is connected to the second node, and the second terminal of the driving transistor is connected to the third node. The data writing module is electrically connected between the data signal terminal and the second node; The bias adjustment module is electrically connected between the threshold bias adjustment signal terminal and the second node or between the threshold bias adjustment signal terminal and the third node.

55. The pixel driving circuit according to claim 54, characterized in that, The same screen update cycle includes multiple data compensation stages with different compensation data voltages.

56. The pixel driving circuit according to claim 54, characterized in that, The pixel driving circuit further includes an initialization module, which at least partially reuses the bias adjustment module.

57. The pixel driving circuit according to claim 54, characterized in that, The data writing module is reused as the bias adjustment module.

58. The pixel driving circuit according to claim 54, characterized in that, The data writing module and the bias adjustment module are electrically connected to different nodes of the driving transistor.

59. The pixel driving circuit according to claim 21, characterized in that, The brightness theoretically corresponding to the compensated data voltage is greater than the brightness theoretically corresponding to the target data voltage.

60. A display panel, characterized in that, Includes the pixel driving circuit described in any one of claims 21 to 59 above.

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