Methods and apparatus for converting AXI protocol to CHI protocol

Abstract

This disclosure relates to a method and apparatus for converting the AXI protocol to the CHI protocol. The method involves receiving an AXI request, including an AXI read / write request; splitting the received AXI read / write request into multiple target AXI read / write requests with a single data volume size conforming to the CHI interface protocol, based on the total data volume required for the AXI read / write request; caching the split target AXI read / write requests and the related write data; converting the cached target AXI read / write requests into read / write requests of the corresponding request type in the CHI interface protocol; converting the write data into write data of the corresponding data packet type in the CHI interface protocol; receiving the converted read / write requests and write data; and processing the requests according to the CHI protocol specifications. Therefore, by splitting and converting the AXI request, multiple target AXI read / write requests can be operated simultaneously, improving the parallelism of data access; facilitating the management of data resources from different interface protocols; and improving conversion efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a method and apparatus for converting the AXI protocol to the CHI protocol. Background Technology

[0002] Currently, with the widespread application of the CHI protocol in multi-core systems, more and more chips are using a hybrid application of the Coherent Hub Interface Protocol (CHI) and the Advanced eXtensible Interface Protocol (AXI), making the conversion from AXI protocol to CHI protocol indispensable.

[0003] However, in related technologies, the request channel of AXI is converted to the request channel of CHI, and the response channel of AXI is converted to the response channel of CHI. This results in an imbalance of data volume between the two protocols, which can cause the AXI request channel to block the reception of the request address and reduce the access bandwidth of the entire system. Summary of the Invention

[0004] This disclosure provides a method and apparatus for converting the AXI protocol to the CHI protocol.

[0005] According to a first aspect of the present disclosure, a method for converting an AXI protocol to a CHI protocol is provided. The method includes: receiving an AXI request, the AXI request including an AXI read / write request; splitting the received AXI read / write request into multiple target AXI read / write requests that conform to the single data volume size of the CHI interface protocol based on the total data volume required to be accessed by the AXI read / write request; caching the split target AXI read / write requests and the write data involved in the target AXI write requests; converting the cached target AXI read / write requests into read / write requests of the corresponding request type of the CHI interface protocol; converting the write data involved in the AXI write requests into write data of the corresponding data packet type of the CHI interface protocol; receiving the converted read / write requests and write data, and processing the requests according to the specifications of the CHI protocol.

[0006] In one embodiment of this disclosure, in response to the target AXI request being an AXI read request, the method includes: receiving an AXI read request, wherein the address of the AXI read request is not related to an address in a first cache queue, and the first cache queue is a cache queue for managing AXI read requests; splitting the received AXI read request into multiple target AXI read requests conforming to the single data volume size of the CHI interface protocol based on the total amount of data to be accessed by the AXI read request, and deploying them respectively in the first cache queue; storing each of the target AXI read requests in the first cache queue in a preset target AXI read request cache module; converting the target AXI read request into a CHI read request of the corresponding request type of the CHI interface protocol according to the cache attributes of the target AXI read request in the target AXI read request cache module, and deploying it in a second cache queue for managing CHI read requests; receiving each CHI read request periodically sent by the second cache queue through a preset CHI interface protocol processing function module, and processing the read request according to the CHI protocol specification.

[0007] In one embodiment of this disclosure, the read request processing according to the CHI protocol specification includes: receiving read response data returned by a CHI read request through a preset CHI interface protocol processing functional module, and forwarding it to the corresponding target cache queue in the second cache queue; wherein, the read response data includes the read data block and the read request identifier; after receiving the read response data, the target cache queue in the second cache queue first completes the CHI interface handshake protocol, then writes the data block and the read request identifier into the preset target AXI read request storage module, and notifies the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released simultaneously, and can be used by the next target AXI read request; the first cache queue receives that all the split target AXI read requests have been completed, reads each data block from the storage module based on the read request identifier and returns it to the AXI interface protocol processing functional module; the AXI protocol handshake processing is performed based on the AXI interface protocol processing functional module to complete the current AXI read request process.

[0008] In one embodiment of this disclosure, in response to the target AXI request being an AXI write request, the method includes: receiving an AXI write request, wherein the address of the AXI write request is not related to the address in a third cache queue, and the third cache queue is a cache queue for managing AXI write requests; splitting the received AXI write request into multiple target AXI write requests conforming to the single data volume size of the CHI interface protocol based on the total data volume of the AXI write request, and deploying them respectively in the third cache queue; and storing each of the target AXI write requests in the third cache queue in a preset target AXI write request cache module. The CHI request is converted according to the cache attributes of the target AXI write request in the cache module of the target AXI write request. The target AXI write request is converted into a CHI write request of the corresponding request type of the CHI interface protocol and deployed in the fourth cache queue that manages CHI write requests. The CHI write requests periodically sent by the fourth cache queue are received through the preset CHI interface protocol processing function module. After obtaining the write data return response signal of the CHI write request, the third cache queue is notified to return the AXI write request completion response. At the same time, the fourth cache queue continues to process the write request according to the CHI protocol specification.

[0009] In one embodiment of this disclosure, the write request processing according to the CHI protocol specification includes: receiving a write data transmittable response signal returned by a CHI write request through a preset request processing module, and forwarding it to the corresponding target cache queue in the fourth cache queue; wherein, the write data transmittable response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and simultaneously notifying the third cache queue; the write data involved in the target AXI write request is stored in a preset target AXI write request storage module; after receiving the write data transmittable response signal, the corresponding target cache queue in the fourth cache queue initiates a read request to the target AXI write request storage module, packages the write data at the corresponding address into a write data packet and sends it to the functional module processing the CHI interface protocol; the functional module processing the CHI interface protocol sends out the write data packet, and the corresponding target cache queue in the fourth cache queue... The cache queue completes the CHI protocol process for the current CHI write request and then releases the resources of the fourth cache queue. Simultaneously, the cache module and storage module for the target AXI write request corresponding to the write request identifier are also released, making them available for the next target AXI write request. Meanwhile, when the third cache queue receives completion identifiers for all split target AXI write requests, it sends a completion signal to the functional module handling the AXI interface protocol, without waiting for the CHI interface protocol processing flow in the fourth cache queue. Based on the completion signal, other internal cache resources are released and the system is reset to the initial state for processing new AXI write requests, completing the current AXI write request process. These other internal cache resources include the third cache queue's own cache, the residual resources of the fourth cache queue, the local cache of the functional module handling the AXI / CHI interface protocol, and the residual data in the storage module of the target AXI write request.

[0010] According to a second aspect of the present disclosure, an apparatus for converting an AXI protocol to a CHI protocol is also provided. The apparatus includes: a receiving module for receiving an AXI request, the AXI request including an AXI read / write request; a splitting module for splitting the received AXI read / write request into target AXI read / write requests conforming to the data access types supported by the CHI interface protocol; a caching module for caching the split target AXI read / write requests and the write data involved in the target AXI write requests; a conversion module for converting the target AXI read / write requests into read / write requests of a corresponding request type of the CHI interface protocol; and converting the write data involved in the AXI write requests into write data of a corresponding data packet type of the CHI interface protocol; and a request processing module for receiving the converted read / write requests and write data, and processing the requests according to the specifications of the CHI protocol.

[0011] According to a third aspect of the present disclosure, an electronic device is also provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to: implement the steps of the method for converting the AXI protocol to the CHI protocol as described above.

[0012] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is also provided, which, when the instructions in the storage medium are executed by a processor, enables the processor to perform the AXI protocol to CHI protocol method as described above.

[0013] The technical solutions provided by the embodiments of this disclosure bring at least the following beneficial effects:

[0014] Based on the total data volume required for AXI read / write requests, the received AXI read / write requests are split into multiple target AXI read / write requests with a single data volume size conforming to the CHI interface protocol. The split target AXI read / write requests and the associated write data are cached. The cached target AXI read / write requests are then converted into read / write requests of the corresponding request type according to the CHI interface protocol. The write data is converted into write data of the corresponding data packet type according to the CHI interface protocol. The converted read / write requests and write data are received and processed according to the CHI protocol specifications. Therefore, by splitting and converting AXI requests, multiple target AXI read / write requests can be operated simultaneously, improving the parallelism of data access; facilitating the management of data resources from different interface protocols; and improving conversion efficiency.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0017] Figure 1 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure;

[0018] Figure 2 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to another embodiment of this disclosure;

[0019] Figure 3 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to another embodiment of this disclosure;

[0020] Figure 4 This is a schematic diagram illustrating the principle of a method for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure;

[0021] Figure 5 This is a schematic diagram of the structure of an AXI protocol to CHI protocol device according to an embodiment of the present disclosure;

[0022] Figure 6 This is a structural block diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0024] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0025] Figure 1 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure. It should be noted that the AXI protocol to CHI protocol method of this embodiment can be applied to an AXI protocol to CHI protocol conversion device, which can be configured in an electronic device to enable the electronic device to perform the AXI protocol to CHI protocol conversion function.

[0026] The electronic device can be any device with computing capabilities, such as a terminal device or a server. The following embodiments use a terminal device as an example for illustration.

[0027] like Figure 1 As shown, the method includes the following steps:

[0028] Step 101: Receive an AXI request, which includes an AXI read / write request.

[0029] In this embodiment of the disclosure, an AXI request can be received through a functional module that processes the AXI interface protocol. This module is responsible for parsing the various channel signals in the AXI protocol (such as read address channel, read data channel, write address channel, write data channel, and write response channel) and performing corresponding processing according to the protocol specifications. For example, parsing read / write requests, managing data transmission, and generating response signals.

[0030] Step 102: Based on the total amount of data that the AXI read / write request needs to access, the received AXI read / write request is split into multiple target AXI read / write requests that conform to the single data volume size of the CHI interface protocol.

[0031] In this embodiment, AXI read / write requests can be split based on the total amount of data they require, enabling devices using the AXI protocol to communicate with devices using the CHI protocol. For example, according to the CHI protocol specification, this information can be reorganized into requests in a format supported by the CHI protocol. By splitting AXI read / write requests, it is easy to identify whether an address is associated with an AXI read / write request without needing to associate it with a CHI read / write request cache queue. This ensures that during the AXI-to-CHI conversion process, both the AXI and CHI protocol interfaces send and receive data independently.

[0032] CHI stands for Coherent Hub Interface Protocol, and AXI stands for Advanced eXtensible Interface Protocol.

[0033] Step 103: Cache the split target AXI read / write requests and the write data involved in the target AXI write requests.

[0034] In this embodiment of the disclosure, a First-In-First-Out (FIFO) buffer can be used to store the target AXI read / write request and the related write data, providing a buffering mechanism for the target AXI read / write request to cope with scenarios such as burst transmissions, rate differences, or cross-clock domain transmissions. Buffering can smooth the data flow and prevent data loss or overflow.

[0035] Step 104: Convert the cached target AXI read / write request into a read / write request of the corresponding request type of the CHI interface protocol; convert the write data involved in the AXI write request into write data of the corresponding data packet type of the CHI interface protocol.

[0036] In this embodiment of the disclosure, the cached target AXI read / write request can be converted into the corresponding request packet type in the CHI interface protocol according to the read / write request format of the AXI and CHI interface protocols. For example, certain protocol-specific signals can be added or removed, and the order and format of the signals can be adjusted. The write data involved in the AXI write request is packaged and transmitted according to the requirements of the CHI protocol. This may involve adjusting the data width, converting the data byte order, etc.

[0037] Step 105: Receive the converted read / write requests and write data, and process the requests according to the CHI protocol specifications.

[0038] In this embodiment of the disclosure, the functional module for processing the CHI interface protocol can receive the converted read / write requests and write data, parse the various channel signals in the CHI protocol (such as request channel, listening channel, response channel, data channel, etc.), and perform corresponding processing according to the CHI protocol specifications. For example, it can handle cache consistency requests, coordinate data access between multiple nodes, and maintain cache state.

[0039] It should be noted that, in this embodiment of the disclosure, as an example, the AXI interface has a burst length (LEN) bit width of 8 bits, a data size (SIZE) bit width of 3 bits, a data bit width of 256 bits, and supports burst types of fixed address burst, incremental address burst (INCR), and wraparound address burst (WRAP). The CHI interface does not have a LEN field, the DATA bit width is 256 bits, the SIZE bit width is 3 bits, the cache size is 512 bits, and the amount of data that can be accessed at one time is 512 bits.

[0040] The method for converting the AXI protocol to the CHI protocol according to this embodiment of the disclosure splits the received AXI read / write request into multiple target AXI read / write requests with a single data volume size conforming to the CHI interface protocol, based on the total data volume required by the AXI read / write request. The split target AXI read / write requests and the related write data are cached. The cached target AXI read / write requests are converted into read / write requests of the corresponding request type of the CHI interface protocol. The write data is converted into write data of the corresponding data packet type of the CHI interface protocol. The converted read / write requests and write data are received and processed according to the CHI protocol specifications. Therefore, by splitting and converting AXI requests, multiple target AXI read / write requests can be operated simultaneously, improving the parallelism of data access; facilitating the management of data resources of different interface protocols; and improving conversion efficiency.

[0041] Figure 2 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to another embodiment of this disclosure. It should be noted that the AXI protocol to CHI protocol method of this embodiment can be applied to an AXI protocol to CHI protocol device, which can be configured in an electronic device to enable the electronic device to perform the AXI protocol to CHI protocol function.

[0042] The electronic device can be any device with computing capabilities, such as a terminal device or a server. The following embodiments use a terminal device as an example for illustration.

[0043] like Figure 2 As shown, the method includes the following steps:

[0044] Step 201: Receive an AXI read request, wherein the address of the AXI read request is not related to the address in the first cache queue, and the first cache queue is a cache queue that manages AXI read requests.

[0045] In this embodiment of the disclosure, as an example, the AXI read request is received by the functional module (AXI_HANDLE) that processes the AXI interface protocol, the AXI read request address is determined, and it is determined whether the AXI read request address is related to the address that was previously entered into the first cache queue (AXI_QUEUE). If there is a correlation, the process enters the waiting state; if there is no correlation, the process requests entry into the AXI_QUEUE for further processing. The first cache queue (AXI_QUEUE) may include 16 items, for example, AXI_QUEUE0, ..., AXI_QUEUE15.

[0046] Step 202: Based on the total amount of data that the AXI read request needs to access, the received AXI read request is split into multiple target AXI read requests that conform to the single data volume size of the CHI interface protocol, and deployed in the first cache queue respectively.

[0047] In this embodiment, AXI_QUEUE splits the received target AXI read request. In the example, the target AXI read request enters the first cache queue, then enters AXI_QUEUE0. Based on the read burst length (ARLEN), read transfer granularity (ARSIZE), and read burst type (ARBURST), the total amount of data that the AXI read request needs to access is calculated. In the example, the AXI read request is: ARADDR='h1000, ARALEN='h5, ARCACHE[3:2]='h3, ARBURST=INCR; ARALEN='h5 indicates that the AXI read request needs to return 6 data entries, ARSIZE='h5 indicates that the data length of a single access is 256 bits, and ARBURST=INCR indicates that the burst type is an incremental address burst mode; at this time, the calculated total amount of data is 6 * 256 bits. AXI_QUEUE0 splits this AXI read request into single data accesses conforming to the CHI interface; thus, it splits into 3 target AXI read requests: 1st: ARADDR='h1000', ARLEN='h1', ARSIZE='h5', ARCACHE[3:2]='h3', NEW_RID0='h1'; 2nd: ARADDR='h1040', ARLEN='h1', ARSIZE='h5', ARCACHE[3:2]='h3', NEW_RID1='h2'; 3rd: ARADDR='h1080', ARLEN='h1', ARSIZE='h5', ARCACHE[3:2]='h3', NEW_RID2='h3'; the values ​​of other fields use the original, unsplit AXI read request values. RDONE_FLAG_CNT can also be added to AXI_QUEUE to identify the number of target AXI read requests to be split. In this example, the number of split requests set in RDONE_FLAG_CNT for this transmission is 3. Each time a target AXI read request completion signal is received, RDONE_FLAG_CNT is decremented by 1. When it is decremented to 0, it means that the split target AXI read request has been completed.

[0048] Step 203: Save each target AXI read request in the first cache queue in the preset target AXI read request cache module.

[0049] In this embodiment of the disclosure, the split target AXI read request is saved to a preset cache module (AR_CMD_BUFFER) to cope with scenarios such as burst transmission, rate difference or cross-clock domain transmission.

[0050] Step 204: Based on the cache attributes of the target AXI read request in the cache module of the target AXI read request, the CHI request is converted into a CHI read request of the corresponding request type of the CHI interface protocol and deployed in the second cache queue that manages CHI read requests.

[0051] The second cache queue (CHI_QUEUE) may include 32 items, for example, CHI_QUEUE0, ..., CHI_QUEUE31.

[0052] In this embodiment, the target AXI read request in AR_CMD_BUFFER is processed in the second cache queue (CHI_QUEUE). The three target AXI read requests are sequentially entered into different CHI_QUEUE queues, namely CHI_QUEUE0, CHI_QUEUE1, and CHI_QUEUE2. The CHI command is converted based on the cache attributes (ARCACHE, e.g., cache status and transaction type) information in the target AXI read request. If ARCACHE[3:2] equals 2'h0, the operation type (OPCODE) field of the request packet (REQ_FLIT) of the CHI protocol uses a non-listening read request (READNOSNP), and the SIZE field is 256 bits; if ARCACHE[3:2] does not equal 2'h0, the REQ_FLIT of the CHI protocol... The OPCODE field in the IT request packet uses a one-time read request (READONCE), and the SIZE field is 256 bits. Therefore, the key field values ​​in the converted REQ_FLIT packet are as follows: 1st REQ_FLIT packet: ADDR='h1000, OPCODE=READONCE, SIZE='h6'; 2nd REQ_FLIT packet: ADDR='h1040, OPCODE=READONCE, SIZE='h6'; 3rd REQ_FLIT packet: ADDR='h1080, OPCODE=READONCE, SIZE='h6'.

[0053] Step 205: Receive each CHI read request sent periodically by the second cache queue through the preset CHI interface protocol processing functional module, and process the read requests according to the CHI protocol specifications.

[0054] In this embodiment of the disclosure, the CHI read request after conversion is sent to the functional module (CHI_HANDLE) that processes the CHI interface protocol. One REQ_FLIT request packet can be sent in each cycle without waiting for the previous CHI read request to be processed.

[0055] Step 206: Receive the read response data returned by the CHI read request through the preset CHI interface protocol processing functional module, and forward it to the corresponding target cache queue in the second cache queue; wherein, the read response data includes the read data block and the read request identifier.

[0056] In this embodiment, CHI_HANDLE receives read response data (DATA_FLIT packet) returned by the read request and forwards the received DATA_FLIT packet to the corresponding CHI_QUEUE. In the example, the first returned DATA_FLIT packet corresponds to CHI_QUEUE5, so CHI_HANDLE sends the DATA_FLIT packet to CHI_QUEUE1, and CHI_QUEUE1 continues to wait for the second DATA_FLIT packet; when CHI_HANDLE receives the second DATA_FLIT packet, which also corresponds to CHI_QUEUE5, CHI_HANDLE sends the DATA_FLIT to CHI_QUEUE1. After receiving the two required DATA_FLIT packets, CHI_QUEUE1 generates a completion confirmation response packet (SRSP_FLIT) and sends the SRSP_FLIT to CHI_HANDLE, which then forwards it to the corresponding target cache queue in the second cache queue.

[0057] The read response data may also include an error check code to verify the correctness of the read response data.

[0058] Step 207: After the target cache queue in the second cache queue obtains the read response data, it first completes the CHI interface handshake protocol, then writes the data block and read request identifier into the preset storage module of the target AXI read request, and notifies the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, which can be used by the next target AXI read request.

[0059] In this embodiment, after forwarding the request to the corresponding target cache queue in the second cache queue, CHI_HANDLE notifies the outside world that the CHI read request process is complete. Simultaneously, CHI_QUEUE1 writes the data block and the corresponding read request identifier (NEW_RID1) into the storage module (R_DATA_BUFFER) of the target AXI read request, and then notifies the first cache queue that the current CHI read request is complete. Finally, the completion status is updated in AXI_QUEUE0, and RDONE_FLAG_CNT of AXI_QUEUE0 is decremented by 1. CHI_QUEUE1 releases the queue, and the AR_CMD_BUFFER corresponding to NEW_RID is also released simultaneously, making it available for the next request.

[0060] Step 208: After the first cache queue receives all the split target AXI read requests, it reads each data block from the storage module based on the read request identifier and returns it to the functional module that processes the AXI interface protocol.

[0061] In this embodiment, similarly, CHI_QUEUE0 and CHI_QUEUE2 execute the same steps 206 and 207, and the CHI_QUEUE0 and CHI_QUEUE2 queues are released, along with the AR_CMD_BUFFE corresponding to NEW_WID. The final result of RDONE_FLAG_CNT for AXI_QUEUE0 is 0, indicating that AXI_QUEUE1 has completed all the split target AXI read requests, and the data blocks required by all target AXI read requests have been stored in R_DATA_BUFFER. The execution order of CHI_QUEUE0, CHI_QUEUE1, and CHI_QUEUE2 is not restricted.

[0062] Step 209: Perform handshake processing on the AXI protocol side based on the functional module that processes the AXI interface protocol to complete the AXI read request process.

[0063] In this embodiment, when RDONE_FLAG_CNT in AXI_QUEUE0 is 0, AXI_QUEUE0 begins subsequent processing. AXI_QUEUE0 reads data from R_DATA_BUFFER according to the currently stored NEW_RID value, acquiring data in the order NEW_RID0, NEW_RID1, and NEW_RID2, and then releases the corresponding R_DATA_BUFFER. AXI_QUEUE0 then sends the data sequentially to AXI_HANDLE for AXI protocol communication, providing corresponding read data valid signals (RVALID), read data signals (RDATA), etc. When all six target AXI read requests have completed the AXI protocol handshake, AXI_QUEUE0 is released, completing the entire AXI read request processing flow.

[0064] In the method for converting the AXI protocol to the CHI protocol according to this embodiment, an AXI read request is received, wherein the address of the AXI read request is not related to the address in the first cache queue, and the first cache queue is a cache queue for managing AXI read requests; based on the total data volume of the AXI read request, the received AXI read request is split into multiple target AXI read requests that conform to the single data volume size of the CHI interface protocol, and deployed in the first cache queue respectively; each target AXI read request in the first cache queue is stored in a preset target AXI read request cache module; according to the cache attributes of the target AXI read request in the target AXI read request cache module, the CHI request is converted into a CHI read request of the corresponding request type of the CHI interface protocol, and deployed in a second cache queue for managing CHI read requests; each CHI read request periodically sent by the second cache queue is received through a preset CHI interface protocol processing function module, and the read requests are processed according to the CHI protocol specifications. The process involves the following steps: The pre-defined CHI interface protocol processing module receives the read response data from the CHI read request and forwards it to the corresponding target cache queue in the second cache queue. The read response data includes the read data block and a read request identifier. Upon receiving the read response data, the target cache queue in the second cache queue first completes the CHI interface handshake protocol, then writes the data block and read request identifier into the pre-defined target AXI read request's storage module, and notifies the first cache queue that the current CHI read request is complete. Simultaneously, the second cache queue releases its queue, and the cache module for the target AXI read request corresponding to the read request identifier is also released, making it available for the next target AXI read request. Once the first cache queue receives confirmation that all split target AXI read requests have been completed, it reads each data block from the storage module based on the read request identifier and returns it to the AXI interface protocol processing module. The AXI interface protocol processing module then performs the AXI protocol handshake, completing the current AXI read request process. Therefore, by splitting AXI read requests, converting protocols, and managing cache queues, the problems of data volume mismatch between AXI and CHI protocols, complex cache management, and differences in handshake protocols are resolved.

[0065] Figure 3 This is a flowchart illustrating a method for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure. It should be noted that the AXI protocol to CHI protocol method of this embodiment can be applied to an AXI protocol to CHI protocol conversion device, which can be configured in an electronic device to enable the electronic device to perform the AXI protocol to CHI protocol conversion function.

[0066] The electronic device can be any device with computing capabilities, such as a terminal device or a server. The following embodiments use a terminal device as an example for illustration.

[0067] like Figure 3 As shown, the method includes the following steps:

[0068] Step 301: Receive an AXI write request, wherein the address of the AXI write request is not related to the address in the third cache queue, and the third cache queue is a cache queue that manages AXI write requests.

[0069] In this embodiment of the disclosure, as an example, an AXI write request can be received by a functional module that processes the AXI interface protocol. It can then determine whether the AXI write request is related to an address that has previously entered the third cache queue (AXI_QUEUE). If there is a correlation, the module will enter a waiting state. If there is no correlation, the module will request to enter the AXI_QUEUE to continue subsequent processing. At the same time, the module will begin receiving the write data corresponding to the AXI write request.

[0070] Step 302: Based on the total data volume of the AXI write requests, the received AXI write requests are split into multiple target AXI write requests that conform to the single data volume size of the CHI interface protocol, and deployed in the third cache queue respectively.

[0071] The third cache queue can be implemented through the first cache queue (AXI_QUEUE) mentioned above, and may include 16 items, such as AXI_QUEUE0, ..., AXI_QUEUE15.

[0072] In this embodiment, the AXI protocol data conversion module receives and completes the AXI write request and performs subsequent parsing. The AXI write request enters AXI_QUEUE1, and calculates the total amount of data that the AXI write request needs to access based on the read burst length (AWLEN), read transfer granularity (AWSIZE), and read burst type (AWBURST). In the example, the AXI write request is: AWADDR='h2000, AWLEN='h5, AWCACHE[3:2]='h3, AWBURST=INCR; AWLEN='h5 indicates that the AXI write request needs to return 6 data entries, and AWSIZE='h5 indicates the data length of a single access. The data is 256 bits. ARBURST=INCR indicates that the burst type is an incrementing address burst. The valid bits (WSTRB) of the 6 data entries are: WSTRB0=32'hffffffff, WSTRB1=32'hffffffff, WSTRB2=32'hffffffff, WSTRB3=32'hffffffff, WSTRB4=32'hffffffff, WSTRB5=32'haaaaaaaa. Therefore, the total data volume of the calculated AXI write request is 6 * 256 bits. AXI_QUEUE1 splits this AXI write request into single data accesses conforming to the CHI interface and inserts a write data valid signal (WSTRB_ALL_EN) flag into the split target AXI write requests. For example, it splits into 3 AXI write requests:

[0073] The first one: AWADDR='h2000, AWLEN='h1, AWSIZE='h5, AWCACHE[3:2]='h3, WSTRB_ALL_EN0=& (WSTRB0&WSTRB1), NEW_WID0='h100, NEW_DATA0={DATA1,DATA0},

[0074] NEW_WSTRB0={WSTRB1,WSTRB0};

[0075] The second one: AWADDR='h2040,AWLEN='h1,AWSIZE='h5,AWCACHE[3:2]='h3,WSTRB_ALL_EN1=&(WSTRB2&WSTRB3.

[0076] NEW_WID1='h101,NEW_DATA1={DATA3,DATA2},

[0077] NEW_WSTRB1={WSTRB3,WSTRB2};

[0078] No. 3: AWADDR='h2080, AWLEN='h1, AWSIZE='h5, AWCACHE[3:2]='h3; WSTRB_ALL_EN2=& (WSTRB4&WSTRB5), NEW_WID2='h102, NEW_DATA2={DATA5,DATA4},

[0079] NEW_WSTRB2={WSTRB5,WSTRB4}.

[0080] The values ​​of other fields use the original, unsplit AXI write request values. WDONE_FLAG_CNT is added to AXI_QUEUE to indicate the number of target AXI write requests to be split. In this example, the number of split requests is set to 3 for this transmission. WDONE_FLAG_CNT is decremented by 1 for each completed write request signal received. When it reaches 0, it indicates that the target AXI write requests to be split have been completed.

[0081] Step 303: Save each target AXI write request in the third cache queue in the preset target AXI write request cache module.

[0082] In this embodiment, the split target AXI write request is saved to the target AXI write request cache module (AW_CMD_BUFFER) to handle scenarios such as burst transmission, rate differences, or cross-clock domain transmission.

[0083] Step 304: Based on the cache attributes of the target AXI write request in the cache module of the target AXI write request, the CHI request is converted into a CHI write request of the corresponding request type of the CHI interface protocol and deployed in the fourth cache queue that manages CHI write requests.

[0084] The fourth cache queue can be implemented through the second cache queue (CHI_QUEUE) mentioned above, and can include 32 items, for example, CHI_QUEUE0, ..., CHI_QUEUE32.

[0085] In this embodiment, the target AXI write request in AW_CMD_BUFFER is processed in CHI_QUEUE. The three write requests are sequentially entered into different CHI_QUEUE queues, namely CHI_QUEUE3, CHI_QUEUE4, and CHI_QUEUE5. The CHI command is converted according to the cache attribute (AWCACHE) and WSTRB_ALL_EN information in the target AXI write request. If AWCACHE[3:2] equals 2'h0 and WSTRB_ALL_EN=0, then the OPCODE field in the CHI write request packet (REQ_FLIT) of the CHI protocol uses a non-listening partial write request (WRITENOSNPPTL); if AWCACHE[3:2] equals 2'h0 and WSTRB_ALL_EN=1, then the OPCODE field in the CHI protocol REQ_FLIT request packet uses a non-listening full write request (WRITENOSNPFULL); if AWCACHE[3:2] does not equal 2'h0 and WSTRB_ALL_EN=0, then the OPCODE field in the CHI protocol REQ_FLIT request packet uses a write unique partial cache line request (WRITEUNIQUEPTL); if AW... If CACHE[3:2] is not equal to 2'h0, and WSTRB_ALL_EN=1, then the OPCODE field in the REQ_FLIT request packet of the CHI protocol uses a write-unique full cache line request (WRITEUNIQUEFULL). In the example, the key field values ​​in the converted REQ_FLIT packet are: 1st REQ_FLIT packet: ADDR='h2000, OPCODE=WRITEUNIQUEFULL, SIZE='h6; 2nd REQ_FLIT packet: ADDR='h2040, OPCODE=WRITEUNIQUEFULL, SIZE='h6; 3rd REQ_FLIT packet: ADDR='h2080, OPCODE=WRITEUNIQUEPTL, SIZE='h6.

[0086] Step 305: Receive each CHI write request periodically sent by the fourth cache queue through the preset CHI interface protocol processing function module. After obtaining the write data and sending the response signal, notify the AXI request queue to return the AXI write request completion response. At the same time, the fourth cache queue continues to process the write requests according to the CHI protocol specifications.

[0087] In this embodiment of the disclosure, the CHI write request after conversion is sent to the CHI_HANDLE module. One REQ_FLIT request packet can be sent in each cycle without waiting for the previous CHI write request to be processed.

[0088] Step 306: After receiving the write data sendable response signal returned by the CHI write request through the preset request processing module, the write data sendable response signal is forwarded to the corresponding target cache queue in the fourth cache queue. The write data sendable response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and at the same time notifies the third cache queue. The write data involved in the target AXI write request is stored in the preset target AXI write request storage module.

[0089] Specifically, when saving the split target AXI write request to the target AXI write request cache module (AW_CMD_BUFFER), the write data is simultaneously stored in the target AXI write request storage module (W_DATA_BUFFER). Furthermore, the corresponding write data validity bits and write request identifier are also stored in W_DATA_BUFFER for verifying and identifying the write data.

[0090] In this embodiment, the data to be written is still in W_DATA_BUFFER. CHI_HANDLE receives a response signal (CRSP_FLIT) indicating that the data to be written in the target AXI write request is ready to be sent. The purpose of CRSP_FLIT in the CHI protocol is to indicate the address of the underlying module to which the data to be written in the target AXI write request should be sent, and simultaneously to notify the third buffer queue. CHI_HANDLE forwards the received CRSP_FLIT to the corresponding CHI_QUEUE. In this example, assuming the first returned CRSP_FLIT corresponds to CHI_QUEUE5, CHI_QUEUE5 will then proceed with further processing.

[0091] Step 307: After the target cache queue in the fourth cache queue obtains the write data and sends a response signal, it initiates a read request to the storage module of the target AXI write request, and packages the write data of the corresponding address into a write data packet and sends it to the functional module that processes the CHI interface protocol.

[0092] In this embodiment, after receiving CRSP_FLIT, CHI_QUEUE5 initiates a data request to W_DATA_BUFFER using the write request identifier (NEW_WID2), reads the write data into CHI_QUEUE5, and generates two write data (DATA_FLIT) packets. The first DATA_FLIT has a DATA field value of DATA4 and a BE field value of WSTRB4; the second DATA_FLIT has a DATA field value of DATA5 and a BE field value of WSTRB5. The two DATA_FLIT packets are then sent sequentially to the CHI_HANDLE module, which sends the write data packets out, completing the CHI write request processing flow. Simultaneously, after receiving the write data sendable response signal, the third buffer queue decrements WDONE_FLAG_CNT by 1.

[0093] In step 308, the functional module that processes the CHI interface protocol sends out the write data packet. The target cache queue in the fourth cache queue completes the CHI protocol process for the current CHI write request and then releases the resources of the fourth cache queue. The cache module and storage module of the target AXI write request corresponding to the write request identifier are also released at the same time and can be used by the next target AXI write request.

[0094] In this embodiment of the disclosure, after CHI_QUEUE5 is processed, CHI_QUEUE5 releases the queue, and the AW_CMD_BUFFER and W_DATA_BUFFER corresponding to NEW_WID are also released at the same time, so that they can be used by the next request.

[0095] Step 309: When the third cache queue receives the completion flags of all split target AXI write requests, it sends a completion signal to the functional module that handles the AXI interface protocol, without waiting for the processing flow of the CHI interface protocol in the fourth cache queue.

[0096] In this embodiment, similarly, after CHI_QUEUE3 and CHI_QUEUE4 execute the same steps 306, 307, and 308, the CHI_QUEUE3 and CHI_QUEUE4 queues are released, and the corresponding NEW_WID's AW_CMD_BUFFER and W_DATA_BUFFER are also released simultaneously. Meanwhile, the final result of AXI_QUEUE1's WDONE_FLAG_CNT is 0, indicating that AXI_QUEUE1 has completed all split target AXI write requests, and WDONE_FLAG_CNT being 0 is an AXI write request completion flag. At this point, a completion signal can be sent to the functional module handling the AXI interface protocol without waiting for the subsequent CHI interface protocol processing flow of CHI_QUEUE to complete. The execution of CHI_QUEUE3, CHI_QUEUE4, and CHI_QUEUE5 is not restricted by order, and the execution of AXI_QUEUE1 after WDONE_FLAG_CNT is 0 is not restricted by CHI_QUEUE.

[0097] Step 310: Based on the completion signal, release other internal cache resources and reset to the initial state for processing new AXI write requests, thus completing the AXI write request process.

[0098] In this embodiment, AXI_QUEUE1 returns a completion signal (BVALID) to the AXI_HANDLE module, indicating that the target AXI write request is valid. After the AXI_HANDLE module completes the AXI protocol communication (performing the AXI protocol handshake), AXI_QUEUE1 is released, completing the entire AXI write request processing flow and becoming available for subsequent new AXI write requests. Other internal cache resources include the third cache queue's own cache, residual resources in the fourth cache queue, local caches of the functional modules handling the AXI / CHI interface protocols, and residual data from the storage module of the target AXI write request.

[0099] In the method for converting the AXI protocol to the CHI protocol in this embodiment, an AXI write request is received, wherein the address of the AXI write request is not related to the address in the third cache queue, and the third cache queue is a cache queue for managing AXI write requests; based on the total data volume of the AXI write request, the received AXI write request is split into multiple target AXI write requests that conform to the single data volume size of the CHI interface protocol, and these targets are deployed in the third cache queue respectively; each target AXI write request in the third cache queue is stored in a preset target AXI write request cache module; and the target AXI write request is stored in the target AXI write request cache module according to the target AXI write request cache module. The AXI write request's cache attributes are used to convert the target AXI write request into a CHI write request of the corresponding request type in the CHI interface protocol, and deployed in the fourth cache queue managing CHI write requests. A pre-defined CHI interface protocol processing module receives each CHI write request periodically sent from the fourth cache queue and processes the write requests according to the CHI protocol specifications. A pre-defined request processing module receives the write data sendable response signal returned by the CHI write request and forwards it to the corresponding target cache queue in the fourth cache queue. The write data sendable response signal is used to... The protocol instructs the target AXI write request to write the data to the address of the lower-level module, and simultaneously notifies the third cache queue; the write data involved in the target AXI write request is stored in the preset storage module of the target AXI write request; after the corresponding target cache queue in the fourth cache queue receives the write data and sends a response signal, it initiates a read request to the storage module of the target AXI write request, packages the write data at the corresponding address into a write data packet, and sends it to the functional module that processes the CHI interface protocol; the functional module that processes the CHI interface protocol sends out the write data packet, and the corresponding target cache queue in the fourth cache queue completes the current CHI write request. The CHI protocol process is initiated, and then the fourth cache queue resources are released. Simultaneously, the cache module and storage module for the target AXI write request, corresponding to the write request identifier, are also released and made available for the next target AXI write request. Meanwhile, when the third cache queue receives completion identifiers for all split target AXI write requests, a completion signal is sent to the functional module handling the AXI interface protocol, without waiting for the CHI interface protocol processing flow in the fourth cache queue. Based on the completion signal, other internal cache resources are released and the system is reset to the initial state for processing new AXI write requests, completing the current AXI write request process. Therefore, by combining the cross-protocol cache management mechanism of AXI and CHI protocols, and through multi-level cache queues and protocol conversion modules, efficient data interaction between AXI and CHI protocols is achieved. Write requests on the AXI interface can receive write completion responses in advance, improving the overall efficiency of the write channel.

[0100] In summary, to clearly describe the principle behind the method of converting the AXI protocol to the CHI protocol, Figure 4 This is a schematic diagram illustrating the principle of a method for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure, as shown below. Figure 4 As shown. The AXI protocol function processing module receives and processes AXI requests. The AXI protocol data conversion module splits the received AXI requests into target AXI read / write requests conforming to the data access types supported by the CHI interface protocol (e.g., multiple target AXI read / write requests conforming to the single data volume size of the CHI interface protocol). The AXI request command buffer and data buffer module caches the parsed target AXI read / write requests and the related write data. The AXI command to CHI command module converts the target AXI read / write requests into read / write requests of the corresponding request type in the CHI interface protocol; and converts the write data involved in the AXI write request into write data of the corresponding data packet type in the CHI interface protocol. The CHI protocol function processing module receives the converted read / write requests and write data, and processes the requests according to the CHI protocol specifications.

[0101] like Figure 4 As shown, the AXI protocol data conversion module, in this example, uses 16 first or third buffer queues (AXI_QUEUE0, ..., AXI_QUEUE15) for illustration; the AXI request command buffer and data buffer module includes a buffer module for target AXI read requests (AR_CMD_BUFFER), a storage module for target AXI read requests (R_DATA_BUFFER), a buffer module for target AXI write requests (AW_CMD_BUFFER), and a storage module for target AXI write requests (W_DATA_BUFFER); the AXI command to CHI command module, in this example, uses 32 second or fourth buffer queues (CHI_QUEUE0, ..., CHI_QUEUE31) for illustration.

[0102] Figure 5 This is a schematic diagram of the structure of an apparatus for converting the AXI protocol to the CHI protocol according to an embodiment of this disclosure.

[0103] like Figure 5 As shown, this is an apparatus for converting the AXI protocol to the CHI protocol, comprising: a receiving module 501, a splitting module 502, a caching module 503, a conversion module 504, and a request processing module 505.

[0104] The receiving module 501 is used to receive AXI requests, including AXI read / write requests.

[0105] The splitting module 502 is used to split the received AXI read and write requests into multiple target AXI read and write requests that conform to the single data volume size of the CHI interface protocol, based on the total amount of data that the AXI read and write requests need to access.

[0106] The caching module 503 is used to cache the split target AXI read / write requests and the write data involved in the target AXI write requests;

[0107] The conversion module 504 is used to convert the cached target AXI read / write request into a read / write request of the corresponding request type of the CHI interface protocol; and to convert the write data involved in the AXI write request into write data of the corresponding data packet type of the CHI interface protocol.

[0108] The request processing module 505 is used to receive the converted read / write requests and write data, and process the requests in accordance with the CHI protocol specifications.

[0109] In one embodiment of this disclosure, in response to the target AXI request being an AXI read request, the apparatus includes: a receiving module 501, configured to receive an AXI read request, wherein the AXI read request address is not related to an address in a first cache queue, and the first cache queue is a cache queue for managing AXI read requests; a splitting module 502, configured to split the received AXI read request based on the total amount of data to be accessed by the AXI read request, splitting it into multiple target AXI read requests conforming to the single data volume size of the CHI interface protocol, and deploying them respectively in the first cache queue; and a caching module 503, configured to cache the first cache queue. Each target AXI read request in the queue is stored in a preset target AXI read request cache module; the conversion module 504 is used to convert the CHI request according to the cache attributes of the target AXI read request in the target AXI read request cache module, converting the target AXI read request into a CHI read request of the corresponding request type of the CHI interface protocol, and deploying it in the second cache queue that manages CHI read requests; the request processing module 505 is used to receive each CHI read request periodically sent by the second cache queue through a preset CHI interface protocol processing function module, and process the read request according to the CHI protocol specification.

[0110] In one embodiment of this disclosure, the read request processing according to the CHI protocol specification includes: a first forwarding module, used to receive read response data returned by a CHI read request through a preset CHI interface protocol processing functional module, and forward it to the corresponding target cache queue in the second cache queue; wherein, the read response data includes the read data block and the read request identifier; a writing module, used to, after the target cache queue in the second cache queue obtains the read response data, first complete the CHI interface handshake protocol, then write the data block and the read request identifier into the preset target AXI read request storage module, and notify the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, so that it can be used by the next target AXI read request; a first reading module, used to, after the first cache queue receives that all the split target AXI read requests have been completed, read each data block from the storage module based on the read request identifier and return it to the AXI interface protocol processing functional module; a first processing module, used to perform AXI protocol handshake processing based on the AXI interface protocol processing functional module to complete the current AXI read request process.

[0111] In one embodiment of this disclosure, in response to the target AXI request being an AXI write request, the apparatus includes: a receiving module 501, configured to receive an AXI write request, wherein the address of the AXI write request is not related to the address in a third cache queue, and the third cache queue is a cache queue for managing AXI write requests; a splitting module 502, configured to split the received AXI write request based on the total data volume of the AXI write request, splitting it into multiple target AXI write requests conforming to the single data volume size of the CHI interface protocol, and deploying them respectively in the third cache queue; and a caching module 503, configured to store each of the target AXI write requests in the third cache queue in a preset target AXI. In the write request caching module, the conversion module 504 is used to convert the CHI request according to the cache attributes in the target AXI write request of the target AXI write request, convert the target AXI write request into a CHI write request of the corresponding request type of the CHI interface protocol, and deploy it in the fourth cache queue that manages CHI write requests; the request processing module 505 is used to receive each CHI write request periodically sent by the fourth cache queue through a preset CHI interface protocol processing function module, and after obtaining a write data ready to send a response signal, notify the AXI request queue to return the AXI write request completion response, while the fourth cache queue continues to process the write request according to the CHI protocol specification.

[0112] In one embodiment of this disclosure, the apparatus further includes: a second forwarding module, configured to receive a write data transmittable response signal returned by a CHI write request through a preset request processing module, and forward it to the corresponding target cache queue in the fourth cache queue; wherein, the write data transmittable response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and simultaneously notifies the third cache queue; the write data involved in the target AXI write request is stored in a preset target AXI write request storage module; a second reading module, configured to, after the target cache queue in the fourth cache queue receives the write data transmittable response signal, initiate a read request to the storage module of the target AXI write request, package the write data at the corresponding address into a write data packet and send it to the functional module processing the CHI interface protocol; a first sending module, configured to send the write data packet to the corresponding target cache queue in the fourth cache queue. The cache queue completes the CHI protocol process for the current CHI write request, then releases the resources of the fourth cache queue. Simultaneously, the cache module and storage module for the target AXI write request corresponding to the write request identifier are also released, making them available for the next target AXI write request. Meanwhile, when the third cache queue receives completion identifiers for all split target AXI write requests, it sends a completion signal to the functional module handling the AXI interface protocol, without waiting for the CHI interface protocol processing flow in the fourth cache queue. The second processing module, based on the completion signal, releases other internal cache resources and resets to the initial state for processing new AXI write requests, completing the current AXI write request process. These other internal cache resources include the third cache queue's own cache, residual resources in the fourth cache queue, the local cache of the functional module handling the AXI / CHI interface protocol, and residual data in the storage module of the target AXI write request.

[0113] The apparatus for converting the AXI protocol to the CHI protocol according to this embodiment of the present disclosure splits the received AXI read / write request into multiple target AXI read / write requests that conform to the single data volume size of the CHI interface protocol, based on the total data volume required for the AXI read / write request. It caches the split target AXI read / write requests and the related write data; converts the cached target AXI read / write requests into read / write requests of the corresponding request type of the CHI interface protocol; converts the write data into write data of the corresponding data packet type of the CHI interface protocol; receives the converted read / write requests and write data, and processes the requests according to the CHI protocol specifications. Therefore, by splitting and converting AXI requests, multiple target AXI read / write requests can be operated simultaneously, improving the parallelism of data access; facilitating the management of data resources of different interface protocols; and improving conversion efficiency.

[0114] According to a third aspect of the present disclosure, an electronic device is also provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor is configured to: implement the method of converting the AXI protocol to the CHI protocol as described above.

[0115] To implement the above embodiments, this disclosure also proposes a storage medium.

[0116] When the instructions in the storage medium are executed by the processor, the processor is able to execute the AXI protocol to CHI protocol method as described above.

[0117] To implement the above embodiments, this disclosure also provides a computer program product.

[0118] When the computer program product is executed by the processor of the electronic device, it enables the electronic device to perform the above-described method.

[0119] Figure 6 This is a structural block diagram of an electronic device according to an exemplary embodiment. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0120] like Figure 6 As shown, the electronic device 600 includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from memory 606 into a random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device 600. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0121] The following components are connected to I / O interface 605: memory 606 including hard disk; and communication section 607 including network interface card such as local area network (LAN) card, modem, etc., communication section 607 performs communication processing via network such as Internet; driver 608 is also connected to I / O interface 605 as needed.

[0122] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 607. When the computer program is executed by processor 601, it performs the functions defined in the methods of this disclosure.

[0123] In an exemplary embodiment, a storage medium including instructions is also provided, such as a memory including instructions, which can be executed by a processor 601 of an electronic device 600 to perform the above-described method. Optionally, the storage medium may be a non-transitory computer-readable storage medium, such as a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0124] In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0125] Furthermore, the term “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as advantageous compared to other aspects or designs. Rather, the use of the term “exemplary” is intended to present the concept in a concrete manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X applies A or B” is intended to mean any of the natural inclusive arrangements. That is, “X applies A or B” satisfies any of the foregoing instances if X applies A; X applies B; or both X applies A and B. Additionally, unless otherwise specified or clear from the context to refer to the singular form, the articles “a” and “an” as used in this application and the appended claims are generally understood to mean “one or more.”

[0126] Similarly, although this disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and variations and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if structurally not equivalent to the disclosed structure. Furthermore, although specific features of this disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations, as may be desired and advantageous to any given or particular application. Moreover, with regard to the terms “comprising,” “owning,” “having,” “having,” or variations thereof as used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term “including.”

[0127] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0128] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for converting AXI protocol to CHI protocol, characterized in that, The method includes: Receive AXI requests, including AXI read and write requests; Based on the total amount of data that the AXI read / write request needs to access, the received AXI read / write request is split into multiple target AXI read / write requests that conform to the single data volume size of the CHI interface protocol. The split target AXI read / write requests and the write data involved in the target AXI write requests are cached. Convert the cached target AXI read / write request into a read / write request of the corresponding request type in the CHI interface protocol; convert the write data involved in the AXI write request into write data of the corresponding data packet type in the CHI interface protocol; It receives the converted read / write requests and write data, and processes the requests according to the CHI protocol specifications. In response to the target AXI request being an AXI write request, the method includes: Receive an AXI write request, wherein the address of the AXI write request is not related to the address in the third cache queue, and the third cache queue is a cache queue that manages AXI write requests; Based on the total data volume of the AXI write requests, the received AXI write requests are split into multiple target AXI write requests that conform to the single data volume size of the CHI interface protocol, and deployed in the third cache queue respectively. Each target AXI write request in the third cache queue is stored in a preset target AXI write request cache module; Based on the cache attributes of the target AXI write request in the cache module of the target AXI write request, the CHI request is converted into a CHI write request of the corresponding request type of the CHI interface protocol and deployed in the fourth cache queue that manages CHI write requests. The pre-defined CHI interface protocol processing module receives each CHI write request periodically sent by the fourth cache queue. After obtaining the write data response signal returned by the CHI write request, it notifies the third cache queue to return the AXI write request completion response. At the same time, the fourth cache queue continues to process the write request according to the CHI protocol specification. The write request processing according to the CHI protocol specifications includes: After receiving the write data response signal returned by the CHI write request through the preset request processing module, the module forwards it to the corresponding target cache queue in the fourth cache queue. The write data response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and at the same time notifies the third cache queue. The write data involved in the target AXI write request is stored in the preset target AXI write request storage module. After the target cache queue in the fourth cache queue obtains the write data and sends a response signal, it initiates a read request to the storage module of the target AXI write request, packages the write data of the corresponding address into a write data packet and sends it to the functional module that processes the CHI interface protocol. The functional module that processes the CHI interface protocol sends out the write data packet. The target cache queue in the fourth cache queue completes the CHI protocol process for the current CHI write request and then releases the resources of the fourth cache queue. The cache module and storage module of the target AXI write request corresponding to the write request identifier are also released at the same time for use by the next target AXI write request. Meanwhile, when the third cache queue receives the completion flags of all split target AXI write requests, it sends a completion signal to the functional module that handles the AXI interface protocol, without waiting for the processing flow of the CHI interface protocol in the fourth cache queue. Based on the completion signal, other internal cache resources are released and the system is reset to the initial state for processing new AXI write requests, thus completing the AXI write request process. The other internal cache resources include the cache of the third cache queue itself, the residual resources of the fourth cache queue, the local cache of the functional module that processes the AXI interface protocol / CHI interface protocol, and the residual data of the storage module of the target AXI write request.

2. The method according to claim 1, characterized in that, In response to the target AXI request being an AXI read request, the method includes: Receive an AXI read request, wherein the address of the AXI read request is not related to the address in the first cache queue, and the first cache queue is a cache queue that manages AXI read requests; Based on the total amount of data that the AXI read request needs to access, the received AXI read request is split into multiple target AXI read requests that conform to the single data volume size of the CHI interface protocol, and deployed in the first cache queue respectively. Each target AXI read request in the first cache queue is stored in a preset target AXI read request cache module; Based on the cache attributes of the target AXI read request in the cache module of the target AXI read request, the CHI request is converted into a CHI read request of the corresponding request type of the CHI interface protocol and deployed in the second cache queue that manages CHI read requests. The system receives each CHI read request periodically sent by the second cache queue through a pre-defined functional module that processes the CHI interface protocol, and processes the read requests in accordance with the specifications of the CHI protocol.

3. The method according to claim 2, characterized in that, The process of handling read requests according to the CHI protocol specifications includes: The pre-defined functional module for processing the CHI interface protocol receives the read response data returned by the CHI read request and forwards it to the corresponding target cache queue in the second cache queue; the read response data includes the data block to be read and the read request identifier. After the target cache queue in the second cache queue obtains the read response data, it first completes the CHI interface handshake protocol, then writes the data block and read request identifier into the preset storage module of the target AXI read request, and notifies the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, for use by the next target AXI request. Once the first cache queue has received all the split target AXI read requests and completed them, it reads each data block from the storage module based on the read request identifier and returns it to the functional module that processes the AXI interface protocol. Based on the functional module for processing the AXI interface protocol, the handshake process on the AXI protocol side is performed to complete the AXI read request process.

4. A device for converting AXI protocol to CHI protocol, characterized in that, The device includes: The receiving module is used to receive AXI requests, including AXI read and write requests. The splitting module is used to split the received AXI read and write requests into multiple target AXI read and write requests that conform to the single data volume size of the CHI interface protocol, based on the total amount of data that the AXI read and write requests need to access. The caching module is used to cache the split target AXI read / write requests and the write data involved in the target AXI write requests; The conversion module is used to convert the cached target AXI read / write request into a read / write request of the corresponding request type of the CHI interface protocol; and to convert the write data involved in the AXI write request into write data of the corresponding data packet type of the CHI interface protocol. The request processing module is used to receive the converted read / write requests and write data, and process the requests in accordance with the CHI protocol specifications. In response to the target AXI request being an AXI write request, the apparatus includes: The receiving module is used to receive AXI write requests, wherein the address of the AXI write request is not related to the address in the third cache queue, and the third cache queue is a cache queue that manages AXI write requests. The splitting module is used to split the received AXI write requests based on the total data volume of the AXI write requests, splitting them into multiple target AXI write requests that conform to the single data volume size of the CHI interface protocol, and deploying them in the third cache queue respectively; A caching module is used to store each of the target AXI write requests in the third caching queue in a preset target AXI write request caching module; The conversion module is used to convert the CHI request according to the cache attributes of the target AXI write request in the cache module of the target AXI write request, convert the target AXI write request into a CHI write request of the corresponding request type of the CHI interface protocol, and deploy it in the fourth cache queue that manages CHI write requests. The request processing module is used to receive each CHI write request periodically sent by the fourth cache queue through a preset CHI interface protocol processing function module. After obtaining the write data return response signal of the CHI write request, it notifies the third cache queue to return the AXI write request completion response. At the same time, the fourth cache queue continues to process the write request according to the CHI protocol specification. The write request processing according to the CHI protocol specifications includes: The second forwarding module is used to receive the write data sendable response signal returned by the CHI write request through the preset request processing module, and then forward it to the corresponding target cache queue in the fourth cache queue. The write data sendable response signal is used to indicate in the CHI protocol that the write data involved in the target AXI write request is written to the address of the lower-level module, and at the same time notifies the third cache queue. The write data involved in the target AXI write request is stored in the preset target AXI write request storage module. The second reading module is used to send a read request to the storage module of the target AXI write request after the target cache queue in the fourth cache queue obtains the write data and can send a response signal. The module packages the write data of the corresponding address into a write data packet and sends it to the functional module that processes the CHI interface protocol. The first sending module, which is a functional module for processing the CHI interface protocol, sends out the write data packet. The target cache queue in the fourth cache queue completes the CHI protocol process for the current CHI write request and then releases the resources of the fourth cache queue. The cache module and storage module of the target AXI write request corresponding to the write request identifier are also released at the same time for use by the next target AXI write request. Meanwhile, when the third cache queue receives the completion flags of all split target AXI write requests, it sends a completion signal to the functional module that handles the AXI interface protocol, without waiting for the processing flow of the CHI interface protocol in the fourth cache queue. The second processing module is used to release other internal cache resources and reset to the initial state for processing new AXI write requests based on the completion signal, thereby completing the current AXI write request process. The other internal cache resources include the cache of the third cache queue itself, the residual resources of the fourth cache queue, the local cache of the functional module for processing the AXI interface protocol / CHI interface protocol, and the residual data of the storage module of the target AXI write request.

5. The apparatus according to claim 4, characterized in that, In response to the target AXI request being an AXI read request, the apparatus includes: The receiving module is used to receive AXI read requests, wherein the address of the AXI read request is not related to the address in the first cache queue, and the first cache queue is a cache queue that manages AXI read requests; The splitting module is used to split the received AXI read request into multiple target AXI read requests that conform to the single data volume size of the CHI interface protocol, based on the total amount of data that the AXI read request needs to access, and deploy them in the first cache queue respectively. A caching module is used to store each of the target AXI read requests in the first cache queue in a preset target AXI read request caching module; The conversion module is used to convert the CHI request according to the cache attribute of the target AXI read request in the cache module of the target AXI read request, convert the target AXI read request into a CHI read request of the corresponding request type of the CHI interface protocol, and deploy it in the second cache queue that manages CHI read requests. The request processing module is used to receive each CHI read request sent periodically by the second cache queue through a preset CHI interface protocol processing function module, and process the read requests in accordance with the CHI protocol specifications.

6. The apparatus according to claim 5, characterized in that, The process of handling read requests according to the CHI protocol specifications includes: The first forwarding module is used to receive the read response data returned by the CHI read request through the preset functional module for processing the CHI interface protocol, and forward it to the corresponding target cache queue in the second cache queue; wherein, the read response data includes the read data block and the read request identifier; The write module is used to complete the CHI interface handshake protocol after the target cache queue corresponding to the second cache queue obtains the read response data, and then write the data block and read request identifier into the preset storage module of the target AXI read request, and notify the first cache queue that the current CHI read request has been completed; at the same time, the second cache queue releases the queue, and the cache module of the target AXI read request corresponding to the read request identifier is also released at the same time, for use by the next target AXI read request. The first reading module is used to read each data block from the storage module based on the read request identifier and return it to the functional module that processes the AXI interface protocol after the first cache queue has received all the split target AXI read requests. The first processing module is used to perform handshake processing on the AXI protocol side based on the functional module for processing the AXI interface protocol, and complete the current AXI read request process.

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