Display device and reset circuit thereof

Abstract

The invention provides a display device and a reset circuit of the display device, and belongs to the technical field of display driving. The display device comprises a power management chip, a time schedule controller and a reset circuit. Wherein the reset circuit is connected with the power management chip and the time schedule controller, and comprises a phase inverter and a trigger circuit. The phase inverter is used for accessing a scanning direction switching signal and generating an inverted signal opposite to the scanning direction switching signal in phase. The trigger circuit is connected with the phase inverter and is used for outputting a reset signal in a pulse form to the time schedule controller at the edge moment of the scanning direction switching signal according to the scanning direction switching signal and the phase inversion signal so as to reset the time schedule controller; therefore, no matter the switching of the scanning direction occurs in the frame gap or the frame of the picture, the reset restart of the time schedule controller can be triggered, and the reset circuit is constructed by the phase inverter and the separated circuit elements in the trigger circuit, so that an integrated chip is not needed, and the cost for realizing the reset of the time schedule controller can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display driving, in particular to a display device and a reset circuit of the display device. BACKGROUND

[0002] Large-screen display effect is usually realized by splicing and combining multiple display panels. In order to adapt to different signal source output formats and panel driving logic, a display device for splicing generally needs to support two working modes of forward scanning (forward scan) and reverse scanning (reverse scan). In the forward scan mode, picture signals are transmitted and displayed row by row in the order from left to right and from top to bottom; in the reverse scan mode, signal scanning is completed in the opposite direction.

[0003] At present, the switching between the forward scan mode and the reverse scan mode is generally triggered by manual operation, and the switching time is random. When the switching action occurs within a frame, the scanning direction and the pixel data transmission order of the previous and subsequent frames will be momentarily confused, resulting in a mismatch between the driving timing of the display panel and the pixel lighting logic, and further causing picture abnormal problems such as picture tearing and ghosting. To solve this problem, the timing controller of the display panel needs to be reset when the scanning direction is switched, so that the driving timing is reinitialized to ensure the consistency of picture display.

[0004] In some common reset methods, when receiving the control signal of scanning direction switching, an integrated chip detects the signal jump and generates a corresponding reset signal to trigger the reset of the timing controller. However, the integrated chip is relatively expensive, which increases the cost of implementing the reset of the timing controller. SUMMARY

[0005] Embodiments of the present application provide a display device to at least partially solve the above technical problems.

[0006] In order to achieve the above purpose, according to the first aspect of the present application, a display device is provided, comprising: a power management chip; a timing controller; a reset circuit connected with the power management chip and the timing controller, comprising: an inverter for accessing the scanning direction switching signal and generating an inverted signal opposite in phase to the scanning direction switching signal; a trigger circuit connected with the inverter, for outputting a reset signal in the form of a pulse to the timing controller according to the scanning direction switching signal and the inverted signal at the edge time of the scanning direction switching signal, and resetting the timing controller.

[0007] Optionally, the inverter comprises a first transistor and a second transistor. The first transistor includes a first electrode connected to the power management chip, a second electrode connected to the second transistor at the signal output node, and a control electrode for receiving the scan direction switching signal; The second transistor includes a first electrode connected to the signal output node, a grounded second electrode, and a control electrode for receiving the scan direction switching signal; The first transistor and the second transistor are of different types.

[0008] Optionally, the triggering circuit includes a first trigger sub-circuit and a second trigger sub-circuit; The first trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the rising edge of the scan direction switching signal under the drive of the scan direction switching signal. The second trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the falling edge of the scan direction switching signal under the drive of the inverting signal.

[0009] Optionally, the first trigger sub-circuit includes a third transistor; The third transistor includes a first electrode connected to the inverter to receive the inverted signal, a second electrode connected to the reset terminal of the timing controller, and a control electrode connected to the scan direction switching signal.

[0010] Optionally, the second trigger sub-circuit includes a fourth transistor; The fourth transistor includes a first electrode for receiving the scan direction switching signal, a second electrode connected to the reset terminal of the timing controller, and a control electrode connected to the inverter to receive the inverted signal.

[0011] Optionally, the reset circuit further includes a pull-up circuit connected to the power management chip and the timing controller to maintain the high level of the reset signal; The pull-up circuit includes a resistor connected between the power management chip and the reset terminal of the timing controller.

[0012] Optionally, the reset circuit further includes a ramp-up sub-circuit connected to the reset terminal of the timing controller, used to control the potential recovery time of the reset signal during the input of the reset signal in the form of a pulse to the timing controller; The climbing sub-circuit includes a capacitor; The capacitor includes a first terminal connected to the reset terminal of the timing controller and a second terminal grounded.

[0013] Optionally, it also includes a gate driver connected to the timing controller. After receiving the scan direction switching signal and resetting it through the reset signal, the timing controller drives the gate driver to switch the scan direction.

[0014] According to a second aspect of this application, a reset circuit for a display device is provided, comprising: An inverter is used to receive the scan direction switching signal and generate an inverted signal that is opposite in phase to the scan direction switching signal; A trigger circuit, connected to the inverter, is used to output a pulse-shaped reset signal to the timing controller at the edge of the scanning direction switching signal based on the scanning direction switching signal and the inverted signal, thereby resetting the timing controller.

[0015] Optionally, the triggering circuit includes a first trigger sub-circuit and a second trigger sub-circuit; The first trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the rising edge of the scan direction switching signal under the drive of the scan direction switching signal. The second trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the falling edge of the scan direction switching signal under the drive of the inverting signal. In summary, in this application, the inverter in the reset circuit receives the scan direction switching signal and generates an inverted signal. The trigger circuit, based on the scan direction switching signal and its inverted signal, outputs a pulse-shaped reset signal to the timing controller at the edge of the scan direction switching signal. This allows the timing controller to respond promptly to the switching action between forward and reverse scans. Regardless of whether the scan direction switching occurs between frames or within a frame, the timing controller can be reset and restarted, thereby eliminating display abnormalities during the switching process. Furthermore, the reset circuit is constructed from separate circuit components in the inverter and trigger circuit, eliminating the need for additional integrated chips and reducing the cost of implementing the timing controller reset.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a schematic diagram of a display device provided in an exemplary embodiment of this disclosure; Figure 2 This is a waveform diagram of the reset signal provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of another display device provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of the current flow direction in a reset circuit provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of another current flow direction in the reset circuit provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the architecture of a display device provided in an exemplary embodiment of this disclosure.

[0019] Figure reference numerals: 10, Power management chip; 20, Timing controller; 30, Reset circuit; 31, Inverter; 32, Trigger circuit; 321, First trigger sub-circuit; 322, Second trigger sub-circuit; 33, Pull-up sub-circuit; 34, Climbing sub-circuit; Q1, First transistor; Q2, Second transistor; Q3, Third transistor; Q4, Fourth transistor; R1, Resistor; C1, Capacitor; Rev, Scan direction switching signal; Reset, Reset signal; 40, Gate driver; 50, Source driver. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] According to the first aspect of this application, referring to Figure 1This disclosure provides a display device, including a power management chip 10, a timing controller 20, and a reset circuit 30. The reset circuit 30, connected to the power management chip 10 and the timing controller 20, includes an inverter 31 and a trigger circuit 32. The inverter 31 receives a scan direction switching signal Rev and generates an inverted signal opposite in phase to Rev. The trigger circuit 32, connected to the inverter 31, outputs a pulse-shaped reset signal Reset to the timing controller 20 based on the scan direction switching signal Rev and the inverted signal, at the edge of the scan direction switching signal Rev, thereby resetting the timing controller 20.

[0022] The scan direction switching signal Rev indicates that the timing controller 20 needs to control the scanning direction switching of the display panel, such as switching from forward scanning to reverse scanning or from reverse scanning to forward scanning. The edges of the scan direction switching signal Rev include rising and falling edges. The rising edge occurs when the scan direction switching signal Rev changes from a low level to a high level, and the falling edge occurs when the scan direction switching signal Rev changes from a high level to a low level. For example, when the scan direction switching signal Rev is low, it indicates that the display panel needs to switch scanning directions. In this case, a reset signal Reset will be output at at least one of the rising and falling edges to reset the timing controller 20.

[0023] The pulse-type reset signal Reset refers to an electrical signal whose level changes suddenly within a short period of time and then quickly returns to its initial value. For example, the reset signal Reset can first maintain a normal level, then switch to a reset level, and then quickly return to a normal level. When the reset signal Reset is in a normal level state, the timing controller 20 works normally, ensuring a continuous and stable output of the display device. When the reset signal Reset is in a reset level state, it triggers the timing controller 20 to reset. When the scan direction switching signal Rev is at its edge, the reset signal Reset will instantaneously switch from a normal level state to a reset level state, forming a narrow pulse; then the reset signal Reset will immediately return to a normal level state, thus completing a "normal-reset-normal" pulse cycle, ensuring that the timing controller 20's reset action can be accurately triggered during scan direction switching and can quickly return to normal operation after the reset is completed. For example, the reset level state of the reset signal Reset can be a low level state, in which case the timing controller 20 is driven to start resetting; the normal level state of the reset signal Reset can be a high level state, allowing the timing controller 20 to drive the display panel normally for display.

[0024] In the above embodiment, the inverter 31 in the reset circuit 30 receives the scan direction switching signal Rev and generates an inverted signal. The trigger circuit 32, based on the scan direction switching signal Rev and its inverted signal, outputs a pulse-shaped reset signal Reset to the timing controller 20 at the edge of the scan direction switching signal Rev. This allows the timing controller 20 to respond promptly to the switching action between forward and reverse scans. Regardless of whether the scan direction switching occurs between frames or within a frame, the timing controller 20 can be reset and restarted, thereby eliminating display abnormalities during the switching process. Furthermore, the reset circuit 30 is constructed from separate circuit elements in the inverter 31 and the trigger circuit 32, eliminating the need for integrated chips and reducing the cost of resetting the timing controller 20.

[0025] In some embodiments, the inverter 31 includes a first transistor Q1 and a second transistor Q2. The first transistor Q1 includes a first electrode connected to the power management chip 10, a second electrode connected to the second transistor Q2 at a signal output node, and a control electrode for receiving the scan direction switching signal Rev. The second transistor Q2 includes a first electrode connected to the signal output node, a grounded second electrode, and a control electrode for receiving the scan direction switching signal Rev. The first transistor Q1 and the second transistor Q2 are of different types.

[0026] As an example, taking a P-type transistor Q1 and an N-type transistor Q2 as an example, the conduction condition of the first transistor Q1 is that the control electrode voltage is lower than the source voltage, and the conduction condition of the second transistor Q2 is that the control electrode voltage is higher than the source voltage. The control electrodes of the first transistor Q1 and the second transistor Q2 are simultaneously connected to the scan direction switching signal Rev. When the scan direction switching signal Rev is high, the control electrode voltage of the first transistor Q1 is higher than its first electrode, and at this time, the first transistor Q1 disconnects the line connection between the power supply and the signal output node. Simultaneously, the control electrode voltage of the second transistor Q2 is higher than its second electrode, and the second transistor Q2 conducts between the signal output node and ground, causing the output node to present a low level, making the inverted signal low. Conversely, when the scan direction switching signal Rev is low, the first transistor Q1 is turned on, and the voltage source output by the power management chip 10 supplies power to the signal output node through the first transistor Q1 to output a high-level inverted signal; while the second transistor Q2 is turned off, disconnecting the path between the signal output node and ground. In this way, an inverted signal with the opposite phase to the scan direction switching signal Rev can be output.

[0027] Reference Figure 1 and Figure 2In some embodiments, the trigger circuit 32 includes a first trigger sub-circuit 321 and a second trigger sub-circuit 322. The first trigger sub-circuit 321 is electrically connected to the inverter 31 and receives the scan direction switching signal Rev. Driven by the scan direction switching signal Rev, it outputs a pulse-form reset signal Reset at the rising edge of the scan direction switching signal Rev based on the inverted signal. The second trigger sub-circuit 322 is electrically connected to the inverter 31 and receives the scan direction switching signal Rev. Driven by the inverted signal, it outputs a pulse-form reset signal Reset at the falling edge of the scan direction switching signal Rev based on the scan direction switching signal Rev.

[0028] In the above embodiments, the first trigger sub-circuit 321 can output a pulse-shaped reset signal Reset at the rising edge of the scan direction switching signal Rev, and the second trigger sub-circuit 322 can output a pulse-shaped reset signal Reset at the falling edge of the scan direction switching signal Rev, so that the timing controller 20 can be reset in a timely manner when the display panel needs to switch scan directions. Furthermore, both the first trigger sub-circuit 321 and the second trigger sub-circuit 322 are driven by the inverted signal and the scan direction switching signal Rev, requiring no additional drive signal, which helps to simplify the circuit topology.

[0029] Reference Figure 1 In some embodiments, the first trigger sub-circuit 321 includes a third transistor Q3. The third transistor Q3 includes a first electrode connected to the inverter 31 to receive an inverted signal, a second electrode connected to the reset terminal of the timing controller 20, and a control electrode connected to the scan direction switching signal Rev.

[0030] Reference Figure 1 In some embodiments, the second trigger sub-circuit 322 includes a fourth transistor Q4. The fourth transistor Q4 includes a first electrode for receiving the scan direction switching signal Rev, a second electrode connected to the reset terminal of the timing controller 20, and a control electrode connected to the inverter 31 to receive the inverted signal.

[0031] As an example, the third transistor Q3 and the fourth transistor Q4 can be P-type transistors. The fourth transistor Q4 is turned on by the inverting signal, and in this state, it transmits the scan direction switching signal Rev to the reset terminal of the timing controller 20 as the reset signal Reset. The third transistor Q3 is turned on by the scan direction switching signal Rev, and in this state, it transmits the inverted signal to the reset terminal of the timing controller 20 as the reset signal Reset.

[0032] Reference Figure 3In some embodiments, the reset circuit 30 further includes a pull-up circuit 33 connected to the power management chip 10 and the timing controller 20 to maintain the high level of the reset signal Reset. The pull-up circuit 33 includes a resistor R1 connected between the reset terminal of the power management chip 10 and the timing controller 20.

[0033] In the above embodiment, resistor R1 is connected to power management chip 10. During the normal display phase, resistor R1 can pull the potential of the reset terminal of timing controller 20 to a high level, so as to avoid abnormal drop in the potential of the reset terminal of timing controller 20 due to leakage current or external interference, thereby preventing the reset circuit 30 from being falsely triggered and causing the timing controller 20 to be falsely reset, which would affect the normal display.

[0034] Reference Figure 3 In some embodiments, the reset circuit 30 further includes a ramp-up sub-circuit 34 connected to the reset terminal of the timing controller 20, for controlling the potential recovery duration of the reset signal Reset during the input pulse form of the reset signal Reset to the timing controller 20. The ramp-up sub-circuit 34 includes a capacitor C1. The capacitor C1 includes a first terminal connected to the reset terminal of the timing controller 20 and a second terminal grounded.

[0035] In the above embodiment, the ramp-up sub-circuit 34 is connected to the reset terminal of the timing controller 20 via a grounded capacitor C1, which can control the potential recovery time of the reset signal Reset. When the pulse-type reset signal Reset pulls the potential of the reset terminal low, the capacitor C1 discharges; while during the process of the reset signal Reset transitioning from a low level to a high level, the capacitor C1 charges, thereby slowing down the speed at which the potential of the reset terminal of the timing controller 20 rises back to a high level, thus controlling the ramp-up time of the reset signal Reset, so that the timing controller 20 has sufficient time to reset.

[0036] Reference Figure 6 In some embodiments, the display device further includes a gate driver 40 connected to a timing controller 20. After receiving a scan direction switching signal Rev and resetting it via a reset signal Reset, the timing controller 20 drives the gate driver 40 to switch the scan direction.

[0037] Reference Figure 6 The architecture of the display device will be further described below. The display device also includes a power management chip 10, a source driver 50, and a gate driver 40.

[0038] The display device includes a display area 60, which may include multiple scan lines G1 to Gn, multiple data lines D1 to Dm intersecting the scan lines G1 to Gn, and multiple pixel units respectively disposed in multiple regions defined by the intersections of the scan lines G1 to Gn and the data lines D1 to Dm. For example, a pixel unit may include a thin-film transistor, which includes a gate and a source respectively connected to the corresponding scan line and data line. When a scan line is selected from the multiple scan lines G1 to Gn, the thin-film transistor of the pixel unit connected to the selected scan line is turned on, and then the source driver 50 can apply a voltage to the multiple data lines D1 to Dm, thereby displaying an image.

[0039] The power management chip 10 provides analog voltage as a power supply for the reset circuit 30, timing controller 20, source driver 50, and gate driver 40. The timing controller 20 receives image data and control signals, and performs preprocessing such as format conversion and data sorting on the image data to obtain a data signal. Simultaneously, the timing controller 20 also generates control signals and clock signals. These data signals and control signals are then sent to the source driver 50 and gate driver 40, respectively. The gate driver 40 receives the control signals and clock signals from the timing controller 20 to generate progressive scan gate drive signals. These gate drive signals sequentially turn the thin-film transistor switches in the display area 60 on or off, controlling the selection of scan lines. After receiving the data signals and control signals from the timing controller 20, the source driver 50 stores the data signals in its internal register and outputs them synchronously according to the scan signals from the gate driver 40.

[0040] Specifically, after the timing controller 20 receives the scan direction switching signal Rev from the motherboard, it switches the control signal and clock signal output to the gate driver 40, enabling the gate driver 40 to switch the scan direction. During this process, after receiving the scan direction switching signal Rev from the motherboard, the reset circuit 30 outputs a reset signal Reset to the timing controller 20 based on the level of the scan direction switching signal Rev, thereby resetting the timing controller 20 to prevent screen abnormalities from occurring during the process of the timing controller 20 driving the gate driver 40 to switch the scan direction.

[0041] Reference Figure 2 Taking the timing controller 20 resetting according to the low-level reset signal Reset as an example, the operation process of the display device is described exemplarily as follows: Combination Figure 4In the first stage, during the period when the scan direction switching signal Rev is high, the first transistor Q1 and the third transistor Q3 are off, the second transistor Q2 is on, and the inverting signal is low, causing the fourth transistor Q4 to turn on. At this time, the output voltage of the power management chip 10 is transmitted to the reset terminal of the timing controller 20 via the fourth transistor Q4 to obtain a high-level reset signal Reset. The timing controller 20 does not perform a reset.

[0042] In the second stage, when the scan direction switching signal Rev changes from a high level to a low level, i.e., when the scan direction switching signal Rev is at its falling edge, the output voltage of the power management chip 10 is quickly pulled down by the scan direction switching signal Rev, causing the potential of the first electrode of the fourth transistor Q4 to be pulled down. The inverter 31 has a certain response time when it outputs the inverted signal according to the scan direction switching signal Rev, so that the inverted signal remains at a low level, keeping the fourth transistor Q4 on at the falling edge. This causes the fourth transistor Q4 to output the low-level reset signal Reset to the reset terminal of the timing controller 20, and the timing controller 20 begins to reset.

[0043] Combination Figure 5 In the third stage, during the period when the scan direction switching signal Rev is low, the second transistor Q2 is off, while the first transistor Q1 and the third transistor Q3 are on, and the inverting signal is high, causing the fourth transistor Q4 to be off. At this time, the output voltage of the power management chip 10 is transmitted to the reset terminal of the timing controller 20 through the first transistor Q1 and the third transistor Q3. During this process, since the fourth transistor Q4 outputs a low-level reset signal Reset in the second stage, combined with the characteristics of capacitor C1, the reset signal Reset will eventually return to a high-level reset signal Reset after a certain potential rise time, giving the timing controller 20 sufficient time to reset.

[0044] In the fourth stage, when the scan direction switching signal Rev transitions from a low level to a high level (i.e., at the rising edge of Rev), the second transistor Q2 turns on, making the inverting signal low. At this time, the first transistor Q1 is not yet off, pulling the potential of the reset terminal of the timing controller 20 low, thus obtaining a low-level reset signal Reset, causing the timing controller 20 to begin resetting. Subsequently, when the scan direction switching signal Rev stabilizes at a high level, the first transistor Q1 turns off, returning to the state of the first stage, and the reset signal Reset turns high. Simultaneously, during the process of the reset signal Reset returning to a high level, the capacitance of capacitor C1 prolongs the rise time of the reset signal Reset, giving the timing controller 20 sufficient time to reset.

[0045] Thus, during the process of the motherboard outputting a low-level scan direction switching signal Rev to the reset circuit 30, at the edge of the scan direction switching signal Rev, the reset circuit 30 will output a pulse signal Reset, causing the reset signal Reset to change from a high-level state to a low-level state, and then autonomously return to a high-level state, so that the timing controller 20 can be reset when the reset signal Reset is in a low-level state.

[0046] According to a second aspect of this application, a reset circuit for a display device is provided, including an inverter 31 and a trigger circuit 32. The inverter 31 receives a scan direction switching signal Rev and generates an inverted signal opposite in phase to the scan direction switching signal Rev. The trigger circuit 32 is connected to the inverter 31 and, based on the scan direction switching signal Rev and the inverted signal, outputs a pulse-shaped reset signal Reset to a timing controller 20 at the edge of the scan direction switching signal Rev, thereby resetting the timing controller 20.

[0047] In some embodiments, the trigger circuit 32 includes a first trigger sub-circuit 321 and a second trigger sub-circuit 322. The first trigger sub-circuit 321 is electrically connected to the inverter 31 and receives the scan direction switching signal Rev. Driven by the scan direction switching signal Rev, it outputs a pulse-form reset signal Reset at the rising edge of the scan direction switching signal Rev according to the inverted signal. The second trigger sub-circuit 322 is electrically connected to the inverter 31 and receives the scan direction switching signal Rev. Driven by the inverted signal, it outputs a pulse-form reset signal Reset at the falling edge of the scan direction switching signal Rev according to the scan direction switching signal Rev. In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0048] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0049] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0050] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display device, characterized in that, include: Power management chip; Timing controller; A reset circuit, connected to the power management chip and the timing controller, includes: An inverter is used to receive a scan direction switching signal and generate an inverted signal that is opposite in phase to the scan direction switching signal; A trigger circuit, connected to the inverter, is used to output a pulse-shaped reset signal to the timing controller at the edge of the scanning direction switching signal based on the scanning direction switching signal and the inverted signal, thereby resetting the timing controller.

2. The display device according to claim 1, characterized in that, The inverter includes a first transistor and a second transistor; The first transistor includes a first electrode connected to the power management chip, a second electrode connected to the second transistor at the signal output node, and a control electrode for receiving the scan direction switching signal; The second transistor includes a first electrode connected to the signal output node, a grounded second electrode, and a control electrode for receiving the scan direction switching signal; The first transistor and the second transistor are of different types.

3. The display device according to claim 1, characterized in that, The triggering circuit includes a first triggering sub-circuit and a second triggering sub-circuit; The first trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the rising edge of the scan direction switching signal under the drive of the scan direction switching signal. The second trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the falling edge of the scan direction switching signal under the drive of the inverting signal.

4. The display device according to claim 3, characterized in that, The first trigger sub-circuit includes a third transistor; The third transistor includes a first electrode connected to the inverter to receive the inverted signal, a second electrode connected to the reset terminal of the timing controller, and a control electrode connected to the scan direction switching signal.

5. The display device according to claim 3, characterized in that, The second trigger sub-circuit includes a fourth transistor; The fourth transistor includes a first electrode for receiving the scan direction switching signal, a second electrode connected to the reset terminal of the timing controller, and a control electrode connected to the inverter to receive the inverted signal.

6. The display device according to any one of claims 1 to 5, characterized in that, The reset circuit also includes a pull-up circuit connected to the power management chip and the timing controller, used to maintain the high level state of the reset signal; The pull-up circuit includes a resistor connected between the power management chip and the reset terminal of the timing controller.

7. The display device according to any one of claims 1 to 5, characterized in that, The reset circuit further includes a creepage sub-circuit, which is connected to the reset terminal of the timing controller and is used to control the potential recovery time of the reset signal during the input of the reset signal in the form of a pulse to the timing controller; The climbing sub-circuit includes a capacitor; The capacitor includes a first terminal connected to the reset terminal of the timing controller and a second terminal grounded.

8. The display device according to claim 1, characterized in that, It also includes a gate driver connected to the timing controller. After receiving the scan direction switching signal and resetting it through the reset signal, the timing controller drives the gate driver to switch the scan direction.

9. A reset circuit for a display device, characterized in that, include: An inverter is used to receive a scan direction switching signal and generate an inverted signal that is opposite in phase to the scan direction switching signal; A trigger circuit, connected to the inverter, is used to output a pulse-shaped reset signal to the timing controller at the edge of the scanning direction switching signal based on the scanning direction switching signal and the inverted signal, thereby resetting the timing controller.

10. The reset circuit of the display device according to claim 9, characterized in that, The triggering circuit includes a first triggering sub-circuit and a second triggering sub-circuit; The first trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the rising edge of the scan direction switching signal under the drive of the scan direction switching signal. The second trigger sub-circuit is electrically connected to the inverter and connected to the scan direction switching signal. It is used to output the reset signal in the form of a pulse at the falling edge of the scan direction switching signal under the drive of the inverting signal.

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