FPGA online upgrading method based on MicroBlaze and PCIE bus

Abstract

The FPGA online upgrading method based on the MicroBlaze and the PCIE bus comprises the steps that a CPU divides a configured file into a plurality of data packages in sequence, each data package comprises a current data package code, a current data package byte length and data package content, and except the data package which is finally divided, the byte lengths of the other data packages are all configured to be bytes with preset sizes; the FPGA receives an online upgrading instruction at the BRAM matching address based on the MicroBlaze; the method comprises the following steps of: writing a data packet into a CPU (Central Processing Unit), erasing an update area of the FLASH, sequentially writing the data packet into a preset storage area of the FLASH through an SPI (Serial Peripheral Interface) protocol, comparing a checksum with a checksum sent by the CPU, feeding back state parameters of online upgrading completion to the CPU by an FPGA end, and quitting online upgrading operation after receiving a quit command sent by the CPU, so that the upgrading efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the technical field of portable display support devices, and particularly relates to an online FPGA upgrade method based on MicroBlaze and PCIe bus. Background Technology

[0002] With the rapid development of information technology, FPGAs (Field-Programmable Gate Arrays) are widely used in monitoring, imaging, and industrial automation due to their powerful performance and high flexibility. Currently, most products undergo continuous updates based on changing needs during production and maintenance, requiring frequent FPGA program upgrades by R&D personnel to ensure normal product operation. Traditionally, FPGA upgrades involve opening the product casing and upgrading the program via USB-JTAG. However, some devices, due to delivery defects or special manufacturing processes, cannot be disassembled for further program upgrades. Therefore, upgrades cannot be performed using dedicated USB-JTAG cables and emulators, necessitating online upgrades.

[0003] Most common online upgrade methods rely on the UART serial port and CPU software to erase and program the FPGA configuration chip's FLASH, achieving online FPGA program upgrades. However, this method is limited by the serial port's error rate, resulting in long upgrade times and slow efficiency, making it difficult to meet diverse, high-speed program upgrade requirements. Generally, using the PCIe bus can solve these problems. MicroBlaze, due to its ease of operation, high portability, and short development cycle in FPGA programming, is widely used in electronic communications, video processing, and other fields. Therefore, MicroBlaze + PCIe bus is an ideal choice for efficient program upgrades. However, the system design combining PCIe bus and MicroBlaze for FPGA online upgrades still faces many challenges, such as how to effectively utilize the characteristics of both to optimize data caching, transmission, and verification processes; how to improve the stability, reliability, and flexibility of the upgrade system across multiple platforms; and how to shorten upgrade time and improve upgrade efficiency—all of which remain unexplored areas.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide an online upgrade method for FPGAs based on MicroBlaze and PCIe bus, effectively reducing the workload of FPGA designers and building an online upgrade system platform that is faster, more stable in transmission, more efficient, and more flexible in structure, thus meeting the diverse application needs of airborne video electronic systems. The technical solution of this invention has many beneficial effects, as described below: An online FPGA upgrade method based on MicroBlaze and PCIe bus is disclosed, applicable to data transmission between the onboard CPU and the FPGA communicating via the PCIe bus interface. The online FPGA upgrade method includes... Step 1: The CPU divides the configured file into multiple data packets in sequence. Each data packet should include the current data packet encoding, the current data packet byte length, and the data packet content. Except for the last data packet to be divided, the byte length of the remaining data packets is configured to a preset size in bytes. The CPU then sends online upgrade instructions and data information to the preset storage space address of the BRAM on the FPGA side via the PCIe bus. The preset storage space address is a region that is separately divided to store data packets. Step 2: After receiving the online upgrade command based on the MicroBlaze BRAM matching address, the FPGA initializes the external FLASH via the SPI bus and reads the FLASH's vendor ID and device ID. If the vendor ID and device ID can be read, proceed to Step 3. If the vendor ID and device ID cannot be read correctly, the FLASH is reset. If the vendor ID and device ID cannot be read correctly after a preset number of resets, the online upgrade is exited. Step 3: Perform an erase operation on the update area of ​​FLASH. If the erase operation is successful, proceed to Step 4. If the erase operation fails, write the address of the FLASH segment that failed to be erased to the specified address in BRAM for the CPU to read. Step 4: The data packets are sequentially written to the preset storage area of ​​the FLASH via the SPI protocol. After the current data packet is written, it is read out and a checksum is calculated. The checksum is compared with the checksum sent by the CPU. If they match, it means that the current data packet has been successfully written to the FLASH, and the next data packet is checked, and so on. If they do not match, it means that the check fails. The FPGA will send the number of the data packet with the current error to the CPU, and exit the online upgrade function or return to step 2 for a maximum of a preset number of loops. If the check still fails, the error data packet number is sent to the CPU for modification using a human-computer interaction method. After all configuration files are sent on the CPU, they are sent in a new order. Step 5: When the FPGA receives the last data packet sent by the CPU, the CPU writes the last data packet number to the preset address in the BRAM. If the FPGA successfully writes the last data packet to the FLASH and completes the verification, the FPGA sends a notification to the CPU that the online upgrade is complete, receives an exit command, and executes the corresponding steps. Exit the online upgrade process.

[0006] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: The method of this invention reduces the complexity and cost of FPGA program upgrades. It eliminates the need for developers to disassemble the FPGA and use a simulator for upgrades; software engineers can complete the upgrade operation via a host computer, meeting the application needs of various scenarios. Traditional online upgrade methods are based on UART serial ports, where data transmission rates are limited by the bit error rate (BER). Higher transmission speeds result in higher BER rates. This patent proposes a PCIe bus-based data transmission method, which not only reduces the BER but also increases the data transmission rate, significantly improving upgrade efficiency. Furthermore, the FPGA program is designed based on MicroBlaze, performing BRAM data read / write control, SPI read / write operations on FLASH, interrupt management, and data verification within a soft core. This design is simple to code, has a clear structure, and offers better operability. Simultaneously, the CPU can obtain real-time status information from the BRAM via the PCIe bus to monitor the FPGA's online upgrade process, improving product maintenance efficiency for developers. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a block diagram of the MicroBlaze + PCIE bus FPGA online upgrade system of the present invention; Figure 2 This is an overall flowchart of the online upgrade function of this invention; Figure 3 This is a schematic diagram of the FLASH partitioning of the present invention; Figure 4 This is a top-level design block diagram of the FPGA module of this invention; Figure 5 This is a timing diagram of data transmission in QSPI mode according to the present invention; Figure 6This is a flowchart of the CPU-side data processing and transmission process of the present invention. Detailed Implementation

[0009] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0010] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this invention, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0011] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0012] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that aspects can be practiced without these specific details. To enable those skilled in the art to better understand the invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of the invention, unless otherwise stated, "a plurality of" means two or more.

[0013] Definitions: BRAM stands for buffer; CPU stands for processor; FPGA stands for chip.

[0014] The FPGA online upgrade method based on MicroBlaze + PCIe bus proposed in this invention patent can be applied to CPU+FPGA platform architecture products in different fields. The system block diagram of this upgrade method is as follows: Figure 1 As shown, the system consists of two parts: a CPU data processing and sending module, and an FPGA data receiving and SPI FLASH data writing module. On the FPGA side, MicroBlaze is used to read and write to the Block RAM (BRAM), primarily to receive online upgrade commands and configuration files sent by the CPU. It also caches various status information during the online upgrade process in the BRAM for subsequent CPU access via the PCIe bus. Then, the CPU reads, writes, and erases the external SPI FLASH via the SPI bus, writing the configuration file received from the BRAM into the FLASH to complete the online upgrade. Finally, the online upgrade status information cached in the BRAM is transmitted to the CPU software via the PCIe bridge module. On the CPU side, the configuration file is divided into data packets, which are sent to the BRAM via the PCIe bus. Simultaneously, the CPU reads the status information cached in the BRAM via PCIe, monitoring the status information during the online upgrade process in real time to ensure stable execution of the online upgrade function. (See figure...) Figures 1 to 6 The illustrated FPGA online upgrade method based on MicroBlaze and PCIe bus is applicable to data transmission between the onboard CPU and the FPGA communicating via the PCIe bus interface. The FPGA online upgrade method includes... Step 1: The CPU divides the configured file into multiple data packets sequentially (sequential division means dividing the packets into 1024-byte segments from header to tail). Each data packet should include the current data packet encoding, the current data packet length in bytes, and the data packet content. Except for the last data packet to be divided, the length of all other data packets is configured to a preset size in bytes, such as 1024 bytes. The CPU then sends an online upgrade command and data information to the preset storage space address of the BRAM on the FPGA side via the PCIe bus. The preset storage space address is a region specifically designated for storing data packets. Step 2: After receiving the online upgrade command based on the MicroBlaze BRAM matching address, the FPGA initializes the external FLASH via the SPI bus and reads the FLASH manufacturer ID and device ID. If they can be read, proceed to Step 3. If they cannot be read correctly, the FLASH is reset. If the manufacturer ID and device ID cannot be read correctly after a preset number of resets, the online upgrade is exited. For example, if the ID number cannot be read correctly after 5 consecutive resets, the online upgrade is exited. Step 3: After the FPGA successfully initializes the FLASH, it performs an erase operation on the FLASH update area. If the erase operation is successful, proceed to Step 4. If the erase operation fails, write the address of the FLASH segment that failed to erase to the specified address in the BRAM for the CPU to read. Step 4: After the FPGA successfully erases the update area of ​​the FLASH, it sequentially writes the data packets sent by the CPU in Step 1 into the preset storage area of ​​the FLASH via the SPI protocol. After the current data packet is written, it reads the data packet and calculates the checksum. The checksum is compared with the checksum sent by the CPU (the CPU generates a checksum for each data packet sent). If they match, it means that the current data packet has been successfully written into the FLASH, and the next data packet is checked, and so on. If they do not match, it means that the check fails. The FPGA sends the number of the data packet that has failed to send to the CPU and exits the online upgrade function. For example, if the 17th data packet fails to send, the upgrade program exits, and the data packets that have already been sent are erased through Step 3, which will not interfere with the data sent in the next cycle. Preferably, it returns to Step 2 for a maximum of a preset number of cycles, usually 3 times. If the check still fails, the error data packet number is sent to the CPU. After the configuration file on the CPU is sent, it is modified through human-computer interaction, and then sent again in the modified order.

[0015] Step 5: When the FPGA receives the last data packet sent by the CPU, the CPU writes the last data packet number to the preset address in the BRAM. If the FPGA successfully writes the last data packet to the FLASH and completes the verification, the FPGA sends the online upgrade completion status parameters back to the CPU, and exits the online upgrade operation after receiving the exit command from the CPU.

[0016] In one embodiment, the BRAM on the FPGA side in step one enables the CPU to write data files to the BRAM address via the PCIe bus, and the FPGA reads the data from the corresponding address. The FPGA can also write data to the corresponding address, and the CPU can read the data from the PCIe bus, completing the data interaction between the CPU and the FPGA. Preferably, the BRAM controller is set to AXI4-lite interface mode. MicroBlaze directly accesses the BRAM address space via the AXI4-lite bus to perform data read and write operations. Simultaneously, the CPU can control the AXI BRAM controller to perform data and command read and write operations on the BRAM via the AXI4-lite interface through the PCIe bus.

[0017] In one embodiment, the preset storage space address of the BRAM register on the FPGA side via the PCIe bus in step 1 includes, FPGA top-level logic design block diagram as follows Figure 4 As shown, the main function of the FPGA platform is to acquire the configuration file data packets sent by the CPU, write the data to the FLASH via the SPI bus, and write the status information during the upgrade process to the BRAM via MicroBlaze for the CPU to read. The FPGA side includes a BRAM address mapping module, which is a true dual-port mode and includes data lines and address lines. It can perform read and write operations simultaneously. The read and write data bit width is set to 32 bits and the address space size is set to 4K. The BRAM address mapping module's read / write mode is configured based on MicroBlaze, avoiding complex logic coding. It utilizes a soft core to perform BRAM read / write operations by adding an AXI BRAM Controller in the block design. Typically, in FPGA designs, logic coding is used to generate the BRAM's clock, address, and read / write control signals for BRAM read / write operations. The FPGA side includes a PCIe bridge module, which is a high-performance IP core and provides a user-selectable AXI4 interface or AXI4-Stream interface. Preferably, the PCIe bridge module is set to BASE mode, the transmission rate is selected as 2.0GT / s, the reference clock is set to 100MHz, and the interface is selected as the AXI4-lite Master interface to realize the mapping from PCIe BAR address to AXI4-Lite register address for reading and writing user logic registers. The clock of the AXI4-lite Master interface is set to 125MHz, and the DMA interface is set to AXI Memory Mapped mode.

[0018] In one embodiment, the CPU side includes a PCIe controller, which acts as the master of the PCIe module. By configuring the PCIe driver BAR space, it obtains the online upgrade status information from the BRAM of the FPGA module according to the mapped address space and performs data transmission simultaneously. The CPU also includes a data processing and transmission unit. When the CPU is in EP mode, it maps virtual memory to the BAR address space via DMA and performs data processing and transmission as follows: Figure 6 As shown; The upgrade process during data processing and transmission includes two modes: manual upgrade and automatic upgrade. In manual upgrade mode, the target program for upgrade is uploaded to the file system via the FTP protocol, and a memory buffer is allocated according to the file size. After the memory allocation is completed, the file is read into the buffer. After the handshake with the FPGA module is completed according to the protocol format, the upgrade data block is calculated. At the same time, the data in the memory buffer is divided into packets and encapsulated. The CRC checksum of each packet is calculated and sent in a loop. After each packet is sent, the FPGA performs a CRC check. If the checksum is consistent with the CPU checksum, the next packet is sent. If they are inconsistent, the retransmission function is triggered to resend the faulty data packet. After the data is sent, the system waits for the response from the FPGA memory to write the result, and then the upgrade process ends. In automatic upgrade mode, the daemon thread periodically scans and identifies the target program signature of the data card FPGA. If there are differences, a notification is pushed to the UI thread indicating that the upgrade is available. The UI can then complete the upgrade process by clicking a button.

[0019] FPGA top-level logic design block diagram as follows Figure 4 As shown, the main function of the FPGA platform is to acquire the configuration file data packets sent by the CPU, write the data to the FLASH via the SPI bus, and write the status information during the upgrade process to the BRAM via MicroBlaze for the CPU to read. The main internal functional modules of the FPGA are: BRAM address mapping module, BRAM control module, SPI FLASH read / write control module, soft core control module, interrupt management module, and PCIe bridge module.

[0020] 6.1.1 BRAM Address Mapping Module The BRAM module in this patent is a True Dual Port module, which has two sets of data lines and address lines. Both ports can perform read and write operations simultaneously. The read / write data width is set to 32 bits, and the address space size is set to 4K. The BRAM read / write mode is configured based on MicroBlaze, avoiding complex logic coding. A soft core is used to perform read and write operations on the BRAM by adding an AXI BRAM Controller in the block design. Typically, in FPGA design, logic coding is used to generate the BRAM's clock, address, and read / write control signals for read and write operations.

[0021] This module is mainly used to generate the buffer space (BRAM) for the FPGA configuration file and declare the BRAM addresses. The CPU writes data files to the BRAM addresses via the PCIe bus, and the FPGA can read the data from the corresponding addresses. Simultaneously, the FPGA can also write data to the corresponding addresses, and the CPU can read the data from the corresponding addresses via PCIe, completing the data interaction between the CPU and the FPGA. Detailed BRAM address space definitions are shown in Table 1.

[0022] Table 1. BRAM Address Space Mapping Description

[0023] This patent sets the AXI BRAM controller to AXI4-lite interface mode, allowing MicroBlaze to directly access the BRAM address space and perform data read / write operations via the AXI4-lite bus. Similarly, the CPU also controls the AXI BRAM controller to perform data and command read / write operations on the BRAM via the AXI4-lite interface through the PCIe bus.

[0024] Steps 2, 3, and 4 correspond to the operation of the FLASH based on the AXI Quad SPI controller IP core.

[0025] 6.1.3 SPI FLASH Read / Write Control Module The FPGA writes data packets sent by the CPU to the FLASH memory via the SPI FLASH read / write control module. Finally, it reads the written data and calculates its checksum. A successful checksum indicates that the data packet has been successfully written to the FLASH. This module is primarily based on the SPI protocol for programming the FLASH erase and read / write operations. The SPI protocol uses the AXI Quad SPI controller IP core, which has three modes: Standard mode, Dual mode, and Quad mode. Standard mode is mainly used to control standard SPI devices; Dual mode is mainly used to communicate with two-wire SPI devices; and Quad mode is mainly used to communicate with four-wire SPI devices. Most FLASH memory currently supports four-wire SPI read / write operations, therefore the AXI Quad SPI controller IP core used in this module also uses Quad mode. The data read / write timing diagram for Quad mode is shown below. Figure 5 As shown, the FIFO depth is set to 256, which is the same as the page size of FLASH, to reduce the interruption frequency.

[0026] 6.1.4 Interrupt Management Module. This module uses the AXI Interrupt Controller IP core provided by Xilinx to manage the interrupt signals of the AXI Quad SPI controller IP core, thereby improving the operating speed of the AXI Quad SPI controller IP core.

[0027] 6.1.5 Soft-core control module. This module mainly uses the AXI4-lite bus to read and write the registers of the AXI BRAM controller, AXIQuad SPI controller, and AXI Interrupt Controller to initialize the entire soft-core program framework.

[0028] 6.1.6 PCIe Bridge Module. The DMA / Bridge Subsystem for PCIExpress IP core provided by Xilinx is a high-performance, configurable SG mode DMA for PCIe 2.0 and PCIe 3.0, offering user-selectable AXI4 or AXI4-Stream interfaces. Generally, configuring it as an AXI4 interface allows it to be added to the system bus interconnect, suitable for asynchronous transmission of large amounts of data. This patent also uses this IP core to build a PCIe bridge module to implement the slave end of PCIe transmission, where the PCIe bridge module uses PCIe 2.0 mode. In practical applications, the operating mode is set to BASE mode, the transmission rate is selected as 2.0GT / s, the reference clock is set to 100MHz, and the interface is selected as the AXI4-lite Master interface to implement the mapping from PCIe BAR address to AXI4-Lite register address, which can be used for reading and writing user logic registers. The AXI4-lite Master interface clock is set to 125MHz, and the DMA interface is set to AXI Memory Mapped mode.

[0029] The upgrade method proposed in this patent connects to an AXI BRAM controller via the PCIe AXI4-lite interface for CPU read and write BRAM memory space. Since each FPGA model supports a different number of PCIe lanes (X1, X2, X4, X8), more lanes result in faster signal transmission. Users need to select the correct number of PCIe lanes based on the actual number of channels the hardware can handle. In this patent, the number of PCIe lanes is set to X2. The BAR address space size is set to 2MB. By configuring PCIe to AXI Translation, the BAR address on the CPU side can be mapped to the AXI-lite device bus address on the FPGA side. This address setting should be the same as the device address of the AXI BRAM controller.

[0030] 6.2 CPU-side data processing and transmission The CPU side mainly includes two functions: the PCIe controller and the data processing and transmission unit.

[0031] 6.2.1 PCIe Controller The CPU-side PCIe controller acts as the master of the PCIe network. The PCIe controller mainly obtains the online upgrade status information from the FPGA module's BRAM according to the mapped address space by configuring the PCIe driver BAR space and simultaneously transmitting the data.

[0032] 6.2.2 Data Processing and Transmission Unit The CPU processor operates in EP mode, mapping virtual memory to the BAR address space via DMA. The data processing and transmission process is as follows: Figure 6 As shown. The upgrade mode supports both manual and automatic upgrades. In manual upgrade mode, the target program for upgrade is uploaded to the file system via the FTP protocol. A memory buffer is allocated according to the file size. After memory allocation, the file is read into the buffer. After handshaking with the FPGA module according to the protocol format, the upgrade data block is calculated. Simultaneously, the data in the memory buffer is divided into packets and encapsulated. The CRC checksum of each packet is calculated and sent sequentially. After each packet is sent, the FPGA performs a CRC check. If the checksum matches the CPU checksum, the next packet is sent. If they do not match, the retransmission function is triggered to resend the faulty data packet. After the data is sent, the system waits for the FPGA's memory to write the result, thus completing the upgrade process. In automatic upgrade mode, a daemon thread periodically scans and identifies the FPGA target program's signature. If a difference is found, a notification is pushed to the UI thread indicating that the upgrade is available. The UI can then complete the upgrade process by clicking a button.

[0033] This online upgrade platform mainly consists of two parts: CPU data processing and instruction sending, and FPGA data receiving and SPI FLASH data writing. The two parts interact by reading and writing BRAM space to exchange data and instructions, completing the online upgrade process. During the upgrade process, the FLASH memory is divided into two areas: a golden area and an update area. Figure 3 As shown. The update area is used to store the latest configuration file for online upgrades, while the golden area is the firmware area, which is generally not used. The FPGA only reads data from the golden area to start up when the update area has no program or the program verification has an error.

[0034] The product provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the invention claims.

Claims

1. An online upgrade method for FPGA based on MicroBlaze and PCIe bus, applicable to data transmission between the onboard CPU and the FPGA communicating via the PCIe bus interface, characterized in that... The FPGA online upgrade method includes, Step 1: The CPU divides the configured file into multiple data packets in sequence. Each data packet should include the current data packet encoding, the current data packet byte length, and the data packet content. Except for the last data packet to be divided, the byte length of the remaining data packets is configured to a preset size in bytes. The CPU then sends online upgrade instructions and data information to the preset storage space address of the BRAM on the FPGA side via the PCIe bus. The preset storage space address is a region that is separately divided to store data packets. Step 2: After receiving the online upgrade command based on the MicroBlaze BRAM matching address, the FPGA initializes the external FLASH via the SPI bus and reads the FLASH's vendor ID and device ID. If the vendor ID and device ID can be read, proceed to Step 3. If the vendor ID and device ID cannot be read correctly, the FLASH is reset. If the vendor ID and device ID cannot be read correctly after a preset number of resets, the online upgrade is exited. Step 3: Perform an erase operation on the update area of ​​FLASH. If the erase operation is successful, proceed to Step 4. If the erase operation fails, write the address of the FLASH segment that failed to be erased to the specified address in BRAM for the CPU to read. Step 4: The data packets are sequentially written to the preset storage area of ​​the FLASH via the SPI protocol. After the current data packet is written, it is read out and a checksum is calculated. The checksum is compared with the checksum sent by the CPU. If they match, it means that the current data packet has been successfully written to the FLASH, and the next data packet is checked, and so on. If they do not match, it means that the check fails. The FPGA will send the number of the data packet with the current error to the CPU, and exit the online upgrade function or return to step 2 for a maximum of a preset number of loops. If the check still fails, the error data packet number is sent to the CPU for modification using a human-computer interaction method. After all configuration files are sent on the CPU, they are sent in a new order. Step 5: When the FPGA receives the last data packet sent by the CPU, the CPU writes the last data packet number to the preset address in the BRAM. If the FPGA successfully writes the last data packet to the FLASH and completes the verification, the FPGA sends the status parameters of online upgrade completion to the CPU. After receiving the exit command from the CPU, the FPGA exits the online upgrade operation.

2. The FPGA online upgrade method according to claim 1, characterized in that, In step one, the BRAM on the FPGA side enables the CPU to write data files to the BRAM address via the PCIe bus. The FPGA reads the data from the corresponding address, and the FPGA side can write data to the corresponding address. The CPU reads the data from the PCIe bus, thus completing the data interaction between the CPU and the FPGA.

3. The FPGA online upgrade method according to claim 2, characterized in that, The BRAM controller is set to AXI4-lite interface mode. MicroBlaze directly accesses the BRAM address space through the AXI4-lite bus to perform data read and write operations. At the same time, the CPU can control the AXI BRAM controller to perform data and command read and write operations on the BRAM through the AXI4-lite interface via the PCIE bus.

4. The FPGA online upgrade method according to claim 1, characterized in that, The preset storage space address of the BRAM register on the FPGA side via the PCIe bus mentioned in step 1 includes, The FPGA acquires the configuration file data packets sent by the CPU and writes the data to the FLASH memory via the SPI bus. It also writes the status information during the upgrade process into the BRAM via MicroBlaze for the CPU to read. The FPGA side includes a BRAM address mapping module, which is a true dual-port mode and includes data lines and address lines. It can perform read and write operations simultaneously. The read and write data bit width is set to 32 bits and the address space size is set to 4K. The read / write mode of the BRAM address mapping module is configured based on MicroBlaze. By adding an AXI BRAM Controller in the Block design, a soft core is used to perform read / write operations on the BRAM.

5. The FPGA online upgrade method according to claim 4, characterized in that, The FPGA side includes a PCIe bridge module, which is a high-performance IP core and provides users with an optional AXI4 interface or AXI4-Stream interface.

6. The FPGA online upgrade method according to claim 5, characterized in that, The PCIe bridging module is set to BASE mode, with a transmission rate of 2.0GT / s, a reference clock of 100MHz, and an AXI4-lite Master interface to map PCIe BAR addresses to AXI4-Lite register addresses for reading and writing user logic registers.

7. The FPGA online upgrade method according to claim 6, characterized in that, The AXI4-lite Master interface clock is set to 125MHz, and the DMA interface is set to AXI Memory Mapped mode.

8. The FPGA online upgrade method according to claim 1, characterized in that, The CPU side includes a PCIe controller, which acts as the master of the PCIe module. By configuring the PCIe driver BAR space, it obtains the online upgrade status information from the BRAM of the FPGA module according to the mapped address space and performs data transmission simultaneously.

9. The FPGA online upgrade method according to claim 8, characterized in that, The CPU also includes a data processing and transmission unit. When the CPU is in EP mode, it maps virtual memory to the BAR address space via DMA and performs data processing and transmission. The upgrade modes during data processing and transmission include manual upgrade and automatic upgrade. In manual upgrade mode, the target program for upgrade is uploaded to the file system via FTP protocol, and a memory buffer is allocated according to the file size. After the memory request is completed, the file is read into the buffer. After the handshake with the FPGA module is completed according to the protocol format, the upgrade data block is calculated. At the same time, the data in the memory buffer is divided into packets and encapsulated. The CRC checksum of each packet is calculated and sent in a loop. After each packet is sent, the FPGA performs a CRC check. If the checksum is consistent with the CPU checksum, the next packet is sent. If they are inconsistent, the retransmission function is triggered to resend the faulty data packet. After the data is sent, the system waits for the response from the FPGA memory to write the result, and then the upgrade process ends. In automatic upgrade mode, the daemon thread periodically scans and identifies the target program signature of the data card FPGA. If there are differences, the UI thread is pushed to indicate that the upgrade is available, and the UI can complete the upgrade by clicking the button.

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