Display device

Abstract

The invention provides a display device, and for a pixel circuit of the display device, a first driving transistor is electrically connected to a first data writing transistor, one of a source electrode and a drain electrode of the first driving transistor is connected with a light-emitting element, and the other one of the source electrode and the drain electrode of the first driving transistor is electrically connected with a power supply manager. And the power supply manager is used for sequentially outputting a first sub-voltage signal and a second sub-voltage signal to the other one of the source electrode and the drain electrode of the first driving transistor in the first time period and the second time period according to the first enable signal, so that the development of high-resolution products is facilitated, and the power consumption of in-plane devices is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to display devices. Background Technology

[0002] In current self-emissive display products, the pixel driving circuit typically includes a first switching transistor. During the light-emitting period, this first switching transistor needs to be turned on to generate current flowing through the light-emitting device, thereby enabling the sub-pixel to emit light. However, since there is also a voltage drop across the first switching transistor during the light-emitting period, a certain amount of power consumption is lost. Summary of the Invention

[0003] The purpose of this invention is to provide a display device that improves the problem of high in-plane power consumption in existing self-emissive display products.

[0004] An embodiment of the present invention provides a display device, including a power manager and a plurality of pixel circuits, wherein the pixel circuits include a first unit, the first unit comprising:

[0005] Light-emitting elements;

[0006] The first data writing transistor is used to output a first data signal during a first time period;

[0007] A first driving transistor is electrically connected to the first data writing transistor. One of the source and drain of the first driving transistor is connected to the light-emitting element. The gate of the first driving transistor is used to receive the first data signal during a first time period. The first driving transistor is used to generate a driving current according to the first data signal during a second time period to drive the light-emitting element to emit light.

[0008] The first capacitor is electrically connected to the gate of the first driving transistor;

[0009] In this configuration, the other of the source and drain of the first driving transistor is electrically connected to the power manager. The power manager is configured to output a first sub-voltage signal to the other of the source and drain of the first driving transistor during the first time period according to a first enable signal, and to output a second sub-voltage signal to the other of the source and drain of the first driving transistor during the second time period.

[0010] Embodiments of the present invention also provide another display device, including a power manager and a plurality of pixel circuits, the pixel circuits including a first unit, the first unit comprising:

[0011] Light-emitting elements;

[0012] The first data writing transistor is used to output a first data signal during a first time period;

[0013] A first driving transistor is electrically connected to the first data writing transistor. One of the source and drain of the first driving transistor is connected to one of the anode and cathode of the light-emitting element. The gate of the first driving transistor is used to receive the first data signal during a first time period. The first driving transistor is used to generate a driving current according to the first data signal during a second time period to drive the light-emitting element to emit light.

[0014] The first capacitor is electrically connected to the gate of the first driving transistor;

[0015] A first switching transistor, wherein one of the source and drain of the first switching transistor is electrically connected to one of the source and drain of the first driving transistor, and the other of the source and drain of the first switching transistor is electrically connected to one of the anode and cathode of the light-emitting element, the first switching transistor being used to be turned off during the first time period and to be turned on during the second time period.

[0016] In this configuration, the other of the source and drain of the first driving transistor is electrically connected to the power manager. The power manager is configured to output a first sub-voltage signal to the other of the source and drain of the first driving transistor during the first time period according to a first enable signal, and to output a second sub-voltage signal to the other of the source and drain of the first driving transistor during the second time period.

[0017] Embodiments of the present invention also provide a further display device, wherein the pixel circuit further includes a second unit, the second unit comprising:

[0018] The second data writing transistor is used to output the second data signal during the third time period;

[0019] The second driving transistor is electrically connected to the second data writing transistor;

[0020] A second capacitor, one end of which is electrically connected to the gate of the second driving transistor, and the other end of which is electrically connected to a sweep line for transmitting a sweep signal, the amplitude of which varies with time.

[0021] The second switching transistor has one of its source and drain electrically connected to the other of its source and drain, and the other of its source and drain electrically connected to the gate of the first driving transistor. The second switching transistor is used to be turned off during the third time period and to be turned on during the fourth time period.

[0022] In this configuration, one of the source and drain of the second driving transistor is electrically connected to the power manager. The power manager is used to output a seventh sub-voltage signal to one of the source and drain of the second driving transistor during the third time period, and to output an eighth sub-voltage signal to one of the source and drain of the second driving transistor during the fourth time period.

[0023] The present invention provides a display device based on a first driving transistor electrically connected to a first data writing transistor, wherein one of the source and drain of the first driving transistor is connected to a light-emitting element, and the other of the source and drain of the first driving transistor is electrically connected to a power manager. The power manager is used to output a first sub-voltage signal and a second sub-voltage signal to the other of the source and drain of the first driving transistor in a first time period and a second time period according to a first enable signal. This can avoid the need to set a switching transistor to control whether to generate driving current, thereby facilitating the development of high-resolution products and reducing the power consumption of in-plane devices. Attached Figure Description

[0024] Figure 1 A schematic diagram of the architecture of a display device provided for an embodiment of the present invention.

[0025] Figures 2 to 6 This is a schematic diagram of the pixel circuit and its connection relationship with the power manager in a display device provided for an embodiment of the present invention.

[0026] Figure 7 and Figure 8 A timing diagram of some signals inside and outside the pixel circuit provided for embodiments of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified; "electrical connection" indicates that the two are conductive, and is not limited to a direct or indirect connection.

[0029] Furthermore, it should be noted that the accompanying drawings only provide structures and steps closely related to the present invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points immediately apparent, not to indicate that the actual device is identical to the one shown in the drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0030] The present invention provides a display device, which may include, but is not limited to, the following embodiments and combinations thereof.

[0031] In some embodiments, such as Figure 1 As shown, the display device 100 includes a power manager 10 and a plurality of pixel circuits 20, combined with Figures 2 to 8 As shown, the pixel circuit 20 includes a first unit 201, which includes: a light-emitting element D; a first data writing transistor T5 for outputting a first data signal Data_PAM during a first time period t1; a first driving transistor T2 electrically connected to the first data writing transistor T5, wherein one of the source and drain of the first driving transistor T2 is connected to the light-emitting element D, and the gate (i.e., node Q) of the first driving transistor T2 is used to receive the first data signal Data_PAM during the first time period t1, and the first driving transistor T2 is used to generate a driving current according to the first data signal Data_PAM during a second time period t2 to drive the light-emitting element D to emit light; and a first capacitor C_PAM, one end of which is electrically connected to the gate of the first driving transistor T2, and the other end of which is electrically connected to a source for transmitting a constant voltage signal (e.g., a capacitor C_PAM). Figure 2 The first constant voltage signal ELVSS1 or Figures 3 to 6 The common voltage signal com (which can be understood as a signal applied to a common electrode) is a constant voltage line; wherein, the other of the source and drain of the first driving transistor T2 is electrically connected to the power manager 10, and the power manager 10 is used to output a first sub-voltage signal V1 to the other of the source and drain of the first driving transistor T2 in the first time period t1 according to the first enable signal EN1, and to output a second sub-voltage signal V2 to the other of the source and drain of the first driving transistor T2 in the second time period t2.

[0032] The display device 100 may include a display panel 30, a driver (not shown), and the power manager 10. The display panel 30 may include a plurality of pixel circuits 20. The power manager 10 may provide corresponding voltage signals to the plurality of pixel circuits and the driver respectively. The driver may generate control signals and data signals acting on the pixel circuits 20 according to the corresponding voltage signals. Under the action of the control signals, data signals, and corresponding voltage signals, the plurality of pixel circuits 20 control the plurality of light-emitting elements D to emit light, thereby presenting a display screen.

[0033] Specifically, the aforementioned drivers may include a gate driver (not shown, which may be integrated into the display panel 30 or set independently of the display panel 30) and a source driver (not shown). Taking the display panel 30 as having N (N is a positive integer) rows of pixel circuits 20 as an example, the gate driver can generate first gate signals scan(1)_PAM to first gate signals scan(N)_PAM respectively transmitted to the N rows of pixel circuits 20, and the source driver can generate multiple first data signals Data_PAM respectively transmitted to multiple columns of pixel circuits 20. Each first data signal Data_PAM may include multiple data voltages corresponding to the multiple pixel circuits 20 in that column. The N gate pulses in the first gate signal scan(1)_PAM to the first gate signal scan(N)_PAM are arranged sequentially on the time axis to control the N rows of pixel circuits 20 to be turned on sequentially. Correspondingly, during the period when each row of pixel circuits 20 is turned on, the multiple first data signals Data_PAM output by the source driver are the multiple data voltages corresponding to the multiple pixel circuits 20 in that row, so that the multiple pixel circuits 20 in that row are loaded with the corresponding multiple data voltages.

[0034] As discussed above, the first data signal Data_PAM can be transmitted to the first driving transistor T2 in the first time period t1. Through the storage function of the first capacitor C_PAM, the first driving transistor T2 can generate a driving current based on the first data signal Data_PAM in the second time period t2 to drive the light-emitting element D to emit light.

[0035] Understandably, in this embodiment, the other of the source and drain of the first driving transistor T2 is electrically connected to the power manager 10. It can be assumed that during the first time period t1, the first driving transistor T2 is turned on due to the loading of the first data signal Data_PAM onto its gate. The signal provided by the power manager 10, after passing through the first driving transistor T2, can cause one of the anode and cathode of the light-emitting element D to have a potential. If this potential causes the voltage drop between the anode and cathode of the light-emitting element D to be greater than its on-state voltage drop, then the light-emitting element D is turned on; otherwise, it is not turned on. Based on this, in this embodiment, the power manager 10... 0 is set to output a first sub-voltage signal V1 and a second sub-voltage signal V2 to the other of the source and drain of the first driving transistor T2 in the first time period t1 and the second time period t2, respectively, according to the first enable signal EN1. By reasonably setting the amplitude of the first sub-voltage signal V1 and the amplitude of the second sub-voltage signal V2, the light-emitting element D can be turned off and turned on in the first time period t1 and the second time period t2, so that the first driving transistor T2 can generate a driving current related to the first data signal Data_PAM in the second time period t2, thereby driving the light-emitting element D to emit light of corresponding brightness.

[0036] It should be noted that in this embodiment, while achieving normal light emission of the light-emitting element D, the other of the source and drain of the first driving transistor T2 is electrically connected to the power manager 10, and the power manager 10 is configured to output the first sub-voltage signal V1 and the second sub-voltage signal V2 sequentially in the first time period t1 and the second time period t2 according to the first enable signal EN1. This replaces the transistor between the other of the source and drain of the first driving transistor T2 and the conventional line for transmitting constant voltage signals to achieve the switching function. This also saves the need for the aforementioned transistor, which is beneficial to the development of high-resolution products. At the same time, the power consumption of the aforementioned transistor is also saved in the second time period t2 when the light-emitting element D emits light, thereby reducing the power consumption of in-plane devices.

[0037] In some embodiments, such as Figure 2 As shown, one of the source and drain of the first data writing transistor T5 is electrically connected to the first data line for transmitting the first data signal Data_PAM, and the other of the source and drain of the first data writing transistor T5 is electrically connected to the gate of the first driving transistor T2. The first data writing transistor T5 is used to be turned on during the first time period t1 to transmit the first data signal Data_PAM to the gate of the first driving transistor T2.

[0038] Specifically, combined Figure 2 and Figure 7As shown, for each of the pixel circuits 20 in the same row, the gate of the first data writing transistor T5 can be electrically connected to the first gate line used to transmit the first gate signal (one of the first gate signal scan(1)_PAM to the first gate signal scan(N)_PAM, the circuit diagram only uses the Nth row pixel circuit 20 as an example), so that the first data writing transistor T5 is turned on during the corresponding gate pulse period, thereby transmitting the data voltage of the first data signal Data_PAM transmitted by the first data line to the gate of the first driving transistor T2.

[0039] Similarly, the multi-row pixel circuit 20 transmits multiple rows of data voltages to the gates of multiple first driving transistors T2 of the corresponding multi-row pixel circuit 20 during the corresponding gate pulse periods (i.e., the corresponding multiple first periods t1). The multiple first periods t1 in this embodiment can be defined as constituting the frame data writing period t11 (i.e., the total period during which the gates of the multiple rows of first driving transistors T2 are sequentially written with the corresponding multiple rows of data voltages). The frame data writing period t11 can be close to at least one of the total period during which multiple rows of gate pulses occupy a frame and the total period during which multiple data voltages in the first data signal Data_PAM occupy a frame. The second period t2 in this embodiment can be located after the multiple first periods t1 (i.e., the frame data writing period t11), that is, in the second period t2 after all rows of data voltages are sequentially written to all rows of pixel circuits 20, the first driving transistors T2 generate a driving current according to the first data signal Data_PAM to drive the light-emitting element D to emit light.

[0040] In some embodiments, such as Figure 2 and Figure 6 As shown, the power manager 10 includes: a first pin electrically connected to a first line to obtain a first operating signal (e.g., a first sub-operating signal Power_IN1) transmitted by the first line; a second pin electrically connected to a second line to obtain a second operating signal (e.g., a ground signal GND) transmitted by the second line; a third pin electrically connected to a third line to obtain a first enable signal EN1 transmitted by the third line, the first enable signal EN1 including a first sub-enable signal E1 located within the first time period t1 and a second sub-enable signal E2 located within the second time period t2; and a fourth pin electrically connected to the other of the source and drain of the first driving transistor T2; wherein the first operating signal (e.g., the first sub-operating signal Power_IN1) and the second operating signal (e.g., the ground signal GND) are used to determine the amplitude of the first sub-voltage signal V1 and the amplitude of the second sub-voltage signal V2, and the first enable signal EN1 is used to determine the first time period t1 and the second time period t2.

[0041] The first operating signal (e.g., the first sub-operating signal Power_IN1) and the second operating signal can be two constant voltage signals with different amplitudes applied to the first and second pins of the power manager 10, respectively. The first enable signal EN1 can be considered to be generated by the aforementioned driver. The power manager 10 can generate a first voltage signal ELVDD output from the fourth pin based on the first operating signal, the second operating signal, and the first enable signal EN1.

[0042] Specifically, during the first time period t1, since the first data signal Data_PAM has not yet been fully transmitted to the gates of the first driving transistors T2 in all rows, in order to avoid the light-emitting element D from emitting light erroneously, the first enable signal EN1 is set to the first sub-enable signal E1 (e.g., with a lower amplitude), so that the power manager 10 does not output the second sub-voltage signal V2. At this time, the first voltage signal ELVDD is presented as the first sub-voltage signal V1 (e.g., with a lower amplitude). During the second time period t2, since the first data signal Data_PAM has been fully transmitted to the gates of the first driving transistors T2 in all rows, the first enable signal EN1 is set to the second sub-enable signal E2 (e.g., with a higher amplitude), so that the power manager 10 outputs the second sub-voltage signal V2 to make the light-emitting element D emit light.

[0043] As can be seen from the above discussion, the pixel circuit 20 in this invention can avoid setting a transistor between the source and drain of the first driving transistor T2 and the conventional line for transmitting constant voltage signals to achieve the switching function. This is beneficial to the development of high-resolution products and reduces the power consumption of in-plane devices. At the same time, the current of the power manager 10 in the first time period t1 is at the microamp level, and the power consumption is also extremely low.

[0044] In some embodiments, combined with Figures 3 to 8 As shown, one of the source and drain of the first driving transistor T2 is connected to one of the anode and cathode of the light-emitting element D, and the other of the anode and cathode of the light-emitting element D is electrically connected to the power manager 10. The power manager 10 is used to output a third sub-voltage signal V3 to the other of the anode and cathode of the light-emitting element D in the first time period t1 according to the second enable signal EN2, and to output a fourth sub-voltage signal V4 to the other of the anode and cathode of the light-emitting element D in the second time period t2.

[0045] It is important to note that, such as Figure 2 and Figure 6 As shown, Figure 2The diagram only illustrates the connection between the anode and cathode of the light-emitting element D and the circuit used to transmit the first constant voltage signal ELVSS1. As discussed above, the first constant voltage signal ELVSS1 should be matched with the aforementioned first voltage signal ELVDD to ensure that the voltage drop between the anode and cathode of the light-emitting element D is greater than and not greater than its conduction voltage drop in the first time period t1 and the second time period t2, respectively. This allows the light-emitting element D to sequentially turn off and on in the first time period t1 and the second time period t2.

[0046] certainly, Figure 2 The anode or cathode of the light-emitting element D can also be electrically connected to the power manager 10 to sequentially load a third sub-voltage signal V3 and a fourth sub-voltage signal V4 with different amplitudes during the first time period t1 and the second time period t2. The third sub-voltage signal V3 and the fourth sub-voltage signal V4 can also be matched with the first voltage signal ELVDD to meet the above requirements. Similarly, Figures 3 to 6 The reason for the arrangement of the pixel circuit 20 shown can be found in the above discussion.

[0047] Similarly, the power manager 10 can generate a second voltage signal ELVSS2 (including a third sub-voltage signal V3 and a fourth sub-voltage signal V4 within the first time period t1 and the second time period t2) based on the second sub-operating signal Power_IN2, the ground signal GND and the second enable signal EN2 mentioned above. The generation principle can refer to the principle of generating the first voltage signal ELVDD mentioned above.

[0048] Similarly, combined Figures 3 to 8 As shown, during the first time period t1, the second enable signal EN2 can be set to (for example, a lower amplitude) the third sub-enable signal E3, so that the power manager 10 outputs the third sub-voltage signal V3 to turn off the light-emitting element D to avoid the light-emitting element D from emitting light erroneously; during the second time period t2, the second enable signal EN2 can be set to (for example, a higher amplitude) the fourth sub-enable signal E4, so that the power manager 10 outputs the fourth sub-voltage signal V4 to provide a path for forming the driving current, so that the light-emitting element D emits light.

[0049] In some embodiments, such as Figure 3 and Figure 4 As shown, with Figure 2At least the difference is that the first unit 201 in the pixel circuit 20 further includes: a first switching transistor T3, one of the source and drain of the first switching transistor T3 is electrically connected to one of the source and drain of the first driving transistor T2, and the other of the source and drain of the first switching transistor T3 is electrically connected to one of the anode and cathode of the light-emitting element D. The first switching transistor T3 is used to be turned off during the first time period t1 and to be turned on during the second time period t2.

[0050] Specifically, in this embodiment, the gate of the first switching transistor T3 can be loaded with a first switching signal EM_PAM. The first switching signal EM_PAM can have different amplitudes in the first time period t1 and the second time period t2 to control the first switching transistor T3 to be turned off in the first time period t1 and turned on in the second time period t2. This causes the first driving transistor T2 to be electrically disconnected from the light-emitting element D in the first time period t1, thereby avoiding the first driving transistor T2, which is not yet fully charged by the first data signal Data_PAM, from generating an incorrect driving current and causing the light-emitting element D to emit light incorrectly. Furthermore, the first driving transistor T2 is electrically disconnected from the light-emitting element D in the second time period t2, at which time the driving current generated by the first driving transistor T2, which is now fully charged by the first data signal Data_PAM, can drive the light-emitting element D to emit light.

[0051] In some embodiments, such as Figure 3 and Figure 4 As shown, with Figure 2The difference lies in that one of the source and drain of the first data writing transistor T5 is electrically connected to the first data line used to transmit the first data signal Data_PAM, and the other of the source and drain of the first data writing transistor T5 is electrically connected to the other of the source and drain of the first driving transistor T2. The first data writing transistor T5 is used to conduct during the first time period t1 to transmit the first data signal Data_PAM to the other of the source and drain of the first driving transistor T2. The first unit 201 further includes: a first reset transistor T6, one of the source and drain of the first reset transistor T6 is electrically connected to the reset line used to transmit the reset signal VI2, and the source of the first reset transistor T6 is electrically connected to the other of the source and drain of the first reset transistor T6. The other of the source and drain of the first driving transistor T2 is electrically connected to the gate of the first driving transistor T2. The first reset transistor T6 is used to turn on before the first time period t1 (e.g., the fifth time period t5) to transmit the reset signal VI2 to the gate of the first driving transistor T2. The first data transmission transistor T4 has one of its source and drain electrically connected to the gate of the first driving transistor T2, and the other of its source and drain is electrically connected to one of the source and drain of the first driving transistor T2. The first data transmission transistor T4 is used to turn on during the first time period t1 to transmit the first data signal Data_PAM to the gate of the first driving transistor T2.

[0052] It is understandable that this embodiment is similar to... Figure 2 The circuit shown also differs in the way the first data signal Data_PAM is written to the first driving transistor T2, and adds a gate reset process for the first driving transistor T2. Combined with... Figure 3 , Figure 4 and Figure 8 As shown, the Nth row pixel circuit 20 is used as an example for illustration.

[0053] In the fifth time period t5, the first gate signal scan(N-1)_PAM has a corresponding gate pulse that turns on the first reset transistor T6, so that the reset signal VI2, which is a constant voltage signal, is transmitted to node Q to reset its potential, so as to avoid the residual charge affecting the subsequent writing of the first data signal Data_PAM.

[0054] During the first time period t1, the first gate signal scan(N)_PAM has a corresponding gate pulse that turns on the first data writing transistor T5 and the first data transmission transistor T4, which in turn turns on the first driving transistor T2. The first data signal Data_PAM can be written to node Q, and when it is stable, the potential of node Q is stable as the sum of the first data signal Data_PAM and the threshold voltage of the first driving transistor T2.

[0055] Based on the analysis above, we know that the fifth time period t5 of the current row of pixel circuit 20 is the first time period t1 of the previous row of pixel circuit 20. Similarly, the Nth row of pixel circuit 20 takes the first time period t1 of the (N-1)th row of pixel circuit 20 as its fifth time period t5. However, since there are only N rows of pixel circuit 20, the first time period t1 of the Nth row of pixel circuit 20 is no longer used as the subsequent fifth time period t5.

[0056] Similarly, the multiple first time periods t1 in this embodiment can be defined as frame data writing time period t11 (that is, the total time period occupied by the gates of multiple rows of first driving transistors T2 being written with the corresponding multiple rows of data voltages in sequence). Likewise, in the second time period t2 after all rows of data voltages are written to all rows of pixel circuits 20 in sequence, the first driving transistors T2 generate driving current according to the first data signal Data_PAM to drive the light-emitting element D to emit light.

[0057] In some embodiments, such as Figure 3 and Figure 4 As shown, the other of the source and drain of the first switching transistor T3 is electrically connected to the power manager 10. The power manager 10 is used to output a fifth sub-voltage signal V5 to the other of the source and drain of the first switching transistor T3 during the first time period t1, and a sixth sub-voltage signal V6 to the other of the source and drain of the first switching transistor during the second time period t2, according to the third enable signal EN3.

[0058] Similarly, the power manager 10 can generate a third voltage signal VI1 based on the third sub-operating signal Power_IN3, the ground signal GND, and the aforementioned third enable signal EN3. The generation principle can refer to the principle of generating the first voltage signal ELVDD.

[0059] Similarly, combined Figure 3 , Figure 4 and Figure 8As shown, during the first time period t1, the third enable signal EN3 can be set to the fifth sub-enable signal E5 (e.g., with a higher amplitude), causing the power manager 10 to output the fifth sub-voltage signal V5 to reset one of the anode and cathode of the light-emitting element D (i.e., one of the source and drain of the first driving transistor T2). Even if the first switching transistor T3 is turned off, the risk of the light-emitting element D malfunctioning due to other signal coupling can still be reduced. At the same time, since the first switching transistor T3 is turned off, the reset of one of the anode and cathode of the light-emitting element D will not affect the writing of the first data signal Data_PAM. During the second time period t2, the first switching transistor T3 is turned on, and the third enable signal EN3 can be set to the sixth sub-enable signal E6 (e.g., with a lower amplitude), causing the power manager 10 not to output the fifth sub-voltage signal V5. At this time, the third voltage signal VI1 presents as the sixth sub-voltage signal V6 so as not to interfere with the potential of one of the source and drain of the first driving transistor T2, so as to avoid affecting the brightness of the light-emitting element D.

[0060] Similarly, combined Figures 3 to 8 As shown, based on the above-mentioned first switching transistor T3, it can also be superimposed as follows: "The power manager 10 is used to output a third sub-voltage signal V3 to the other of the anode and cathode of the light-emitting element D during the first time period t1 according to the second enable signal EN2, and to output a fourth sub-voltage signal V4 to the other of the anode and cathode of the light-emitting element D during the second time period t2." See the above discussion for details.

[0061] In some embodiments, such as Figure 5 and Figure 6 As shown, with Figure 3 and Figure 4 At least the difference lies in that, in the pixel circuit 20, one of the source and drain of the first driving transistor T2 in the first unit 201 is electrically connected to the light-emitting element D (i.e., no first switching transistor T3 is provided between them), and the third sub-voltage signal V3 and the fourth sub-voltage signal V4 in the second voltage signal ELVSS2 generated by the power manager 10 are electrically connected to the other of the anode and cathode of the light-emitting element D, respectively, can satisfy the following: the difference between the amplitude (potential) of the third sub-voltage signal V3 and the potential of one of the source and drain of the first driving transistor T2 is used to control the light-emitting element D to be turned off, and the difference between the amplitude (potential) of the fourth sub-voltage signal V4 and the potential of one of the source and drain of the first driving transistor T2 is used to control the light-emitting element D to be turned on.

[0062] That is, without setting the first switching transistor T3, the amplitude of the third sub-voltage signal V3 in the first time period t1 can be set to be relatively large, so that the voltage difference between the anode and cathode of the light-emitting element D is less than the on-state voltage drop, so that the light-emitting element D is turned off. At this time, it will not interfere with the potential of either the source or drain of the first driving transistor T2 to avoid affecting the writing of the first data signal Data_PAM. The amplitude of the fourth sub-voltage signal V4 in the second time period t2 can be set to be relatively small, so that the voltage difference between the anode and cathode of the light-emitting element D is greater than the on-state voltage drop, so as to form a path for driving current.

[0063] Similarly, such as Figure 5 and Figure 6 As shown, even without setting the first switching transistor T3, the aforementioned first reset transistor T6 and first data transmission transistor T4 can still be set.

[0064] It is important to note that, such as Figure 5 and Figure 6 As shown, without setting the first switching transistor T3, neither the source nor the drain of the first driving transistor T2 can be electrically connected to the power manager 10 to receive the third voltage signal VI1, so as to avoid affecting the writing of the first data signal Data_PAM.

[0065] In some embodiments, such as Figure 4 and Figure 6As shown, the pixel circuit 20 includes a first unit 201 and a second unit 202. The second unit 202 includes: a second data writing transistor T11, used to output a second data signal Data_PWM during a third time period; a second driving transistor T9, electrically connected to the second data writing transistor T11; a second capacitor C_PWM, one end of the second capacitor C_PWM being electrically connected to the gate of the second driving transistor T9, and the other end of the second capacitor C_PWM being electrically connected to a sweep line for transmitting a sweep signal SWEEP, the amplitude of which varies with time; and a second switching transistor T10, one of the source and drain of the second switching transistor T10 being connected to the gate of the second driving transistor T9. The source and drain of the second driving transistor T9 are electrically connected, and the source and drain of the second switching transistor T10 are electrically connected to the gate of the first driving transistor T2. The second switching transistor T10 is used to be turned off during the third time period and to be turned on during the fourth time period after the third time period. The source and drain of the second driving transistor T9 are electrically connected to the power manager 10. The power manager 10 is used to output a seventh sub-voltage signal V7 to one of the source and drain of the second driving transistor T9 during the third time period and to output an eighth sub-voltage signal V8 to one of the source and drain of the second driving transistor T9 during the fourth time period.

[0066] Similarly, the power manager 10 can generate a fourth voltage signal VDD_PWM (including the seventh sub-voltage signal V7 and the eighth sub-voltage signal V8 within the first time period t1 and the second time period t2) based on the fourth sub-operating signal Power_IN4, the ground signal GND and the fourth enable signal EN4. The generation principle can refer to the principle of generating the first voltage signal ELVDD described above.

[0067] Among them, such as Figure 4 and Figure 6 Compared Figure 3 and Figure 5 The difference lies in the inclusion of the aforementioned second unit 202; similarly, in Figure 2The second unit 202 described above can also be configured based on this, but it is not shown. Specifically, the functions of the second data writing transistor T11 and the second driving transistor T9 in the second unit 202 are analogous to the functions of the first data writing transistor T5 and the first driving transistor T2. Similarly, the second unit 202 can also be configured with a second data transmission transistor T12 corresponding to the first data transmission transistor T4 and a second reset transistor T13 corresponding to the first reset transistor T6. The gates of the second data writing transistor T11 and the second data transmission transistor T12 can both be loaded with the second gate signal scan(N)_PWM, and the gate of the second reset transistor T13 can be loaded with the second gate signal scan(N-1)_PWM.

[0068] Specifically, the second reset transistor T13 and the first reset transistor T6 can respectively respond to the first gate signal scan(N-1)_PAM and the second gate signal scan(N-1)_PWM by transmitting the reset signal VI2 to the gate of the second driving transistor T9 and the gate of the first driving transistor T2 for reset. Afterwards, the first unit 201 can refer to the preceding working process to at least realize the writing of the first data signal Data_PAM and the emission of the light-emitting element D. For the second unit 202, it can be considered that in the third time period after the reset, the second data signal Data_PWM is transmitted to the gate of the second driving transistor T9, causing the second driving transistor T2 to... The transistor cannot be turned on, and the seventh sub-voltage signal V7 generated by the power manager 10 cannot be transmitted to the gate of the second driving transistor T9. At this time, the second switching transistor T10 can be turned off to avoid affecting the potential of the gate of the second driving transistor T9. Furthermore, since the amplitude of the sweep frequency signal SWEEP changes with time, the second driving transistor T9 will be turned on due to the change in its gate potential. In the fourth time period, the second switching transistor T10 is turned on, thereby transmitting the eighth sub-voltage signal V8 generated by the power manager 10 to the gate of the first driving transistor T2 to turn it off. As a result, the first driving transistor T2 no longer generates the above-mentioned driving current, and the light-emitting element D stops emitting light.

[0069] Based on the above analysis of the working principle, in this embodiment, by adding a second unit 202, and referring to the first driving transistor T2 in the first unit 201, one of its source and drain is electrically connected to the power manager 10 to obtain the first voltage signal ELVDD. Similarly, in this embodiment, one of the source and drain of the second driving transistor T9 in the second unit 202 can be electrically connected to the power manager 10 to obtain the fourth voltage signal VDD_PWM. This can also benefit the development of high-resolution products and reduce the power consumption of in-plane devices.

[0070] In summary, such as Figure 2 , Figure 3 and Figure 5 As shown, the pixel circuits 20 all use amplitude modulation, while... Figure 4 and Figure 6 As shown, by adding a second unit 202, the pixel circuit 20 at least uses frequency modulation. Based on this, if the first data signal Data_PAM loaded in the global first unit 201 is set to be the same, it can be understood that only frequency modulation is implemented. If the first data signal Data_PAM loaded in each first unit 201 is set to be related to the corresponding gray level value, it can be understood that both frequency modulation and amplitude modulation can be implemented.

[0071] It should be noted that in this invention, it is possible to... Figures 2 to 6 As shown, in the power manager 10, a first sub-power manager 101, a second sub-power manager 102, a third sub-power manager 103, and a fourth sub-power manager 104 are respectively set to generate the first voltage signal ELVDD, the second voltage signal ELVSS2, the third voltage signal VI1, and the fourth voltage signal VDD_PWM respectively according to the corresponding enable signal and a set of working signals; of course, the function of generating the above multiple voltage signals can also be integrated into the power manager 10 without setting up the above multiple sub-power managers.

[0072] The structure of the display device provided in the embodiments of the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that, It includes a power manager and multiple pixel circuits, the pixel circuits including a first unit, the first unit including: Light-emitting elements; The first data writing transistor is used to output a first data signal during a first time period; A first driving transistor is electrically connected to the first data writing transistor. One of the source and drain of the first driving transistor is connected to the light-emitting element. The gate of the first driving transistor is used to receive the first data signal during a first time period. The first driving transistor is used to generate a driving current according to the first data signal during a second time period to drive the light-emitting element to emit light. The first capacitor is electrically connected to the gate of the first driving transistor; In this configuration, the other of the source and drain of the first driving transistor is electrically connected to the power manager. The power manager is configured to output a first sub-voltage signal to the other of the source and drain of the first driving transistor during the first time period according to a first enable signal, and to output a second sub-voltage signal to the other of the source and drain of the first driving transistor during the second time period.

2. The display device as claimed in claim 1, characterized in that, One of the source and drain of the first data writing transistor is electrically connected to a first data line for transmitting the first data signal, and the other of the source and drain of the first data writing transistor is electrically connected to the gate of the first driving transistor. The first data writing transistor is used to be turned on during the first time period to transmit the first data signal to the gate of the first driving transistor.

3. The display device as claimed in claim 1, characterized in that, The power manager includes: The first pin is electrically connected to the first line to obtain the first working signal transmitted by the first line; The second pin is electrically connected to the second line to obtain the second operating signal transmitted by the second line; The third pin is electrically connected to the third line to obtain the first enable signal transmitted by the third line. The enable signal includes a first sub-enable signal located in the first time period and a second sub-enable signal located in the second time period. The fourth pin is electrically connected to the other of the source and drain of the first driving transistor. The first working signal and the second working signal are used to determine the amplitude of the first sub-voltage signal and the amplitude of the second sub-voltage signal, and the enable signal is used to determine the first time period and the second time period.

4. The display device as claimed in claim 1, characterized in that, One of the source and drain of the first driving transistor is connected to one of the anode and cathode of the light-emitting element, and the other of the anode and cathode of the light-emitting element is electrically connected to the power manager. The power manager is used to output a third sub-voltage signal to the other of the anode and cathode of the light-emitting element during the first time period according to the second enable signal, and to output a fourth sub-voltage signal to the other of the anode and cathode of the light-emitting element during the second time period.

5. The display device according to any one of claims 1 to 4, characterized in that, The pixel circuit further includes a second unit, the second unit comprising: The second data writing transistor is used to output the second data signal during the third time period; The second driving transistor is electrically connected to the second data writing transistor; A second capacitor, one end of which is electrically connected to the gate of the second driving transistor, and the other end of which is electrically connected to a sweep line for transmitting a sweep signal, the amplitude of which varies with time. The second switching transistor has one of its source and drain electrically connected to the other of its source and drain, and the other of its source and drain electrically connected to the gate of the first driving transistor. The second switching transistor is used to be turned off during the third time period and to be turned on during the fourth time period. In this configuration, one of the source and drain of the second driving transistor is electrically connected to the power manager. The power manager is used to output a seventh sub-voltage signal to one of the source and drain of the second driving transistor during the third time period, and to output an eighth sub-voltage signal to one of the source and drain of the second driving transistor during the fourth time period.

6. A display device, characterized in that, It includes a power manager and multiple pixel circuits, the pixel circuits including a first unit, the first unit including: Light-emitting elements; The first data writing transistor is used to output a first data signal during a first time period; A first driving transistor is electrically connected to the first data writing transistor. One of the source and drain of the first driving transistor is connected to one of the anode and cathode of the light-emitting element. The gate of the first driving transistor is used to receive the first data signal during a first time period. The first driving transistor is used to generate a driving current according to the first data signal during a second time period to drive the light-emitting element to emit light. The first capacitor is electrically connected to the gate of the first driving transistor; A first switching transistor, wherein one of the source and drain of the first switching transistor is electrically connected to one of the source and drain of the first driving transistor, and the other of the source and drain of the first switching transistor is electrically connected to one of the anode and cathode of the light-emitting element, the first switching transistor being used to be turned off during the first time period and to be turned on during the second time period. In this configuration, the other of the source and drain of the first driving transistor is electrically connected to the power manager. The power manager is configured to output a first sub-voltage signal to the other of the source and drain of the first driving transistor during the first time period according to a first enable signal, and to output a second sub-voltage signal to the other of the source and drain of the first driving transistor during the second time period.

7. The display device as claimed in claim 6, characterized in that, The other of the source and drain of the first switching transistor is electrically connected to the power manager, which is used to output a fifth sub-voltage signal to the other of the source and drain of the first switching transistor during the first time period, and to output a sixth sub-voltage signal to the other of the source and drain of the first switching transistor during the second time period.

8. The display device as claimed in claim 6, characterized in that, The other of the anode and cathode of the light-emitting element is electrically connected to the power manager. The power manager is used to output a third sub-voltage signal to the other of the anode and cathode of the light-emitting element during the first time period according to the second enable signal, and to output a fourth sub-voltage signal to the other of the anode and cathode of the light-emitting element during the second time period.

9. The display device as claimed in claim 6, characterized in that, One of the source and drain of the first data writing transistor is electrically connected to the first data line for transmitting the first data signal, and the other of the source and drain of the first data writing transistor is electrically connected to the other of the source and drain of the first driving transistor. The first data writing transistor is used to be turned on during the first time period to transmit the first data signal to the other of the source and drain of the first driving transistor. The first unit further includes: A first reset transistor, wherein one of the source and drain of the first reset transistor is electrically connected to a reset line for transmitting a reset signal, and the other of the source and drain of the first reset transistor is electrically connected to the gate of the first driving transistor, and the first reset transistor is used to turn on before the first time period to transmit the reset signal to the gate of the first driving transistor. A first data transmission transistor, wherein one of its source and drain is electrically connected to the gate of the first driving transistor, and the other of its source and drain is electrically connected to one of the source and drain of the first driving transistor, the first data transmission transistor being turned on during the first time period to transmit the first data signal to the gate of the first driving transistor.

10. The display device according to any one of claims 6 to 9, characterized in that, The pixel circuit further includes a second unit, the second unit comprising: The second data writing transistor is used to output the second data signal during the third time period; The second driving transistor is electrically connected to the second data writing transistor; A second capacitor, one end of which is electrically connected to the gate of the second driving transistor, and the other end of which is electrically connected to a sweep line for transmitting a sweep signal, the amplitude of which varies with time. The second switching transistor has one of its source and drain electrically connected to the other of its source and drain, and the other of its source and drain electrically connected to the gate of the first driving transistor. The second switching transistor is used to be turned off during the third time period and to be turned on during the fourth time period. In this configuration, one of the source and drain of the second driving transistor is electrically connected to the power manager. The power manager is used to output a seventh sub-voltage signal to one of the source and drain of the second driving transistor during the third time period, and to output an eighth sub-voltage signal to one of the source and drain of the second driving transistor during the fourth time period.

11. A display device, characterized in that, It includes a power manager and multiple pixel circuits, the pixel circuits including a first unit, the first unit including: Light-emitting elements; The first data writing transistor is used to output a first data signal during a first time period; A first driving transistor is electrically connected to the first data writing transistor. One of the source and drain of the first driving transistor is connected to one of the anode and cathode of the light-emitting element. The gate of the first driving transistor is used to receive the first data signal during a first time period. The first driving transistor is used to generate a driving current according to the first data signal during a second time period to drive the light-emitting element to emit light. The first capacitor is electrically connected to the gate of the first driving transistor; The other of the source and drain of the first driving transistor is electrically connected to the power manager. The power manager is used to output a first sub-voltage signal to the other of the source and drain of the first driving transistor during the first time period according to the first enable signal, and to output a second sub-voltage signal to the other of the source and drain of the first driving transistor during the second time period. The light-emitting element is electrically connected to the power manager, which is used to output a third sub-voltage signal to the other of the light-emitting element's anode and cathode during the first time period according to a second enable signal, and to output a fourth sub-voltage signal to the other of the light-emitting element's anode and cathode during the second time period. The difference between the potential of the third sub-voltage signal and the potential of one of the source and drain terminals of the first driving transistor is used to control the light-emitting element to be turned off, and the difference between the potential of the fourth sub-voltage signal and the potential of one of the source and drain terminals of the first driving transistor is used to control the light-emitting element to be turned on.

12. The display device as claimed in claim 11, characterized in that, One of the source and drain of the first data writing transistor is electrically connected to the first data line for transmitting the first data signal, and the other of the source and drain of the first data writing transistor is electrically connected to the other of the source and drain of the first driving transistor. The first data writing transistor is used to be turned on during the first time period to transmit the first data signal to the other of the source and drain of the first driving transistor. The first unit further includes: A first reset transistor, wherein one of the source and drain of the first reset transistor is electrically connected to a reset line for transmitting a reset signal, and the other of the source and drain of the first reset transistor is electrically connected to the gate of the first driving transistor, and the first reset transistor is used to turn on before the first time period to transmit the reset signal to the gate of the first driving transistor. A first data transmission transistor, wherein one of its source and drain is electrically connected to the gate of the first driving transistor, and the other of its source and drain is electrically connected to one of the source and drain of the first driving transistor, the first data transmission transistor being turned on during the first time period to transmit the first data signal to the gate of the first driving transistor.

13. The display device as claimed in claim 11 or 12, characterized in that, The pixel circuit further includes a second unit, the second unit comprising: The second data writing transistor is used to output the second data signal during the third time period; The second driving transistor is electrically connected to the second data writing transistor; A second capacitor, one end of which is electrically connected to the gate of the second driving transistor, and the other end of which is electrically connected to a sweep line for transmitting a sweep signal, the amplitude of which varies with time. The second switching transistor has one of its source and drain electrically connected to the other of its source and drain, and the other of its source and drain electrically connected to the gate of the first driving transistor. The second switching transistor is used to be turned off during the third time period and to be turned on during the fourth time period. In this configuration, one of the source and drain of the second driving transistor is electrically connected to the power manager. The power manager is used to output a seventh sub-voltage signal to one of the source and drain of the second driving transistor during the third time period, and to output an eighth sub-voltage signal to one of the source and drain of the second driving transistor during the fourth time period.

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