Gamma voltage generation circuit and display device including same

Abstract

A gamma voltage generation circuit according to an embodiment and a display device including the same are disclosed. The gamma voltage generation circuit includes: a plurality of first buffers, each of which is supplied with a first reference voltage and a second reference voltage from a power supply; a first resistor string that divides a first reference voltage and a second reference voltage applied from the plurality of first buffers; a plurality of second buffers that output a plurality of predetermined gamma reference voltages based on a divided voltage from the first resistor string; and a second resistor string generating a plurality of predetermined gamma voltages by dividing a gamma reference voltage output from the plurality of second buffers, in which a bias current having a first amplitude is supplied to at least one of the plurality of first buffers and the plurality of second buffers within a first portion of a horizontal period, and a bias current having a second amplitude is supplied to at least one of the plurality of second buffers within a second portion of the horizontal period. And provide a bias current having a second amplitude less than the first amplitude to at least one of the plurality of first buffers and the plurality of second buffers within a second portion of the horizontal period.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, for example, but not limited to, a gamma voltage generating circuit and a display device including the same. Background Technology

[0002] Electroluminescent display devices are classified into inorganic light-emitting display devices and organic light-emitting display devices based on the material of the light-emitting layer. Active matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), which have the advantages of fast response speed and high luminous efficiency, brightness and viewing angle.

[0003] In organic light-emitting display devices, organic light-emitting diodes (called "OLEDs") are formed in each of the pixels. These OLED displays not only have fast response and excellent luminous efficiency, brightness, and viewing angle, but also excellent contrast and color reproduction rate because they can render black tones as perfect black.

[0004] Some display devices (e.g., liquid crystal displays or organic light-emitting displays) include a display panel comprising a plurality of sub-pixels, a driver that outputs drive signals for driving the display panel, a power supply that generates power to be supplied to the display panel or the driver, etc. The driver includes a gating driver that provides gating signals such as scan signals and light-emitting signals to the display panel, and a data driver that provides data signals to the display panel. Summary of the Invention

[0005] The data driver is integrated into at least one integrated circuit (IC), each driver IC including a gamma voltage generation circuit that generates a gamma voltage, and the gamma voltage generation circuit outputs a gamma voltage via multiple gamma buffers. The driving capability of such gamma buffers is determined by a bias current, and the criteria used to set the bias current are determined based on driving conditions such as driving voltage and driving frequency.

[0006] However, since the bias current applied to multiple gamma buffers is shared, it is difficult to set the bias current to be applied to each of the multiple gamma voltages. In other words, unnecessary current consumption occurs because the bias current applied to the multiple gamma buffers is fixed at a single level or within a single frame, independent of the drive conditions. Therefore, a method is needed to control the bias current applied to each gamma buffer.

[0007] This disclosure addresses all the aforementioned necessities and issues.

[0008] This disclosure provides a gamma voltage generating circuit and a display device including the same.

[0009] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0010] A gamma voltage generation circuit according to embodiments of the present disclosure may include a plurality of first buffers, each of the plurality of first buffers being provided with a first reference voltage and a second reference voltage from a power source; a first resistor string configured to divide the first reference voltage and the second reference voltage applied from the plurality of first buffers; a plurality of second buffers configured to output a plurality of predetermined gamma reference voltages based on the voltage divided from the first resistor string; and a second resistor string configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers, wherein a bias current having a first amplitude is provided to at least one of the plurality of first buffers and the plurality of second buffers during a first portion of a horizontal time period, and a bias current having a second amplitude less than the first amplitude is provided to at least one of the plurality of first buffers and the plurality of second buffers during a second portion of a horizontal time period.

[0011] A gamma voltage generation circuit according to embodiments of the present disclosure may include: a plurality of first buffers, each of the plurality of first buffers being supplied with a first reference voltage and a second reference voltage from a power source; a first resistor string configured to divide the first reference voltage and the second reference voltage applied from the plurality of first buffers; a plurality of second buffers configured to output a plurality of predetermined gamma reference voltages based on the voltage divided from the first resistor string; a second resistor string configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers; and a biasing component configured to generate a bias current to be applied to the first buffers and the second buffers, wherein the biasing component provides a bias current having a first amplitude to at least one of the plurality of first buffers and the plurality of second buffers during a first portion of a horizontal time period, and provides a bias current having a second amplitude less than the first amplitude to at least one of the plurality of first buffers and the plurality of second buffers during a second portion of the horizontal time period.

[0012] A display device according to an embodiment of the present disclosure may include: a pixel array, wherein a plurality of data lines, a plurality of gating lines, and a plurality of pixel circuits are disposed therein; a data driver configured to output a data voltage generated using gamma voltage to the plurality of data lines; a gating driver configured to output gating signals to the plurality of gating lines; and a timing controller configured to control the data driver and the gating driver, wherein the data driver includes a gamma voltage generation circuit configured to generate a gamma voltage, wherein the gamma voltage generation circuit includes: a plurality of first buffers, each of the plurality of first buffers being provided with a first reference voltage and a second reference voltage from a power supply; and a first resistor string configured to supply a first reference voltage and a second reference voltage to the plurality of data lines. A first buffer applies a first reference voltage and a second reference voltage, which are then divided; a plurality of second buffers are configured to output a plurality of predetermined gamma reference voltages based on the voltage divided from a first resistor string; a second resistor string is configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers; and a biasing component is configured to generate a bias current to be applied to the first and second buffers, wherein a bias current having a first amplitude is provided to the plurality of first and second buffers during a first portion of a horizontal time period, and a bias current having a second amplitude less than the first amplitude is provided to the plurality of first and second buffers during a second portion of the horizontal time period.

[0013] A display device according to embodiments of the present disclosure may include: a pixel array, wherein a plurality of data lines, a plurality of gating lines, and a plurality of pixel circuits are disposed; a data driver configured to output a data voltage generated using gamma voltage to the plurality of data lines; a gating driver configured to output a gating signal to the plurality of gating lines; and a timing controller configured to control the data driver and the gating driver, wherein the data driver includes a gamma voltage generating circuit configured to generate a gamma voltage, wherein the gamma voltage generating circuit includes a plurality of first buffers, each of the plurality of first buffers receiving a first reference voltage and a second reference voltage from a power supply; and a first resistor string configured to apply the first reference voltage and the second reference voltage from the plurality of first buffers. The system comprises: a voltage divider; a plurality of second buffers configured to output a plurality of predetermined gamma reference voltages based on the voltage divider from the first resistor string; a second resistor string configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers; a biasing component configured to generate a bias current to be applied to the first and second buffers, wherein the biasing component comprises n (where n is a natural number greater than 1) transistors, each transistor having a gate electrode to which the generated bias current is applied, a first electrode connected to the first and second buffers, and a second electrode connected to a power line to which a low potential voltage is applied; and m (where m is a natural number) switches connected between the gate electrodes of the n transistors.

[0014] According to this disclosure, current consumption can be reduced by adjusting the drive current of the gamma buffer in the gamma voltage generation circuit according to the load of the display panel or by adjusting the bias current applied to the gamma buffer according to the output voltage of the gamma buffer.

[0015] According to this disclosure, low-power drive can be performed because current consumption can be reduced.

[0016] The effects of this specification are not limited to those described above, and those skilled in the art will clearly understand from the following description and the appended claims other effects not mentioned.

[0017] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0018] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0019] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0020] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0021] Figure 2 This is a diagram illustrating the configuration of a data driver according to an embodiment of the present disclosure;

[0022] Figure 3 This is a diagram illustrating data grouping according to embodiments of the present disclosure;

[0023] Figure 4 This is an example of an embodiment according to the present disclosure. Figure 2 The diagram shows the configuration of the gamma voltage generation circuit.

[0024] Figure 5 This is a diagram illustrating a specific configuration of the buffer component according to the first embodiment of this disclosure;

[0025] Figures 6 to 9 This is a diagram illustrating the bias current adjustment principle for adjusting the bias current according to an embodiment of the present disclosure;

[0026] Figure 10 This is a diagram illustrating a specific configuration of the first buffer component according to a second embodiment of the present disclosure;

[0027] Figure 11A , Figure 11B and Figure 12 This is a diagram illustrating the operating principle of a first buffer for comparison according to an embodiment of the present disclosure;

[0028] Figure 13 This is a diagram illustrating a specific configuration of the second buffer component according to a third embodiment of the present disclosure;

[0029] Figure 14 This is a diagram illustrating a specific configuration of the second buffer component according to the fourth embodiment of this disclosure; and

[0030] Figure 15A , Figure 15B and Figure 16 This is a diagram illustrating the operating principle of a second buffer for comparison according to an embodiment of the present disclosure. Detailed Implementation

[0031] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always refer to the same elements. The names of the corresponding elements used in the following explanation may be chosen solely for the convenience of writing the specification and may therefore differ from those used in actual products.

[0032] The advantages and features of this specification and its implementation methods will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this specification is not limited to the embodiments described below and can be implemented in different forms. These embodiments are provided only to fully disclose this disclosure and to fully convey the scope of this disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0033] Since the shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the gist of this disclosure.

[0034] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0035] In the description of various embodiments of this disclosure, for example, when the positional relationship between two components is described as "on," "above," "below," "adjacent," etc., unless more limiting terms such as "exactly" or "directly" are used, one or more other components may be present between these two components. For example, if an element or layer is disposed "on" another element or layer, a third layer or third element may be inserted between them. Furthermore, when describing an element or layer as "connected," "joined," or "adheded" to another element or layer, unless otherwise stated, it means that the element or layer can not only be directly connected or adhered to the other element or layer, but also that the two are indirectly connected or adhered to each other by means of one or more intermediate elements or layers (i.e., intermediate elements or layers are "disposed" or "inserted" between them). It should be understood that the elements can be arranged to be in direct contact with each other, or they can be arranged to be not in direct contact with each other.

[0036] The expressions "first element," "second element," and " / or" "third element" should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0037] The term “at least one” should be understood to include any and all combinations of one or more associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0038] When using terms such as "including," "having," or "comprising" in this specification, other components may be added unless "only" is used. Unless otherwise expressly stated, components are expressed in the singular form, including the plural form.

[0039] When explaining components, it should be understood that the error range is included even if there is no separate explicit description.

[0040] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "on top", "below", "next", etc., one or more other parts may be placed between the two parts unless "immediately" or "directly" is used.

[0041] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be a second component within the technical concept of this disclosure.

[0042] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0044] In contrast, these embodiments may be provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0045] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may be interoperable and technically driven differently from each other. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0046] The following implementations can be partially or completely combined or integrated with each other, and can be linked and operated in various technical ways. The implementations can be performed independently or in conjunction with each other.

[0047] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0049] Reference Figure 1 According to one embodiment of the present disclosure, the display device includes a display panel 100 and a display panel driving circuit, the display panel driving circuit being used to write pixel data into the pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0050] The display panel 100 may be, but is not limited to, a panel with a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be an irregularly shaped panel in which at least a portion is curved or elliptical.

[0051] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels. These power lines may be commonly connected to pixel circuitry to provide the voltage required to drive the pixels 101.

[0052] Each of pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gating lines, and power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0053] The display area AA comprises multiple pixel lines L1 to Ln. Each of pixel lines L1 to Ln consists of a row of pixels arranged along the row direction (X-axis direction) of the pixel array in the display panel 100. Pixels arranged in a pixel row share a gate line 103. Subpixels arranged along the data line direction in the column direction Y share the same data line 102. A horizontal time period is obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0054] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device in which an image is displayed on the screen while a real object in the background is visible. The display panel 100 can be made of a flexible display panel.

[0055] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltage required to drive display panel 100 and pixels 101 of display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 may output a constant voltage (or DC voltage) (e.g., gate on-state voltage, gate off-state voltage, pixel drive voltage, cathode voltage, reference voltage, IC drive voltage of display panel driving circuitry) via the DC-DC converter. Gate on-state voltage and gate off-state voltage may be provided to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage may be provided to pixel 101 via a power line commonly connected to pixel 101.

[0056] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gating driver 120.

[0057] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not included. Figure 1 As shown in the diagram, the data driver 110 and the touch sensor driver can be integrated into a single source driver IC.

[0058] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage via a voltage divider circuit and generate a gamma compensation voltage for each grayscale. The gamma compensation voltage for each grayscale is provided to a digital-to-analog converter (hereinafter referred to as "DAC") located in each channel of the data driver 110.

[0059] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs a data voltage for the pixel data.

[0060] The gating driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gating driver 120 may be disposed in at least one of the left and right non-display areas NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA.

[0061] Under the control of the timing controller 130, the gating driver 120 sequentially outputs the pulses of the gating signal to the gating line 103. The gating driver 120 can sequentially provide gating signals to the gating line 103 by shifting the pulses of the gating signal.

[0062] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a period of one horizontal time period (1H).

[0063] The timing controller 130 can control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gating timing control signal for controlling the operation timing of the gating driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 300. The timing controller 130 can synchronize the data driver 110 and the gating driver 120 by controlling the operation timing of the display panel driving circuit.

[0064] The gating timing control signal output from the timing controller 130 can be input to the shift register of the gating driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gating timing control signal received from the timing controller 130 into the swing width between the gate on voltage and the gate off voltage, and provide it to the gating driver 120.

[0065] The host system 300 may include a motherboard from one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, and wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can send it along with a timing signal to the timing controller 130.

[0066] Figure 2 This is a diagram illustrating the configuration of a data driver according to an embodiment of the present disclosure, and Figure 3 This is a diagram illustrating data grouping.

[0067] Reference Figure 2 According to embodiments of the present disclosure, the data driver 110 may include a control circuit 110a, a gamma voltage generation circuit 110b, a shift register SR, a latch LAT, a DA converter DAC, and a buffer component BUF. The data driver 110 may also include a level shifter LS.

[0068] The control circuit 110a can control the drive current or bias current of the gamma buffer in the gamma voltage generation circuit 110b based on data packets sent from the timing controller.

[0069] like Figure 3 As shown, the data grouping may include clock training data (C / T), control data (CRT), and pixel data (RGB). The control data may include at least one of a first power control information GPWRC, a second power control information SGC, and a third power control information D_SEL. The first power control information GPWRC is used to determine the portion of the bias current to be applied in each horizontal time period, the second power control information SGC is used to control the bias current to be applied to the gamma buffer, and the third power control information D_SEL is used to control the drive current of the gamma buffer.

[0070] In this case, the first to third power control information can each have two bits and can include four pieces of information. For example, the first to third power control information can include HH, HL, LH, and LL. Although the case where the first to third power control information has two bits has been described as an example, this disclosure is not limited thereto.

[0071] The gamma voltage generation circuit 110b can generate gamma voltage and provide the generated gamma voltage to the DA converter DAC.

[0072] The shift register SR can shift the clock input from the timing controller to generate a sampling clock, and can output the generated sampling clock sequentially to the latch LAT.

[0073] The latch (LAT) can sample and store pixel data of the input image according to the timing of the sequentially input sampling clock, and can simultaneously output the stored pixel data.

[0074] A level shifter (LS) can convert the voltage level of stored pixel data. The LS level shifter can convert the voltage level of the pixel data into a voltage level that can drive a digital-to-analog converter (DAC).

[0075] A DA converter (DAC) can convert pixel data output from a latch (LAT) or pixel data whose voltage level has been converted into analog form by a level shifter (LS).

[0076] The buffer component BUF can amplify the voltage level of pixel data in analog form, and can output the pixel data with the amplified voltage level to the corresponding data line through the output terminal.

[0077] Figure 4 This is an example Figure 2 The diagram shows the configuration of the gamma voltage generation circuit.

[0078] Reference Figure 4 According to an embodiment of the present disclosure, the gamma voltage generation circuit 110b may include a first buffer component BUF1, a first resistor string RS1, a decoder component DEC, a second buffer component BUF2, and a second resistor string RS2.

[0079] The first buffer component BUF1 may include multiple first gamma buffers or first buffers B1. The multiple first buffers B1 may apply reference voltages VREF1 and VREF2 supplied from the power supply to predetermined nodes of the first resistor string RS1. Each first buffer B1 may include an input terminal connected to the power supply and an output terminal connected to one end of the first resistor string RS1. Another first buffer B1 may include an input terminal connected to the power supply and an output terminal connected to the other end of the first resistor string RS1.

[0080] The first resistor string RS1 may include multiple first resistors R1. Multiple first resistors R1 may be connected in series and may have the same resistance value, but are not limited to this.

[0081] The decoder component DEC may include multiple decoders D1, D2, D3, D4, and D5. The decoder component DEC can convert the voltage divided from the first resistor string RS1 into gamma reference voltages VGMA2, VGMA3, VGMA4, VGMA5, and VGMA6, and can output the gamma reference voltages VGMA2, VGMA3, VGMA4, VGMA5, and VGMA6.

[0082] The second buffer component BUF2 may include multiple second gamma buffers or second buffers B2. The multiple second buffers B2 may apply the gamma reference voltage applied to the decoder component DEC to a predetermined node of the second resistor string RS2.

[0083] The second resistor string RS2 may include multiple second resistors R2. These multiple second resistors R2 may be connected in series and may have the same resistance value, but are not limited to this. The second resistor string RS2 can divide the gamma reference voltage applied to a predetermined node to generate gamma voltages GMA1, GMA2, GMA3, GMA4, GMA5, GMA6, and GMA7, and can output the generated gamma voltages GMA1, GMA2, GMA3, GMA4, GMA5, GMA6, and GMA7. These gamma voltages GMA1, GMA2, GMA3, GMA4, GMA5, GMA6, and GMA7 can be provided to the DA converter.

[0084] In the embodiments, although the use of a single gamma voltage generation circuit has been described as an example, this disclosure is not necessarily limited thereto. For example, the gamma voltage generation circuit can be implemented as a positive (+) gamma voltage generation circuit and a negative (-) gamma voltage generation circuit.

[0085] Figure 5 A diagram illustrating a specific configuration of the buffer component according to a first embodiment of the present disclosure is provided. Figures 6 to 9 This is a diagram illustrating the principle of bias current adjustment used to adjust the bias current.

[0086] Reference Figure 5 According to a first embodiment of this disclosure, the buffer component BUF may include a biasing component BI and a buffer B. Here, the buffer component BUF may include a first buffer component BUF1 and a second buffer component BUF2 in the gamma voltage generation circuit 110b, and the first buffer component BUF1 and the second buffer component BUF2 may have the same configuration. The biasing component BI may be commonly applied to the first buffer component BUF1 and the second buffer component BUF2.

[0087] The biasing component BI may include a first circuit component CIR1 and a second circuit component CIR2 that output a bias current based on a reference current generated in the current source IM.

[0088] The first circuit component CIR1 can generate a bias current with a predetermined amplitude based on the first power control information GPWRC. For example, when the first power control information GPWRC is 'LL', transistor A1 can be turned on, and Isum = Iref. When the first power control information GPWRC is 'HH', transistor Ak can be turned on, and Isum = a × Iref (for example, Isum = 4 × Iref). This is because transistors A1 to Ak in the current mirror circuit are designed to have different channel capacitances.

[0089] The second circuit component CIR2 can apply a bias current to each of the first buffers B1. The second circuit component CIR2 may include a transistor T connected to each of the first buffers B1.

[0090] The first transistor T1 can be turned on by applying a bias current generated by the first circuit component CIR1 as a gate current to apply a bias current to the corresponding buffer B.

[0091] In the implementation method, such as Figure 6 As shown, the bias current of buffer B is adjusted to a horizontal period (1H) using the first power control information GPWRC. That is, the biasing component BI according to the embodiment can apply a bias current with a first amplitude to a first portion having a predetermined proportion, and can apply a bias current with a second amplitude less than the first amplitude to a second portion having a remaining proportion, wherein the rise time of the source output enable (SOE) is used as a reference.

[0092] In this case, the first power control information GPWRC can be pre-set according to the load of the display panel. Here, the load of the display panel may include, but is not limited to, characteristic values ​​(e.g., resistance and capacitance) that may differ due to variations in the display panel's manufacturing process. Since the output voltage of the buffers for each display panel varies depending on the load of the manufactured display panel, the first power control information GPWRC can be set differently based on the output voltage. For example, when the display panel is manufactured with a large load, the ratio can be determined to be large, and when the display panel is manufactured with a small load, the ratio can be determined to be small. Therefore, by using the first power control information GPWRC, the bias current of the buffers in the display panel with different loads can be easily adjusted.

[0093] like Figure 7As shown, when the first power control information GPWRC is 'LL', a first bias current can be applied to the buffer of the first part with a ratio of a for 1H, and a second bias current can be applied to the buffer for the second part with a ratio of (100 - a). Here, the ratio can be a < b < c < d. For example, the ratio is set to a = 10%, b = 20%, c = 30%, and d = 40%, but is not necessarily limited to this.

[0094] In this embodiment, the power consumption can be reduced by the second part to which the second bias current is applied.

[0095] As Figure 8 and Figure 9 shown, one-bit first-first power control information L_GPWRC can be added, the second part can be divided into a second-first part and a second-second part, and different bias currents can be applied to the buffers for the second-first part and the second-second part. For example, when the first-first power control information L_GPWRC is 'H', a bias current Bias_H with a second amplitude can be applied to the second-first part, and a bias current Bias_L with a third amplitude less than the second amplitude can be applied to the second-second part.

[0096] The reason is to prepare for unexpected situations that may occur when the lowest bias current is applied to the second part that occupies most of 1H.

[0097] The buffer B can output a predetermined output voltage based on the applied bias current. Each of the buffers B can include an input circuit IST and an output circuit OST. The input circuit IST can amplify the input voltage Vin and can output the amplified voltage. The output circuit OST can output the output voltage Vout using the amplified voltage from the input circuit IST. For example, the buffer B can include Figure 4 a first buffer component BUF1 and a second buffer component BUF2. The first buffer component BUF1 outputs a reference voltage as the output voltage, and the second buffer component BUF2 outputs a gamma reference voltage as the output voltage.

[0098] Figure 10 is a diagram illustrating a specific configuration of the first buffer component according to the second embodiment of the present disclosure, and Figure 11A 、 Figure 11B and Figure 12 are diagrams illustrating the operating principle of the first buffer for comparison.

[0099] Referring to Figure 10 , the buffer component BUF according to the second embodiment of the present disclosure can include a bias component BI and a buffer B.

[0100] The biasing component BI can apply a bias current to the buffer B. The biasing component BI can include a first circuit component CIR1 and a second circuit component CIR2. The first circuit component CIR1 can generate a bias current with an amplitude determined according to power control information.

[0101] The second circuit component CIR2 can apply a bias current to each buffer B, and specifically, can apply different bias currents according to the output voltage of the buffer B. The second circuit component CIR2 may include multiple transistors T11, T12, T13 and T14 and multiple switches SW11, SW12 and SW13.

[0102] The plurality of transistors T11, T12, T13, and T14 may include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. The plurality of transistors T11, T12, T13, and T14 may be connected in parallel between a first line BL to which a bias current is applied and a second power line PL2 to which a low-potential voltage VSS is applied. Each of the plurality of transistors T11, T12, T13, and T14 includes a gate electrode connected to a second line RL to which a reference bias current is applied, a first electrode to which a buffer is connected to the first line BL to apply the bias current, and a second electrode connected to the second power line PL2.

[0103] The multiple switches may include an eleventh switch SW11, a twelfth switch SW12, and a thirteenth switch SW13. The eleventh switch SW11 is connected between the gate electrode of the eleventh transistor T11 and the gate electrode of the twelfth transistor T12, the twelfth switch SW12 is connected between the gate electrode of the twelfth transistor T12 and the gate electrode of the thirteenth transistor T13, and the thirteenth switch SW13 is connected between the gate electrode of the thirteenth transistor T13 and the gate electrode of the fourteenth transistor T14.

[0104] The eleventh switch SW11, the twelfth switch SW12, and the thirteenth switch SW13 can be selectively turned on according to the output voltage of the buffer. That is, when the output voltage of the buffer is higher, the number of switches turned on increases, and vice versa.

[0105] For example, when the output voltage of the buffer is the first voltage, all eleventh switches SW11, twelfth switches SW12 and thirteenth switches SW13 are turned on. When the output voltage of the buffer is the second voltage, which is lower than the first voltage, eleventh switches SW11 and twelfth switches SW12 are turned on and thirteenth switches SW13 are turned off. When the output voltage of the buffer is the third voltage, which is lower than the second voltage, eleventh switches SW11 are turned on and twelfth switches SW12 and thirteenth switches SW13 are turned off. And when the output voltage of the buffer is the fourth voltage, which is lower than the third voltage, all eleventh switches SW11, twelfth switches SW12 and thirteenth switches SW13 are turned off.

[0106] Buffer B can output a predetermined output voltage based on the applied bias current. Each of the buffers B may include a first input circuit IST1 and a first output circuit OST1.

[0107] The first input circuit IST1 can amplify the input voltage Vin and output amplified positive and negative voltages.

[0108] The first output circuit OST1 can output a reference voltage Vout using an amplified voltage. The first output circuit OST1 may include a pull-up transistor Mp and a pull-down transistor Mn. The pull-up transistor Mp and pull-down transistor Mn can be turned on according to the amplified voltage. The pull-up transistor Mp includes a gate electrode to which the amplified voltage is applied, a first electrode connected to a first power line PL1 to which a high potential voltage VDD is applied, and a second electrode connected to the output node. The pull-down transistor Mn includes a gate electrode to which the amplified voltage is applied, a first electrode connected to the output node, and a second electrode connected to a second power line PL2 to which a low potential voltage VSS is applied.

[0109] The first output circuit OST1 can adjust the output voltage Vout output through the output node according to the voltage level of the amplified voltage. The output voltage Vout can be adjusted between a high potential voltage VDD and a low potential voltage VSS.

[0110] When the second circuit component CIR2 is configured as follows Figure 11A When a single transistor is used, it consumes a current Isum with a fixed amplitude; however, when the second circuit component CIR2 is configured as follows... Figure 11B When there are multiple transistors in a circuit, the current Isum / 4*n (where n = 1, 2, 3, 4) can be consumed by selectively driving the transistors. Therefore, with... Figure 11A Compared to the size of transistor T1, Figure 11BTransistors T11, T12, T13, and T14 can be designed to have a size of 1 / 4, and therefore, transistors T11, T12, T13, and T14 can have a channel capacitance of 1 / 4 compared to that of transistor T1.

[0111] When the second power control information SGC is as follows Figure 12 When 'LL' is specified, all switches 11 through 13, SW11, SW12 and SW13, are turned off and the bias current becomes Isum / 4. When the second power control information SGC is 'LH', switch 11, SW11, is turned on and the bias current becomes Isum / 2. When the second power control information SGC is 'HL', switch 11, SW11 and switch 12, SW12, are turned on and the bias current becomes Isum×3 / 4. When the second power control information SGC is 'HH', all switches 11 through 13, SW11, SW12 and SW13, are turned on and the bias current becomes Isum.

[0112] In this scenario, the second power control information SGC can vary based on the output voltage of the gamma buffer. For example, when the output voltage of the gamma buffer is relatively high, the bias current can be adjusted to be large, and when the output voltage of the gamma buffer is relatively low, the bias current can be adjusted to be small. (Refer to...) Figure 4 The output voltage of the gamma buffer can be adjusted to a minimum in the following order: first buffer with output gamma reference voltage VGMA1, second buffer with output gamma reference voltage VGMA2, second buffer with output gamma reference voltage VGMA3, second buffer with output gamma reference voltage VGMA4, second buffer with output gamma reference voltage VGMA5, second buffer with output gamma reference voltage VGMA6, and first buffer with output gamma reference voltage VGMA7. Therefore, the bias current of the corresponding gamma buffer can be adjusted to different values ​​based on the gamma reference voltages VGMA1 to VGMA7 that serve as the output voltages of the gamma buffer.

[0113] In the embodiments, although the case in which the second circuit component CIR2 is configured with four transistors has been described as an example, this disclosure is not necessarily limited thereto, and the second circuit component CIR2 may be configured with, for example, two or more transistors.

[0114] For example, when the number of first buffers B1 is 5 and the second circuit component CIR2 is configured with one transistor, a current consumption of Isum × 5 is generated; however, as in the embodiment, when the second circuit component CIR2 is configured with four transistors, a current consumption of Isum / 4 × 5 = Isum × 1.25 is generated. Thus, it can be understood that the current consumption is reduced to approximately 25%.

[0115] Figure 13 This is a diagram illustrating the specific configuration of the second buffer component according to the third embodiment of this disclosure.

[0116] Reference Figure 13 According to the third embodiment of the present disclosure, the second buffer component BUF2 may include a biasing component BI and a second buffer B2.

[0117] The biasing component BI can apply a bias current to the second buffer B2. The biasing component BI can include a first circuit component CIR1 and a second circuit component CIR2. The first circuit component CIR1 can generate a bias current with an amplitude determined according to power control information.

[0118] The second circuit component CIR2 can apply a bias current to each second buffer B2. The second circuit component CIR2 may include a transistor T1 connected to each second buffer B2.

[0119] Each of the second buffers B2 can output an output voltage Vout based on the applied bias current. Each of the second buffers B2 may include a second input circuit IST2 and a second output circuit OST2.

[0120] The second input circuit IST2 can amplify the input voltage Vin and output amplified positive and negative voltages.

[0121] The second output circuit OST2 can use amplified voltage to output output voltage Vout. The second output circuit OST2 may include multiple pull-up transistors M1p, M2p, M3p and M4p, pull-down transistors M1n, M2n, M3n and M4n, multiple pull-up switches SW1p, SW2p and SW3p, and pull-down switches SW1n, SW2n and SW3n.

[0122] The multiple pull-up transistors M1p, M2p, M3p, and M4p may include a first pull-up transistor M1p, a second pull-up transistor M2p, a third pull-up transistor M3p, and a fourth pull-up transistor M4p. The multiple pull-up transistors M1p, M2p, M3p, and M4p may be connected in parallel between a first power line PL1, to which a high-potential voltage VDD is applied, and the output node OUT.

[0123] The multiple pull-down transistors M1n, M2n, M3n, and M4n may include a first pull-down transistor M1n, a second pull-down transistor M2n, a third pull-down transistor M3n, and a fourth pull-down transistor M4n. The multiple pull-down transistors M1n, M2n, M3n, and M4n may be connected in parallel between the output node OUT and the second power line PL2 to which a low-potential voltage VSS is applied.

[0124] The multiple pull-up switches SW1p, SW2p, and SW3p may include a first pull-up switch SW1p, a second pull-up switch SW2p, and a third pull-up switch SW3p. The first pull-up switch SW1p is connected between the gate electrode of the first pull-up transistor M1p and the gate electrode of the second pull-up transistor M2p; the second pull-up switch SW2p is connected between the gate electrode of the second pull-up transistor M2p and the gate electrode of the third pull-up transistor M3p; and the third pull-up switch SW3p is connected between the gate electrode of the third pull-up transistor M3p and the gate electrode of the fourth pull-up transistor M4p.

[0125] The multiple pull-down switches SW1n, SW2n, and SW3n may include a first pull-down switch SW1n, a second pull-down switch SW2n, and a third pull-down switch SW3n. The first pull-down switch SW1n is connected between the gate electrode of the first pull-down transistor M1n and the gate electrode of the second pull-down transistor M2n; the second pull-down switch SW2n is connected between the gate electrode of the second pull-down transistor M2n and the gate electrode of the third pull-down transistor M3n; and the third pull-down switch SW3n is connected between the gate electrode of the third pull-down transistor M3n and the gate electrode of the fourth pull-down transistor M4n.

[0126] Figure 14 This is a diagram illustrating a specific configuration of the second buffer component according to the fourth embodiment of this disclosure, and Figure 15A , Figure 15B and Figure 16 This is a diagram illustrating the operating principle of the second buffer used for comparison.

[0127] Reference Figure 14 According to the fourth embodiment of the present disclosure, the second buffer component BUF2 may include a biasing component BI and a second buffer B2.

[0128] The biasing component BI can apply a bias current to the second buffer B2. The biasing component BI can include a first circuit component CIR1 and a second circuit component CIR2. The first circuit component CIR1 can generate a bias current with an amplitude determined according to power control information.

[0129] The second circuit component CIR2 can apply a bias current to each second buffer B2, and specifically, can apply different bias currents to the second buffer B2 according to the driving voltage of the corresponding second buffer B2. The second circuit component CIR2 may include multiple transistors T11, T12, T13 and T14 and multiple switches SW11, SW12 and SW13.

[0130] The plurality of transistors T21, T22, T23, and T24 may include a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fourth transistor T24. The plurality of transistors T21, T22, T23, and T24 may be connected in parallel between a first line BL to which a bias current is applied and a second power line PL2 to which a low-potential voltage VSS is applied. Each of the plurality of transistors T21, T22, T23, and T24 includes a gate electrode connected to a second line RL to which a reference current is applied, a first electrode connected to the first line BL, and a second electrode connected to the second power line PL2.

[0131] The multiple switches may include a twenty-first switch SW21, a twenty-second switch SW22, and a twenty-third switch SW23. The twenty-first switch SW21 is connected between the gate electrode of the twenty-first transistor T21 and the gate electrode of the twenty-second transistor T22; the twenty-second switch SW22 is connected between the gate electrode of the twenty-second transistor T22 and the gate electrode of the twenty-third transistor T23; and the twenty-third switch SW23 is connected between the gate electrode of the twenty-third transistor T23 and the gate electrode of the twenty-fourth transistor T24.

[0132] Switches SW21 (21), SW22 (22), and SW23 (23) can be selectively switched on based on the output voltage of the first buffer. That is, if the output voltage of the first buffer is higher, the number of switches switched on increases; otherwise, the number of switches switched on decreases.

[0133] The second buffer B2 can output the output voltage Vout based on the applied bias current. Each second buffer B2 may include a second input circuit IST2 and a second output circuit OST2.

[0134] The second input circuit IST2 can amplify the input voltage Vin to output amplified positive and negative voltages.

[0135] The second output circuit OST2 can use amplified voltage to output output voltage Vout. The second output circuit OST2 may include multiple pull-up transistors M1p, M2p, M3p and M4p, pull-down transistors M1n, M2n, M3n and M4n, multiple pull-up switches SW1p, SW2p and SW3p, and pull-down switches SW1n, SW2n and SW3n.

[0136] The multiple pull-up transistors M1p, M2p, M3p, and M4p may include a first pull-up transistor M1p, a second pull-up transistor M2p, a third pull-up transistor M3p, and a fourth pull-up transistor M4p. The multiple pull-up transistors M1p, M2p, M3p, and M4p may be connected in parallel between a first power line PL1, to which a high-potential voltage VDD is applied, and the output node OUT.

[0137] The multiple pull-down transistors M1n, M2n, M3n, and M4n may include a first pull-down transistor M1n, a second pull-down transistor M2n, a third pull-down transistor M3n, and a fourth pull-down transistor M4n. The multiple pull-down transistors M1n, M2n, M3n, and M4n may be connected in parallel between the output node OUT and the second power line PL2 to which a low-potential voltage VSS is applied.

[0138] The multiple pull-up switches SW1p, SW2p, and SW3p may include a first pull-up switch SW1p, a second pull-up switch SW2p, and a third pull-up switch SW3p. The first pull-up switch SW1p is connected between the gate electrode of the first pull-up transistor M1p and the gate electrode of the second pull-up transistor M2p; the second pull-up switch SW2p is connected between the gate electrode of the second pull-up transistor M2p and the gate electrode of the third pull-up transistor M3p; and the third pull-up switch SW3p is connected between the gate electrode of the third pull-up transistor M3p and the gate electrode of the fourth pull-up transistor M4p.

[0139] The multiple pull-down switches SW1n, SW2n, and SW3n may include a first pull-down switch SW1n, a second pull-down switch SW2n, and a third pull-down switch SW3n. The first pull-down switch SW1n is connected between the gate electrode of the first pull-down transistor M1n and the gate electrode of the second pull-down transistor M2n; the second pull-down switch SW2n is connected between the gate electrode of the second pull-down transistor M2n and the gate electrode of the third pull-down transistor M3n; and the third pull-down switch SW3n is connected between the gate electrode of the third pull-down transistor M3n and the gate electrode of the fourth pull-down transistor M4n.

[0140] When each configuration in the second buffer B2 is as follows Figure 15A When there is only one pair of transistors, it consumes a current ID with a fixed amplitude; however, as Figure 15B In this configuration, when the second buffer B2 is configured with multiple pairs of transistors, a current with a variable amplitude, ID / 4*n (where n = 1, 2, 3, 4), can be consumed by selectively driving the transistors. Therefore, in conjunction with... Figure 15A Compared to the size of transistor Mp / Mn, Figure 15B The transistors M1p / M1n, M2p / M2n, M3p / M3n, and M4p / M4n can be designed to have a size of 1 / 4.

[0141] like Figure 16 As shown, when the third power control information D_SEL is 'LL', all first pull-up switches to third pull-up switches SW1p, SW2p, and SW3p, and first pull-down switches to third pull-down switches SW1n, SW2n, and SW3n are turned off, and the drive current becomes ID / 4; when the third power control information D_SEL is 'LH', the third pull-up switch SW3p and the third pull-down switch SW3n are turned on, and the drive current becomes ID / 2; when the third power control information D_SEL is 'HL', the second pull-up switch SW2p and the third pull-up switch SW3p, and the second pull-down switch SW2n and the third pull-down switch SW3n are turned on, and the drive current becomes ID*3 / 4; and when the third power control information D_SEL is 'HH', all first pull-up switches to third pull-up switches SW1p, SW2p, and SW3p, and first pull-down switches to third pull-down switches SW1n, SW2n, and SW3n are turned on, and the drive current becomes ID.

[0142] In this case, the third power control information D_SEL can be set in advance according to the load of the display panel. For example, when the load of the display panel is large, the drive current can be determined to be large, and when the load of the display panel is small, the drive current can be determined to be small.

[0143] In the implementation, although the case of providing a pair of transistors has been described as an example, for example, two or more pairs of transistors may be provided.

[0144] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

[0145] Cross-references to related applications

[0146] This application claims priority and benefit to Korean Patent Application No. 10-2024-0113348, filed on August 23, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A gamma voltage generating circuit, the gamma voltage generating circuit comprising: A plurality of first buffers, each of which is supplied with a first reference voltage and a second reference voltage from a power source; A first resistor string, configured to divide the first reference voltage and the second reference voltage applied from the plurality of first buffers; Multiple second buffers are configured to output multiple predetermined gamma reference voltages based on the voltage divided from the first resistor string; as well as A second resistor string, configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltage output from the plurality of second buffers. Specifically, during a first portion of the horizontal time period, a bias current having a first amplitude is provided to at least one of the plurality of first buffers and the plurality of second buffers, and during a second portion of the horizontal time period, a bias current having a second amplitude less than the first amplitude is provided to at least one of the plurality of first buffers and the plurality of second buffers.

2. The gamma voltage generating circuit according to claim 1, wherein, The first part is determined according to the load of the display panel at a predetermined ratio.

3. The gamma voltage generating circuit according to claim 2, wherein, The first part is determined by a predetermined ratio with reference to the rise time of the source output enable SOE.

4. The gamma voltage generating circuit according to claim 1, wherein, The second part includes a second-first part and a second-second part, wherein the bias current having the second amplitude is provided to the second-first part, and a bias current having a third amplitude less than the second amplitude is provided to the second-second part.

5. The gamma voltage generating circuit according to claim 1, further comprising: A biasing component, configured to generate a bias current to be applied to the plurality of first buffers and the plurality of second buffers, and The biasing component includes: n transistors, each transistor having a gate electrode, a first electrode, and a second electrode, the gate electrode being applied with a generated bias current, the first electrode being connected to a first buffer and a second buffer, and the second electrode being connected to an electric field line applied with a low potential voltage, where n is a natural number greater than 1; and There are m switches connected between the gate electrodes of the n transistors, where m is a natural number.

6. The gamma voltage generating circuit according to claim 1, wherein, Each of the plurality of second buffers includes: An input circuit configured to amplify an input voltage and output a positive and a negative voltage; n pull-up transistors, each pull-up transistor having a gate electrode, a first electrode and a second electrode, the gate electrode being applied with the positive polarity voltage, the first electrode being connected to an electric power line with an applied high potential voltage, and the second electrode being connected to an output terminal; m pull-up switches are connected between the gate electrodes of the n pull-up transistors; n pull-down transistors, each pull-down transistor having a gate electrode, a first electrode, and a second electrode, the gate electrode being applied with the negative polarity voltage, the first electrode being connected to the output terminal, and the second electrode being connected to a power line applied with a low potential voltage; and m pull-down switches are connected between the gate electrodes of the n pull-down transistors.

7. A gamma voltage generating circuit, the gamma voltage generating circuit comprising: A plurality of first buffers, each of which is supplied with a first reference voltage and a second reference voltage from a power source; A first resistor string, configured to divide the first reference voltage and the second reference voltage applied from the plurality of first buffers; Multiple second buffers are configured to output multiple predetermined gamma reference voltages based on the voltage divided from the first resistor string; A second resistor string is configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers. as well as A biasing component, configured to generate a bias current to be applied to the first and second buffers, and The biasing component provides a bias current with a first amplitude to at least one of the plurality of first buffers and the plurality of second buffers during a first portion of the horizontal time period, and provides a bias current with a second amplitude less than the first amplitude to at least one of the plurality of first buffers and the plurality of second buffers during a second portion of the horizontal time period.

8. The gamma voltage generating circuit according to claim 7, wherein, The biasing component includes: n transistors, each transistor having a gate electrode, a first electrode, and a second electrode, the gate electrode being applied with a generated bias current, the first electrode being connected to a first buffer and a second buffer, and the second electrode being connected to an electric field line applied with a low potential voltage, where n is a natural number greater than 1; and There are m switches connected between the gate electrodes of the n transistors, where m is a natural number.

9. The gamma voltage generating circuit according to claim 7, wherein, Each of the second buffers includes: An input circuit configured to amplify an input voltage and output a positive and a negative voltage; n pull-up transistors, each pull-up transistor having a gate electrode, a first electrode and a second electrode, the gate electrode being applied with the positive voltage, the first electrode being connected to an electric power line to which a high potential voltage is applied, and the second electrode being connected to an output terminal; m pull-up switches are connected between the gate electrodes of the n pull-up transistors; n pull-down transistors, each pull-down transistor having a gate electrode, a first electrode, and a second electrode, the gate electrode being applied with the negative polarity voltage, the first electrode being connected to the output terminal, and the second electrode being connected to a power line applied with a low potential voltage; and m pull-down switches are connected between the gate electrodes of the n pull-down transistors.

10. The gamma voltage generating circuit according to claim 9, wherein, The number of switches that are turned on among the m pull-up switches and the m pull-down switches is determined in advance based on the amplitude of the output voltage of each of the second buffers.

11. A display device, the display device comprising: A pixel array, wherein multiple data lines, multiple gate lines and multiple pixel circuits are provided in the pixel array; A data driver configured to output a data voltage generated using gamma voltage to the plurality of data lines; A gating driver configured to output gating signals to the plurality of gating lines; as well as A timing controller configured to control the data driver and the strobe driver. The data driver includes a gamma voltage generation circuit configured to generate a gamma voltage. The gamma voltage generation circuit includes: A plurality of first buffers, each of which is supplied with a first reference voltage and a second reference voltage from a power source; A first resistor string, configured to divide the first reference voltage and the second reference voltage applied from the plurality of first buffers; Multiple second buffers are configured to output multiple predetermined gamma reference voltages based on the voltage divided from the first resistor string; A second resistor string, configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers; and A biasing component, configured to generate a bias current to be applied to the first and second buffers, and Specifically, during the first part of the horizontal time period, a bias current with a first amplitude is provided to the plurality of first buffers and the plurality of second buffers, and during the second part of the horizontal time period, a bias current with a second amplitude less than the first amplitude is provided to the plurality of first buffers and the plurality of second buffers.

12. The display device according to claim 11, wherein, The timing controller is configured to send data packets to the data driver, the data packets including power control information for determining the first and second portions of the horizontal time period.

13. The display device according to claim 12, wherein, The first part is determined according to the load of the display panel at a predetermined ratio.

14. The display device according to claim 13, wherein, The first part is determined by a predetermined ratio with reference to the rise time of the source output enable SOE.

15. The display device according to claim 12, wherein, The second part includes a second-first part and a second-second part, wherein the bias current having the second amplitude is provided to the second-first part, and a bias current having a third amplitude less than the second amplitude is provided to the second-second part.

16. A display device, the display device comprising: A pixel array, wherein multiple data lines, multiple gate lines and multiple pixel circuits are provided in the pixel array; A data driver configured to output a data voltage generated using gamma voltage to the plurality of data lines; A gating driver configured to output gating signals to the plurality of gating lines; as well as A timing controller configured to control the data driver and the strobe driver. The data driver includes a gamma voltage generation circuit configured to generate a gamma voltage. The gamma voltage generation circuit includes: A plurality of first buffers, each of which is supplied with a first reference voltage and a second reference voltage from a power source; A first resistor string, configured to divide the first reference voltage and the second reference voltage applied from the plurality of first buffers; Multiple second buffers are configured to output multiple predetermined gamma reference voltages based on the voltage divided from the first resistor string; A second resistor string, configured to generate a plurality of predetermined gamma voltages by dividing the gamma reference voltages output from the plurality of second buffers; and A biasing component, configured to generate a bias current to be applied to the first and second buffers, and The biasing component includes: n transistors, each transistor having a gate electrode, a first electrode, and a second electrode, the gate electrode being applied with a generated bias current, the first electrode being connected to a first buffer and a second buffer, and the second electrode being connected to an electric field line applied with a low potential voltage, where n is a natural number greater than 1; and There are m switches connected between the gate electrodes of the n transistors, where m is a natural number.

17. The display device according to claim 16, wherein, The timing controller is configured to send data packets to the data driver, the data packets including power control information for controlling the bias current to be applied to each of the first and second buffers.

18. The display device according to claim 16, wherein, Each of the second buffers includes: An input circuit configured to amplify an input voltage and output a positive and a negative voltage; n pull-up transistors, each pull-up transistor having a gate electrode, a first electrode and a second electrode, the gate electrode being applied with the positive polarity voltage, the first electrode being connected to an electric power line with an applied high potential voltage, and the second electrode being connected to an output terminal; m pull-up switches are connected between the gate electrodes of the n pull-up transistors; n pull-down transistors, each pull-down transistor having a gate electrode, a first electrode, and a second electrode, the gate electrode being applied with the negative polarity voltage, the first electrode being connected to the output terminal, and the second electrode being connected to a power line applied with a low potential voltage; and m pull-down switches are connected between the gate electrodes of the n pull-down transistors.

19. The display device according to claim 18, wherein, The timing controller is configured to send data packets to the data driver, the data packets including power control information for controlling the drive current of the second buffer.

20. The display device according to claim 18, wherein, The number of switches that are turned on among the m pull-up switches and the m pull-down switches is determined in advance based on the amplitude of the output voltage of each of the second buffers.

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