Display device and driving method thereof

Abstract

The embodiment of the invention provides a display device and a driving method thereof, the display device comprises N levels of gate driving units and 2N rows of pixel units, and the ith level of gate driving unit is electrically connected with a gate line of the (2i-1) th row of pixel units and a gate line of the 2ith row of pixel units. The ith-level gate driving unit comprises a first transistor and a second transistor, gates of the first transistor and the second transistor are electrically connected with the first node, one of a source electrode and a drain electrode of the first transistor is electrically connected with a first clock signal line, and the other of the source electrode and the drain electrode of the first transistor is electrically connected with a first gate driving signal output end; one of the source electrode and the drain electrode of the second transistor is electrically connected with a second clock signal line, and the other one of the source electrode and the drain electrode of the second transistor is electrically connected with a second gate drive signal output end. According to the invention, the function of outputting two paths of gate driving signals by one-stage gate driving unit is realized, the number of thin film transistors is reduced, and the requirement of a narrow-frame display panel is met.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] Gate-driver-on-array (GOA) circuits are widely used in display panels to provide gate drive signals to pixel units. Traditional gate drive circuits consist of multiple cascaded gate drive units. Each stage typically includes functional modules such as a pull-up control module, a pull-up module, a pull-down module, a pull-down sustaining module, and a reset module. Each functional module is composed of multiple thin-film transistors (TFTs). A traditional single-stage gate drive unit outputs one row of gate drive signals. This single-stage gate drive unit typically requires more than 16 TFTs to achieve the function of outputting gate drive signals, and high-reliability gate drive units may even require more than 20 TFTs.

[0003] The area occupied by the gate drive circuit directly affects the bezel width of the display panel, and the number of thin-film transistors in the gate drive unit is one of the key factors affecting the width of the gate drive circuit. Traditional gate drive units have a large number of thin-film transistors, resulting in a large overall width of the gate drive circuit, which makes it difficult to meet the requirements of narrow bezel display panels.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a display device and its driving method, which aims to reduce the area occupied by the gate driving circuit and meet the requirements of narrow bezel display panels.

[0006] This application provides a display device, the display device including a display panel, the display panel including at least one gate driving circuit and a plurality of pixel units, the plurality of pixel units including 2N rows of pixel units, the gate driving circuit including N levels of gate driving units, the i-th level gate driving unit being electrically connected to the gate line of the (2i-1)-th row of pixel units and the gate line of the 2i-th row of pixel units; the i-th level gate driving unit including: a pull-up control unit configured to control the potential of a first node; a pull-up unit including a first transistor and a second transistor, the gate of the first transistor being electrically connected to the first node, and one of the source and drain of the first transistor being connected to a first clock. The signal lines are electrically connected, with one of the source and drain of the first transistor electrically connected to the first gate drive signal output terminal, the gate of the second transistor electrically connected to the first node, one of the source and drain of the second transistor electrically connected to the second clock signal line, and the other of the source and drain of the second transistor electrically connected to the second gate drive signal output terminal; and a pull-down sustaining unit, including at least two inverters, wherein the inverters are electrically connected to the stage pass signal output terminal of the i-th stage gate drive unit, the first node, the first gate drive signal output terminal, and the second gate drive signal output terminal; wherein i and N are positive integers, and i is less than or equal to N.

[0007] In the above-mentioned display device, the pull-up control unit includes a third transistor, the gate of the third transistor is electrically connected to the stage transmission signal output terminal of the ixth stage gate driving unit, one of the source and drain of the third transistor is electrically connected to the first power supply signal line or the stage transmission signal output terminal of the ixth stage gate driving unit, and the other of the source and drain of the third transistor is electrically connected to the first node, where x is a positive integer.

[0008] In the above-described display device, x is half the number of clock signal lines of the gate drive circuit.

[0009] In the above-mentioned display device, the pull-up unit further includes a fourth transistor, the gate of the fourth transistor is electrically connected to the first node, one of the source and drain of the fourth transistor is electrically connected to the first clock signal line, and the other of the source and drain of the fourth transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate driving unit.

[0010] In the above-described display device, the i-th stage gate driving unit further includes a reset unit. The reset unit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the fifth transistor is electrically connected to a reset control signal line. One of the source and drain of the fifth transistor is electrically connected to a second power supply signal line. The other of the source and drain of the fifth transistor is electrically connected to the first node. The gate of the sixth transistor is electrically connected to the reset control signal line. One of the source and drain of the sixth transistor is electrically connected to the second power supply signal line. The source and drain of the sixth transistor... The other of the seven transistors is electrically connected to the stage transmission signal output terminal of the i-th stage gate drive unit. The gate of the seventh transistor is electrically connected to the reset control signal line. One of the source and drain of the seventh transistor is electrically connected to the third power supply signal line. The other of the source and drain of the seventh transistor is electrically connected to the first gate drive signal output terminal. The gate of the eighth transistor is electrically connected to the reset control signal line. One of the source and drain of the eighth transistor is electrically connected to the third power supply signal line. The other of the source and drain of the eighth transistor is electrically connected to the second gate drive signal output terminal.

[0011] In the above-mentioned display device, the i-th level gate driving unit further includes a pull-down unit, the pull-down unit includes a ninth transistor, the gate of the ninth transistor is electrically connected to the stage transmission signal output terminal of the i+y-th level gate driving unit, one of the source and drain of the ninth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the ninth transistor is electrically connected to the first node, where y is a positive integer.

[0012] In the above-mentioned display device, the at least two inverters include a first inverter and a second inverter. Both the first inverter and the second inverter include a plurality of transistors electrically connected to the output terminals of different stages of the transmission signals. The width of the effective pulse of any one of the transmission signals output from the output terminals of the multiple different stages is less than the width of the effective pulse of the signal transmitted by the first node. The sum of the widths of the effective pulses of the transmission signals output from the output terminals of the multiple different stages is greater than the width of the effective pulse of the signal transmitted by the first node.

[0013] In the aforementioned display device, the first inverter includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; the pull-down sustaining unit further includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; the gate of the tenth transistor is electrically connected to a first control signal line, one of the source and drain of the tenth transistor is electrically connected to the first control signal line, the other of the source and drain of the tenth transistor is electrically connected to a second node, the gate of the eleventh transistor is electrically connected to a second control signal line, and one of the source and drain of the eleventh transistor is electrically connected to a second power supply signal line. One of the source and drain of the transistor is electrically connected to the second node. The gate of the twelfth transistor is electrically connected to the stage transmission signal output terminal of the ia-th level gate driving unit. One of the source and drain of the twelfth transistor is electrically connected to the second power supply signal line. The other of the source and drain of the twelfth transistor is electrically connected to the second node. The gate of the thirteenth transistor is electrically connected to the stage transmission signal output terminal of the ib-th level gate driving unit. One of the source and drain of the thirteenth transistor is electrically connected to the second power supply signal line. The other of the source and drain of the thirteenth transistor is electrically connected to the second node. The gate of the fourteenth transistor is electrically connected to the stage transmission signal output terminal of the i-th level gate driving unit. The fourteenth transistor is electrically connected to the output terminal. One of its source and drain is electrically connected to the second power signal line, and the other of its source and drain is electrically connected to the second node. The gate of the fifteenth transistor is electrically connected to the stage transmission signal output terminal of the i+c stage gate drive unit. One of its source and drain is electrically connected to the second power signal line, and the other of its source and drain is electrically connected to the second node. The gate of the sixteenth transistor is electrically connected to the first node. One of its source and drain is electrically connected to the second power signal line, and the other of its source and drain is electrically connected to the second node. The nodes are electrically connected as follows: the gate of the seventeenth transistor is electrically connected to the second node; one of the source and drain of the seventeenth transistor is electrically connected to the third power supply signal line; the other of the source and drain of the seventeenth transistor is electrically connected to the first gate drive signal output terminal; the gate of the eighteenth transistor is electrically connected to the second node; one of the source and drain of the eighteenth transistor is electrically connected to the second power supply signal line; the other of the source and drain of the eighteenth transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate drive unit; the gate of the nineteenth transistor is electrically connected to the second node; and one of the source and drain of the nineteenth transistor is electrically connected to the second power supply signal line.The source or drain of the nineteenth transistor is electrically connected to the first node; the gate of the twentieth transistor is electrically connected to the second node; one of the source or drain of the twentieth transistor is electrically connected to the third power supply signal line; and the other of the source or drain of the twentieth transistor is electrically connected to the second gate drive signal output terminal, where a, b, and c are positive integers.

[0014] In the above-described display device, the channel widths of the twelfth, thirteenth, fourteenth, fifteenth, and sixteenth transistors are greater than the channel width of the eleventh transistor, and the channel width of the eleventh transistor is greater than the channel width of the tenth transistor.

[0015] In the aforementioned display device, the second inverter includes a 21st transistor, a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, a 26th transistor, and a 27th transistor; the pull-down sustaining unit further includes a 28th transistor, a 29th transistor, a 30th transistor, and a 31st transistor; the gate of the 21st transistor is electrically connected to a second control signal line, one of the source and drain of the 21st transistor is electrically connected to the second control signal line, the other of the source and drain of the 21st transistor is electrically connected to a third node, the gate of the 22nd transistor is electrically connected to a first control signal line, and one of the source and drain of the 22nd transistor... The 22nd transistor is electrically connected to the second power signal line; the other of the source and drain of the 22nd transistor is electrically connected to the third node; the gate of the 23rd transistor is electrically connected to the stage transmission signal output terminal of the ia-th stage gate drive unit; one of the source and drain of the 23rd transistor is electrically connected to the second power signal line; the other of the source and drain of the 23rd transistor is electrically connected to the third node; the gate of the 24th transistor is electrically connected to the stage transmission signal output terminal of the ib-th stage gate drive unit; one of the source and drain of the 24th transistor is electrically connected to the second power signal line; the other of the source and drain of the 24th transistor is electrically connected to the third node; the 20th transistor... The gate of the fifth transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate driving unit. One of the source and drain of the twenty-fifth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the twenty-fifth transistor is electrically connected to the third node. The gate of the twenty-sixth transistor is electrically connected to the stage transmission signal output terminal of the (i+c)-th stage gate driving unit. One of the source and drain of the twenty-sixth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the twenty-sixth transistor is electrically connected to the third node. The gate of the twenty-seventh transistor is electrically connected to the first node, and one of the source and drain of the twenty-seventh transistor is electrically connected to the second power supply signal line. The connections are as follows: one of the source and drain of the 27th transistor is electrically connected to the third node; the gate of the 28th transistor is electrically connected to the third node; one of the source and drain of the 28th transistor is electrically connected to the third power supply signal line; the other of the source and drain of the 28th transistor is electrically connected to the first gate drive signal output terminal; the gate of the 29th transistor is electrically connected to the third node; one of the source and drain of the 29th transistor is electrically connected to the second power supply signal line; the other of the source and drain of the 29th transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate drive unit; and the gate of the 30th transistor is electrically connected to the third node.One of the source and drain of the thirtieth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the thirtieth transistor is electrically connected to the first node. The gate of the thirty-first transistor is electrically connected to the third node, one of the source and drain of the thirty-first transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the thirty-first transistor is electrically connected to the second gate drive signal output terminal, where a, b, and c are positive integers.

[0016] In the above-described display device, the channel widths of the 23rd transistor, the 24th transistor, the 25th transistor, the 26th transistor, and the 27th transistor are greater than the channel width of the 22nd transistor, and the channel width of the 22nd transistor is greater than the channel width of the 21st transistor.

[0017] In the above-described display device, the first gate drive signal output terminal is electrically connected to the gate line of the 2i-1 row pixel unit, and the second gate drive signal output terminal is electrically connected to the gate line of the 2i row pixel unit.

[0018] In the above-mentioned display device, the pull-up unit further includes a first capacitor, the first plate of the first capacitor being electrically connected to the first node, and the second plate of the first capacitor being electrically connected to the first gate drive signal output terminal; and / or the pull-up unit further includes a second capacitor, the first plate of the second capacitor being electrically connected to the first node, and the second plate of the second capacitor being electrically connected to the second gate drive signal output terminal.

[0019] In the above-described display device, the transistor in the i-th gate driving unit is an oxide semiconductor thin-film transistor.

[0020] This application also provides a driving method for a display device, the display device including a display panel, the display panel including at least one gate driving circuit and a plurality of pixel units, the plurality of pixel units including 2N rows of pixel units, the gate driving circuit including N levels of gate driving units, the i-th level gate driving unit being electrically connected to the gate line of the (2i-1)-th row of pixel units and the gate line of the 2i-th row of pixel units, the i-th level gate driving unit including a pull-up unit, the pull-up unit including a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor being electrically connected to a first node, one of the source and drain of the first transistor being electrically connected to a first clock signal line, and the other of the source and drain of the first transistor being electrically connected to the first gate driving unit. The signal output terminal is electrically connected, one of the source and drain of the second transistor is electrically connected to the second clock signal line, and the other of the source and drain of the second transistor is electrically connected to the second gate drive signal output terminal; the driving method includes: when the first node is in a high potential state, the first transistor is turned on, the first clock signal transmitted by the first clock signal line is transmitted to the first gate drive signal output terminal through the first transistor, the second transistor is turned on, the second clock signal transmitted by the second clock signal line is transmitted to the second gate drive signal output terminal through the second transistor, and the output time of the effective level of the first clock signal and the second clock signal is different; wherein, i and N are positive integers, and i is less than or equal to N.

[0021] In the above driving method, the i-th stage gate driving unit further includes a pull-down sustaining unit, which includes a first inverter and a second inverter. Both the first inverter and the second inverter include multiple transistors electrically connected to the stage transmission signal output terminals of different stages. The width of the effective pulse of any one of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is less than the width of the effective pulse of the signal transmitted by the first node, and the sum of the widths of the effective pulses of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is greater than the width of the effective pulse of the signal transmitted by the first node.

[0022] In the display device provided in the embodiments of this application, the i-th level gate driving unit outputs gate driving signals for driving two rows of pixel units. That is, the i-th level gate driving unit is electrically connected to the gate lines of the (2i-1)th row of pixel units and the gate lines of the 2ith row of pixel units. The i-th level gate driving unit outputs a first gate driving signal to the (2i-1)th row of pixel units and a second gate driving signal to the 2ith row of pixel units. The pull-up unit includes a first transistor and a second transistor. The gates of both the first transistor and the second transistor are electrically connected to a first node. One of the source and drain of the first transistor is electrically connected to a first clock signal line, and the other of the source and drain is electrically connected to the first gate driving signal output terminal. One of the source and drain of the second transistor is electrically connected to a second clock signal line, and the other of the source and drain is electrically connected to the second gate driving signal output terminal. When the first node is at a high potential, the first transistor and the second transistor are simultaneously turned on. The first clock signal transmitted by the first clock signal line is transmitted to the first gate drive signal output terminal through the first transistor, and the second clock signal transmitted by the second clock signal line is transmitted to the second gate drive signal output terminal through the second transistor. Since the output times of the effective levels of the first clock signal and the second clock signal are different, the first gate drive signal output terminal and the second gate drive signal output terminal output effective levels at different times, thereby realizing the function of outputting two gate drive signals by a single gate drive unit. In this way, the number of rows of pixel units in the display panel is twice the number of stages of the gate drive unit in the gate drive circuit. Compared with the traditional gate drive circuit that requires two stages of gate drive units to output gate drive signals for driving two rows of pixel units, the technical solution of this application only requires one stage of gate drive unit to realize the function of outputting gate drive signals for driving two rows of pixel units, reducing the number of transistors in the gate drive unit, thereby reducing the area occupied by the gate drive circuit.

[0023] In the display device provided in the embodiments of this application, the pull-down sustaining unit includes at least two inverters. The inverters are electrically connected to the stage transmission signal output terminal, the first node, the first gate drive signal output terminal, and the second gate drive signal output terminal of the i-th stage gate drive unit. The inverters receive the stage transmission signal output from the stage transmission signal output terminal and the signal from the first node. The stage transmission signal, as a dedicated signal within the gate drive unit, is not affected by signals within the display area of ​​the display panel, making the inverter's signal more stable. The inverter, with dual control of the stage transmission signal and the first node signal, has stronger stability. When either the stage transmission signal or the first node signal fails, the inverter still operates normally, continuing to work with only the input of the stage transmission signal or the first node signal, thus improving the reliability of the gate drive circuit.

[0024] The inverter includes multiple transistors, whose gates are electrically connected to the stage transmission signal output terminals of the ia-th stage gate drive unit, the ib-th stage gate drive unit, the i-th stage gate drive unit, the i+c-th stage gate drive unit, and the first node, respectively. The stage transmission signal received by the inverter covers the same waveform width range as the signal of the first node. The inverter can operate normally during the entire effective level of the signal of the first node, ensuring the output performance of the gate drive circuit.

[0025] In an inverter, the channel width of the transistor connecting the stage signal output terminal and the first node is greater than the channel width of the transistor connecting the second control signal line or the first control signal line. The channel width of the transistor connecting the second control signal line or the first control signal line is greater than the channel width of the transistor connecting the first control signal line or the second control signal line. This enables the inverter to output a highly reliable waveform and improves the stability of the gate drive circuit.

[0026] The technical solution of this application, compared to the conventional gate drive circuit which uses a two-stage gate drive unit to output gate drive signals for driving two rows of pixel units, including 32 thin-film transistors, uses a single-stage gate drive unit with 31 thin-film transistors, saving one thin-film transistor and improving reliability. Compared to the conventional high-reliability gate drive circuit which uses a two-stage gate drive unit to output gate drive signals for driving two rows of pixel units, including 40 or more thin-film transistors, the technical solution of this application saves at least 9 thin-film transistors while meeting the same reliability requirements, reducing the area occupied by the gate drive circuit and meeting the needs of narrow-bezel display panels. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0028] Figure 2 A circuit diagram of the i-th stage gate driving unit of the gate driving circuit of the display device provided in an embodiment of this application.

[0029] Figure 3 A waveform diagram of the relevant signals of the i-th stage gate driving unit of the gate driving circuit of the display device provided in the embodiments of this application. Detailed Implementation

[0030] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0031] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0032] The technical solutions of different embodiments of this application can be combined with each other.

[0033] The display device provided in the embodiments of this application may be, for example, an LCD display device, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of this application will be described using an LCD display device as an example.

[0034] like Figure 1 As shown, an embodiment of this application provides a display device, which includes a display panel, a source driver chip, and a timing controller. The display panel includes at least one gate driver circuit, multiple pixel units PX, multiple data lines DATA, and multiple gate lines SCAN.

[0035] In the display device of this application, a source driver chip is electrically connected to multiple data lines DATA, and a timing controller is electrically connected to the source driver chip and the gate driver circuit. The timing controller is configured to provide control signals to the source driver chip and the gate driver circuit. The timing controller receives externally input image data and control signals. After processing the image data, the timing controller transmits it to the source driver chip. The source driver chip generates a data voltage signal based on the image data and transmits it to the pixel unit PX through multiple data lines DATA. The timing controller also provides clock signals, control signals, etc., to the gate driver circuit. The gate driver circuit generates a gate drive signal based on the clock signal and control signals and transmits it to the pixel unit PX through multiple gate lines SCAN. The pixel unit PX includes a thin-film transistor and a liquid crystal capacitor. The gate of the thin-film transistor is electrically connected to the gate line SCAN, the source of the thin-film transistor is electrically connected to the data line DATA, and the drain of the thin-film transistor is electrically connected to one electrode of the liquid crystal capacitor. When the gate drive signal transmitted by the gate line SCAN is at an effective level, the thin-film transistor is turned on, and the data voltage signal transmitted by the data line DATA is transmitted to the liquid crystal capacitor through the thin-film transistor. The liquid crystal capacitor stores the data voltage signal, and the voltage difference across the liquid crystal capacitor controls the deflection angle of the liquid crystal molecules, thereby controlling the transmittance of the pixel unit PX and realizing image display.

[0036] Multiple pixel units PX are arranged in an array, comprising 2N rows of pixel units PX. The gate driving circuit includes N levels of gate driving units, which are cascaded together. The i-th level gate driving unit is electrically connected to the gate line SCAN of the (2i-1)-th row of pixel units PX and the gate line SCAN of the 2i-th row of pixel units PX. The i-th level gate driving unit outputs a first gate driving signal to the (2i-1)-th row of pixel units PX and a second gate driving signal to the 2i-th row of pixel units PX, where i and N are positive integers, and i is less than or equal to N. The number of rows of pixel units PX in the display panel is twice the number of levels of the gate driving units in the gate driving circuit.

[0037] The first gate drive signal output terminal G(2i-1) is electrically connected to the gate line SCAN of the (2i-1)th row pixel unit PX, and the second gate drive signal output terminal G(2i) is electrically connected to the gate line SCAN of the 2ith row pixel unit PX. In this way, the first-stage gate drive unit outputs two gate drive signals, driving two rows of pixel units PX respectively. Compared to the traditional gate drive circuit where the first-stage gate drive unit outputs one gate drive signal to drive one row of pixel units PX, the technical solution of this application reduces the number of gate drive unit stages, thereby reducing the area occupied by the gate drive circuit.

[0038] The thin-film transistor in the gate driving unit is an oxide semiconductor thin-film transistor, that is, the active layer of the thin-film transistor in the gate driving unit is made of an oxide semiconductor material, which includes at least one of indium gallium zinc oxide, indium zinc oxide, indium tin oxide, indium gallium zinc tin oxide, indium gallium tin oxide, and indium gallium oxide.

[0039] The active layers of the transistors in the first transistor T21, the second transistor T23, and the pull-down sustaining unit 104 are made of oxide semiconductor material. The high mobility of oxide semiconductor material enables the first transistor T21 and the second transistor T23 to have stronger current driving capability when turned on, resulting in higher voltage amplitudes of the gate driving signals output from the first gate driving signal output terminal G(2i-1) and the second gate driving signal output terminal G(2i), thus improving the driving capability of the gate driving signal. The low leakage current characteristic of oxide semiconductor material results in lower leakage current in the transistors in the pull-down sustaining unit 104 when turned off, thereby making the low-potential states of the first gate driving signal output terminal G(2i-1), the second gate driving signal output terminal G(2i), the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit, and the first node Q(i) more stable, improving the stability of the gate driving circuit.

[0040] The i-th level gate drive unit includes a pull-up control unit 101, a reset unit 103, a pull-down sustaining unit 104, a pull-up unit 102, and a pull-down unit 105.

[0041] like Figure 2 As shown, the pull-up control unit 101 is configured to control the potential of the first node Q(i). The pull-up control unit 101 includes a third transistor T11. The gate of the third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit. One of the source and drain of the third transistor T11 is electrically connected to one of the first power supply signal line VGH, the gate drive signal output terminal G(ix) of the ixth stage, and the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit. The other of the source and drain of the third transistor T11 is electrically connected to the first node Q(i), where x is a positive integer. The first node Q(i) is electrically connected to the gate of the first transistor T21.

[0042] In one embodiment, the gate of the third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit, one of the source and drain of the third transistor T11 is electrically connected to the first power supply signal line VGH, and the other of the source and drain of the third transistor T11 is electrically connected to the first node Q(i). When the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit outputs a high-level signal, the third transistor T11 is turned on, and the high-level signal transmitted through the first power supply signal line VGH is transmitted to the first node Q(i) through the third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0043] In another embodiment, the gate of the third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit, one of the source and drain of the third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit, and the other of the source and drain of the third transistor T11 is electrically connected to the first node Q(i). Thus, the gate and one of the source and drain of the third transistor T11 are both electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit. When the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit outputs a high-level signal, the third transistor T11 is turned on. The high-level signal output by the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit is transmitted to the first node Q(i) through the third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0044] In another embodiment, the gate of the third transistor T11 is electrically connected to the gate drive signal output terminal G(ix) of the ixth stage, one of the source and drain of the third transistor T11 is electrically connected to the first power supply signal line VGH, and the other of the source and drain of the third transistor T11 is electrically connected to the first node Q(i). When the gate drive signal output terminal G(ix) of the ixth stage outputs a high-level signal, the third transistor T11 is turned on, and the high-level signal transmitted through the first power supply signal line VGH is transmitted to the first node Q(i) through the third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0045] x is greater than or equal to 1 and less than or equal to the number of clock signal lines in the gate drive circuit. Specifically, x is half the number of clock signal lines in the gate drive circuit. The gate drive circuit includes multiple clock signal lines, with the number of clock signal lines ranging from 12 to 16, and x ranging from 6 to 8. For example, the number of clock signal lines is 12, and x is 6. Thus, the gate of the third transistor T11 is electrically connected to the stage transmission signal output terminal ST(i-6) of the (i-6)th stage gate drive unit. The high-level signal output from the stage transmission signal output terminal ST(i-6) of the (i-6)th stage gate drive unit is transmitted to the first node Q(i) through the third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state, thereby controlling the conduction state of the first transistor T21 and the second transistor T23.

[0046] The i-th stage gate driving unit also includes a reset unit 103, which is configured to reset the potential of the critical nodes of the gate driving unit at the beginning of each frame. The reset unit 103 includes a fifth transistor T41, a sixth transistor T42, a seventh transistor T43, and an eighth transistor T44. The gate of the fifth transistor T41 is electrically connected to the reset control signal line RESET, one of the source and drain of the fifth transistor T41 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the fifth transistor T41 is electrically connected to the first node Q(i). The gate of the sixth transistor T42 is electrically connected to the reset control signal line RESET, one of the source and drain of the sixth transistor T42 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the sixth transistor T42 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit. The gate of the seventh transistor T43 is electrically connected to the reset control signal line RESET. One of the sources and drains of the seventh transistor T43 is electrically connected to the third power supply signal line VSSG. The other of the sources and drains of the seventh transistor T43 is electrically connected to the first gate drive signal output terminal G(2i-1). The gate of the eighth transistor T44 is electrically connected to the reset control signal line RESET. One of the sources and drains of the eighth transistor T44 is electrically connected to the third power supply signal line VSSG. The other of the sources and drains of the eighth transistor T44 is electrically connected to the second gate drive signal output terminal G(2i).

[0047] The reset unit 103 is electrically connected to the first node Q(i), the first gate drive signal output terminal G(2i-1), the second gate drive signal output terminal G(2i), and the cascade signal output terminal ST(i). The reset control signal line RESET transmits the reset control signal. The reset control signal outputs a high-level signal at the beginning of each frame during the reset phase. That is, during the reset phase, the reset unit 103 pulls the potentials of the first node Q(i), the first gate drive signal output terminal G(2i-1), the second gate drive signal output terminal G(2i), and the cascade signal output terminal ST(i) down to a low potential state. When the reset control signal line RESET outputs a high-level signal, transistors T41, T42, T43, and T44 are simultaneously turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the first node Q(i) through the fifth transistor T41, causing the potential of the first node Q(i) to drop to a low potential state. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit through the sixth transistor T42, causing the i-th stage gate drive... The potential of the stage transmission signal output terminal ST(i) of the unit drops to a low potential state. The low-level signal transmitted by the third power signal line VSSG is transmitted to the first gate drive signal output terminal G(2i-1) through the seventh transistor T43, causing the potential of the first gate drive signal output terminal G(2i-1) to drop to a low potential state. The low-level signal transmitted by the third power signal line VSSG is transmitted to the second gate drive signal output terminal G(2i) through the eighth transistor T44, causing the potential of the second gate drive signal output terminal G(2i) to drop to a low potential state. In this way, the reset unit 103 resets the potentials of the first node Q(i), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, the first gate drive signal output terminal G(2i-1), and the second gate drive signal output terminal G(2i) at the beginning of each frame, ensuring that the gate drive unit is in the initial state at the beginning of each frame.

[0048] Pull-up unit 102 is configured to generate and output gate drive signals, as well as cascade signals. Pull-up unit 102 includes a first transistor T21, a second transistor T23, and a fourth transistor T22. The gate of the first transistor T21 is electrically connected to the first node Q(i), one of the source and drain of the first transistor T21 is electrically connected to the first clock signal line CK(j), and the other of the source and drain of the first transistor T21 is electrically connected to the first gate drive signal output terminal G(2i-1). The gate of the second transistor T23 is electrically connected to the first node Q(i), one of the source and drain of the second transistor T23 is electrically connected to the second clock signal line CK(j+1), and the other of the source and drain of the second transistor T23 is electrically connected to the second gate drive signal output terminal G(2i). The gate of the fourth transistor T22 is electrically connected to the first node Q(i), one of the source and drain of the fourth transistor T22 is electrically connected to the first clock signal line CK(j), and the other of the source and drain of the fourth transistor T22 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit. The fourth transistor T22 is configured to transmit the first clock signal to the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit, thereby realizing the generation and output of the stage transmission signal.

[0049] The first clock signal line CK(j) transmits the first clock signal, and the second clock signal line CK(j+1) transmits the second clock signal. The output times of the effective levels of the first and second clock signals are different. The output time of the effective level of the first clock signal is earlier than the output time of the effective level of the second clock signal. Therefore, the first gate drive signal output terminal G(2i-1) outputs the gate drive signal earlier than the second gate drive signal output terminal G(2i), thus ensuring that the pixel unit PX in row 2i-1 is driven before the pixel unit PX in row 2i.

[0050] The duty cycle of the clock signals transmitted on the first clock signal line CK(j) and the second clock signal line CK(j+1) is 40% to 44%. The duty cycle of a clock signal refers to the ratio of the duration of the high level of the clock signal within one cycle to the total duration of the entire cycle.

[0051] When the first node Q(i) is at a high potential, the first transistor T21, the second transistor T23, and the fourth transistor T22 are simultaneously turned on. The first clock signal transmitted by the first clock signal line CK(j) is transmitted to the first gate drive signal output terminal G(2i-1) through the first transistor T21, the second clock signal transmitted by the second clock signal line CK(j+1) is transmitted to the second gate drive signal output terminal G(2i) through the second transistor T23, and the first clock signal transmitted by the first clock signal line CK(j) is transmitted to the stage drive signal output terminal ST(i) of the i-th stage gate drive unit through the fourth transistor T22. Since the output times of the effective levels of the first clock signal and the second clock signal are different, the first gate drive signal output terminal G(2i-1) and the second gate drive signal output terminal G(2i) output effective levels at different times, thereby realizing the function of outputting two gate drive signals by the first stage gate drive unit.

[0052] The pull-up unit 102 also includes a first capacitor C1. The first plate of the first capacitor C1 is electrically connected to the first node Q(i), and the second plate of the first capacitor C1 is electrically connected to the first gate drive signal output terminal G(2i-1). When the potential of the first gate drive signal output terminal G(2i-1) rises, the potential of the second plate of the first capacitor C1 rises. Due to the coupling effect of the capacitor, the potential of the first plate of the first capacitor C1 also rises, thereby further increasing the potential of the first node Q(i), raising the gate potential of the first transistor T21, enhancing the conduction capability of the first transistor T21, and making the voltage amplitude of the gate drive signal output by the first gate drive signal output terminal G(2i-1) higher, thus improving the driving capability of the gate drive signal.

[0053] In one embodiment, the pull-up unit 102 further includes a second capacitor C2. The first plate of the second capacitor C2 is electrically connected to the first node Q(i), and the second plate of the second capacitor C2 is electrically connected to the second gate drive signal output terminal G(2i). When the potential of the second gate drive signal output terminal G(2i) rises, the potential of the second plate of the second capacitor C2 rises. Due to the coupling effect of the capacitor, the potential of the first plate of the second capacitor C2 also rises, thereby further increasing the potential of the first node Q(i), raising the gate potential of the second transistor T23, enhancing the conduction capability of the second transistor T23, and making the voltage amplitude of the gate drive signal output by the second gate drive signal output terminal G(2i) higher, thus improving the driving capability of the gate drive signal.

[0054] The i-th stage gate driving unit also includes a pull-down unit 105, which is configured to pull down the potential of the first node Q(i). The pull-down unit 105 includes a ninth transistor T31, the gate of which is electrically connected to the stage transmission signal output terminal ST(i+y) of the (i+y)-th stage gate driving unit, one of the source and drain of the ninth transistor T31 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the ninth transistor T31 is electrically connected to the first node Q(i), where y is a positive integer.

[0055] In one embodiment, y is 8, and the gate of the ninth transistor T31 is electrically connected to the stage transmission signal output terminal ST(i+8) of the (i+8)th stage gate drive unit. When the stage transmission signal output terminal ST(i+8) of the (i+8)th stage gate drive unit outputs a high-level signal, the ninth transistor T31 is turned on, and the low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the first node Q(i) through the ninth transistor T31, causing the potential of the first node Q(i) to drop to a low potential state. This causes the first transistor T21, the second transistor T23, and the fourth transistor T22 to be turned off, and the first gate drive signal output terminal G(2i), the second gate drive signal output terminal G(2i), and the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit to stop outputting gate drive signals.

[0056] The pull-down sustaining units 104 are all electrically connected to the first gate drive signal output terminal G(2i-1), the second gate drive signal output terminal G(2i), the stage transmission signal output terminal ST(i), and the first node Q(i). The pull-down sustaining units 104 are configured to maintain the first gate drive signal output terminal G(2i-1), the second gate drive signal output terminal G(2i), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, and the first node Q(i) at a low potential.

[0057] The pull-down sustaining unit 104 includes at least two inverters, including a first inverter and a second inverter. Both the first inverter and the second inverter include multiple transistors electrically connected to the output terminals of different stages of the stage transmission signals. The width of the effective pulse of any one of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is less than the width of the effective pulse of the signal transmitted by the first node Q(i). The sum of the widths of the effective pulses of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is greater than the width of the effective pulse of the signal transmitted by the first node Q(i).

[0058] The first inverter includes transistors T51 (tenth), T52 (eleventh), T53 (twelfth), T54 (thirteenth), T55 (fourteenth), T56 (fifteenth), and T57 (sixteenth). The pull-down sustaining unit 104 also includes transistors T71 (seventeenth), T72 (eighteenth), T73 (nineteenth), and T74 (twentieth).

[0059] The gate of the tenth transistor T51 is electrically connected to the first control signal line LC1. One of the sources and drains of the tenth transistor T51 is electrically connected to the first control signal line LC1, and the other of the sources and drains of the tenth transistor T51 is electrically connected to the second node P(i). The gate of the eleventh transistor T52 is electrically connected to the second control signal line LC2. One of the sources and drains of the eleventh transistor T52 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the eleventh transistor T52 is electrically connected to the second node P(i). The gate of the twelfth transistor T53 is electrically connected to the stage transmission signal output terminal ST(ia) of the ia-th stage gate drive unit. One of the sources and drains of the twelfth transistor T53 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the twelfth transistor T53 is electrically connected to the second node P(i). The gate of the thirteenth transistor T54 is electrically connected to the stage transmission signal output terminal ST(ib) of the ib-level gate drive unit. One of the source and drain of the thirteenth transistor T54 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the thirteenth transistor T54 is electrically connected to the second node P(i). The gate of the fourteenth transistor T55 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th level gate drive unit. One of the source and drain of the fourteenth transistor T55 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the fourteenth transistor T55 is electrically connected to the second node P(i). The gate of the fifteenth transistor T56 is electrically connected to the stage transmission signal output terminal ST(i+c) of the i+c-th level gate drive unit. One of the source and drain of the fifteenth transistor T56 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the fifteenth transistor T56 is electrically connected to the second node P(i). The gate of the sixteenth transistor T57 is electrically connected to the first node Q(i). One of the sources and drains of the sixteenth transistor T57 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the sixteenth transistor T57 is electrically connected to the second node P(i). The gate of the seventeenth transistor T71 is electrically connected to the second node P(i). One of the sources and drains of the seventeenth transistor T71 is electrically connected to the third power supply signal line VSSG, and the other of the sources and drains of the seventeenth transistor T71 is electrically connected to the first gate drive signal output terminal G(2i-1). The gate of the eighteenth transistor T72 is electrically connected to the second node P(i). One of the sources and drains of the eighteenth transistor T72 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the eighteenth transistor T72 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit.The gate of the nineteenth transistor T73 is electrically connected to the second node P(i). One of the source and drain of the nineteenth transistor T73 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the nineteenth transistor T73 is electrically connected to the first node Q(i). The gate of the twentieth transistor T74 is electrically connected to the second node P(i). One of the source and drain of the twentieth transistor T74 is electrically connected to the third power supply signal line VSSG, and the other of the source and drain of the twentieth transistor T74 is electrically connected to the second gate drive signal output terminal G(2i), where a, b, and c are positive integers.

[0060] In one embodiment, a is 8, b is 4, and c is 4. The gate of the twelfth transistor T53 is electrically connected to the stage transmission signal output terminal ST(i-8) of the i-8th stage gate drive unit, the gate of the thirteenth transistor T54 is electrically connected to the stage transmission signal output terminal ST(i-4) of the i-4th stage gate drive unit, and the gate of the fifteenth transistor T56 is electrically connected to the stage transmission signal output terminal ST(i+4) of the i+4th stage gate drive unit.

[0061] The first control signal line LC1 transmits the first control signal, and the second control signal line LC2 transmits the second control signal. The first control signal transmitted by the first control signal line LC1 and the second control signal transmitted by the second control signal line LC2 are out of phase. The first control signal and the second control signal switch between high and low on a second-level basis. The level states of the first control signal and the second control signal are opposite; when the first control signal is high, the second control signal is low, and when the first control signal is low, the second control signal is high.

[0062] When the first control signal line LC1 outputs a high-level signal, the tenth transistor T51 is turned on. The high-level signal transmitted by the first control signal line LC1 is transmitted to the second node P(i) through the tenth transistor T51, causing the potential of the second node P(i) to rise to a high potential state. When the second node P(i) is in a high potential state, the seventeenth transistor T71, the eighteenth transistor T72, the nineteenth transistor T73, and the twentieth transistor T74 are simultaneously turned on. The low-level signal transmitted by the third power signal line VSSG is transmitted to the first gate drive signal output terminal G(2i-1) through the seventeenth transistor T71, causing the potential of the first gate drive signal output terminal G(2i-1) to remain in a low potential state. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage drive of the i-th stage gate drive unit through the eighteenth transistor T72. The signal output terminal ST(i) keeps the potential of the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit at a low potential. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the nineteenth transistor T73, keeping the potential of the first node Q(i) at a low potential. The low-level signal transmitted by the third power signal line VSSG is transmitted to the second gate drive signal output terminal G(2i) through the twentieth transistor T74, keeping the potential of the second gate drive signal output terminal G(2i) at a low potential.

[0063] When the second control signal line LC2 outputs a high-level signal, the eleventh transistor T52 is turned on, and the low-level signal transmitted by the second power signal line VSSQ is transmitted to the second node P(i) through the eleventh transistor T52, causing the potential of the second node P(i) to drop to a low potential state. When the second node P(i) is in a low potential state, the seventeenth transistor T71, the eighteenth transistor T72, the nineteenth transistor T73, and the twentieth transistor T74 are simultaneously turned off. The potentials of the first gate drive signal output terminal G(2i-1), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, the first node Q(i), and the second gate drive signal output terminal G(2i) are not affected by the first inverter.

[0064] When the stage transmission signal output terminal ST(i-8) of the (i-8)th stage gate drive unit outputs a high-level signal, the twelfth transistor T53 is turned on. The low-level signal transmitted through the second power signal line VSSQ is transmitted to the second node P(i) through the twelfth transistor T53, causing the potential of the second node P(i) to drop to a low potential state. When the stage transmission signal output terminal ST(i-4) of the (i-4)th stage gate drive unit outputs a high-level signal, the thirteenth transistor T54 is turned on. The low-level signal transmitted through the second power signal line VSSQ is transmitted to the second node P(i) through the thirteenth transistor T54, causing the potential of the second node P(i) to drop to a low potential state. When the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit outputs a high-level signal, the fourteenth transistor T55 is turned on. The low-level signal transmitted through the second power signal line VSSQ is transmitted to the second node P(i) through the fourteenth transistor T55, causing the potential of the second node P(i) to drop to a low potential state. When the stage transmission signal output terminal ST(i+4) of the (i+4)th stage gate drive unit outputs a high-level signal, the fifteenth transistor T56 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the second node P(i) through the fifteenth transistor T56, causing the potential of the second node P(i) to drop to a low potential state. When the first node Q(i) is in a high potential state, the sixteenth transistor T57 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the second node P(i) through the sixteenth transistor T57, causing the potential of the second node P(i) to drop to a low potential state.

[0065] The gates of the twelfth transistor T53, the thirteenth transistor T54, the fourteenth transistor T55, the fifteenth transistor T56, and the sixteenth transistor T57 are respectively electrically connected to the stage transmission signal output terminal ST(i-8) of the i-8th stage gate drive unit, the stage transmission signal output terminal ST(i-4) of the i-4th stage gate drive unit, the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, the stage transmission signal output terminal ST(i+4) of the i+4th stage gate drive unit, and the first node Q(i). The stage transmission signal received by the first inverter covers the same waveform width range as the signal of the first node Q(i). The first inverter operates normally during the entire effective level of the signal of the first node Q(i), ensuring the output performance of the gate drive circuit.

[0066] As a dedicated signal within the gate drive unit, the stage transmission signal is unaffected by signals within the display area of ​​the display panel, resulting in more stable control signals received by the first inverter. The first inverter, controlled by both the stage transmission signal and the first node Q(i), exhibits enhanced stability. Even if either the stage transmission signal or the first node Q(i) signal fails, the first inverter continues to operate normally, relying on either the stage transmission signal or the first node Q(i) signal for input, thus improving the reliability of the gate drive circuit.

[0067] The channel widths of transistors T53, T54, T55, T56, and T57 are greater than that of transistor T52, which in turn has a greater channel width than T51. This ensures a more reliable waveform output from the first inverter, improving the stability of the gate drive circuit. The larger channel widths of transistors T53, T54, T55, T56, and T57 result in stronger current drive capability during conduction, leading to a faster potential drop at the second node P(i) and a faster response from the first inverter. The moderate channel width of transistor T52 provides adequate current drive capability during conduction, ensuring a faster potential drop at the second node P(i) while avoiding the increased area caused by an excessively large channel width. The channel width of the tenth transistor T51 is relatively small, which makes the current driving capability of the tenth transistor T51 weak when it is turned on. This results in a slower potential rise rate of the second node P(i), avoiding the malfunction of the first inverter caused by the potential rise of the second node P(i) too fast.

[0068] The second inverter includes transistors T61 (21st), T62 (22nd), T63 (23rd), T64 (24th), T65 (25th), T66 (26th), and T67 (27th). The pull-down sustaining unit 104 also includes transistors T81 (28th), T82 (29th), T83 (30th), and T84 (31st).

[0069] The gate of transistor T61 (21st stage) is electrically connected to the second control signal line LC2. One of the sources and drains of transistor T61 is also electrically connected to the second control signal line LC2, and the other of the sources and drains of transistor T61 is electrically connected to the third node K(i). The gate of transistor T62 (22nd stage) is electrically connected to the first control signal line LC1. One of the sources and drains of transistor T62 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of transistor T62 is electrically connected to the third node K(i). The gate of transistor T63 (23rd stage) is electrically connected to the stage transmission signal output terminal ST(ia) of the ia-th stage gate drive unit. One of the sources and drains of transistor T63 is also electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of transistor T63 is electrically connected to the third node K(i). The gate of the 24th transistor T64 is electrically connected to the stage transmission signal output terminal ST(ib) of the ib-th stage gate drive unit. One of the sources and drains of the 24th transistor T64 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the 24th transistor T64 is electrically connected to the third node K(i). The gate of the 25th transistor T65 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit. One of the sources and drains of the 25th transistor T65 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the 25th transistor T65 is electrically connected to the third node K(i). The gate of the 26th transistor T66 is electrically connected to the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate drive unit. One of the sources and drains of the 26th transistor T66 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the 26th transistor T66 is electrically connected to the third node K(i). The gate of the 27th transistor T67 is electrically connected to the first node Q(i). One of the sources and drains of the 27th transistor T67 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the 27th transistor T67 is electrically connected to the third node K(i). The gate of the 28th transistor T81 is electrically connected to the third node K(i). One of the sources and drains of the 28th transistor T81 is electrically connected to the third power supply signal line VSSG. The other of the sources and drains of the 28th transistor T81 is electrically connected to the first gate drive signal output terminal G(2i-1). The gate of the 29th transistor T82 is electrically connected to the third node K(i). One of the sources and drains of the 29th transistor T82 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the 29th transistor T82 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit.The gate of the 30th transistor T83 is electrically connected to the third node K(i). One of the sources and drains of the 30th transistor T83 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the 30th transistor T83 is electrically connected to the first node Q(i). The gate of the 31st transistor T84 is electrically connected to the third node K(i). One of the sources and drains of the 31st transistor T84 is electrically connected to the third power supply signal line VSSG, and the other of the sources and drains of the 31st transistor T84 is electrically connected to the second gate drive signal output terminal G(2i), where a, b, and c are positive integers.

[0070] In one embodiment, a is 8, b is 4, and c is 4. The gate of the twenty-third transistor T63 is electrically connected to the stage transmission signal output terminal ST(i-8) of the (i-8)th stage gate drive unit, the gate of the twenty-fourth transistor T64 is electrically connected to the stage transmission signal output terminal ST(i-4) of the (i-4)th stage gate drive unit, and the gate of the twenty-sixth transistor T66 is electrically connected to the stage transmission signal output terminal ST(i+4) of the (i+4)th stage gate drive unit.

[0071] When the second control signal line LC2 outputs a high-level signal, the twenty-first transistor T61 is turned on. The high-level signal transmitted by the second control signal line LC2 is transmitted to the third node K(i) through the twenty-first transistor T61, causing the potential of the third node K(i) to rise to a high potential state. When the third node K(i) is in a high potential state, the twenty-eighth transistor T81, the twenty-ninth transistor T82, the thirtieth transistor T83, and the thirty-first transistor T84 are simultaneously turned on. The low-level signal transmitted by the third power supply signal line VSSG is transmitted to the first gate drive signal output terminal G(2i-1) through the twenty-eighth transistor T81, causing the potential of the first gate drive signal output terminal G(2i-1) to remain in a low potential state. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the i-th stage gate drive unit through the twenty-ninth transistor T82. The stage transmission signal output terminal ST(i) is connected to maintain the potential of the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit at a low potential. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the first node Q(i) through the thirtieth transistor T83, so that the potential of the first node Q(i) is maintained at a low potential. The low-level signal transmitted by the third power supply signal line VSSG is transmitted to the second gate drive signal output terminal G(2i) through the thirty-first transistor T84, so that the potential of the second gate drive signal output terminal G(2i) is maintained at a low potential.

[0072] When the first control signal line LC1 outputs a high-level signal, the twenty-second transistor T62 is turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the third node K(i) through the twenty-second transistor T62, causing the potential of the third node K(i) to drop to a low potential state. When the third node K(i) is in a low potential state, the twenty-eighth transistor T81, the twenty-ninth transistor T82, the thirtieth transistor T83, and the thirty-first transistor T84 are simultaneously turned off. The potentials of the first gate drive signal output terminal G(2i-1), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, the first node Q(i), and the second gate drive signal output terminal G(2i) are not affected by the second inverter.

[0073] When the stage transmission signal output terminal ST(i-8) of the (i-8)th stage gate drive unit outputs a high-level signal, the twenty-third transistor T63 is turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the third node K(i) through the twenty-third transistor T63, causing the potential of the third node K(i) to drop to a low potential state. When the stage transmission signal output terminal ST(i-4) of the (i-4)th stage gate drive unit outputs a high-level signal, the twenty-fourth transistor T64 is turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the third node K(i) through the twenty-fourth transistor T64, causing the potential of the third node K(i) to drop to a low potential state. When the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit outputs a high-level signal, the twenty-fifth transistor T65 is turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the third node K(i) through the twenty-fifth transistor T65, causing the potential of the third node K(i) to drop to a low potential state. When the stage transmission signal output terminal ST(i+4) of the (i+4)th stage gate drive unit outputs a high-level signal, the twenty-sixth transistor T66 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the third node K(i) through the twenty-sixth transistor T66, causing the potential of the third node K(i) to drop to a low potential state. When the first node Q(i) is in a high potential state, the twenty-seventh transistor T67 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the third node K(i) through the twenty-seventh transistor T67, causing the potential of the third node K(i) to drop to a low potential state.

[0074] The gates of transistors T63 (23rd), T64 (24th), T65 (25th), T66 (26th), and T67 (27th) are electrically connected to the stage transmission signal output terminals ST(i-8), ST(i-4), ST(i-4), ST(i), and ST(i+4) of the (i-8th), (i-4th), (i-1st), and (i+4th) of the gate drive unit, respectively, and to the first node Q(i). The stage transmission signal received by the second inverter covers the same waveform width range as the signal of the first node Q(i). The second inverter operates normally throughout the entire effective level of the signal of the first node Q(i), ensuring the output performance of the gate drive circuit.

[0075] As a dedicated signal within the gate drive unit, the stage transmission signal is unaffected by signals within the display area of ​​the display panel, resulting in more stable control signals received by the second inverter. The second inverter, controlled by both the stage transmission signal and the first node Q(i), exhibits enhanced stability. Even if either the stage transmission signal or the first node Q(i) signal fails, the second inverter continues to operate normally, relying on either the stage transmission signal or the first node Q(i) signal for input, thus improving the reliability of the gate drive circuit.

[0076] The channel widths of transistors T63 (23), T64 (24), T65 (25), T66 (26), and T67 (27) are greater than that of transistor T62 (22), and the channel width of T62 is greater than that of transistor T61 (21). This size configuration results in a highly reliable waveform output by the second inverter, improving the stability of the gate drive circuit. The larger channel widths of transistors T63, T64, T65, T66, and T67 give them stronger current drive capability when turned on, resulting in a faster potential drop at the third node K(i) and a faster response speed for the second inverter. The moderate channel width of transistor T62 provides it with appropriate current drive capability when turned on, ensuring a fast potential drop at the third node K(i) while avoiding an increase in area due to an excessively large channel width. The channel width of the 21st transistor T61 is relatively small, which makes its current driving capability weak when it is turned on. This results in a slower potential rise rate of the third node K(i), thus avoiding the malfunction of the second inverter caused by the potential rise of the third node K(i) too fast.

[0077] In one embodiment, the widths W1, W2, W3, W4 of the effective pulses of the stage-transmitted signal output from ST(ia) of the ia-th stage gate driving unit, ST(ib) of the ib-th stage gate driving unit, and ST(i+c) of the i-th stage gate driving unit are all smaller than the width W5 of the effective pulse of the signal transmitted by the first node Q(i). Furthermore, the widths W1, W2, W3, and W4 of the effective pulses of the stage-transmitted signal output from ST(i+c) of the i+c stage gate driving unit are all smaller than the width W5 of the effective pulse of the signal transmitted by the first node Q(i). The sum of the width W3 of the effective pulse of the output stage transmission signal and the width W4 of the effective pulse of the stage transmission signal output terminal ST(i+c) of the i+c stage gate drive unit (W1+W2+W3+W4) is greater than the width W5 of the effective pulse of the signal transmitted by the first node Q(i).

[0078] The first and second inverters operate alternately. When the first control signal line LC1 outputs a high-level signal, the first inverter operates, and the second inverter does not. Conversely, when the second control signal line LC2 outputs a high-level signal, the second inverter operates, and the first inverter does not. This alternating operation avoids the performance degradation caused by prolonged operation of a single inverter, thus extending the lifespan of the gate drive circuit. Furthermore, the alternating operation halves the operating time of each inverter, thereby reducing the stress time of the thin-film transistor (TFT), lowering its threshold voltage drift, and improving the stability of the gate drive circuit.

[0079] Embodiments of this application also provide a driving method for a display device. The display device includes a display panel, which includes at least one gate driving circuit and a plurality of pixel units PX. The plurality of pixel units PX includes 2N rows of pixel units PX. The gate driving circuit includes N levels of gate driving units. The i-th level gate driving unit is electrically connected to the gate line SCAN of the (2i-1)-th row of pixel units PX and the gate line SCAN of the 2i-th row of pixel units PX. The i-th level gate driving unit includes a pull-up unit 102, which includes a first transistor T21 and a second transistor T23. The gate of transistor T1 and the gate of transistor T23 are both electrically connected to the first node Q(i). One of the source and drain of the first transistor T21 is electrically connected to the first clock signal line CK(j), and the other of the source and drain of the first transistor T21 is electrically connected to the first gate drive signal output terminal G(2i-1). One of the source and drain of the second transistor T23 is electrically connected to the second clock signal line CK(j+1), and the other of the source and drain of the second transistor T23 is electrically connected to the second gate drive signal output terminal G(2i), where i and N are positive integers, and i is less than or equal to N.

[0080] The driving method includes: when the first node Q(i) is in a high potential state, the first transistor T21 is turned on, and the first clock signal transmitted by the first clock signal line CK(j) is transmitted to the first gate drive signal output terminal G(2i-1) through the first transistor T21; the second transistor T23 is turned on, and the second clock signal transmitted by the second clock signal line CK(j+1) is transmitted to the second gate drive signal output terminal G(2i) through the second transistor T23; the output time of the effective level of the first clock signal and the second clock signal is different.

[0081] The i-th stage gate drive unit also includes a pull-down sustaining unit 104. The pull-down sustaining unit 104 includes a first inverter and a second inverter. Both the first inverter and the second inverter include multiple transistors electrically connected to the stage transmission signal output terminals of different stages. The width of the effective pulse of any one of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is less than the width of the effective pulse of the signal transmitted by the first node Q(i). The sum of the widths of the effective pulses of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is greater than the width of the effective pulse of the signal transmitted by the first node Q(i).

[0082] Both the first inverter and the second inverter include four transistors that are electrically connected to the stage transmission signal output terminal ST(ia) of the ia-th stage gate driving unit, the stage transmission signal output terminal ST(ib) of the ib-th stage gate driving unit, the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit, and the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate driving unit, respectively.

[0083] In one embodiment, the widths W1, W2, W3, W4 of the effective pulses of the stage-transmitted signal output from ST(ia) of the ia-th stage gate driving unit, ST(ib) of the ib-th stage gate driving unit, and ST(i+c) of the i-th stage gate driving unit are all smaller than the width W5 of the effective pulse of the signal transmitted by the first node Q(i). Furthermore, the widths W1, W2, W3, and W4 of the effective pulses of the stage-transmitted signal output from ST(i+c) of the i+c stage gate driving unit are all smaller than the width W5 of the effective pulse of the signal transmitted by the first node Q(i). The sum of the width W3 of the effective pulse of the output stage transmission signal and the width W4 of the effective pulse of the stage transmission signal output terminal ST(i+c) of the i+c stage gate drive unit (W1+W2+W3+W4) is greater than the width W5 of the effective pulse of the signal transmitted by the first node Q(i).

[0084] like Figure 3 As shown, the driving cycle of a frame displayed on the display panel includes a first time period S1, a second time period S2, a third time period S3, a fourth time period S4, and a fifth time period S5.

[0085] The driving method further includes: in the first time period S1, the stage transmission signal output terminal ST(ia) of the ia-th stage gate driving unit outputs a high-level signal, the stage transmission signal output terminal ST(ib) of the ib-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit outputs a low-level signal, and the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate driving unit outputs a low-level signal, and the potential of the first node Q(i) is a first potential. In the second time period S2, the stage transmission signal output terminal ST(ia) of the ia-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(ib) of the ib-th stage gate driving unit outputs a high-level signal, the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit outputs a low-level signal, and the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate driving unit outputs a low-level signal, and the potential of the first node Q(i) is a second potential, which is higher than the first potential. During the third time period S3, the stage transmission signal output terminal ST(ia) of the ia-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(ib) of the ib-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit outputs a high-level signal, and the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate driving unit outputs a low-level signal. The potential of the first node Q(i) is the third potential, which is higher than the second potential. During the fourth time period S4, the stage transmission signal output terminal ST(ia) of the ia-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(ib) of the ib-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit outputs a low-level signal, and the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate driving unit outputs a high-level signal. The potential of the first node Q(i) is the second potential. During the fifth time period S5, the stage transmission signal output terminal ST(ia) of the ia-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(ib) of the ib-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(i) of the i-th stage gate driving unit outputs a low-level signal, the stage transmission signal output terminal ST(i+c) of the i+c-th stage gate driving unit outputs a low-level signal, and the potential of the first node Q(i) is the first potential, where a, b, and c are positive integers.

[0086] During the second time period S2, the potential of the first node Q(i) is the second potential. During the third time period S3, the potential of the first node Q(i) is the third potential. During the fourth time period S4, the potential of the first node Q(i) is the second potential. Both the second and third potentials are high potentials. The first transistor T21 and the second transistor T23 are all turned on during the second time period S2, the third time period S3, and the fourth time period S4. The first clock signal transmitted by the first clock signal line CK(j) is transmitted to the first gate drive signal output terminal G(2i-1) through the first transistor T21. The second clock signal transmitted by the second clock signal line CK(j+1) is transmitted to the second gate drive signal output terminal G(2i) through the second transistor T23. Since the output times of the effective levels of the first clock signal and the second clock signal are different, the first gate drive signal output terminal G(2i-1) and the second gate drive signal output terminal G(2i) output effective levels at different times, thereby realizing the function of outputting two gate drive signals by the first-level gate drive unit.

[0087] The i-th stage gate driving unit further includes a reset unit 103, which is electrically connected to the first node Q(i), the first gate driving signal output terminal G(2i-1), the second gate driving signal output terminal G(2i), and the stage transmission signal output terminal ST(i). The driving method further includes: during the reset phase, the reset unit 103 pulls down the potentials of the first node Q(i), the first gate driving signal output terminal G(2i-1), the second gate driving signal output terminal G(2i), and the stage transmission signal output terminal ST(i) to a low potential state.

[0088]

[0089] Table 1 As shown in Table 1, the display device provided in the embodiments of this application was verified on a 22-inch full HD resolution display panel. The number of clock signal lines was 12 to 16, the duty cycle of the clock signal was 40% to 44%, the voltage transmitted by the first power signal line VGH was 25 to 30 volts, the threshold voltage positive offset margin was 7 volts (a criterion for being greater than 5 volts), the threshold voltage negative offset margin was -7 volts (a criterion for being less than -4 volts), the transistor electrical offset reliability verification passed, the transistor electrical offset reliability verification plus 3 volts passed, the 80-degree Celsius electrical parameter table verification passed, the -20-degree Celsius electrical parameter table verification passed, and the voltage margin of the first power signal line VGH was 5 volts (a criterion for being less than 10 volts). The verification results show that the technical solution of this application, while maintaining the same reliability as traditional gate drive units, reduces the bezel width of the display panel, meeting the requirements of narrow bezel display panels.

[0090] The technical solution of this application, compared to the conventional gate drive circuit which uses a two-stage gate drive unit to output the gate drive signal for driving two rows of pixel units PX, including 32 thin-film transistors, uses a single-stage gate drive unit with 31 thin-film transistors, saving one thin-film transistor and improving reliability. Compared to the conventional high-reliability gate drive circuit which uses a two-stage gate drive unit to output the gate drive signal for driving two rows of pixel units PX, including 40 or more thin-film transistors, the technical solution of this application saves at least 9 thin-film transistors while meeting the same reliability requirements, reducing the area occupied by the gate drive circuit and meeting the needs of narrow-bezel display panels.

[0091] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, which includes at least one gate driving circuit and a plurality of pixel units. The plurality of pixel units include 2N rows of pixel units. The gate driving circuit includes N levels of gate driving units, and the i-th level gate driving unit is electrically connected to the gate line of the (2i-1)-th row of pixel units and the gate line of the 2i-th row of pixel units. The i-th stage gate drive unit includes: The pull-up control unit is configured to control the potential of the first node; A pull-up unit includes a first transistor and a second transistor. The gate of the first transistor is electrically connected to the first node. One of the source and drain of the first transistor is electrically connected to a first clock signal line. The other of the source and drain of the first transistor is electrically connected to a first gate drive signal output terminal. The gate of the second transistor is electrically connected to the first node. One of the source and drain of the second transistor is electrically connected to a second clock signal line. The other of the source and drain of the second transistor is electrically connected to a second gate drive signal output terminal. The pull-down sustaining unit includes at least two inverters, which are electrically connected to the stage transmission signal output terminal of the i-th stage gate drive unit, the first node, the first gate drive signal output terminal, and the second gate drive signal output terminal. Where i and N are positive integers, and i is less than or equal to N.

2. The display device according to claim 1, characterized in that, The pull-up control unit includes a third transistor, the gate of which is electrically connected to the stage transmission signal output terminal of the ixth stage gate driving unit, one of the source and drain of the third transistor is electrically connected to the first power supply signal line or the stage transmission signal output terminal of the ixth stage gate driving unit, and the other of the source and drain of the third transistor is electrically connected to the first node, where x is a positive integer.

3. The display device according to claim 2, characterized in that, The x is half the number of clock signal lines of the gate drive circuit.

4. The display device according to claim 1, characterized in that, The pull-up unit further includes a fourth transistor, the gate of which is electrically connected to the first node, one of the source and drain of the fourth transistor is electrically connected to the first clock signal line, and the other of the source and drain of the fourth transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate driving unit.

5. The display device according to claim 1, characterized in that, The i-th level gate driving unit further includes a reset unit, which includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the fifth transistor is electrically connected to a reset control signal line, one of the source and drain of the fifth transistor is electrically connected to a second power supply signal line, and the other of the source and drain of the fifth transistor is electrically connected to the first node. The gate of the sixth transistor is electrically connected to the reset control signal line, one of the source and drain of the sixth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the sixth transistor is electrically connected to the first node. The gate of the seventh transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate driving unit. The gate of the seventh transistor is electrically connected to the reset control signal line. One of the source and drain of the seventh transistor is electrically connected to the third power supply signal line. The other of the source and drain of the seventh transistor is electrically connected to the first gate driving signal output terminal. The gate of the eighth transistor is electrically connected to the reset control signal line. One of the source and drain of the eighth transistor is electrically connected to the third power supply signal line. The other of the source and drain of the eighth transistor is electrically connected to the second gate driving signal output terminal.

6. The display device according to claim 1, characterized in that, The i-th stage gate driving unit further includes a pull-down unit, which includes a ninth transistor. The gate of the ninth transistor is electrically connected to the stage transmission signal output terminal of the (i+y)-th stage gate driving unit. One of the source and drain of the ninth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the ninth transistor is electrically connected to the first node, where y is a positive integer.

7. The display device according to claim 1, characterized in that, The at least two inverters include a first inverter and a second inverter. Both the first inverter and the second inverter include multiple transistors electrically connected to the output terminals of different stages of the transmission signal. The width of the effective pulse of any one of the transmission signals output from the multiple stages of the transmission signal output terminals is less than the width of the effective pulse of the signal transmitted by the first node. The sum of the widths of the effective pulses of the transmission signals output from the multiple stages of the transmission signal output terminals is greater than the width of the effective pulse of the signal transmitted by the first node.

8. The display device according to claim 7, characterized in that, The first inverter includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; The pull-down sustaining unit also includes the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor; The gate of the tenth transistor is electrically connected to the first control signal line. One of the source and drain of the tenth transistor is electrically connected to the first control signal line, and the other of the source and drain of the tenth transistor is electrically connected to the second node. The gate of the eleventh transistor is electrically connected to the second control signal line. One of the source and drain of the eleventh transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eleventh transistor is electrically connected to the second node. The gate of the twelfth transistor is electrically connected to the stage transmission signal output terminal of the ia-th stage gate drive unit. One of the source and drain of the twelfth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the twelfth transistor... The gate of the thirteenth transistor is electrically connected to the second node. The gate of the thirteenth transistor is electrically connected to the stage transmission signal output terminal of the ib-level gate drive unit. One of the source and drain of the thirteenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the thirteenth transistor is electrically connected to the second node. The gate of the fourteenth transistor is electrically connected to the stage transmission signal output terminal of the i-th level gate drive unit. One of the source and drain of the fourteenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the fourteenth transistor is electrically connected to the second node. The gate of the fifteenth transistor is electrically connected to the stage transmission signal output terminal of the (i+c)-th level gate drive unit. The source of the fifteenth transistor... One of the source and drain terminals of the fifteenth transistor is electrically connected to the second power supply signal line; the other of the source and drain terminals of the fifteenth transistor is electrically connected to the second node; the gate of the sixteenth transistor is electrically connected to the first node; one of the source and drain terminals of the sixteenth transistor is electrically connected to the second power supply signal line; the other of the source and drain terminals of the sixteenth transistor is electrically connected to the second node; the gate of the seventeenth transistor is electrically connected to the second node; one of the source and drain terminals of the seventeenth transistor is electrically connected to the third power supply signal line; the other of the source and drain terminals of the seventeenth transistor is electrically connected to the first gate drive signal output terminal; and the gate of the eighteenth transistor is electrically connected to the second node. One of the source and drain of the eighteenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eighteenth transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate drive unit. The gate of the nineteenth transistor is electrically connected to the second node, and one of the source and drain of the nineteenth transistor is electrically connected to the second power supply signal line. The other of the source and drain of the nineteenth transistor is electrically connected to the first node. The gate of the twentieth transistor is electrically connected to the second node. One of the source and drain of the twentieth transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the twentieth transistor is electrically connected to the second gate drive signal output terminal.Where a, b, and c are positive integers.

9. The display device according to claim 8, characterized in that, The channel widths of the twelfth, thirteenth, fourteenth, fifteenth, and sixteenth transistors are greater than the channel width of the eleventh transistor, and the channel width of the eleventh transistor is greater than the channel width of the tenth transistor.

10. The display device according to claim 7, characterized in that, The second inverter includes transistors 21, 22, 23, 24, 25, 26, and 27. The pull-down sustaining unit also includes a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, and a thirty-first transistor; The gate of the 21st transistor is electrically connected to the second control signal line. One of the source and drain of the 21st transistor is electrically connected to the second control signal line, and the other of the source and drain of the 21st transistor is electrically connected to the third node. The gate of the 22nd transistor is electrically connected to the first control signal line. One of the source and drain of the 22nd transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the 22nd transistor is electrically connected to the third node. The gate of the 23rd transistor is electrically connected to the stage transmission signal output terminal of the ia-th stage gate drive unit. One of the source and drain of the 23rd transistor is electrically connected to the second power supply signal line. One of the source and drain of the transistor is electrically connected to the third node; the gate of the twenty-fourth transistor is electrically connected to the stage transmission signal output terminal of the ib-level gate driving unit; one of the source and drain of the twenty-fourth transistor is electrically connected to the second power supply signal line; the other of the source and drain of the twenty-fourth transistor is electrically connected to the third node; the gate of the twenty-fifth transistor is electrically connected to the stage transmission signal output terminal of the i-level gate driving unit; one of the source and drain of the twenty-fifth transistor is electrically connected to the second power supply signal line; the other of the source and drain of the twenty-fifth transistor is electrically connected to the third node; and the gate of the twenty-sixth transistor is connected to the (i+c)-level gate driving unit. The output terminal of the stage transmission signal is electrically connected. One of the source and drain of the 26th transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the 26th transistor is electrically connected to the third node. The gate of the 27th transistor is electrically connected to the first node. One of the source and drain of the 27th transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the 27th transistor is electrically connected to the third node. The gate of the 28th transistor is electrically connected to the third node. One of the source and drain of the 28th transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the 28th transistor is driven by the first gate. The signal output terminal is electrically connected. The gate of the twenty-ninth transistor is electrically connected to the third node. One of the source and drain of the twenty-ninth transistor is electrically connected to the second power supply signal line. The other of the source and drain of the twenty-ninth transistor is electrically connected to the stage transmission signal output terminal of the i-th stage gate drive unit. The gate of the thirtieth transistor is electrically connected to the third node. One of the source and drain of the thirtieth transistor is electrically connected to the second power supply signal line. The other of the source and drain of the thirtieth transistor is electrically connected to the first node. The gate of the thirty-first transistor is electrically connected to the third node. One of the source and drain of the thirty-first transistor is electrically connected to the third power supply signal line.The other of the source and drain of the thirty-first transistor is electrically connected to the output terminal of the second gate drive signal, where a, b, and c are positive integers.

11. The display device according to claim 10, characterized in that, The channel widths of the 23rd, 24th, 25th, 26th, and 27th transistors are greater than the channel width of the 22nd transistor, and the channel width of the 22nd transistor is greater than the channel width of the 21st transistor.

12. The display device according to claim 1, characterized in that, The first gate drive signal output terminal is electrically connected to the gate line of the 2i-1 row pixel unit, and the second gate drive signal output terminal is electrically connected to the gate line of the 2i row pixel unit.

13. The display device according to claim 1, characterized in that, The pull-up unit further includes a first capacitor, the first plate of the first capacitor being electrically connected to the first node, and the second plate of the first capacitor being electrically connected to the first gate drive signal output terminal; and / or the pull-up unit further includes a second capacitor, the first plate of the second capacitor being electrically connected to the first node, and the second plate of the second capacitor being electrically connected to the second gate drive signal output terminal.

14. The display device according to any one of claims 1 to 13, characterized in that, The transistor in the i-th gate drive unit is an oxide semiconductor thin-film transistor.

15. A driving method for a display device, characterized in that, The display device includes a display panel, which includes at least one gate driving circuit and a plurality of pixel units. The plurality of pixel units include 2N rows of pixel units. The gate driving circuit includes N levels of gate driving units. The i-th level gate driving unit is electrically connected to the gate line of the (2i-1)-th row of pixel units and the gate line of the 2i-th row of pixel units. The i-th level gate driving unit includes a pull-up unit. The pull-up unit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are both electrically connected to a first node. One of the source and drain of the first transistor is electrically connected to a first clock signal line. The other of the source and drain of the first transistor is electrically connected to a first gate driving signal output terminal. One of the source and drain of the second transistor is electrically connected to a second clock signal line. The other of the source and drain of the second transistor is electrically connected to a second gate driving signal output terminal. The driving method includes: When the first node is in a high potential state, the first transistor is turned on, and the first clock signal transmitted by the first clock signal line is transmitted to the first gate drive signal output terminal through the first transistor. The second transistor is turned on, and the second clock signal transmitted by the second clock signal line is transmitted to the second gate drive signal output terminal through the second transistor. The output time of the effective level of the first clock signal and the second clock signal is different. Where i and N are positive integers, and i is less than or equal to N.

16. The driving method according to claim 15, characterized in that, The i-th stage gate driving unit further includes a pull-down sustaining unit, which includes a first inverter and a second inverter. Both the first inverter and the second inverter include multiple transistors electrically connected to the stage transmission signal output terminals of different stages. The width of the effective pulse of any one of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is less than the width of the effective pulse of the signal transmitted by the first node, and the sum of the widths of the effective pulses of the stage transmission signals output from the multiple stage transmission signal output terminals of different stages is greater than the width of the effective pulse of the signal transmitted by the first node.

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