Pixel driving circuit and display device

Abstract

The pixel driving circuit comprises a plurality of sub-driving circuits, each sub-driving circuit corresponds to one pixel unit, each sub-driving circuit comprises a pre-storage unit and a driving unit, the pre-storage unit comprises a first transistor, and a first end of the first transistor is used for receiving a data signal; the driving unit comprises a second transistor, the first end of the second transistor is coupled with the second end of the first transistor, the second end of the second transistor is coupled with the pixel electrode of the pixel unit corresponding to the sub-driving circuit, and the control end of the second transistor is used for receiving a transfer signal; wherein in the sub-drive circuits in adjacent rows, the two sub-drive circuits in the same column correspond to each other, the sub-drive circuit in one row further comprises a pre-storage capacitor, the first end of the pre-storage capacitor is coupled with the second end of the first transistor, and the second end of the pre-storage capacitor is coupled with a common electrode; in the sub-drive circuits in adjacent rows, the corresponding two sub-drive circuits share the same first transistor.

Description

Technical Field

[0001] This invention relates to the field of display devices, and particularly to a pixel driving circuit and a display device. Background Technology

[0002] In color-sequential display technology, the backlight can only be turned on after all the data signals for the entire image have been written. This significantly reduces the backlight's on-time, thus decreasing display brightness. Pre-charging methods can shorten the data signal writing time, thereby increasing the backlight's on-time and improving brightness. However, improving pre-charging efficiency remains a crucial problem to be solved. Summary of the Invention

[0003] To address the aforementioned problems, this invention proposes a pixel driving circuit for driving a pixel array, wherein the pixel array comprises a plurality of pixel units arranged in an array, and the pixel driving circuit comprises a plurality of sub-driving circuits, each sub-driving circuit corresponding to one pixel unit, the sub-driving circuit comprising:

[0004] Pre-store unit and drive unit,

[0005] The pre-storage unit includes:

[0006] The first transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal is used to receive a scan signal, and the first terminal is used to receive a data signal.

[0007] The driving unit includes:

[0008] The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit. The control terminal is used to receive a transfer signal.

[0009] In the sub-driving circuits of adjacent rows, two sub-driving circuits in the same column correspond to each other, and one row of sub-driving circuits includes:

[0010] A pre-storage capacitor has a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor, and the second terminal being coupled to a common electrode;

[0011] In the adjacent row of sub-driving circuits, the second terminal of the first transistor of each sub-driving circuit in the other row is coupled to the second terminal of the first transistor of the corresponding sub-driving circuit.

[0012] In one embodiment of the pixel driving circuit described above, the sub-driving circuit further includes:

[0013] Reset unit, comprising:

[0014] The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit, the second terminal is coupled to the common electrode, and the control terminal is used to receive a reset signal.

[0015] In one embodiment of the pixel driving circuit described above, the pixel driving circuit is configured as follows:

[0016] Within the current frame time, for the first portion of pixel units, the first transistor is turned on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the first portion of pixel units completes voltage pre-storage, the second transistor is turned on based on a first transfer signal. The second transistor outputs the voltage of the first portion of pixel units for the next frame to the pixel electrode based on the pre-charge voltage. For the second portion of pixel units, the first transistor is turned on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the second portion of pixel units completes voltage pre-storage, the second transistor is turned on based on a second transfer signal. The second transistor outputs the voltage of the second portion of pixel units for the next frame to the pixel electrode based on the pre-charge voltage.

[0017] In one embodiment of the pixel driving circuit described above, the pixel driving circuit is configured as follows:

[0018] When the first transfer signal changes from low level to high level, the corresponding second transistor turns on based on the first transfer signal. The first reset signal corresponds to the first transfer signal. The first reset signal is high level during the non-display stage. When the first transfer signal is high level, the first reset signal is low level.

[0019] When the second transfer signal changes from low to high, the corresponding second transistor turns on based on the second transfer signal. The second reset signal corresponds to the second transfer signal. The second reset signal is high during the non-display phase, and low when the second transfer signal is high.

[0020] In one embodiment of the pixel driving circuit described above, the time during which the first reset signal is low is greater than the time during which the first transfer signal is high, and / or, the time during which the second reset signal is low is greater than the time during which the second transfer signal is high.

[0021] The present invention also provides a display device, including a display panel and a backlight module. The display panel includes a pixel driving circuit and a pixel array. The pixel driving circuit is connected to the pixel array and is used to drive the pixel array. The pixel array includes a plurality of pixel units arranged in an array. The pixel driving circuit includes a plurality of sub-driving circuits, each of the sub-driving circuits corresponding to one pixel unit. The sub-driving circuit includes:

[0022] Pre-store unit and drive unit,

[0023] The pre-storage unit includes:

[0024] The first transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal is used to receive a scan signal, and the first terminal is used to receive a data signal.

[0025] The driving unit includes:

[0026] The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit. The control terminal is used to receive a transfer signal.

[0027] In the sub-driving circuits of adjacent rows, two sub-driving circuits in the same column correspond to each other, and one row of sub-driving circuits includes:

[0028] A pre-storage capacitor has a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor, and the second terminal being coupled to a common electrode;

[0029] In the adjacent row of sub-driving circuits, the second terminal of the first transistor of each sub-driving circuit in the other row is coupled to the second terminal of the first transistor of the corresponding sub-driving circuit.

[0030] In one embodiment of the above-described display device, the sub-driving circuit further includes:

[0031] Reset unit, comprising:

[0032] The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit, the second terminal is coupled to the common electrode, and the control terminal is used to receive a reset signal.

[0033] In one embodiment of the above-described display device, the pixel driving circuit is configured as follows:

[0034] Within the current frame time, for the first portion of pixel units, the first transistor is turned on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the first portion of pixel units completes voltage pre-storage, the second transistor is turned on based on a first transfer signal. The second transistor outputs the voltage of the first portion of pixel units for the next frame to the pixel electrode based on the pre-charge voltage. For the second portion of pixel units, the first transistor is turned on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the second portion of pixel units completes voltage pre-storage, the second transistor is turned on based on a second transfer signal. The second transistor outputs the voltage of the second portion of pixel units for the next frame to the pixel electrode based on the pre-charge voltage.

[0035] In one embodiment of the above-described display device, the pixel driving circuit is configured as follows:

[0036] When the first transfer signal changes from low level to high level, the corresponding second transistor turns on based on the first transfer signal. The first reset signal corresponds to the first transfer signal. The first reset signal is high level during the non-display stage. When the first transfer signal is high level, the first reset signal is low level.

[0037] When the second transfer signal changes from low to high, the corresponding second transistor turns on based on the second transfer signal. The second reset signal corresponds to the second transfer signal. The second reset signal is high during the non-display phase, and low when the second transfer signal is high.

[0038] In one embodiment of the above-described display device, the duration of the first reset signal being low is greater than the duration of the first transfer signal being high, and / or the duration of the second reset signal being low is greater than the duration of the second transfer signal being high.

[0039] The pixel driving circuit and display device disclosed in this invention improve the pre-charging efficiency of the overall display panel by sharing the first transistor in one row of sub-driving circuits in the adjacent rows of sub-driving circuits.

[0040] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0041] Figure 1 A schematic diagram of a pixel driving circuit in a prior art embodiment is shown.

[0042] Figure 2 A schematic diagram of a pixel driving circuit in one embodiment of the present invention is shown.

[0043] Figure 3 A waveform diagram of a pixel driving circuit in one embodiment of the present invention is shown.

[0044] Figure 4 A schematic diagram of a display device according to an embodiment of the present invention is shown.

[0045] In the attached figures, the following labels are used:

[0046] 10…pixel driving circuit

[0047] T1…First transistor

[0048] T2…Second transistor

[0049] T3…Third transistor

[0050] Cs1…Pre-stored capacitor

[0051] Cs2…holding capacitor

[0052] Clc…pixel capacitor

[0053] Reset… resets the signal.

[0054] Reset_even... First reset signal

[0055] Reset_odd...Second reset signal

[0056] Tran…transfer signal

[0057] Tran_even…First transfer signal

[0058] Tran_odd…Second transfer signal

[0059] Scan, Scan1, Scan2… scan signals

[0060] Com… Common Electrode

[0061] 100… display device

[0062] AA… Display Area

[0063] BA…surrounding area

[0064] 20...Substrate

[0065] GL…scan line

[0066] DL… data cable Detailed Implementation

[0067] The following specific embodiments, in conjunction with the accompanying drawings, illustrate the implementation methods disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. However, the following disclosure is not intended to limit the scope of protection of this invention. Without departing from the spirit of the invention, those skilled in the art can implement this invention with other different embodiments based on different viewpoints and applications.

[0068] For clarity, the figures shown in this invention are simplified schematic diagrams illustrating the basic structure of the invention. Therefore, the structures shown in the figures are not drawn to scale according to the actual shape and size of the implementation. For example, the dimensions of certain components have been enlarged for ease of explanation.

[0069] Furthermore, it should be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another component, it may be directly on or connected to the other component, or an intermediate component may also be present. Conversely, when a component is referred to as being "directly on" or "directly connected" to another component, no intermediate component exists. As used herein, "connection" can refer to physical and / or electrical connections. Moreover, "electrical connection" or "coupling" can refer to the presence of other components between the two components.

[0070] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of the relevant technology and this invention, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0071] Furthermore, it should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, the “first component,” “part,” “region,” “layer,” or “part” discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings of this document.

[0072] Please see Figures 1 to 4 , Figure 1 A schematic diagram of a pixel driving circuit in a prior art embodiment is shown. Figure 2 A schematic diagram of a pixel driving circuit in one embodiment of the present invention is shown. Figure 3A waveform diagram of a pixel driving circuit in one embodiment of the present invention is shown. Figure 4 A schematic diagram of a display device according to an embodiment of the present invention is shown. Figure 1 As shown, the scanning signal controls the first transistor T1 to turn on. The first transistor T1 outputs a pre-charge voltage based on the data signal Data and stores it in the pre-storage capacitor Cs1. After all pixels have completed voltage pre-storage, the transfer signal Tran controls the second transistor T2 to turn on. The second transistor T2 outputs the voltage required for the next frame of the pixel to the pixel electrode based on the pre-charge voltage, forming a voltage difference with the common electrode Com, completing the deflection of the liquid crystal target angle, and turning on the backlight to complete the image display. Figure 2 As shown, to address the pre-charging efficiency problem of display panels, this invention proposes a pixel driving circuit 10 for driving a pixel array. The pixel array includes multiple pixel units arranged in an array. The pixel driving circuit 10 includes multiple sub-driving circuits, each corresponding to one pixel unit. Each sub-driving circuit includes a pre-storage unit and a driving unit. The pre-storage unit includes at least a first transistor T1, which has a first terminal, a second terminal, and a control terminal. The control terminal of the first transistor T1 is used to receive a scan signal, and the first terminal of the first transistor T1 is used to receive a data signal. The driving unit includes at least a second transistor T2, which has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor T2 is coupled to the second terminal of the first transistor T1. The second terminal of the second transistor T2 is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit. The control terminal of the second transistor T2 is used to receive transfer signals (Tran_even, Tran_odd). In adjacent rows of sub-driving circuits, two sub-driving circuits in the same column correspond to each other. One row of sub-driving circuits includes a pre-storage capacitor Cs1, which has a first terminal and a second terminal. The first terminal of the pre-storage capacitor Cs1 is coupled to the second terminal of the first transistor T1, and the second terminal of the pre-storage capacitor Cs1 is coupled to a common electrode. In another row of sub-driving circuits, the second terminal of the first transistor T1 of each sub-driving circuit is coupled to the second terminal of the first transistor T1 of the corresponding sub-driving circuit. Another row of sub-driving circuits does not include a pre-storage capacitor Cs1, but its corresponding sub-driving circuit shares the pre-storage capacitor Cs1. By sharing the first transistor T1 in one row of sub-driving circuits in adjacent rows, the pre-charging efficiency of the overall display panel is improved.

[0073] In one embodiment, the sub-driving circuit further includes a reset unit, which includes a third transistor T3. The third transistor T3 has a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor T3 is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit, and the second terminal of the third transistor T3 is coupled to a common electrode. The control terminal of the third transistor T3 is used to receive a reset signal (Reset_even, Reset_odd). By outputting the reset signal (Reset_even, Reset_odd) before outputting the transfer signal (Tran_even, Tran_odd) to complete the reset of the pixel voltage, the pixel voltage can be prevented from being affected by the previous frame.

[0074] like Figure 2 and Figure 3 As shown, in one embodiment, the pixel driving circuit 10 is configured to: during the current frame time, for the first part of the pixel units, control the first transistor T1 to turn on based on the scan signal, the first transistor T1 outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor Cs1, and after the first part of the pixel units completes voltage pre-storage, control the second transistor T2 to turn on based on a first transfer signal Tran_even, and the second transistor T2 outputs the voltage of the first part of the pixel units in the next frame to the pixel electrode based on the pre-charge voltage (in this process, the capacitance of the holding capacitor Cs2 is much larger than the capacitance of the pixel capacitor Clc, the holding capacitor Cs2 is used to hold the voltage of the next frame pixel, and the pixel capacitor Clc is used to drive the liquid crystal to twist); for the second part of the pixel units, control the first transistor T1 to turn on based on the scan signal, the first transistor T1 outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor Cs1, and after the second part of the pixel units completes voltage pre-storage, control the second transistor T2 to turn on based on a second transfer signal Tran_odd, and the second transistor T2 outputs the voltage of the second part of the pixel units in the next frame to the pixel electrode based on the pre-charge voltage. In one embodiment, the first portion of pixel units consists of pixel units in odd-numbered rows, and the second portion consists of pixel units in even-numbered rows. In another embodiment, the first portion of pixel units consists of pixel units in even-numbered rows, and the second portion consists of pixel units in odd-numbered rows, which is suitable for reverse scanning scenarios. Thus, by sharing the pre-charge capacitors of the odd-numbered row pixel units with the even-numbered row pixel driving circuit 10, the odd-numbered and even-numbered row pixel units are displayed sequentially. With high refresh rate support, normal display functionality can be achieved, while improving pre-charging efficiency and reducing the number of pre-charge capacitors. Furthermore, the reduced number of pre-charge capacitors increases the aperture ratio, which also helps improve the display effect.

[0075] In one embodiment, the pixel driving circuit 10 is configured as follows:

[0076] When the first transfer signal Tran_even changes from low to high, the corresponding second transistor T2 turns on based on the first transfer signal Tran_even. The first reset signal Reset_even corresponds to the first transfer signal Tran_even. The first reset signal Reset_even is high during the non-display phase. When the first transfer signal Tran_even is high, the first reset signal Reset_even is low.

[0077] When the second transfer signal Tran_odd transitions from low to high, the corresponding second transistor T2 turns on. The second reset signal Reset_odd corresponds to Tran_odd; it is high during the non-display phase, and low when Tran_odd is high. Because voltage coupling between adjacent signal lines becomes more severe under high refresh rate conditions, optimizing the timing of the Reset signal can improve image quality. Enabling the Reset signal throughout the non-display phase can mitigate display abnormalities caused by leakage current in the second transistor T2.

[0078] In one embodiment, the duration of the first reset signal Reset_even being low is greater than the duration of the first transfer signal Tran_even being high, and / or, the duration of the second reset signal Reset_odd being low is greater than the duration of the second transfer signal Tran_odd being high. Outputting the reset signal Reset before outputting the transfer signal Tran to reset the pixel voltage avoids the pixel voltage being affected by the previous frame.

[0079] like Figure 4 As shown, the present invention also provides a display device 100, including a display panel and a backlight module. The display panel includes a substrate 20 and a display area AA and a peripheral area BA on the substrate 20. Multiple scan lines GL and multiple data lines DL intersect to define multiple pixel units arranged in an array. A pixel driving circuit 10 is connected to the pixel array and is used to drive the pixel array. The pixel driving circuit 10 includes multiple sub-driving circuits, each sub-driving circuit corresponding to a pixel unit. The sub-driving circuits are the same as those described above and will not be repeated here.

[0080] The pixel driving circuit and display device disclosed in this invention improve the pre-charging efficiency of the overall display panel by sharing the first transistor in one row of sub-driving circuits in adjacent rows of sub-driving circuits.

[0081] The above-disclosed content is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, any equivalent technical changes made based on the contents of the present invention specification and drawings fall within the scope of the patent application of the present invention.

Claims

1. A pixel driving circuit for driving a pixel array, the pixel array comprising a plurality of pixel units arranged in an array, the pixel driving circuit comprising a plurality of sub-driving circuits, each of the sub-driving circuits corresponding to one pixel unit, characterized in that, The sub-driving circuit includes: Pre-store unit and drive unit, The pre-storage unit includes: The first transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal is used to receive a scan signal, and the first terminal is used to receive a data signal. The driving unit includes: The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit. The control terminal is used to receive a transfer signal. In the sub-driving circuits of adjacent rows, two sub-driving circuits in the same column correspond to each other, and one row of sub-driving circuits includes: A pre-storage capacitor has a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor, and the second terminal being coupled to a common electrode; In the adjacent row of sub-driving circuits, the second terminal of the first transistor of each sub-driving circuit in the other row is coupled to the second terminal of the first transistor of the corresponding sub-driving circuit.

2. The pixel driving circuit according to claim 1, characterized in that, The sub-driving circuit also includes: Reset unit, comprising: The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit, the second terminal is coupled to the common electrode, and the control terminal is used to receive a reset signal.

3. The pixel driving circuit according to claim 2, characterized in that, The pixel driving circuit is configured as follows: Within the current frame time, for the first part of the pixel units, the first transistor is controlled to turn on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the first part of the pixel units completes voltage pre-storage, the second transistor is controlled to turn on based on a first transfer signal. The second transistor outputs the voltage of the first part of the pixel units in the next frame to the pixel electrode based on the pre-charge voltage. For the pixel unit in the second part, the first transistor is turned on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the pixel unit in the second part completes the voltage pre-storage, the second transistor is turned on based on a second transfer signal. The second transistor outputs the voltage of the second pixel unit in the next frame to the pixel electrode based on the pre-charge voltage.

4. The pixel driving circuit according to claim 3, characterized in that, The pixel driving circuit is configured as follows: When the first transfer signal changes from low level to high level, the corresponding second transistor turns on based on the first transfer signal. The first reset signal corresponds to the first transfer signal. The first reset signal is high level during the non-display stage. When the first transfer signal is high level, the first reset signal is low level. When the second transfer signal changes from low to high, the corresponding second transistor turns on based on the second transfer signal. The second reset signal corresponds to the second transfer signal. The second reset signal is high during the non-display phase, and low when the second transfer signal is high.

5. The pixel driving circuit according to claim 4, characterized in that, The duration of the first reset signal being low is greater than the duration of the first transfer signal being high, and / or the duration of the second reset signal being low is greater than the duration of the second transfer signal being high.

6. A display device, comprising a display panel and a backlight module, the display panel comprising a pixel driving circuit and a pixel array, the pixel driving circuit being connected to the pixel array and used to drive the pixel array, the pixel array comprising a plurality of pixel units arranged in an array, the pixel driving circuit comprising a plurality of sub-driving circuits, each sub-driving circuit corresponding to one pixel unit, characterized in that, The sub-driving circuit includes: Pre-store unit and drive unit, The pre-storage unit includes: The first transistor has a first terminal, a second terminal, and a control terminal, wherein the control terminal is used to receive a scan signal, and the first terminal is used to receive a data signal. The driving unit includes: The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the second terminal of the first transistor, and the second terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit. The control terminal is used to receive a transfer signal. In the sub-driving circuits of adjacent rows, two sub-driving circuits in the same column correspond to each other, and one row of sub-driving circuits includes: A pre-storage capacitor has a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor, and the second terminal being coupled to a common electrode; In the adjacent row of sub-driving circuits, the second terminal of the first transistor of each sub-driving circuit in the other row is coupled to the second terminal of the first transistor of the corresponding sub-driving circuit.

7. The display device according to claim 6, characterized in that, The sub-driving circuit also includes: Reset unit, comprising: The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the pixel electrode of the pixel unit corresponding to the sub-driving circuit, the second terminal is coupled to the common electrode, and the control terminal is used to receive a reset signal.

8. The display device according to claim 7, characterized in that, The pixel driving circuit is configured as follows: Within the current frame time, for the first part of the pixel units, the first transistor is controlled to turn on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the first part of the pixel units completes voltage pre-storage, the second transistor is controlled to turn on based on a first transfer signal. The second transistor outputs the voltage of the first part of the pixel units in the next frame to the pixel electrode based on the pre-charge voltage. For the pixel unit in the second part, the first transistor is turned on based on the scan signal. The first transistor outputs a pre-charge voltage based on the data signal and stores it in the pre-storage capacitor. After the pixel unit in the second part completes the voltage pre-storage, the second transistor is turned on based on a second transfer signal. The second transistor outputs the voltage of the second pixel unit in the next frame to the pixel electrode based on the pre-charge voltage.

9. The display device according to claim 8, characterized in that, The pixel driving circuit is configured as follows: When the first transfer signal changes from low level to high level, the corresponding second transistor turns on based on the first transfer signal. The first reset signal corresponds to the first transfer signal. The first reset signal is high level during the non-display stage. When the first transfer signal is high level, the first reset signal is low level. When the second transfer signal changes from low to high, the corresponding second transistor turns on based on the second transfer signal. The second reset signal corresponds to the second transfer signal. The second reset signal is high during the non-display phase, and low when the second transfer signal is high.

10. The display device according to claim 9, characterized in that, The duration of the first reset signal being low is greater than the duration of the first transfer signal being high, and / or the duration of the second reset signal being low is greater than the duration of the second transfer signal being high.

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