LED chip with vertical structure and preparation method thereof

Abstract

The invention provides an LED chip with a vertical structure and a preparation method thereof, the chip comprises a conductive substrate, a bonding metal layer, a reflecting layer, a current blocking layer, an epitaxial layer and an N electrode from bottom to top in sequence, and the epitaxial layer is of a mesa structure; the current blocking layer is composed of a middle region current blocking layer and an edge region current blocking layer which are not connected with each other; the current blocking layer in the middle area corresponds to the vertical projection position of the N electrode on the plane of the conductive substrate, the projection of the N electrode on the plane of the conductive substrate is a closed annular pattern, and the closed annular pattern is in mirror symmetry along the vertical axis and the horizontal axis of the center of the chip. The problem of electric leakage caused by chip cracks due to non-uniform thermal stress distribution and overlarge local stress of the chip is effectively solved, and the reliability of the LED chip with the vertical structure is improved.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diodes, and more particularly to a vertical structure LED chip and its fabrication method. Background Technology

[0002] Compared to traditional upright LED structures, vertical LEDs offer advantages such as better heat dissipation, higher current handling capacity, higher luminous intensity, and lower power consumption, making them widely used in high-power lighting applications. In vertical LED chips, two electrodes are located on opposite sides of the epitaxial wafer. When energized, almost all current flows through the LED epitaxial layer, with very little current flowing laterally. The area below the N-electrode is where current injection is most concentrated; light emitted from this area is blocked or absorbed by the N-electrode, resulting in ineffective light emission and reducing the LED's luminous intensity and efficiency. To address this issue, a common solution in vertical LEDs is to introduce a current blocking layer below the electrodes. This layer prevents direct vertical current injection between the upper and lower electrodes, reducing the current density in the active region below the N-electrode and suppressing light emission from this region, thereby improving luminous efficiency.

[0003] For example, Chinese invention patent CN117393662A discloses a method for fabricating a current blocking layer and a vertical structure LED chip on a silicon substrate. By suppressing the light emission of the active region below the N-electrode through the current blocking layer, more uniform current diffusion is achieved, thereby improving the chip's luminous efficiency. However, this solution has a significant drawback: the current blocking layers in each region are completely interconnected, such as... Figure 1 As shown, when LED chips are used in high-temperature and high-humidity environments, the long-term accumulated thermal stress can easily cause cracks at the interface of the current blocking layer, ultimately leading to LED chip failure. Meanwhile, in this design, the electrode lines of the N electrode are arranged parallel to each other along the vertical direction, as shown... Figure 2 As shown, this electrode line design makes the areas on the top and bottom sides of the chip without lateral electrodes more susceptible to thermal stress accumulation than the left and right sides of the chip, which can lead to chip cracks and cause abnormal reliability of the LED chip. Summary of the Invention

[0004] In view of the above problems, the present invention provides a vertical structure LED chip and its fabrication method to solve the reliability problems of vertical structure LED chips in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a vertical structure LED chip, comprising, from bottom to top, a conductive substrate, a bonding metal layer, a reflective layer, a current blocking layer, an epitaxial layer, and an N-electrode. The epitaxial layer has a mesa structure. The current blocking layer consists of an unconnected intermediate region current blocking layer and an edge region current blocking layer. The intermediate region current blocking layer corresponds to the vertical projection position of the N-electrode on the plane of the conductive substrate. The projection of the N-electrode on the plane of the conductive substrate is a closed annular pattern, and the closed annular pattern is mirror-symmetrical along the vertical axis and the horizontal axis of the chip center.

[0006] The vertical structure LED chip provided by this invention designs the current blocking layers as a middle region current blocking layer and an edge region current blocking layer that are not connected to each other. The edge region current blocking layer is separated from the middle region current blocking layer, which effectively improves the problem of LED chip failure caused by cracks extending into the current blocking layer and epitaxial layer due to long-term thermal stress accumulation. At the same time, the N electrode is designed as a closed ring pattern, and the closed ring pattern is mirror-symmetrical along the vertical axis and horizontal axis of the chip center, so that the current is more evenly distributed on the four sides of the LED chip, which improves the problem of uneven thermal stress distribution caused by unbalanced current expansion.

[0007] As an alternative to the vertical structure LED chip of the present invention, the vertical projection of the current blocking layer in the middle region completely covers the vertical projection of the N electrode; the N electrode is composed of pads and electrode lines, and the electrode lines at the edge form a closed ring pattern.

[0008] As an optional embodiment of the vertical structure LED chip of the present invention, the edge region current blocking layer is located between the epitaxial layer and the bonding metal layer, and the edge region current blocking layer covers part of the sidewall of the reflective layer; the projection of the edge region current blocking layer on the conductive substrate plane is a closed ring pattern, and the closed ring pattern corresponds to the outer edge of the mesa structure of the epitaxial layer.

[0009] As an alternative to the vertical structure LED chip of the present invention, the projection of the epitaxial layer on the plane of the conductive substrate completely covers the reflective layer.

[0010] As an optional embodiment of the vertical structure LED chip of the present invention, the material of the current blocking layer is one or more of SiO2, Si3N4, SiON, TiO2, Ti3O5, Al2O3, Nb2O5, and Ta2O5; the thickness of the current blocking layer is 100Å to 8000Å.

[0011] As an optional embodiment of the vertical structure LED chip of the present invention, the material of the reflective layer is one or more of Au, Ag, NiAu, NiAg, AuBe, and AuZn.

[0012] This invention also provides a method for fabricating a vertical LED chip, comprising the following steps: S1. Provide a growth substrate and form an epitaxial layer on the growth substrate. The epitaxial layer includes an N-type layer, a quantum well layer and a P-type layer stacked sequentially on the growth substrate. S2. A current blocking layer is formed on the P-type layer; S3. Etching the current blocking layer exposes the P-type layer, forming patterned, unconnected intermediate and edge current blocking layers. Both the intermediate and edge current blocking layers are closed ring patterns, and the closed ring pattern of the intermediate current blocking layer is mirror-symmetrical along the vertical and horizontal axes of the chip center. S4. Form a reflective layer on the current blocking layer; S5. Form a bonding metal layer on the reflective layer; S6. Bond a conductive substrate onto the bonding metal layer; S7. Remove the growth substrate to expose the N-type layer; S8. Etching removes the periphery of the epitaxial layer to form a mesa structure; S9. An N-electrode is formed on the surface of the N-type layer. The N-electrode corresponds to the position of the current blocking layer in the middle region, and the vertical projection of the current blocking layer in the middle region completely covers the projection of the N-electrode.

[0013] As an optional embodiment of the preparation method of the present invention, the method for forming the reflective layer in step S4 is to sputter or vapor-deposit the reflective layer on the surface of the current blocking layer, and etch or peel off the reflective layer at the edge of the chip; the formed reflective layer completely covers the current blocking layer in the middle region and covers part of the current blocking layer in the edge region.

[0014] As a preferred embodiment of the above optional solutions, in step S5, the bonding metal layer completely covers the reflective layer, and the bonding metal layer covers the area of ​​the edge region where the current blocking layer is not covered by the reflective layer.

[0015] As an optional embodiment of the preparation method of the present invention, in step S8, etching removes the periphery of the epitaxial layer to expose a portion of the edge region current blocking layer, and the mesa structure completely covers the reflective layer and a portion of the edge region current blocking layer.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, some of which will become clear as the description proceeds, and others will be learned by practicing the invention. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of the current blocking layer of a vertically structured LED chip in the prior art.

[0019] Figure 2 This is a top view of the N-electrode of a vertically structured LED chip in the prior art.

[0020] Figure 3 This is a cross-sectional schematic diagram of the epitaxial layer after growth in an embodiment of the present invention.

[0021] Figure 4 This is a cross-sectional view of the current blocking layer after it has been formed in an embodiment of the present invention.

[0022] Figure 5 This is a cross-sectional view of the patterned current blocking layer in an embodiment of the present invention.

[0023] Figure 6 This is a top view of the patterned current blocking layer in an embodiment of the present invention.

[0024] Figure 7 This is a cross-sectional view of the reflective layer after it has been formed in an embodiment of the present invention.

[0025] Figure 8 This is a top view of the reflective layer after it has been formed in an embodiment of the present invention.

[0026] Figure 9 This is a cross-sectional view of the bonding metal layer after it has been formed in an embodiment of the present invention.

[0027] Figure 10 This is a cross-sectional view of the conductive substrate after bonding in an embodiment of the present invention.

[0028] Figure 11 This is a cross-sectional view after removing the growth substrate in an embodiment of the present invention.

[0029] Figure 12 This is a cross-sectional schematic diagram of the epitaxial layer after etching to form a mesa structure in an embodiment of the present invention.

[0030] Figure 13 This is a top view of the epitaxial layer after etching to form a mesa structure in an embodiment of the present invention.

[0031] Figure 14This is a cross-sectional view of the N-electrode formed in an embodiment of the present invention.

[0032] Figure 15 This is a top view schematic diagram of the N-electrode formed in an embodiment of the present invention.

[0033] Component labeling: 10 Conductive substrate, 11 Bonding metal layer, 12 Reflective layer, 13 Current blocking layer, 131 Middle region current blocking layer, 132 Edge region current blocking layer, 14 Epitaxial layer, 141 P-type layer, 142 Quantum well layer, 143 N-type layer, 15 N electrode, 151 Pad, 152 Electrode line, 16 Growth substrate. Detailed Implementation

[0034] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] The invention will be described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the invention. Although the illustrations only show components related to the invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] Vertical LED chips contain semiconductor, insulating, and metallic materials. The different coefficients of thermal expansion of these materials lead to varying degrees of thermal stress accumulation during use in high-temperature and high-humidity environments. This can cause interface delamination between the reflective and current-blocking layers, and between the reflective and epitaxial layers, resulting in cracks in the current-blocking and epitaxial layers, metal migration, and ultimately catastrophic chip failure. The applicant's research revealed that these cracks extend from the edges to the center, and the current-blocking layers in the central and edge regions have different functions. The primary function of the central current-blocking layer is to block direct vertical current injection between the upper and lower electrodes, reducing the current density in the active region below the N-electrode and suppressing light emission from this region. This results in a more uniform current distribution in the vertical LED chip, improving its photoelectric performance. The edge current-blocking layer, on the other hand, primarily blocks the direct connection between conductive metal particles adhering to the PN junction sidewalls of the epitaxial layer and the metal layer, preventing leakage paths and improving chip manufacturing yield. Without an edge region current blocking layer, when metal particles adhere to the sidewalls of the epitaxial layer, these particles will directly conduct to the reflective layer or bonding metal layer, forming a leakage path. With an edge region current blocking layer, even if metal particles adhere to the sidewalls of the quantum well, a leakage path cannot be formed because the current blocking layer is an insulating material and does not conduct electricity. Therefore, the probability of leakage can still be reduced even without protecting the PN junction sidewalls of the epitaxial layer. This application creatively designs the current blocking layer as an unconnected intermediate region current blocking layer and an edge region current blocking layer, blocking the extension of cracks without affecting the current spreading function, thus improving the reliability of the chip. Based on this, embodiments of this application provide a vertical structure LED chip, such as... Figure 14 , 15 As shown, from bottom to top, the structure includes a conductive substrate 10, a bonding metal layer 11, a reflective layer 12, a current blocking layer 13, an epitaxial layer 14, and an N-electrode 15. The epitaxial layer 14 has a mesa structure. The current blocking layer 13 consists of an unconnected intermediate region current blocking layer 131 and an edge region current blocking layer 132. The intermediate region current blocking layer 131 corresponds to the vertical projection position of the N-electrode 15 on the plane of the conductive substrate 10. The projection of the N-electrode 15 on the plane of the conductive substrate is a closed ring pattern, and the closed ring pattern is mirror-symmetrical along the vertical axis and horizontal axis of the chip center. The projection of the edge region current blocking layer 132 on the plane of the conductive substrate 10 is also a closed ring pattern.

[0037] It should be noted that the current blocking layer in the middle region and the current blocking layer in the edge region are not connected. When cracks appear in the current blocking layer in the edge region due to long-term thermal stress accumulation, the cracks will not extend from the edge region to the middle region, thus preventing LED chip failure and improving the lifespan of the LED chip. Simultaneously, the N-electrode is designed as a closed ring pattern, and this closed ring pattern is mirror-symmetrical along the vertical and horizontal axes of the chip center. This makes the current distribution more uniform around the four sides of the LED chip, improving the problem of uneven thermal stress distribution caused by unbalanced current expansion, thereby reducing the probability of cracks appearing in the current blocking layer. Furthermore, the middle region current blocking layer corresponds to the vertical projection position of the N-electrode on the conductive substrate plane, specifically blocking the current congestion effect below the N-electrode, resulting in more uniform current expansion in the vertical structure LED chip.

[0038] In some embodiments, the vertical projection of the intermediate current blocking layer 131 completely covers the vertical projection of the N electrode 15; the N electrode 15 consists of pads 151 and electrode lines 152, with the edge electrode lines 152 forming a closed ring pattern. Since the area of ​​the intermediate current blocking layer is greater than or equal to that of the N electrode, current cannot flow along the vertical path directly below the electrode. To reach the N electrode, the current must "bypass" the intermediate current blocking layer, expanding laterally within the epitaxial layer and flowing to the unblocked area outside the edge of the intermediate current blocking layer. This promotes lateral current expansion, alleviates the current congestion effect below the N electrode, and makes current diffusion more uniform. The edge electrode lines forming a closed ring further facilitates current expansion within the chip, and balances the stress on all four sides of the chip.

[0039] In some embodiments, the edge region current blocking layer 132 is located between the epitaxial layer 14 and the bonding metal layer 11, and the edge region current blocking layer 132 covers part of the sidewall of the reflective layer 12; the projection of the edge region current blocking layer 132 onto the plane of the conductive substrate 10 is a closed annular pattern, and the closed annular pattern corresponds to the outer edge of the mesa structure of the epitaxial layer 14. Forming a closed annular pattern can ensure that the edge of the epitaxial layer mesa is surrounded by the current blocking layer, effectively improving the leakage problem caused by metal contamination on the sidewall of the epitaxial layer mesa.

[0040] In some embodiments, the projection of the epitaxial layer 14 onto the plane of the conductive substrate 10 completely covers the reflective layer 12. It should be noted that the reflective layer material is typically metal, and metal materials are prone to metal migration issues in LEDs. The fact that the projection of the reflective layer onto the plane of the conductive substrate is completely covered by the projection of the MESA mesa helps to prevent metal migration to the PN junction of the epitaxial layer, thus avoiding LED chip failure. In some embodiments, the material of the current blocking layer 13 is one or more of SiO2, Si3N4, SiON, TiO2, Ti3O5, Al2O3, Nb2O5, and Ta2O5; the thickness of the current blocking layer 13 is 100 Å to 8000 Å. The current blocking layer is an insulating material with two functions. First, the current blocking layer in the middle region corresponds to the vertical projection position of the N electrode on the conductive substrate plane, which allows the injected current to be effectively spread, alleviates the current congestion below the N electrode, and improves the uniform distribution of the current, thereby improving the luminous performance of the vertical structure LED chip. Second, the current blocking layer in the edge region blocks the direct conduction channel between the metal particles and other conductors adhering to the PN junction sidewalls of the epitaxial layer and the metal layer, avoiding the formation of leakage current paths and improving the chip manufacturing yield.

[0041] In some embodiments, the material of the reflective layer 12 is one or more of Au, Ag, NiAu, NiAg, AuBe, and AuZn. Using these materials allows the reflective layer to form an ohmic contact with the P-type layer while also possessing a certain reflectivity, enabling it to reflect light back to the light-emitting surface, thereby improving light extraction efficiency.

[0042] This application also provides a method for fabricating a vertical structure LED chip, such as... Figure 3-15 As shown, it includes the following steps: S1. Provide a growth substrate 16, and form an epitaxial layer 14 on the growth substrate 16. The epitaxial layer 14 includes an N-type layer 143, a quantum well layer 142 and a P-type layer 141 stacked sequentially on the growth substrate 16. S2. A current blocking layer 13 is formed on the P-type layer 141; S3, the etching current blocking layer 13 exposes the P-type layer 141, forming a patterned, unconnected middle region current blocking layer 131 and edge region current blocking layer 132; both the middle region current blocking layer 131 and the edge region current blocking layer 132 are closed ring patterns, and the closed ring pattern of the middle region current blocking layer 131 is mirror symmetrical along the vertical axis and horizontal axis of the chip center. S4. A reflective layer 12 is formed on the current blocking layer 13; S5. A bonding metal layer 11 is formed on the reflective layer 12; S6. Bond the conductive substrate 10 onto the bonding metal layer 11; S7. Remove the growth substrate 16 to expose the N-type layer 143; S8. Etching removes the four edges of the epitaxial layer 14 to form a mesa structure. It should be noted that since subsequent chip dicing requires the reservation of dicing trenches, the four edges of the epitaxial layer 14 need to be etched during the design to leave a certain gap between the edge of the mesa and the edge of the chip. After the epitaxial layer is etched, the PN junction in the epitaxial layer is exposed. During chip fabrication and subsequent use, metal particles and other conductors may come into contact with the PN junction, causing LED chip leakage, affecting LED chip yield and reliability. The function of the current blocking layer 132 in the edge region is mainly to block the direct conduction channel between the metal particles and other conductors adhering to the sidewall of the PN junction and the metal layer, avoiding the formation of leakage path and improving chip manufacturing yield.

[0043] S9. An N-electrode 15 is formed on the surface of the N-type layer 143. The N-electrode 15 corresponds to the position of the current blocking layer 131 in the middle region, and the vertical projection of the current blocking layer 131 in the middle region completely covers the projection of the N-electrode 15.

[0044] In some embodiments, the method for forming the reflective layer 12 in step S4 is to sputter or vapor-deposit the reflective layer 12 on the surface of the current blocking layer 13, and etch or peel off the reflective layer 12 at the chip edge; the formed reflective layer 12 completely covers the current blocking layer 131 in the middle region and covers a portion of the current blocking layer 132 in the edge region. The reflective layer is one of the key design features that distinguishes vertical LED chips from horizontal structures and enables high performance. The reflective layer efficiently reflects light back to the light-emitting surface, solving the problem of light absorption by the substrate, while also undertaking the critical tasks of conductivity and heat dissipation. As a material that directly contacts the P-type layer, an ohmic contact needs to be formed between the reflective layer and the P-type layer. Its material selection and process optimization directly determine the brightness, efficiency, and lifespan of the LED.

[0045] In some embodiments, in step S5, the bonding metal layer 11 completely covers the reflective layer 12, and the bonding metal layer 11 covers the area of ​​the edge region current blocking layer 132 not covered by the reflective layer 12. Bonding is a crucial process step in the manufacturing of vertical structure LED chips. Bonding involves connecting the epitaxial layer grown on the original substrate to a new support substrate (conductive substrate) via the bonding metal layer, followed by removal of the original substrate by methods such as laser lift-off or chemical etching. The bonding metal layer needs to undergo eutectic reaction, diffusion, or interatomic bonding with the metal layer on the conductive substrate under specific process conditions (such as heating and pressurization) to form a strong, dense, and uniform bonding interface.

[0046] In some embodiments, in step S8, etching removes the periphery of the epitaxial layer 14, exposing a portion of the edge region current blocking layer 132. The mesa structure completely covers the reflective layer 12 and the remaining area of ​​the edge region current blocking layer 132. The reflective layer is made of materials such as Au, Ag, NiAu, NiAg, AuBe, and AuZn. When used in harsh environments such as high temperature and high humidity, metal migration problems are prone to occur. The epitaxial mesa structure completely covers the reflective layer, which can prevent migrating metal ions from climbing to the sidewalls of the epitaxial mesa and causing a PN junction short circuit.

[0047] In some embodiments, the deposition equipment used in step S2 is one or more of plasma-enhanced chemical vapor deposition (PECVD), electron beam evaporation (EBOD), atomic layer deposition (ALD), and optical thin film deposition (OSD). The current blocking layer is an insulating material such as SiO2, Si3N4, SiON, TiO2, Ti3O5, Al2O3, Nb2O5, or Ta2O5. The quality of the current blocking layer (e.g., density, uniformity, absence of pinholes, and controllable stress) directly determines the upper limit of performance and the lower limit of reliability of the vertical structure LED chip. Selecting an appropriate film deposition technology to ensure the growth of a high-quality current blocking layer is one of the key processes in manufacturing high-performance vertical structure LED chips.

[0048] In some embodiments, the growth substrate 16 is a substrate suitable for LED chip manufacturing, such as a sapphire substrate, silicon substrate, silicon carbide substrate, or patterned substrate. The epitaxial layer is formed by arranging atoms layer by layer on the surface of the growth substrate. The choice of growth substrate is mainly determined by crystal matching and epitaxial growth process. The conductive substrate is the supporting body of the final chip and can be a metal substrate or a silicon substrate. The selection of the conductive substrate needs to consider its electrical and thermal conductivity as well as the growth and manufacturing cost.

[0049] In some embodiments, the bonding metal layer 11 is made of one or more of Cr, Ni, Ti, Cu, In, Pt, Au, and Sn. As part of the P-electrode, the bonding metal layer, together with the conductive substrate, provides a low-resistance vertical path for current from the top electrode to the bottom electrode. Furthermore, the Joule heating and non-radiative recombination heat generated during LED operation can drastically increase the junction temperature; therefore, the bonding metal layer needs to be selected from the aforementioned materials with high thermal conductivity and low resistance.

[0050] In some embodiments, step S7 further includes roughening the N-type layer 143. Roughening is achieved by using chemical or physical methods to create a microscopic or nanoscale uneven textured structure on the light-emitting surface or sidewalls of the chip, fundamentally solving the core problem of "total internal reflection" that restricts the light-emitting efficiency of LEDs, thereby "liberating" more internal photons and converting them into useful light output, thus improving the luminous efficiency of the chip.

[0051] The following are some embodiments of this application. The embodiments of the present invention will further describe in detail each technical step and process parameter in the preparation process. Example 1

[0052] This embodiment provides a method for fabricating a vertical structure LED chip, including the following steps: Step S1: Provide a growth substrate 16, and grow an epitaxial layer 14 on the growth substrate 16 using a metal-organic chemical vapor deposition (MOCVD) apparatus. The epitaxial layer 14 includes an N-type layer 143, a quantum well layer 142, and a P-type layer 141 sequentially stacked on the growth substrate 16, such as... Figure 3 As shown. Among them, the growth substrate 16 is a 4-inch silicon substrate with a thickness of 1030µm; the N-type layer 143 is N-type GaN, the quantum well layer 142 is InGaN / GaN multiple quantum well, and the P-type layer 141 is P-type GaN.

[0053] Step S2: A current blocking layer 13 is deposited on the p-type layer 141 using a plasma-enhanced chemical vapor deposition (Plasmalab 800 Plus) apparatus (Oxford Instruments). The deposition rate is 10 Å / s. The material of the current blocking layer 13 is SiO2, and the thickness of the current blocking layer 13 is 1500 Å. Figure 4 As shown.

[0054] Step S3: Perform photolithography patterning and etching on the current blocking layer 13 to expose the P-type layer 141, forming the central region current blocking layer 131 and the edge region current blocking layer 132, as shown. Figure 5 As shown. The central region current blocking layer 131 and the edge region current blocking layer 132 are not connected to each other. The central region current blocking layer 131 is located in the central region, and the edge region current blocking layer 132 is located in the surrounding region. Both the central region current blocking layer 131 and the edge region current blocking layer 132 are closed annular patterns. The closed annular pattern of the central region current blocking layer 131 is mirror-symmetrical along the vertical axis and horizontal axis of the chip center, as shown. Figure 6 As shown.

[0055] Step S4: An electron beam evaporation coating system (ULVAC Ei-5z evaporation coating machine) is used to deposit a reflective layer 12 on the entire surface of the current blocking layer 13. The material of the reflective layer 12 is NiAg. Then, the reflective layer 12 at the chip edge is removed through spin coating, exposure, development, and wet etching. The distance from the edge of the formed reflective layer 12 to the chip edge is 30 μm. Figure 7 , 8 As shown, the reflective layer 12 completely covers the current blocking layer 131 in the middle region and a portion of the current blocking layer 132 in the edge region. It contacts the P-type layer 141 through the gap in the current blocking layer 13 and forms an ohmic contact.

[0056] Step S5: A bonding metal layer 11 is prepared on the reflective layer 12 using a vapor deposition process. The material of the bonding metal layer 11 is CuIn, and the bonding metal layer 11 covers the entire surface, such as... Figure 9 As shown.

[0057] Step S6: A conductive substrate 10 is bonded to the bonding metal layer 11 using a high-temperature bonding process. The conductive substrate 10 is a silicon substrate with a thickness of 170µm. Figure 10 As shown.

[0058] Step S7: The growth substrate 16 is removed by chemical etching to expose the N-type layer 143, as shown below. Figure 11 As shown, the surface of the N-type layer 143 is roughened using an ICP etching and humidification process, making the surface of the N-type layer 143 rough (not shown in the figure), increasing the light-emitting area, and thus improving the light-emitting efficiency of the LED.

[0059] Step S8: Perform photolithography on the epitaxial layer 14, and use a wet etching process to remove the periphery of the epitaxial layer 14 to form a mesa structure, such as... Figure 12 , 13 As shown, the distance from the edge of the mesa structure to the edge of the chip is 20μm, which allows the mesa structure to completely cover the reflective layer 12, which helps to prevent metal from migrating to the PN junction and causing the LED chip to fail.

[0060] Step S9: An N-electrode 15 is formed on the surface of the N-type layer 143 using a vapor deposition process and a metal stripping process, such as... Figure 14 As shown. The material of the N electrode is CrPtAu. The N electrode 15 corresponds to the position of the current blocking layer 131 in the middle region, and the vertical projection of the current blocking layer 131 in the middle region completely covers the projection of the N electrode 15. The pattern of the N electrode 15 is also a closed ring pattern, which is mirror-symmetrical along the vertical axis and horizontal axis of the chip center, as shown. Figure 15 As shown. Example 2

[0061] This embodiment provides a vertical structure LED chip, which is prepared using the method provided in Embodiment 1, such as... Figure 14 As shown, from bottom to top, it includes a conductive substrate 10, a bonding metal layer 11, a reflective layer 12, a current blocking layer 13, an epitaxial layer 14, and an N-electrode 15. Among them, the epitaxial layer 14 has a mesa structure, which completely covers the reflective layer 12.

[0062] N electrode 15 is a closed ring pattern, which is mirror-symmetrical along the vertical and horizontal axes of the chip center, such as... Figure 15As shown. Specifically, the N electrode 15 consists of two pads 151 and electrode lines 152. The four electrode lines 152 at the edge form a closed ring pattern, and the remaining electrode lines 152 are connected to the closed ring pattern.

[0063] The current blocking layer 13 is composed of an unconnected intermediate region current blocking layer 131 and an edge region current blocking layer 132, as shown below. Figure 6 As shown. The middle region current blocking layer 131 and the N electrode 15 are positioned opposite each other and have the same pattern, and the vertical projection of the middle region current blocking layer 131 completely covers the vertical projection of the N electrode 15. The edge region current blocking layer 132 is located between the epitaxial layer 14 and the bonding metal layer 11. The edge region current blocking layer 132 covers part of the sidewall of the reflective layer 12 and is connected to the epitaxial layer 14, the reflective layer 12, and the bonding metal layer 11. The projection of the edge region current blocking layer 132 onto the plane of the conductive substrate 10 is a closed annular pattern, which corresponds to the outer edge of the mesa structure of the epitaxial layer 14.

[0064] The vertical structure LED chip provided in this embodiment designs the current blocking layer as a non-connected middle region current blocking layer and an edge region current blocking layer. The edge region current blocking layer is located at the edge of the epitaxial layer's mesa, preventing cracks caused by long-term thermal stress accumulation at the edge from extending into the middle region and causing LED failure. Simultaneously, the N-electrode is designed as a closed ring pattern, and this closed ring pattern is mirror-symmetrical along the vertical and horizontal axes of the chip center. This makes the current distribution more uniform across the four sides of the LED chip, improving the problem of uneven thermal stress distribution and excessive local stress leading to chip cracks and leakage caused by unbalanced current expansion, thereby improving the reliability of the vertical structure LED chip.

[0065] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A vertically oriented LED chip, comprising, from bottom to top, a conductive substrate, a bonding metal layer, a reflective layer, a current blocking layer, an epitaxial layer, and an N-electrode, characterized in that: The epitaxial layer has a mesa structure; the current blocking layer consists of an unconnected intermediate region current blocking layer and an edge region current blocking layer; the intermediate region current blocking layer corresponds to the vertical projection position of the N electrode on the conductive substrate plane, and the projection of the N electrode on the conductive substrate plane is a closed ring pattern, which is mirror-symmetrical along the vertical axis and horizontal axis of the chip center.

2. The vertical structure LED chip according to claim 1, characterized in that: The vertical projection of the current blocking layer in the middle region completely covers the vertical projection of the N electrode; the N electrode consists of pads and electrode lines, with the electrode lines at the edge forming a closed ring pattern and the remaining electrode lines connected to the closed ring pattern.

3. The vertical structure LED chip according to claim 1, characterized in that: The edge region current blocking layer is located between the epitaxial layer and the bonding metal layer, and the edge region current blocking layer covers part of the sidewall of the reflective layer; the projection of the edge region current blocking layer on the conductive substrate plane is a closed ring pattern, and the closed ring pattern corresponds to the outer edge of the mesa structure of the epitaxial layer.

4. The vertical structure LED chip according to claim 1, characterized in that: The projection of the epitaxial layer onto the plane of the conductive substrate completely covers the reflective layer.

5. The vertical structure LED chip according to claim 1, characterized in that: The material of the current blocking layer is one or more of SiO2, Si3N4, SiON, TiO2, Ti3O5, Al2O3, Nb2O5, and Ta2O5; the thickness of the current blocking layer is 100 Å to 8000 Å.

6. The vertical structure LED chip according to claim 1, characterized in that: The material of the reflective layer is one or more of Au, Ag, NiAu, NiAg, AuBe, and AuZn.

7. A method for fabricating a vertically structured LED chip, characterized in that, Includes the following steps: S1. Provide a growth substrate and form an epitaxial layer on the growth substrate, the epitaxial layer comprising an N-type layer, a quantum well layer and a P-type layer sequentially stacked on the growth substrate; S2. A current blocking layer is formed on the P-type layer; S3. Etching the current blocking layer exposes the P-type layer, forming a patterned, unconnected intermediate region current blocking layer and edge region current blocking layer; both the intermediate region current blocking layer and the edge region current blocking layer are closed annular patterns, and the closed annular pattern of the intermediate region current blocking layer is mirror-symmetrical along the vertical axis and horizontal axis of the chip center. S4. A reflective layer is formed on the current blocking layer; S5. A bonding metal layer is formed on the reflective layer; S6. Bond a conductive substrate onto the bonding metal layer; S7. Remove the growth substrate to expose the N-type layer; S8. Etch away the periphery of the epitaxial layer to form a mesa structure; S9. An N-electrode is formed on the surface of the N-type layer, the N-electrode being positioned corresponding to the current blocking layer in the middle region, and the vertical projection of the current blocking layer in the middle region completely covers the projection of the N-electrode.

8. The method for fabricating a vertical structure LED chip according to claim 7, characterized in that: The method for forming the reflective layer in step S4 is to sputter or vapor-deposit the reflective layer on the surface of the current blocking layer, and etch or peel off the reflective layer at the edge of the chip; the formed reflective layer completely covers the current blocking layer in the middle region and covers part of the current blocking layer in the edge region.

9. The method for fabricating a vertical structure LED chip according to claim 7, characterized in that: In step S5, the bonding metal layer completely covers the reflective layer, and the bonding metal layer covers the area of ​​the edge region where the current blocking layer is not covered by the reflective layer.

10. The method for fabricating a vertical structure LED chip according to claim 7, characterized in that: In step S8, etching removes the periphery of the epitaxial layer to expose a portion of the edge region current blocking layer. The mesa structure completely covers the reflective layer and a portion of the edge region current blocking layer.

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