Display device

Abstract

The display device includes: a substrate including a display area and a non-display area surrounding the display area; a buffer layer disposed on the substrate, a plurality of 1-1-th connection lines disposed on the buffer layer in the display area; a pixel driving circuit disposed on the plurality of (1-1) th connection lines and including a main body, a plurality of circuit pads disposed on a bottom surface of the main body, and a passivation film disposed to surround the main body and the plurality of circuit pads; a plurality of bonding patterns configured to connect the plurality of (1-1) th connection lines and the plurality of circuit pads; a bank disposed on the pixel driving circuit; and a plurality of micro LEDs disposed on the bank and electrically connected to the pixel driving circuit. Accordingly, the layered structure is simplified so that flatness may be ensured, and a thin display device may be implemented.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0112649, filed on August 22, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] Display devices are used in a variety of electronic devices, such as TVs, mobile phones, laptops, and tablets.

[0005] As display devices, there are organic light-emitting displays (OLEDs) that are configured to emit light independently and liquid crystal displays (LCDs) that require a separate light source.

[0006] Recently, display devices including light-emitting diodes (LEDs) have attracted attention as the next generation of display devices. Because LEDs are made of inorganic materials rather than organic materials, they can quickly turn on and off compared to liquid crystal displays or organic light-emitting displays, exhibiting excellent luminous efficiency and displaying high-brightness images. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display device that is implemented as a thin display device.

[0008] Another objective of this disclosure is to provide a display device that optimizes the manufacturing process by reducing process costs and time.

[0009] Another objective of this disclosure is to provide a display device with improved flatness.

[0010] Another objective of this disclosure is to provide a display device that suppresses defects caused by foreign objects.

[0011] The purpose of this disclosure is not limited to the purposes mentioned above, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0012] A display device according to an embodiment of this disclosure includes: a substrate including a display area and a non-display area configured to surround the display area; a buffer layer disposed on the substrate, and a plurality of first-1 connection lines disposed on the buffer layer in the display area; a pixel driving circuit disposed on the plurality of first-1 connection lines and including a body, a plurality of circuit pads disposed on a bottom surface of the body, and a passivation film disposed around the body and the plurality of circuit pads; a plurality of bonding patterns configured to connect the plurality of first-1 connection lines and the plurality of circuit pads; a dam disposed on the pixel driving circuit; and a plurality of micro-LEDs disposed on the dam and electrically connected to the pixel driving circuit. Therefore, the layered structure is simplified, allowing flatness to be ensured and a thin display device to be realized.

[0013] Other specific details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0014] According to this disclosure, the pixel driving circuit is disposed on the connecting line and is bonded by diffusion bonding, so that the pixel driving circuit can be fixed on the connecting line and electrically connected to the connecting line.

[0015] According to this disclosure, no bonding layer is included for bonding or fixing pixel driving circuits, which can reduce process costs and time and achieve process optimization.

[0016] According to this disclosure, no bonding layer is included, which minimizes defects caused by unwanted foreign matter adhering to the bonding layer.

[0017] According to this disclosure, the connecting line located below the pixel driving circuit is used as an alignment key, and there is no separate process for forming the alignment key in order to align the position of the pixel driving circuit. This can reduce process cost and time, and achieve process optimization.

[0018] According to this disclosure, multiple connection lines are set to be spaced apart from each other based on the pixel driving circuit, and no additional protective or insulating layer is required for setting the multiple connection lines. This can reduce process costs and time, and achieve process optimization.

[0019] According to this disclosure, excluding the bonding layer and additional protective layer, this simplifies the layered structure of the display device, ensures the flatness of the upper part of the display device, and enables a thin display device.

[0020] The effects of this disclosure are not limited to those illustrated above, and include, for example, a variety of other effects further described in the detailed description section. Attached Figure Description

[0021] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0023] Figure 2 This is a top plan view of a display device according to an embodiment of the present disclosure;

[0024] Figure 3 This is an enlarged view of a display device according to an embodiment of the present disclosure;

[0025] Figure 4 This is a view showing the circuit structure according to an embodiment of the present disclosure;

[0026] Figure 5 This is a top plan view of a display device according to an embodiment of the present disclosure;

[0027] Figure 6 This is a top plan view of a display device according to an embodiment of the present disclosure;

[0028] Figure 7 This is a top plan view of a display device according to an embodiment of the present disclosure;

[0029] Figure 8 It is along Figure 3 A cross-sectional view taken from line VIII-VIII' in the middle;

[0030] Figure 9A and Figure 9B This is an enlarged view illustrating the process of the bonding pixel driving circuit and the first connecting line of the display device according to an embodiment of the present disclosure;

[0031] Figure 10 This is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0032] Figure 11 This is a cross-sectional view of a display device according to another embodiment of the present disclosure;

[0033] Figure 12A and Figure 12B This is an enlarged view illustrating the process of joining pixel driving circuit and first connecting line 1-1 of a display device according to another embodiment of the present disclosure;

[0034] Figure 13 This is a cross-sectional view of a display device according to yet another embodiment of the present disclosure;

[0035] Figure 14A and Figure 14B This is an enlarged view illustrating the process of bonding the pixel driving circuit and the first-1 connection line of a display device according to another embodiment of the present disclosure; and

[0036] Figures 15 to 18 This is a view showing a display device applied according to an embodiment of the present disclosure. Detailed Implementation

[0037] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below, together with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0038] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0039] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0040] When using terms such as “on top of,” “above,” “below,” and “near” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0041] When describing time relationships, terms such as “after,” “follow,” “subsequently,” or “before” can include non-continuous cases, unless terms such as “immediately after” or “directly” are used.

[0042] Terms such as "first" and "second" are used to describe various components, but these components are not limited by these terms. These terms are only intended to distinguish one component from another. Therefore, the first component mentioned herein can be a second component within the technical scope of this disclosure.

[0043] In describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish one component from others, and the nature, order, sequence, or number of the components are not limited by these terms.

[0044] When a component is described as “connected,” “coupled,” “joined,” or “attached” to another component, it should be understood that the component may be directly connected, coupled, joined, or attached to the other component, unless otherwise expressly stated, the component may also be indirectly connected, coupled, joined, or attached, in which each component is connected to another component.

[0045] When a component or layer is described as "in contact" or "overlapping" with another component or layer, the component or layer may be in direct contact or overlap with the other component or layer, but unless otherwise expressly stated, it should be understood that the component or layer may also be in indirect contact or overlap, in which there is another component intervening between each component.

[0046] The term "at least one" should be understood to include all combinations of one or more associated components. For example, "at least one of the first component, the second component, and the third component" means not only the first component, the second component, or the third component, but also all combinations of two or more of the first component, the second component, and the third component.

[0047] The terms “first direction,” “second direction,” “third direction,” “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted merely as mutually perpendicular geometric relationships, but can also indicate a broader range of directions within which the configuration of this disclosure can function.

[0048] The features of the various embodiments in this disclosure can be combined or associated with each other in part or in whole, and various technical interlocks and operations can be performed. Each embodiment can be implemented independently or together in an associated relationship.

[0049] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 1 This is a perspective view showing a display device according to an embodiment of the present disclosure. Figure 2 This is a top plan view of a display device according to an embodiment of the present disclosure. Figure 3 This is an enlarged view of a display device according to an embodiment of the present disclosure.

[0051] Reference Figures 1 to 3The display device 1000 according to the embodiments of the present disclosure may include a display panel 100, a polarizing layer 293, a bonding layer 295, a cover member 120, a support substrate 170, a flexible circuit board FCB, and a printed circuit board 160.

[0052] For example, the display panel 100 of the display device 1000 may include a substrate 110. The substrate 110 may be a component configured to support other components of the display device 1000. The substrate 110 may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, or the like. Furthermore, the substrate 110 may be made of a flexible material. For example, the substrate 110 may be made of a flexible organic insulating material, i.e., a plastic material (e.g., polyimide (PI)). However, embodiments of this disclosure are not limited thereto.

[0053] The display panel 100 can display information, video, and / or images to be provided to the user. For example, the display panel 100 may include a display area AA and a non-display area NA. For example, the substrate 110 may include a display area AA and a non-display area NA. The display area AA and the non-display area NA may not be described as limited to the substrate 110, but the display area AA and the non-display area NA may be described with respect to the entire display device 1000.

[0054] The display area AA can be the area where an image is displayed. The display area AA can include multiple pixels PX. Each of the multiple pixels PX can include multiple sub-pixels. Multiple micro-LEDs can be respectively set in the multiple sub-pixels.

[0055] The non-display area NA can be an area where no image is displayed. Various lines and circuits for operating the multiple pixels PX in the display area AA can be provided in the non-display area NA. For example, various types of lines and drive circuits can be installed in the non-display area NA, and pad portions PADs connected to integrated circuits, printed circuits, etc., can be provided. However, embodiments of this disclosure are not limited thereto.

[0056] For example, the driving circuit may be a data driving circuit and / or a gate driving circuit. However, embodiments of this disclosure are not limited thereto. Lines for supplying control signals to the control driving circuit may be provided. For example, the control signals may include various types of timing signals, including clock signals, input data enable signals, and synchronization signals. However, embodiments of this disclosure are not limited thereto. The control signals may be received via the pad portion PAD. For example, a link line LL for transmitting signals may be provided in the non-display area NA. For example, driving components such as the flexible circuit board FCB and the printed circuit board 160 may be connected to the pad portion PAD.

[0057] According to this disclosure, the non-display area NA may include a first non-display area NA1, a curved area BA, and a second non-display area NA2. For example, the first non-display area NA1 may be a region surrounding at least a portion of the display area AA. The curved area BA may be a flexible region extending from at least any one of a plurality of sides of the first non-display area NA1. The second non-display area NA2 may be a region extending from the curved area BA, and a pad portion PAD may be disposed in the second non-display area NA2. For example, the curved area BA may be in a curved state, and the remaining area of ​​the substrate 110, excluding the curved area BA, may be in a flat state. In this case, as the curved area BA bends, the second non-display area NA2 may be positioned on the rear surface of the display area AA. However, embodiments of this disclosure are not limited thereto.

[0058] According to the design of the display device 1000, the substrate 110 or the display area AA of the display device 1000 can have various shapes. For example, the display area AA can have a rectangular shape with rounded corners. However, the embodiments of this disclosure are not limited to this. In another example, the display area AA can have a circular shape or a rectangular shape with right angles at the four corners. However, the embodiments of this disclosure are not limited to this.

[0059] According to this disclosure, the width of the second non-display area NA2, which is provided with multiple pad electrodes PE, can be greater than the width of the curved area BA, which is provided with only multiple link lines LL. Furthermore, the width of the display area AA, which is provided with multiple sub-pixels, can be greater than the width of the curved area BA, which is provided with multiple link lines LL. As shown in the accompanying drawings, the width of the curved area BA can be smaller than the width of another area of ​​the substrate 110. However, the shape of the substrate 110 including the curved area BA is illustrative, and embodiments of this disclosure are not limited thereto.

[0060] Reference Figure 3Multiple pixel driving circuits (PDs) can be disposed in the display area AA. The multiple pixel driving circuits (PDs) can be circuits for operating multiple sub-pixels of micro-LEDs. Each of the multiple pixel driving circuits (PDs) can include multiple transistors (including driving transistors) and multiple storage capacitors. The multiple pixel driving circuits (PDs) can control the light-emitting operation of the multiple micro-LEDs by supplying control signals, power, and driving current to the multiple sub-pixels of micro-LEDs. For example, the pixel driving circuit (PD) can include power lines and signal lines for controlling the light-emitting on / off operation and / or light-emitting time of the micro-LEDs. For example, the multiple pixel driving circuits (PDs) can be operation drivers fabricated on a semiconductor substrate using a metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication process. However, embodiments of this disclosure are not limited thereto. An operation driver can include multiple pixel driving circuits (PDs) and operate multiple sub-pixels.

[0061] Refer to together Figure 1 The flexible circuit board (FCB) and the printed circuit board 160 can be disposed below the display panel 100. The FCB and the printed circuit board 160 can be disposed at least at one edge of the display panel 100. However, embodiments of this disclosure are not limited thereto. One side of the flexible circuit board (FCB) can be attached to the display panel 100, and the other side of the FCB can be attached to the printed circuit board 160. However, embodiments of this disclosure are not limited thereto. The flexible circuit board (FCB) can be a flexible film. However, embodiments of this disclosure are not limited thereto.

[0062] A pad portion PAD, including multiple pad electrodes PE, can be disposed in a second non-display area NA2. A driving component, including one or more flexible circuit boards (or flexible films) FCB and a printed circuit board 160, can be attached or bonded to the pad portion PAD. The multiple pad electrodes PE of the pad portion PAD can be electrically connected to one or more flexible circuit boards (or flexible films) FCB, and various types of signals (or power) can be sent from the printed circuit board 160 and the flexible circuit boards (or flexible films) FCB to multiple pixel driving circuits PD in the display area AA.

[0063] A flexible circuit board (or flexible film) FCB can be a film having various types of components disposed on a flexible base film. For example, a driver IC, such as a gate driver IC or a data driver IC, can be disposed on the flexible circuit board (or flexible film) FCB. However, embodiments of this disclosure are not limited thereto. The driver IC can be a component configured to process data and drive signals for displaying images. Depending on how the driver IC is mounted, it can be disposed in a manner such as chip-on-glass (COG) method, chip-on-film (COF) method, and carrier package (TCP) method. However, embodiments of this disclosure are not limited thereto. The flexible circuit board (or flexible film) FCB can be attached or bonded to multiple pad electrodes PE by means of a conductive bonding layer. However, embodiments of this disclosure are not limited thereto.

[0064] Printed circuit board 160 may be a component electrically connected to one or more flexible circuit boards (or flexible films) FCBs and configured to supply signals to a driver IC. Printed circuit board 160 may be disposed on one side of a flexible circuit board (or flexible film) FCB and electrically connected to the FCB. Various types of components for supplying various signals to the driver IC may be disposed on printed circuit board 160. For example, various components such as timing controllers, power supplies, memory, or processors may be disposed on printed circuit board 160. For example, printed circuit board 160 may include a power management integrated circuit (PMIC). However, embodiments of this disclosure are not limited thereto.

[0065] The printed circuit board 160 may include at least one hole 180. However, embodiments of this disclosure are not limited thereto. Internal components may be disposed in the area corresponding to the at least one hole 180 and may detect ambient light, temperature, etc., which may be provided to multiple sensors. For example, the internal components may include an ambient light sensor (ALS), a temperature sensor, etc. However, embodiments of this disclosure are not limited thereto. For example, the hole 180 may be a transmission hole, etc. However, embodiments of this disclosure are not limited thereto.

[0066] Reference Figure 1 The polarization layer 293 can be disposed on the display panel 100. The polarization layer 293 can suppress or reduce the situation where light generated from an external light source is introduced into the display panel 100 and affects micro-LEDs, etc.

[0067] Cover member 120 may be disposed on polarizing layer 293. Cover member 120 may be a component for protecting display panel 100. Bonding layer 295 may be disposed between polarizing layer 293 and cover member 120. Cover member 120 can be attached to display panel 100 by using bonding layer 295. Bonding layer 295 may include optically clear adhesive (OCA), optically clear resin (OCR), pressure-sensitive adhesive (PSA), etc. However, embodiments of this disclosure are not limited thereto.

[0068] A support substrate 170 may be disposed between the display panel 100 and the printed circuit board 160. The support substrate 170 may enhance the rigidity of the display panel 100. The support substrate 170 may be a backplate. However, embodiments of this disclosure are not limited thereto.

[0069] Reference Figures 1 to 3 Multiple link lines LL can be disposed in the non-display area NA. These link lines LL can be lines configured to transmit various types of signals from one or more flexible circuit boards (or flexible films) FCB and printed circuit boards 160 to the display area AA. The link lines LL can extend from multiple pad electrodes PE of the second non-display area NA2 toward the curved area BA and the first non-display area NA1, and are electrically connected to multiple drive lines VL in the display area AA. Multiple pixel drive circuits PD can operate by receiving signals from one or more flexible circuit boards (or flexible films) FCB and printed circuit boards 160 through the drive lines VL in the display area AA and the link lines LL in the non-display area NA.

[0070] For example, multiple drive lines VL can be lines configured, together with multiple link lines LL, to transmit signals output from the flexible circuit board (or flexible film) FCB and printed circuit board 160 to multiple pixel driving circuits PD. The multiple drive lines VL can be disposed in the display area AA and electrically connected to the multiple pixel driving circuits PD, respectively. The multiple drive lines VL can extend from the display area AA towards the non-display area NA and are electrically connected to the multiple link lines LL. Therefore, signals output from the flexible circuit board (or flexible film) FCB and printed circuit board 160 can be transmitted to the multiple pixel driving circuits PD through the multiple link lines LL and the multiple drive lines VL.

[0071] When the bending region BA bends, the multiple connecting lines LL may also partially bend. Stress may concentrate on a portion of the bent connecting lines LL, and therefore the connecting lines LL may crack. Therefore, the multiple connecting lines LL can be made of a highly flexible conductive material to reduce the occurrence of cracks when the bending region BA bends. For example, the multiple connecting lines LL can be made of a highly flexible conductive material such as gold (Au), silver (Ag), or aluminum (Al). However, embodiments of this disclosure are not limited thereto. Furthermore, the multiple connecting lines LL can be made of one of various conductive materials used for the display region AA. For example, the multiple connecting lines LL can be made of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or alloys thereof. However, embodiments of this disclosure are not limited thereto. The multiple connecting lines LL can have a multilayer structure comprising various conductive materials. For example, the multiple connecting lines LL can have a three-layer structure made of titanium (Ti), aluminum (Al), and titanium (Ti). However, embodiments of this disclosure are not limited thereto.

[0072] Multiple link lines LL can have various shapes to reduce stress. At least a portion of each of the multiple link lines LL disposed in the bending region BA can extend in the same direction as the extending direction of the bending region BA, or in a direction different from the extending direction of the bending region BA, to reduce stress. For example, when the bending region BA extends in a direction from the first non-display region NA1 toward the second non-display region NA2, at least a portion of the link lines LL disposed in the bending region BA can extend in a direction inclined relative to that direction. In another example, at least a portion of each of the multiple link lines LL can have a pattern of various shapes. For example, at least a portion of each of the multiple link lines LL disposed in the bending region BA can have a shape in which a conductive pattern is repeatedly disposed, the conductive pattern having at least one of the following shapes: rhombus shape, oblique square shape, trapezoidal wave shape, triangular wave shape, sawtooth wave shape, sine wave shape, circular shape, and omega (Ω) shape. However, embodiments of the present disclosure are not limited thereto. Therefore, in order to minimize the stress concentrated on the multiple link lines LL and to minimize the occurrence of stress-induced cracks, the multiple link lines LL can have various shapes including the shapes described above. However, the implementation of this disclosure is not limited thereto.

[0073] Figure 4 This is a view showing the circuit structure according to an embodiment of the present disclosure.

[0074] The pixel driving circuit (PD) may include a micro driver (μDriver). A micro LED (ED) may be electrically connected to and operate the micro driver (μDriver) of the pixel driving circuit (PD). Figure 4 A micro LED ED connected to a micro driver μDriver is shown. However, this disclosure is not limited thereto. For example, eight micro LED EDs can be connected to one micro driver μDriver. In another example, sixteen micro LED EDs can be connected to one micro driver μDriver, or thirty-two micro LED EDs or sixty-four micro LED EDs can be connected to one micro driver μDriver simultaneously.

[0075] A micro-driver μDriver may include a driving transistor T DR and light-emitting transistor T EM However, the implementation of this disclosure is not limited thereto.

[0076] For example, a high-potential power voltage VDD can be applied to the driving transistor T. DR The first electrode, the light-emitting transistor T EM The first electrode can be connected to the driving transistor T DR The second electrode, and the scan signal SC can be applied to the driving transistor T. DR The gate electrode. Applied to the driving transistor T DR The scan signal SC of the gate electrode can be a DC power supply, and a fixed reference voltage can be applied for each frame. However, the embodiments of this disclosure are not limited thereto.

[0077] Drive transistor T DR The second electrode can be connected to the light-emitting transistor T. EM The first electrode of the micro LED can be connected to the light-emitting transistor T. EM The second electrode, and the light-emitting signal EM can be applied to the light-emitting transistor T. EM The gate electrode of the light-emitting transistor T is applied. EM The light emission signal EM from the gate electrode can be a pulse width modulated signal that varies with each frame. However, embodiments of the present disclosure are not limited thereto.

[0078] The first electrode of a miniature LED can be connected to a light-emitting transistor T. EM The second electrode of the micro LED ED can be connected to ground. For example, the first electrode can be an anode electrode, and the second electrode can be a cathode electrode. However, embodiments of this disclosure are not limited thereto.

[0079] Drive transistor T DR and light-emitting transistor TEM They can each be either n-type transistors or p-type transistors.

[0080] Drive transistor T DR The micro-driver μDriver can be turned on by a scan signal SC applied from the timing controller, and the light-emitting transistor T... EM It can be turned on by emitting a light signal EM. Therefore, the drive current is applied to the drive transistor T. DR The high potential power voltage VDD of the first electrode is driven by the transistor T. DR and light-emitting transistor T EM Applying this to the micro LEDs allows them to emit light.

[0081] Figures 5 to 7 This is a top plan view of a display device according to an embodiment of the present disclosure. For example, Figure 5 It is a magnified top-down plan view of a display area that includes multiple pixels. For example, Figure 6 It is a magnified top-down plan view of the display area, including individual pixels. For example, Figure 7 It is a magnified top-down plan view of a display area that includes multiple pixels. Figure 5 and Figure 6 Only multiple signal lines TL, multiple communication lines NL, multiple first electrodes CE1, multiple dams BNK, and multiple miniature LEDs ED are shown. However, embodiments of this disclosure are not limited thereto. Figure 7 It is shown in Figure 5 An enlarged top view of the configuration with multiple second electrodes CE2 attached.

[0082] Reference Figure 5 and Figure 6 Multiple pixels (PX), including multiple sub-pixels, can be disposed in the display area (AA). Each of the multiple sub-pixels can include a micro-LED (ED) and emit light independently. The multiple sub-pixels can be arranged in multiple rows and multiple columns, while defining a matrix shape. However, the embodiments of this disclosure are not limited thereto.

[0083] The plurality of sub-pixels may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel, another sub-pixel may be a green sub-pixel, and the remaining sub-pixels may be blue sub-pixels. The type of the plurality of sub-pixels is illustrative. However, embodiments of this disclosure are not limited thereto.

[0084] Multiple pixels PX may each include one or more first sub-pixels SP1, one or more second sub-pixels SP2, and one or more third sub-pixels SP3. For example, a pixel PX may include a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3. The pair of first sub-pixels SP1 may include first-1 sub-pixels SP1a and first-2 sub-pixels SP1b. The pair of second sub-pixels SP2 may include second-1 sub-pixels SP2a and second-2 sub-pixels SP2b. The pair of third sub-pixels SP3 may include third-1 sub-pixels SP3a and third-2 sub-pixels SP3b. For example, a pixel PX may include first-1 sub-pixels SP1a, first-2 sub-pixels SP1b, second-1 sub-pixels SP2a, second-2 sub-pixels SP2b, third-1 sub-pixels SP3a, and third-2 sub-pixels SP3b. However, the embodiments of this disclosure are not limited thereto.

[0085] The multiple subpixels constituting a pixel PX can be arranged in various ways. For example, in a pixel PX, a pair of first subpixels SP1 can be arranged in the same column, a pair of second subpixels SP2 can be arranged in the same column, and a pair of third subpixels SP3 can be arranged in the same column. The first subpixels SP1, second subpixels SP2, and third subpixels SP3 can be arranged in the same row. The number and arrangement of the multiple subpixels constituting a pixel PX are illustrative. However, embodiments of this disclosure are not limited thereto.

[0086] Multiple signal lines TL can be positioned in the region between multiple sub-pixels. The multiple signal lines TL can extend along the column direction between the multiple sub-pixels. The multiple signal lines TL can be lines configured to transmit an anode voltage from a pixel driving circuit PD to the multiple sub-pixels. For example, the multiple signal lines TL can be electrically connected to the multiple pixel driving circuits PD and the first electrode CE1 of the multiple sub-pixels. The anode voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 of the multiple sub-pixels via the multiple signal lines TL. For example, the first electrode CE1 can be an anode electrode 134 electrically connected to a micro LED ED (see example...). Figure 10 Therefore, the anode voltage from the signal line TL can be transmitted to the anode electrode 134 of the miniature LEDED via the first electrode CE1.

[0087] Therefore, by using a pixel drive circuit PD that integrates multiple pixel circuits, instead of forming multiple transistors and multiple storage capacitors in multiple sub-pixels, the structure of the display device 1000 can be simplified. Furthermore, since the circuits that are respectively located in multiple sub-pixels are integrated into a single pixel drive circuit PD, low-power, high-efficiency operation can be performed.

[0088] Multiple signal lines TL may include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. The first signal line TL1 and the second signal line TL2 may each be electrically connected to each of a pair of first sub-pixels SP1. The third signal line TL3 and the fourth signal line TL4 may each be electrically connected to each of a pair of second sub-pixels SP2. The fifth signal line TL5 and the sixth signal line TL6 may each be electrically connected to each of a pair of third sub-pixels SP3.

[0089] A first signal line TL1 can be disposed on one side of a pair of first sub-pixels SP1, and a second signal line TL2 can be disposed on the other side of the pair of first sub-pixels SP1. The first signal line TL1 can be electrically connected to the first electrode CE1 of one of the pair of first sub-pixels SP1, for example, the first electrode CE1 of sub-pixel SP1a. The second signal line TL2 can be electrically connected to the first electrode CE1 of the remaining one of the pair of first sub-pixels SP1, for example, the first electrode CE1 of sub-pixel SP1b.

[0090] The third signal line TL3 can be positioned on one side of a pair of second sub-pixels SP2, and the fourth signal line TL4 can be positioned on the other side of the pair of second sub-pixels SP2. For example, the third signal line TL3 can be positioned adjacent to the second signal line TL2. The third signal line TL3 can be electrically connected to the first electrode CE1 of one of the pair of second sub-pixels SP2, for example, the 2-1st sub-pixel SP2a. The fourth signal line TL4 can be electrically connected to the first electrode CE1 of the remaining one of the pair of second sub-pixels SP2, for example, the 2-2nd sub-pixel SP2b.

[0091] The fifth signal line TL5 can be located on one side of a pair of third sub-pixels SP3, and the sixth signal line TL6 can be located on the other side of the pair of third sub-pixels SP3. For example, the fifth signal line TL5 can be located adjacent to the fourth signal line TL4. The sixth signal line TL6 can be located adjacent to the first signal line TL1 connected to the adjacent pixel PX. The fifth signal line TL5 can be electrically connected to the first electrode CE1 of one of the pair of third sub-pixels SP3, for example, the 3-1st sub-pixel SP3a. The sixth signal line TL6 can be electrically connected to the first electrode CE1 of the remaining one of the pair of third sub-pixels SP3, for example, the 3-2nd sub-pixel SP3b.

[0092] Multiple signal lines TL can be made of conductive materials. For example, multiple signal lines TL can be made of conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). However, embodiments of this disclosure are not limited thereto. In another example, multiple signal lines TL can have a multilayer structure made of conductive materials. For example, multiple signal lines TL can have a multilayer structure made of titanium (Ti), aluminum (Al), titanium (Ti), and indium tin oxide (ITO). However, embodiments of this disclosure are not limited thereto.

[0093] Multiple communication lines NL can be disposed in the region between multiple pixels PX. The multiple communication lines NL can be configured to extend along the row direction in the region between the multiple pixels PX. The multiple communication lines NL can be disposed in the region between multiple second electrodes CE2, and may not overlap with the multiple second electrodes CE2. For example, the multiple communication lines NL can be lines for short-range communication such as near field communication (NFC). The multiple communication lines NL can be used as antennas. For example, the multiple communication lines NL can be multiple connecting lines, etc. However, embodiments of this disclosure are not limited thereto.

[0094] According to this disclosure, a dam BNK can be provided in each of a plurality of sub-pixels. The plurality of dam BNKs can have a structure on which a plurality of micro LEDs are mounted. During the transfer of the plurality of micro LEDs to the display device 1000, the plurality of dam BNKs can guide the position of the plurality of micro LEDs. During the transfer of the plurality of micro LEDs, the plurality of micro LEDs can be transferred onto the plurality of dam BNKs. The plurality of dam BNKs can be dam patterns, structures, etc. However, the embodiments of this disclosure are not limited thereto.

[0095] The BNK of the first sub-pixel SP1, the BNK of the second sub-pixel SP2, and the BNK of the third sub-pixel SP3 can be set to be spaced apart from each other. Therefore, it is easy to identify which types of micro-LEDs are transferred to the BNK of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0096] The BNK of sub-pixel SP1a and the BNK of sub-pixel SP1b can be connected, spaced apart, or separated from each other. For example, considering design requirements such as those of the transfer process, the BNK of sub-pixel SP1a and the BNK of sub-pixel SP1b (on which the same type of micro-LED ED is disposed) can be connected, spaced apart, or separated from each other. Furthermore, the BNK of sub-pixel SP2a and the BNK of sub-pixel SP2b can be connected, spaced apart, or separated from each other. The BNK of sub-pixel SP3a and the BNK of sub-pixel SP3b can be connected, spaced apart, or separated from each other. Therefore, a pair of BNK of first sub-pixels SP1, a pair of BNK of second sub-pixels SP2, and a pair of BNK of third sub-pixels SP3 can be formed in various ways. However, embodiments of this disclosure are not limited thereto.

[0097] For example, multiple dammed BNKs can be made of organic insulating materials. Each of the multiple dammed BNKs can be configured as a single layer or multiple layers made of organic insulating materials. For example, the multiple dammed BNKs can be made of photoresist, polyimide (PI), acrylic materials, etc. However, embodiments of this disclosure are not limited thereto.

[0098] A first electrode CE1 may be disposed in each of a plurality of sub-pixels. The first electrode CE1 may be disposed on a dam BNK. The first electrode CE1 may be electrically connected to one of a plurality of signal lines TL. At least a portion of the first electrode CE1 may extend outside the dam BNK and be electrically connected to the signal line TL closest to the first electrode CE1. For example, a portion of the first electrode CE1 of sub-pixel SP1a may extend to one side of sub-pixel SP1a and be electrically connected to the first signal line TL1, and a portion of the first electrode CE1 of sub-pixel SP1b may extend to the other side of sub-pixel SP1b and be electrically connected to the second signal line TL2. A portion of the first electrode CE1 of sub-pixel SP2a may extend to one side of sub-pixel SP2a and be electrically connected to the third signal line TL3, and a portion of the first electrode CE1 of sub-pixel SP2b may extend to the other side of sub-pixel SP2b and be electrically connected to the fourth signal line TL4. A portion of the first electrode CE1 of the 3-1 sub-pixel SP3a may extend to one side of the 3-1 sub-pixel SP3a and be electrically connected to the fifth signal line TL5, and a portion of the first electrode CE1 of the 3-2 sub-pixel SP3b may extend to the other side of the 3-2 sub-pixel SP3b and be electrically connected to the sixth signal line TL6.

[0099] The first electrode CE1 can be electrically connected to the anode electrode 134 of the micro LED ED, and transmits the anode voltage from the pixel driving circuit PD to the micro LED ED via the signal line TL. Different voltages can be applied to the first electrode CE1 of each of the multiple sub-pixels depending on the displayed image. For example, different voltages can be applied to the first electrode CE1 of each of the multiple sub-pixels. Therefore, the first electrode CE1 can be a pixel electrode. However, embodiments of this disclosure are not limited thereto.

[0100] The first electrode CE1 can be made of a conductive material. For example, the first electrode CE1 can be integrated with multiple signal lines TL. For example, the first electrode CE1 can be made of the same conductive material as the multiple signal lines TL. However, embodiments of this disclosure are not limited to this. For example, the first electrode CE1 can be made of a conductive material such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). However, embodiments of this disclosure are not limited to this. In another example, the first electrode CE1 can have a multilayer structure made of a conductive material. For example, multiple first electrodes CE1 can each have a multilayer structure made of titanium (Ti), aluminum (Al), titanium (Ti), and indium tin oxide (ITO). However, embodiments of this disclosure are not limited to this.

[0101] A micro LED ED can be disposed in each of a plurality of sub-pixels. The plurality of micro LED EDs can be any of light-emitting diodes (LEDs) or micro-light-emitting diodes (micro-LEDs). However, embodiments of this disclosure are not limited thereto. The plurality of micro LED EDs can be disposed on the diaphragm BNK and the first electrode CE1. The plurality of micro LED EDs can be disposed on and electrically connected to the first electrode CE1. Therefore, the micro LED EDs can emit light by receiving the anode voltage from the pixel driving circuit PD through the signal line TL and the first electrode CE1.

[0102] Multiple microLEDs may include a first microLED 130, a second microLED 140, and a third microLED 150. The first microLED 130 may be disposed in a first sub-pixel SP1. The second microLED 140 may be disposed in a second sub-pixel SP2. The third microLED 150 may be disposed in a third sub-pixel SP3. For example, any one of the first microLED 130, the second microLED 140, and the third microLED 150 may be a red microLED, another microLED may be a green microLED, and the others may be blue microLEDs. However, embodiments of this disclosure are not limited thereto. Therefore, beams of various colors, including white, can be achieved by combining red, green, and blue light emitted from multiple microLEDs. The types of microLEDs are illustrative. However, embodiments of this disclosure are not limited thereto.

[0103] The first micro-LED 130 may include a first-1 micro-LED 130a disposed in the first-1 sub-pixel SP1a and a first-2 micro-LED 130b disposed in the first-2 sub-pixel SP1b. The second micro-LED 140 may include a second-1 micro-LED 140a disposed in the second-1 sub-pixel SP2a and a second-2 micro-LED 140b disposed in the second-2 sub-pixel SP2b. The third micro-LED 150 may include a third-1 micro-LED 150a disposed in the third-1 sub-pixel SP3a and a third-2 micro-LED 150b disposed in the third-2 sub-pixel SP3b.

[0104] Refer to together Figure 5 , Figure 6 and Figure 7 The second electrode CE2 can be disposed in each of the multiple sub-pixels. The second electrode CE2 can be disposed on the micro-LED ED. The second electrode CE2 can be electrically connected to the pixel driving circuit PD via multiple contact electrodes CCE.

[0105] For example, the second electrode CE2 can be electrically connected to the cathode electrode 135 of the miniature LED ED (see example). Figure 10 The cathode voltage from the pixel driving circuit PD is transmitted to the micro LED ED. The same cathode voltage can be applied to the second electrode CE2 of multiple sub-pixels. For example, the same voltage can be applied to the second electrode CE2 in each of the multiple sub-pixels and the cathode electrode 135 of the micro LED ED. Therefore, the second electrode CE2 can be a common electrode. However, embodiments of this disclosure are not limited thereto.

[0106] At least some of the multiple sub-pixels can share the second electrode CE2. At least some of the second electrodes CE2 of the multiple sub-pixels can be electrically connected to each other. Because the same voltage is applied to the second electrodes CE2, at least some of the sub-pixels can use and share the second electrode CE2. For example, the second electrodes CE2 of at least some of the multiple pixels PX located in the same row can be connected to each other. For example, one second electrode CE2 can be provided in each of the multiple pixels PX. One second electrode CE2 can be provided for each of n sub-pixels.

[0107] For example, some of the second electrodes CE2 of the plurality of sub-pixels can be configured to be spaced apart or separated from each other. For example, the second electrode CE2 connected to the pixel PX located in the nth row and the second electrode CE2 connected to the pixel PX located in the (n+1)th row can be configured to be spaced apart or separated from each other. For example, the plurality of second electrodes CE2 can be configured to be spaced apart from each other, with a plurality of communication lines NL between them and extending along the row direction. Therefore, the number of sub-pixels may be greater than the number of second electrodes CE2. In another example, all the second electrodes CE2 of the plurality of sub-pixels can be connected to each other, and only one second electrode CE2 can be provided on the substrate 110. However, the embodiments of the present disclosure are not limited thereto.

[0108] Multiple second electrodes CE2 can be made of a transparent conductive material. However, embodiments of this disclosure are not limited thereto. The multiple second electrodes CE2 can be made of a transparent conductive material, and light emitted from the micro LED ED can be guided towards the upper side of the second electrodes CE2. For example, the second electrodes CE2 can be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). However, embodiments of this disclosure are not limited thereto.

[0109] Multiple contact electrodes CCE can be disposed on the substrate 110. For example, the multiple contact electrodes CCE can be disposed spaced apart from multiple BNKs and multiple signal lines TL. Multiple second electrodes CE2 can each overlap with at least one contact electrode CCE. For example, one second electrode CE2 can overlap with multiple contact electrodes CCE.

[0110] For example, multiple contact electrodes CCE can be electrically connected to multiple second electrodes CE2. Multiple contact electrodes CCE can be disposed between the substrate 110 and the multiple second electrodes CE2, and transmit the cathode voltage from the pixel driving circuit PD to the second electrodes CE2. For example, multiple contact electrodes CCE can be electrically connected to the pixel driving circuit PD via a first connection line 121, and receive the cathode voltage from the pixel driving circuit PD.

[0111] For example, when using micro-LEDs as micro-LED EDs, the display device 1000 can be manufactured by forming multiple micro-LEDs on a wafer and transferring the micro-LEDs to the substrate 110 of the display device 1000. During the process of transferring multiple micro-LED EDs with minute dimensions to the substrate 110, various types of defects may occur. For example, in some sub-pixels, there may be non-transfer defects caused by micro-LED EDs not being transferred; and in some sub-pixels, due to alignment errors, there may be defects where micro-LED EDs are transferred out of position. Furthermore, even if the transfer process is performed normally, the transferred micro-LED EDs may still be defective. Therefore, considering the defects that may occur during the process of transferring multiple micro-LED EDs, multiple micro-LED EDs of the same type can be transferred to a single sub-pixel. A lighting check can be performed on the multiple micro-LED EDs, and only the micro-LED ED that is ultimately determined to be normal can be used.

[0112] For example, both micro-LED 130a (1-1) and micro-LED 130b (1-2) can be transferred to a single pixel PX, and their defects can be checked. If both micro-LED 130a and micro-LED 130b are determined to be normal, only micro-LED 130a can be used, without micro-LED 130b. In another example, if only micro-LED 130b (1-2) is determined to be normal between micro-LED 130a and micro-LED 130b, only micro-LED 130b can be used without micro-LED 130a. Therefore, even if multiple micro-LEDs of the same type are transferred to a single pixel PX, only one micro-LED can ultimately be used.

[0113] Therefore, either one of a pair of microLEDs can be a primary (main or dominant) microLED, and the other in the pair can be a redundant microLED. The redundant microLED can be an additional microLED prepared to be transferred in preparation for defects in the primary microLED. When the primary microLED is defective, the redundant microLED can be used to replace it. Thus, both the primary and redundant microLEDs are transferred to a single pixel (PX), which minimizes the degradation in display quality caused by defects in both the primary and redundant microLEDs.

[0114] For example, the first-1 microLED 130a, the second-1 microLED 140a, and the third-1 microLED 150a transferred to a pixel PX can be used as the main microLED ED, and the first-2 microLED 130b, the second-2 microLED 140b, and the third-2 microLED 150b can be used as redundant microLED EDs.

[0115] Figure 8 It is along Figure 3 The cross-sectional view taken from line VIII-VIII' in the diagram. Figure 9A and Figure 9B This is an enlarged view illustrating the process of the bonding pixel driving circuit and the first connecting line of the display device according to an embodiment of the present disclosure. Figure 10 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 8 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. For example, Figure 8 This is a cross-sectional view of the display area AA, the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, Figure 9A and Figure 9B This is a view used to illustrate the principle of forming the joining pattern, in which Figure 9A This is a view showing the state before diffusion bonding. Figure 9B This is a view showing the state after diffusion bonding. Figure 10 This is a magnified cross-sectional view of the first sub-pixel. Also, for ease of explanation, Figure 3 It is shown that the cutting line VIII-VIII', the driving line VL, and the connecting line LL do not overlap. However, Figure 3 The cutting line VIII-VIII' in the diagram indicates the same position as the adjacent drive line VL and the adjacent link line LL.

[0116] Reference Figure 8 The first buffer layer 111a and the second buffer layer 111b can be disposed in the remaining areas of the substrate 110 except for the bending area BA.

[0117] The first buffer layer 111a and the second buffer layer 111b can be disposed in the display area AA, the first non-display area NA1, and the second non-display area NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or impurities through the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be made of inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can each be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the embodiments of this disclosure are not limited thereto.

[0118] For example, the first buffer layer 111a and the second buffer layer 111b disposed in the bending region BA can be partially removed. The top surface of the substrate 110 located in the bending region BA can be exposed from the first buffer layer 111a and the second buffer layer 111b. Removing the first buffer layer 111a and the second buffer layer 111b made of inorganic insulating material from the bending region BA can minimize the occurrence of cracks in the first buffer layer 111a and the second buffer layer 111b that may be caused when the bending region BA is bent.

[0119] According to this disclosure, a plurality of first connection lines 121 may be provided on the second buffer layer 111b in the display area AA. The plurality of first connection lines 121 may be lines configured to electrically connect a pixel driving circuit PD to other components. For example, the pixel driving circuit PD may be electrically connected to a plurality of signal lines TL, a plurality of contact electrodes CCE, etc., via the plurality of first connection lines 121. For example, the plurality of first connection lines 121 may include a first-1 connection line 121a, a first-2 connection line 121b, a first-3 connection line 121c, and a first-4 connection line 121d. However, embodiments of this disclosure are not limited thereto.

[0120] For example, a plurality of first-1 connection lines 121a can be disposed on the second buffer layer 111b. The plurality of first-1 connection lines 121a can be electrically connected to the pixel driving circuit PD. The plurality of first-1 connection lines 121a can transmit the voltage output from the pixel driving circuit PD to the first electrode CE1 or the second electrode CE2. Simultaneously, the plurality of first-1 connection lines 121a can be used as alignment keys for aligning the position of the pixel driving circuit PD. However, this disclosure is not limited thereto.

[0121] The plurality of first-1 connection lines 121a may include recesses. The recesses of the plurality of first-1 connection lines 121a are the locations of the plurality of circuit pads PDb for mounting the pixel driving circuit PD.

[0122] Multiple first-1 connection lines 121a and multiple circuit pads PDb are coupled and electrically connected to each other in the grooves of the multiple first-1 connection lines 121a, and simultaneously fix the pixel driving circuit PD. For example, the multiple first-1 connection lines 121a and multiple circuit pads PDb can be electrically connected by diffusion bonding. For example, the multiple first-1 connection lines 121a and multiple circuit pads PDb can be connected by applying predetermined heat and pressure. However, this disclosure is not limited thereto.

[0123] The pixel driving circuit PD can be disposed on multiple first-to-first connection lines 121a in the display area AA. The pixel driving circuit PD may include a main body PDA, multiple circuit pads PDb, and a passivation film PDc.

[0124] The main body PDA of the pixel driving circuit PD can be configured to mount various types of components, and can be a semiconductor substrate on which various types of components are mounted. However, this disclosure is not limited thereto.

[0125] Multiple circuit pads PDb can be disposed on the bottom surface of the body PDA of the pixel driving circuit PD, and spaced apart from each other. The multiple circuit pads PDb can be electrically connected to the first connection line 121a via a bonding pattern BP, and transmit various signals. For example, the multiple circuit pads PDb can protrude further than the passivation film PDc, and are respectively disposed in the grooves of the first connection line 121a. However, this disclosure is not limited thereto. The multiple circuit pads PDb can be made of a conductive material, such as a material containing titanium (Ti). However, this disclosure is not limited thereto.

[0126] The passivation film PDc of the pixel driving circuit PD can be configured to surround the main body PDA and multiple circuit pads PDb. The passivation film PDc can protect the main body PDA and the multiple circuit pads PDb from the penetration of moisture or impurities. The passivation film PDc can be made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). However, this disclosure is not limited thereto.

[0127] When the pixel driving circuit PD is implemented as an operation driver, the operation driver can be electrically connected to the multiple first-1 connection lines 121a via diffusion bonding while being mounted on multiple first-1 connection lines 121a through a transfer process. However, embodiments of the present disclosure are not limited thereto.

[0128] Refer to together Figures 8 to 9B The bonding pattern BP can be disposed between the plurality of first-1 connection lines 121a and the pixel driving circuit PD. Specifically, the bonding pattern BP can be disposed in the grooves of the plurality of first-1 connection lines 121a between the plurality of first-1 connection lines 121a and the plurality of circuit pads PDb of the pixel driving circuit PD. The bonding pattern BP can electrically connect the plurality of first-1 connection lines 121a and the plurality of circuit pads PDb of the pixel driving circuit PD.

[0129] For example, the bonding pattern BP can be formed by diffusion bonding between the first-1 connection line 121a and the circuit pad PDb. That is, when the material constituting the first-1 connection line 121a and the material constituting the circuit pad PDb diffuse towards each other, the bonding pattern BP can be formed between the first-1 connection line 121a and the circuit pad PDb. However, this disclosure is not limited thereto.

[0130] For example, refer to Figure 9AThe material constituting the initial first-1 connection line 121a' can diffuse from the portion of the groove where the initial first-1 connection line 121a' is provided (adjacent to the initial circuit pad PDb') toward the initial circuit pad PDb'. Therefore, the thickness of the portion where the groove of the initial first-1 connection line 121a' is provided can be reduced. That is, the depth of the groove of the initial first-1 connection line 121a' can be further increased. However, this disclosure is not limited thereto.

[0131] Similarly, the material constituting the initial circuit pad PDb' moves from the portion of the initial circuit pad PDb' (adjacent to the initial first-1 connection line 121a') protruding toward the initial first-1 connection line 121a', such that the thickness of the protruding portion of the initial circuit pad PDb' can be reduced by a diffusion bonding process. However, this disclosure is not limited thereto.

[0132] In other words, referencing Figure 9A and Figure 9B The reduced thickness of the initial first-1 connection line 121a' and circuit pad PDb' through the diffusion bonding process allows for the formation of a bonding pattern BP between the first-1 connection line 121a and the circuit pad PDb. Therefore, the bonding pattern BP can be disposed in the groove of the first-1 connection line 121a between the first-1 connection line 121a and the circuit pad PDb, and simultaneously adjacent to both the first-1 connection line 121a and the circuit pad PDb. Thus, the bonding pattern BP can simultaneously fix and electrically connect the first-1 connection line 121a and the circuit pad PDb.

[0133] Therefore, after diffusion bonding, the first-1 connection line 121a and the circuit pad PDb can be spaced apart from each other based on the bonding pattern BP. However, this disclosure is not limited thereto.

[0134] Furthermore, the thickness of the bonding pattern BP can be determined based on the thickness of the initial first-1 connection line 121a' and the initial circuit pad PDb'. However, this disclosure is not limited thereto.

[0135] For example, the bonding pattern BP can be made of an intermetallic compound. For example, the bonding pattern BP can be made of an intermetallic compound of the material constituting the plurality of first-1 connection lines 121a and the material constituting the plurality of circuit pads PDb of the pixel driving circuit PD. For example, if the first-1 connection lines 121a are made of aluminum (Al) and the circuit pads PDb are made of titanium (Ti), the bonding pattern BP can be made of titanium aluminide (TiAl3). However, this disclosure is not limited thereto.

[0136] A protective layer 112 may be disposed on a plurality of first-1 connection lines 121a and a pixel driving circuit PD. The protective layer 112 may include a first protective layer 112a and a second protective layer 112b. However, this disclosure is not limited thereto. The protective layer 112 may be configured as a single layer. The first protective layer 112a and the second protective layer 112b may be disposed around the side surface of the pixel driving circuit PD. However, embodiments of this disclosure are not limited thereto. For example, the second protective layer 112b may be disposed to cover at least a portion of the top surface of the pixel driving circuit PD. For example, at least one of the first protective layer 112a and the second protective layer 112b disposed on the curved region BA may be excluded. For example, the first protective layer 112a may be completely disposed in the display region AA and the non-display region NA, and the second protective layer 112b may be partially disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2. For example, the portion of the second protective layer 112b disposed in the curved region BA may be removed. However, embodiments of this disclosure are not limited thereto. The first protective layer 112a and the second protective layer 112b disposed in the curved region BA can be partially removed.

[0137] The first protective layer 112a and the second protective layer 112b can each be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the first protective layer 112a and the second protective layer 112b can each be made of a photoresist, polyimide (PI), or photoacrylic material. However, embodiments of the present disclosure are not limited thereto. For example, the first protective layer 112a and the second protective layer 112b can each be an outer coating or an insulating layer. However, embodiments of the present disclosure are not limited thereto.

[0138] Multiple first-second connection lines 121b can be disposed on the second protective layer 112b. These multiple first-second connection lines 121b can be connected indirectly or directly to the pixel driving circuit PD. For example, the first-second connection lines 121b can be electrically connected to the first-first connection line 121a through contact holes in the second protective layer 112b. However, embodiments of this disclosure are not limited thereto. The voltage output from the pixel driving circuit PD can be transmitted to the first electrode CE1 or the second electrode CE2 via connection lines different from the multiple first-second connection lines 121b.

[0139] The first insulating layer 113a may be disposed on a plurality of first-second connecting lines 121b. The first insulating layer 113a may be completely disposed within the display area AA and the non-display area NA. However, embodiments of this disclosure are not limited thereto. The first insulating layer 113a may be made of an organic insulating material. However, embodiments of this disclosure are not limited thereto. For example, the first insulating layer 113a may be made of a photoresist, polyimide (PI), or photoacrylic material. However, embodiments of this disclosure are not limited thereto.

[0140] Multiple first-to-third connecting lines 121c can be disposed on the first insulating layer 113a. Multiple first-to-third connecting lines 121c can be electrically connected to multiple first-to-second connecting lines 121b. For example, the first-to-third connecting lines 121c can be electrically connected to the first-to-second connecting lines 121b through contact holes in the first insulating layer 113a.

[0141] The second insulating layer 113b can be disposed on a plurality of first-to-third connecting lines 121c. As shown in the figure, the second insulating layer 113b is disposed in a plurality of regions including the bending region BA. However, embodiments of the present disclosure are not limited thereto. The second insulating layer 113b can be disposed in the remaining regions other than the bending region BA. The second insulating layer 113b can be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2. However, embodiments of the present disclosure are not limited thereto. For example, the portion of the second insulating layer 113b disposed in the bending region BA can be removed. The second insulating layer 113b can be made of an organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, the second insulating layer 113b can be made of a photoresist, polyimide (PI), or photoacrylic material. However, embodiments of the present disclosure are not limited thereto.

[0142] Multiple first-to-fourth connection lines 121d can be disposed on the second insulating layer 113b. Multiple first-to-fourth connection lines 121d can be electrically connected to multiple first-to-third connection lines 121c. For example, the first-to-fourth connection lines 121d can be electrically connected to the first-to-third connection lines 121c through contact holes in the second insulating layer 113b.

[0143] According to this disclosure, a plurality of second connection lines 122 may be disposed on a second buffer layer 111b in the non-display area NA. The plurality of second connection lines 122 may be configured to connect the flexible circuit board (or flexible film) FCB and the printed circuit board 160 (see [link to relevant documentation]). Figure 1The signal transmitted to the pad portion PAD is transmitted to the pixel driving circuit PD in the display area AA via a line. For example, multiple second connection lines 122 can be electrically connected to multiple pad electrodes PE and receive signals from the flexible circuit board (or flexible film) FCB and the printed circuit board 160. Furthermore, the multiple second connection lines 122 can directly transmit signals from the flexible circuit board FCB and the printed circuit board 160 to the pixel driving circuit PD, or transmit signals to the pixel driving circuit PD via the first connection line 121. The pixel driving circuit PD can output cathode voltages to multiple contact electrodes CCE and multiple sub-pixels based on the signals applied from the second connection lines 122.

[0144] For example, multiple second connection lines 122 can extend from the pad portion PAD toward the display area AA and transmit signals to the pixel driving circuit PD in the display area AA. In this case, the multiple second connection lines 122 can be used as link lines LL. The multiple second connection lines 122 may include second-1 connection line 122a, second-2 connection line 122b, second-3 connection line 122c, and second-4 connection line 122d.

[0145] Multiple second-first connection lines 122a may be disposed on the second buffer layer 111b. These multiple second-first connection lines 122a may extend from the second non-display area NA2 to the curved area BA and the first non-display area NA1. Therefore, the second-first connection lines 122a may be adjacent (e.g., partially adjacent) to the first buffer layer 111a and the second buffer layer 111b in the display area AA, the first non-display area NA1, and the second non-display area NA2, and adjacent to the substrate 110 in the curved area BA. However, this disclosure is not limited thereto. The multiple second-first connection lines 122a may transmit signals from the flexible circuit board (or flexible film) FCB and the printed circuit board 160 to the pad portion PAD to the pixel driving circuit PD in the display area AA. For example, the second-first connecting line 122a can extend from the second non-display area NA2 to the first non-display area NA1 and is electrically connected to any one of the first-first connecting lines 121a, 1-2 connecting lines 121b, 1-3 connecting lines 121c, and 1-4 connecting lines 121d. For example, the second-first connecting line 122a can be directly connected to the first-first connecting line 121a disposed on the same layer, or the second-first connecting line 122a can be connected to the first-second connecting line 121b disposed on another layer through the contact hole of the protective layer 112. However, this disclosure is not limited thereto.

[0146] Multiple second-2 connection lines 122b can be disposed on the second protective layer 112b. Multiple second-2 connection lines 122b can be disposed in the second non-display area NA2. The second-2 connection lines 122b can be electrically connected to the second-1 connection line 122a through contact holes in the protective layer 112. Therefore, signals from the flexible circuit board (or flexible film) FCB and the printed circuit board 160 can be transmitted to the second-1 connection line 122a through the second-2 connection lines 122b.

[0147] The second-third connection line 122c can be disposed on the first insulating layer 113a. The second-third connection line 122c can be disposed in the second non-display area NA2. The second-third connection line 122c can be electrically connected to the second-second connection line 122b through the contact hole of the first insulating layer 113a. Therefore, signals from the flexible circuit board (or flexible film) FCB and the printed circuit board 160 can be transmitted to the second-first connection line 122a through the second-third connection line 122c and the second-second connection line 122b.

[0148] The second-fourth connection line 122d can be disposed on the second insulating layer 113b. The second-fourth connection line 122d can be disposed in the second non-display area NA2. The second-fourth connection line 122d can be electrically connected to the second-third connection line 122c through the contact hole of the second insulating layer 113b. Therefore, signals from the flexible circuit board (or flexible film) FCB and the printed circuit board 160 can be transmitted to the second-first connection line 122a through the second-fourth connection line 122d, the second-third connection line 122c, and the second-second connection line 122b.

[0149] The plurality of first connecting lines 121 and the plurality of second connecting lines 122 can be made of a conductive material with excellent flexibility or any of a variety of conductive materials used for the display area AA. For example, the second connecting lines 122, which are partially disposed in the curved area BA, can be made of a highly flexible conductive material such as gold (Au), silver (Ag), or aluminum (Al). However, embodiments of the present disclosure are not limited thereto. In another example, the plurality of first connecting lines 121 and the plurality of second connecting lines 122 can be made of an alloy of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and silver (Ag) and magnesium (Mg), or alloys thereof. However, embodiments of the present disclosure are not limited thereto.

[0150] The third insulating layer 113c can be disposed on a plurality of first connecting lines 121 and a plurality of second connecting lines 122. The third insulating layer 113c can be disposed in the remaining areas except for the bending region BA. However, embodiments of this disclosure are not limited thereto. The third insulating layer 113c can be disposed in the display region AA, the first non-display region NA1, and the second non-display region NA2. The portion of the third insulating layer 113c disposed in the bending region BA can be removed. The third insulating layer 113c can be made of an organic insulating material. However, embodiments of this disclosure are not limited thereto. For example, the third insulating layer 113c can be made of a photoresist, polyimide (PI), or photoacrylic material. However, embodiments of this disclosure are not limited thereto.

[0151] Multiple dammed LEDs (BNKs) can be disposed on the third insulating layer 113c in the display area AA. The multiple dammed LEDs (BNKs) can be configured to overlap with multiple sub-pixels. One or more micro-LEDs of the same type (EDs) can be disposed above the multiple dammed LEDs (BNKs).

[0152] Multiple signal lines TL can be disposed on the third insulating layer 113c in the display area AA. Multiple signal lines TL can be disposed in the area between multiple dams BNK. For example, multiple signal lines TL can be disposed adjacent to any one of the multiple dams BNK.

[0153] Multiple contact electrodes CCE can be disposed on the third insulating layer 113c in the display area AA. The multiple contact electrodes CCE can supply the cathode voltage from the pixel driving circuit PD to the second electrode CE2.

[0154] The first electrode CE1 can be disposed on the dam BNK. For example, the first electrode CE1 can be disposed from the adjacent signal line TL to the upper side of the dam BNK. The first electrode CE1 can be disposed on the top surface and the side surface of the dam BNK. For example, the first electrode CE1 can be disposed from the signal line TL on the top surface of the third insulating layer 113c to the side surface and the top surface of the dam BNK.

[0155] Reference Figure 10 The first electrode CE1 may include multiple conductive layers. For example, the first electrode CE1 may include a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d. However, the embodiments of this disclosure are not limited thereto.

[0156] A first conductive layer CE1a can be disposed on the embankment BNK. A second conductive layer CE1b can be disposed on the first conductive layer CE1a. A third conductive layer CE1c can be disposed on the second conductive layer CE1b. A fourth conductive layer CE1d can be disposed on the third conductive layer CE1c. For example, the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can each be made of titanium (Ti), molybdenum (Mo), aluminum (Al), or indium tin oxide (ITO). However, the embodiments of this disclosure are not limited thereto.

[0157] According to this disclosure, among the plurality of conductive layers constituting the first electrode CE1, some conductive layers having high reflectivity may include alignment keys and / or reflectors for aligning the micro-LED ED. For example, among the plurality of conductive layers of the first electrode CE1, the second conductive layer CE1b may include a reflective material. For example, the second conductive layer CE1b may include aluminum (Al). However, embodiments of this disclosure are not limited thereto. Therefore, the second conductive layer CE1b may be configured as a reflector. Furthermore, utilizing the high reflectivity of the second conductive layer CE1b, the second conductive layer CE1b can be easily identified during the manufacturing process. Therefore, the position or transfer position of the micro-LED ED can be aligned relative to the second conductive layer CE1b.

[0158] For example, to configure the second conductive layer CE1b as a reflector, the third conductive layer CE1c and the fourth conductive layer CE1d covering the second conductive layer CE1b can be partially removed or etched. For example, the third conductive layer CE1c and the fourth conductive layer CE1d disposed on the embankment BNK can be partially removed or etched so that the top surface of the second conductive layer CE1b can be exposed. For example, the central and boundary (or edge) portions of the solder pattern SDP of the third conductive layer CE1c and the fourth conductive layer CE1d can be retained, and the remaining portions other than those mentioned above can be removed. For example, the boundary (or edge) portions of the third conductive layer CE1c made of titanium (Ti) and the boundary (or edge) portions of the fourth conductive layer CE1d made of indium tin oxide (ITO) can be left unetched. Therefore, the etching of other conductive layers of the first electrode CE1 by the tetramethylammonium hydroxide (TMAH) solution used in the masking process of the first electrode CE1 can be suppressed.

[0159] According to this disclosure, the first conductive layer CE1a and the third conductive layer CE1c may comprise titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b may comprise aluminum (Al). The fourth conductive layer CE1d may comprise a transparent conductive oxide layer made of indium tin oxide (ITO) or indium zinc oxide (IZO), which has high adhesion to the solder pattern SDP and is corrosion-resistant and acid-resistant. However, embodiments of this disclosure are not limited thereto.

[0160] The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can be deposited sequentially and then patterned by photolithography and etching processes. However, the embodiments of this disclosure are not limited thereto.

[0161] According to this disclosure, the signal line TL, contact electrode CCE, and pad electrode PE disposed on the same layer as the first electrode CE1 can each be configured as a multilayer made of conductive material. However, embodiments of this disclosure are not limited thereto. For example, the signal line TL, contact electrode CCE, and pad electrode PE can each be configured as a multilayer made of indium tin oxide (ITO), titanium (Ti), aluminum (Al), and titanium (Ti). However, embodiments of this disclosure are not limited thereto.

[0162] According to this disclosure, a solder pattern SDP can be disposed on a first electrode CE1 in each of a plurality of sub-pixels. The solder pattern SDP can electrically connect the first electrode CE1 and the micro-LED ED by bonding the micro-LED ED to the first electrode CE1. For example, the first electrode CE1 and the anode electrode 134 of the micro-LED ED can be electrically connected via eutectic bonding using the solder pattern SDP. However, embodiments of this disclosure are not limited thereto. For example, in the case where the solder pattern SDP is made of indium (In) and the anode electrode 134 of the micro-LED ED is made of gold (Au), the solder pattern SDP and the anode electrode 134 can be bonded by applying heat and pressure during the transfer of the micro-LED ED. The micro-LED ED can be bonded to the solder pattern SDP and the first electrode CE1 via eutectic bonding without the need for separate bonding materials. For example, the solder pattern SDP can be made of indium (In), tin (Sn), or alloys thereof. However, embodiments of this disclosure are not limited thereto. For example, the solder pattern SDP can be a bonding pad or a bonding pad. However, embodiments of this disclosure are not limited thereto.

[0163] According to this disclosure, a passivation layer 114 can be disposed on multiple signal lines TL, multiple first electrodes CE1, multiple contact electrodes CCE, and a third insulating layer 113c. For example, the passivation layer 114 can be disposed in a display area AA, a first non-display area NA1, and a second non-display area NA2. A portion of the passivation layer 114 disposed in a curved area BA can be removed. A portion of the passivation layer 114 covering multiple pad electrodes PE in the second non-display area NA2 can be removed. The passivation layer 114 is configured to cover the remaining area except for the area where the curved area BA, multiple pad electrodes PE, and solder pattern SDP are disposed, and therefore, the penetration of moisture or impurities introduced into the micro LED ED can be reduced. For example, the passivation layer 114 can be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, embodiments of this disclosure are not limited thereto. For example, the passivation layer 114 can be a protective layer, an insulating layer, etc. However, embodiments of this disclosure are not limited thereto. For example, passivation layer 114 may include a hole through which the weld pattern SDP is exposed.

[0164] In each of the multiple sub-pixels, a micro-LED ED can be disposed on the welding pattern SDP. A first micro-LED 130 can be disposed in the first sub-pixel SP1. A second micro-LED 140 can be disposed in the second sub-pixel SP2. A third micro-LED 150 can be disposed in the third sub-pixel SP3.

[0165] Micro-LEDs can be formed on silicon wafers using methods such as metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or sputtering. However, embodiments of the present disclosure are not limited thereto.

[0166] Reference Figure 10 The first micro-LED 130 may include an anode electrode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode electrode 135, and an encapsulation film 136. However, embodiments of this disclosure are not limited thereto. For example, the first micro-LED 130 may not include the encapsulation film 136.

[0167] The first semiconductor layer 131 can be disposed on the welding pattern SDP. The second semiconductor layer 133 can be disposed on the first semiconductor layer 131.

[0168] For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be implemented as a group III-V or group II-VI compound semiconductor and doped with impurities (or dopants). For example, one of the first semiconductor layer 131 and the second semiconductor layer 133 can be a semiconductor layer doped with n-type impurities, and the other of the first semiconductor layer 131 and the second semiconductor layer 133 can be a semiconductor layer doped with p-type impurities. However, embodiments of the present disclosure are not limited thereto. For example, one or both of the first semiconductor layer 131 and the second semiconductor layer 133 can be layers made by doping with n-type or p-type impurities with materials such as gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenide (AlGaAs), or gallium arsenide (GaAs). However, embodiments of the present disclosure are not limited thereto. For example, n-type impurities can be silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), tin (Sn), etc. However, the embodiments of this disclosure are not limited to these. For example, p-type impurities can be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), beryllium (Be), etc. However, the embodiments of this disclosure are not limited to these.

[0169] For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities and a nitride semiconductor containing p-type impurities, respectively. However, the embodiments of this disclosure are not limited to this. For example, the first semiconductor layer 131 may be a nitride semiconductor containing p-type impurities, and the second semiconductor layer 133 may be a nitride semiconductor containing n-type impurities. However, the embodiments of this disclosure are not limited to this.

[0170] An active layer 132 may be disposed between a first semiconductor layer 131 and a second semiconductor layer 133. The active layer 132 can emit light by receiving positive holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. For example, the active layer 132 may have any of the following structures: a single-well structure, a multi-well structure, a single quantum well structure, a multiple quantum well (MQW) structure, a quantum dot structure, and a quantum wire structure. However, embodiments of this disclosure are not limited thereto. For example, the active layer 132 may be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, embodiments of this disclosure are not limited thereto.

[0171] In another example, the active layer 132 may include a multiple quantum well (MQW) structure having a well layer and a barrier layer having a higher bandgap than the well layer. For example, the active layer 132 may be configured with an InGaN layer as the well layer and an AlGaN layer as the barrier layer. However, embodiments of this disclosure are not limited thereto.

[0172] An anode electrode 134 may be disposed between the first semiconductor layer 131 and the solder pattern SDP. For example, the anode electrode 134 may electrically connect the first semiconductor layer 131 to the first electrode CE1. The anode voltage output from the pixel driving circuit PD may be applied to the first semiconductor layer 131 via the signal line TL, the first electrode CE1, and the anode electrode 134. For example, the anode electrode 134 may be made of a conductive material that can be bonded to the solder pattern SDP via eutectic bonding. However, embodiments of this disclosure are not limited thereto. For example, the anode electrode 134 may be made of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), copper (Cu), or alloys thereof. However, embodiments of this disclosure are not limited thereto.

[0173] A cathode electrode 135 may be disposed on the second semiconductor layer 133. For example, the cathode electrode 135 may electrically connect the second semiconductor layer 133 to the second electrode CE2. The cathode voltage output from the pixel driving circuit PD may be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode electrode 135. The cathode electrode 135 may be made of a transparent conductive material, allowing light emitted from the micro LED ED to propagate to the upper side of the micro LED ED. However, embodiments of this disclosure are not limited thereto. For example, the cathode electrode 135 may be made of materials such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). However, embodiments of this disclosure are not limited thereto.

[0174] The encapsulation film 136 may be at least partially disposed on the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135. For example, the encapsulation film 136 may at least partially surround the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode electrode 134, and the cathode electrode 135.

[0175] For example, the encapsulation film 136 can protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. For example, the encapsulation film 136 can be disposed on the side surface of the first semiconductor layer 131, the side surface of the active layer 132, and the side surface of the second semiconductor layer 133.

[0176] For example, the encapsulation film 136 may be disposed on at least a portion of the anode electrode 134 and at least a portion of the cathode electrode 135, for example, on the edge portion (or edge portion or side) of the anode electrode 134 and the edge portion (or edge portion or side) of the cathode electrode 135. At least a portion of the anode electrode 134 may be exposed from the encapsulation film 136, allowing the anode electrode 134 and the solder pattern SDP to be connected. For example, at least a portion of the cathode electrode 135 may be exposed from the encapsulation film 136, allowing the cathode electrode 135 and the second electrode CE2 to be connected. For example, the encapsulation film 136 may be made of an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). However, embodiments of this disclosure are not limited thereto.

[0177] In another example, the encapsulation film 136 may have a structure in which reflective material is dispersed in a resin layer. However, embodiments of the present disclosure are not limited thereto. For example, the encapsulation film 136 may be manufactured as a reflector with various structures. However, embodiments of the present disclosure are not limited thereto. Light emitted from the active layer 132 is reflected upward by the encapsulation film 136, which can improve light extraction efficiency. For example, the encapsulation film 136 may be a reflective layer. However, embodiments of the present disclosure are not limited thereto.

[0178] According to this disclosure, micro LED EDs have been described as having a vertical structure. However, embodiments of this disclosure are not limited to this. For example, micro LED EDs may have a horizontal structure or a flip-chip structure.

[0179] Already referred to Figure 10 A first microLED 130 is described. A second microLED 140 and a third microLED 150 may have substantially the same structure as the first microLED 130. For example, the first semiconductor layer 131, active layer 132, second semiconductor layer 133, anode electrode 134, cathode electrode 135, and encapsulation film 136 of the first microLED 130 may be substantially the same as those of the second microLED 140 and the third microLED 150.

[0180] According to this disclosure, the first optical layer 115a can be configured to surround a plurality of micro-LEDs ED in a display area AA. For example, the first optical layer 115a can be configured to cover a plurality of micro-LEDs ED and a BNK in a region of a plurality of sub-pixels. For example, the first optical layer 115a can cover a portion of the BNK, the passivation layer 114, and the portion between the plurality of micro-LEDs ED. The first optical layer 115a can be disposed between a plurality of micro-LEDs ED and a plurality of BNK included in a pixel PX, or cover a plurality of micro-LEDs ED and a plurality of BNK. For example, the first optical layer 115a can extend in the row direction and be configured to be spaced apart from each other in the column direction. For example, the first optical layer 115a can be disposed between the passivation layer 114 and the second electrode CE2, and surround the side (or side) of the micro-LEDs ED and the side (or side) of the BNK. However, the embodiments of this disclosure are not limited thereto. For example, the first optical layer 115a can be a diffusion layer, a sidewall diffusion layer, etc. However, the embodiments of this disclosure are not limited thereto.

[0181] The first optical layer 115a may include an organic insulating material in which fine particles are dispersed. However, embodiments of the present disclosure are not limited thereto. For example, the first optical layer 115a may be made of a siloxane in which fine metal particles such as titanium dioxide (TiO2) particles are dispersed. However, embodiments of the present disclosure are not limited thereto. Light emitted from the plurality of micro LEDs can be scattered by the fine particles dispersed in the first optical layer 115a, and the light can be emitted to the outside of the display device 1000. Therefore, the first optical layer 115a can improve the extraction efficiency of light emitted from the plurality of micro LEDs.

[0182] For example, the first optical layer 115a may be disposed in each of the plurality of pixels PX, or disposed together with some pixels PX disposed in the same row. However, the embodiments of the present disclosure are not limited thereto. For example, the first optical layer 115a may be disposed in each of the plurality of pixels PX, or the plurality of pixels PX may share a first optical layer 115a. In another example, the plurality of sub-pixels may each individually include the first optical layer 115a. However, the embodiments of the present disclosure are not limited thereto.

[0183] According to this disclosure, the second optical layer 115b can be disposed on the third insulating layer 113c in the display area AA. For example, the second optical layer 115b can be disposed around the first optical layer 115a. For example, the second optical layer 115b can be adjacent to the side surface of the first optical layer 115a. For example, the second optical layer 115b can be disposed in the area between a plurality of pixels PX. However, the embodiments of this disclosure are not limited thereto. For example, the second optical layer 115b can be a diffusion layer, a diffusion layer window, a window diffusion layer, etc. However, the embodiments of this disclosure are not limited thereto.

[0184] The second optical layer 115b may be made of an organic insulating material. However, embodiments of this disclosure are not limited thereto. The second optical layer 115b may be made of the same material as the first optical layer 115a. However, embodiments of this disclosure are not limited thereto. For example, the first optical layer 115a may include fine particles, and the second optical layer 115b may not include fine particles. For example, the second optical layer 115b may be made of siloxane. However, embodiments of this disclosure are not limited thereto.

[0185] For example, the thickness of the first optical layer 115a may be less than the thickness of the second optical layer 115b. However, embodiments of this disclosure are not limited thereto. Therefore, when viewed in a plan view, the area where the first optical layer 115a is disposed may include a recessed portion recessed inward from the top surface of the second optical layer 115b.

[0186] According to this disclosure, the second electrode CE2 can be disposed on the first optical layer 115a and the second optical layer 115b. For example, the second electrode CE2 can be electrically connected to multiple contact electrodes CCE through contact holes in the second optical layer 115b. For example, the second electrode CE2 can be disposed on multiple micro LEDs ED. For example, the second electrode CE2 can include a transparent conductive oxide made of indium tin oxide (ITO), indium zinc oxide (IZO), etc. However, embodiments of this disclosure are not limited thereto. For example, the second electrode CE2 can be disposed in contact with the cathode electrode 135. For example, the second electrode CE2 can overlap with the first optical layer 115a. For example, the second electrode CE2 can cover the outer flat surface of the first optical layer 115a.

[0187] The second electrode CE2 can extend continuously in the first direction of the substrate 110. Therefore, the second electrode CE2 can be commonly connected to a plurality of pixels PX arranged in the first direction of the substrate 110. For example, the second electrode CE2 can be commonly connected to a plurality of pixels PX.

[0188] According to this disclosure, the second electrode CE2 can extend continuously over the first optical layer 115a, the second optical layer 115b, and the micro LED ED. The region where the first optical layer 115a is disposed may include a recessed portion that is recessed inward from the top surface of the second optical layer 115b. Therefore, since the first portion of the second electrode CE2 disposed on the first optical layer 115a is disposed along the recessed portion, the first portion of the second electrode CE2 can be disposed at a position lower than the second portion of the second electrode CE2 disposed on the second optical layer 115b.

[0189] The third optical layer 115c can be disposed on the second electrode CE2. The third optical layer 115c can be disposed overlapping the plurality of micro LEDs and the first optical layer 115a. Since the third optical layer 115c is disposed above the second electrode CE2 and the plurality of micro LEDs, it can suppress any murmurs that may occur among some of the plurality of micro LEDs. For example, when the plurality of micro LEDs are transferred onto the substrate 110 of the display device 1000, areas of uneven spacing between the plurality of micro LEDs may appear due to process variations, etc. In the case of uneven spacing between the plurality of micro LEDs, the light-emitting areas of the plurality of micro LEDs may be unevenly arranged, and the user may visually perceive the unevenness. Therefore, the third optical layer 115c, which is configured to uniformly diffuse light, is disposed above the plurality of micro LEDs, which can reduce the situation where the light emitted from some micro LEDs is visually perceived as uneven. Therefore, the light emitted from multiple micro LEDs can be uniformly diffused and extracted to the outside of the display device 1000 by the third optical layer 115c, which can improve the brightness uniformity of the display device 1000.

[0190] The third optical layer 115c can be made of an organic insulating material with dispersed fine particles. However, embodiments of the present disclosure are not limited thereto. For example, the third optical layer 115c can be made of a siloxane in which fine metal particles such as titanium dioxide (TiO2) particles are dispersed. However, embodiments of the present disclosure are not limited thereto. For example, the third optical layer 115c can be made of the same material as the first optical layer 115a. However, embodiments of the present disclosure are not limited thereto. For example, the third optical layer 115c can be a diffusion layer or a top diffusion layer. However, embodiments of the present disclosure are not limited thereto.

[0191] According to this disclosure, light emitted from multiple micro-LEDs can be scattered by fine particles dispersed in the third optical layer 115c, and the light can be emitted to the outside of the display device 1000. The third optical layer 115c can uniformly mix the light beams emitted from the multiple micro-LEDs, which can further improve the brightness uniformity of the display device 1000. In addition, the light extraction efficiency of the display device 1000 can be improved by the light scattered by the multiple fine particles, enabling the display device 1000 to operate with low power consumption.

[0192] In the display area AA, a black matrix BM can be disposed on the second electrode CE2, the first optical layer 115a, the second optical layer 115b, and the third optical layer 115c. For example, the contact holes of the second optical layer 115b can be filled with the black matrix BM. Since the black matrix BM is configured to cover the display area AA, color mixing and external light reflection of light emitted from multiple sub-pixels can be reduced. For example, the black matrix BM can even be disposed in the contact holes connecting the second electrode CE2 and the contact electrode CCE, which can suppress light leakage between multiple adjacent sub-pixels.

[0193] For example, the black matrix BM can be made of an opaque material. However, embodiments of this disclosure are not limited thereto. For example, the black matrix BM can be made of an organic insulating material with added black pigment or dye. However, embodiments of this disclosure are not limited thereto.

[0194] Cover layer 116 can be disposed on the black matrix BM in the display area AA. Cover layer 116 can protect components disposed beneath cover layer 116. For example, cover layer 116 can be made of organic insulating material. However, embodiments of the present disclosure are not limited thereto. For example, cover layer 116 can be made of photoresist, polyimide (PI), or photoacrylic material. However, embodiments of the present disclosure are not limited thereto. For example, cover layer 116 can be an outer coating, an insulating layer, etc. However, embodiments of the present disclosure are not limited thereto.

[0195] The polarizing layer 293 can be disposed on the cover layer 116 by means of the first bonding layer 291. The cover member 120 can be disposed on the polarizing layer 293 by means of the second bonding layer 295. For example, the first bonding layer 291 and the second bonding layer 295 may each include optically transparent adhesive (OCA), optically transparent resin (OCR), pressure-sensitive adhesive (PSA), etc. However, embodiments of the present disclosure are not limited thereto.

[0196] According to this disclosure, multiple pad electrodes PE can be disposed on a third insulating layer 113c in the second non-display area NA2. For example, the multiple pad electrodes PE can be exposed at least partially from the passivation layer 114. For example, the multiple pad electrodes PE can be electrically connected to the second-fourth connection line 122d through contact holes in the third insulating layer 113c.

[0197] A bonding layer ACF can be disposed on multiple pad electrodes PE. The bonding layer ACF can be a bonding layer made by dispersing conductive balls in an insulating material. However, embodiments of this disclosure are not limited to this. When heat or pressure is applied to the bonding layer ACF, the conductive balls are electrically connected in the portions where heat or pressure is applied, such that the bonding layer ACF can have conductive properties. The bonding layer ACF can be disposed between multiple pad electrodes PE and a flexible circuit board (or flexible film) FCB, and the flexible circuit board (or flexible film) FCB is attached or bonded to the multiple pad electrodes PE. For example, the bonding layer ACF can be an anisotropic conductive film (ACF). However, embodiments of this disclosure are not limited to this.

[0198] A flexible circuit board (or flexible film) FCB can be disposed on a bonding layer ACF. The flexible circuit board (or flexible film) FCB can be electrically connected to multiple pad electrodes PE through the bonding layer ACF. Therefore, signals output from the flexible circuit board (or flexible film) FCB and the printed circuit board 160 can be transmitted to the pixel driving circuit PD in the display area AA through the multiple pad electrodes PE, connection line 122d (2-4), connection line 122c (2-3), connection line 122b (2-2), and connection line 122a (2-1).

[0199] In display devices, pixel driving circuitry, including micro-drivers, can be positioned below micro-LEDs to operate them. This requires various constituent elements and processes for forming these elements.

[0200] For example, a bonding layer can be disposed between the substrate and the pixel driving circuit to fix the pixel driving circuit to the substrate. Typically, since the bonding layer is made of an insulating material, a process is required to separately form alignment keys made of a metal material around the bonding layer to align the position of the pixel driving circuit.

[0201] Furthermore, when the bonding layer is applied across the entire substrate, foreign matter may adhere to areas excluding those where pixel driving circuitry is located during the process. If a protective or insulating layer is applied with foreign matter attached, the flatness of the upper portion of the protective or insulating layer may deteriorate. For this reason, an additional process to remove the foreign matter is required.

[0202] At the same time, when the passivation film surrounds the circuit pads of the pixel driving circuit, it is necessary to perform an additional process to remove the passivation film to expose the circuit pads.

[0203] For example, the circuit pads of the pixel driver circuit can be configured to be directed upwards, i.e., towards the micro-LED. Therefore, all the multiple connection lines used to connect the circuit pads and the micro-LED can be positioned on the pixel driver circuit. Typically, a protective layer can be configured to surround the pixel driver circuit to flatten the upper portion of the area where the pixel driver circuit is located and the surrounding area. For example, the protective layer can be at least the thickness of the pixel driver circuit.

[0204] However, with all the multiple connection lines used to connect the micro-LEDs and the pixel driving circuit arranged on the pixel driving circuit as described above, an additional protective layer or insulating layer is required on the protective layer to insulate the multiple connection lines from each other. For this reason, process costs and time increase, and the number of layered structures increases, making it difficult to achieve a thin display device. Furthermore, with multiple additional protective or insulating layers, there is a problem of deterioration in the flatness of the upper portion of the substrate.

[0205] In the display device 1000 according to an embodiment of the present disclosure, a pixel driving circuit PD is disposed on the first-1 connection line 121a and bonded without a separate bonding layer, such that the pixel driving circuit PD and the first-1 connection line 121a are electrically connected, and the pixel driving circuit PD can be fixed. Specifically, the pixel driving circuit PD can be configured such that the circuit pad PDb is directed downwards, so that the pixel driving circuit PD can be disposed on the first-1 connection line 121a disposed below the pixel driving circuit PD. For example, the circuit pad PDb disposed on the bottom surface of the body PDA of the pixel driving circuit PD can be configured to protrude more than the passivation film PDc, and the first-1 connection line 121a can include a groove. That is, since the circuit pad PDb is disposed in the groove of the first-1 connection line 121a, the pixel driving circuit PD can be electrically connected to the first-1 connection line 121a while being transferred to the first-1 connection line 121a. In other words, the pixel driving circuit PD can be electrically connected to the first-1 connection line 121a without the need to remove the passivation film PDc to expose the circuit pad PDb. In this case, the circuit pad PDb and the first-1 connection line 121a are structurally coupled, and the circuit pad PDb and the first-1 connection line 121a are joined by diffusion bonding, which ensures the fixing force generated by diffusion bonding.

[0206] In other words, in the display device 1000 according to the embodiments of the present disclosure, the pixel driving circuit PD can be effectively fixed to the substrate 110 without a separate bonding layer, and may even be excluded from the bonding layer, which can reduce process time and cost. Furthermore, since no bonding layer is included, defects caused by unwanted foreign matter adhering to the bonding layer can be suppressed. Therefore, since the process of removing foreign matter can also be omitted, process time and cost can be reduced more effectively.

[0207] Furthermore, in the display device 1000 according to the embodiments of the present disclosure, the layered structure can be further simplified by omitting the bonding layer. Therefore, a thin display device can be realized, and various constituent elements can be stacked to minimize the problem of flatness degradation of the upper portion of the substrate 110, thereby ensuring the flatness of the display device 1000.

[0208] Furthermore, since the pixel driving circuit PD is disposed on the first-1 connection line 121a made of metal material, the first-1 connection line 121a can be used as an alignment key. Therefore, since the process of separately forming an alignment key made of metal material to align the position of the pixel driving circuit PD can be eliminated, process time and cost can be reduced.

[0209] Furthermore, in the display device 1000 according to the embodiments of the present disclosure, the first-1 connection line 121a and the first-2 connection line 121b can be spaced apart from each other based on the pixel driving circuit PD and the protective layer 112 surrounding the pixel driving circuit PD. That is, since the first-2 connection line 121b is disposed on the protective layer 112, which is substantially configured to planarize the pixel driving circuit PD and the surrounding area, it is not necessary to provide a separate additional protective layer or insulating layer between the first-1 connection line 121a and the first-2 connection line 121b. Therefore, the process cost and time that may be caused by the arrangement of additional protective layers or insulating layers can be reduced. In addition, the layered structure can be minimized by omitting additional protective layers or insulating layers, making it possible to realize a thin display device and ensuring the flatness of the upper portion of the substrate 110.

[0210] Figure 11 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. Figure 12A and Figure 12B This is an enlarged view illustrating the process of joining the pixel driving circuit and the first connecting line 1-1 of a display device according to another embodiment of the present disclosure. Figures 11 to 12B The display device 2000 in the middle is configured with Figures 1 to 10The display device 1000 is basically the same as that in the above, except for the pixel driving circuit PD, the bonding pattern BP, and the first-1 connecting line 221a. Therefore, repeated descriptions of the same components will be omitted.

[0211] Reference Figure 11 The plurality of first-1 connection lines 221a may include protruding portions. The protruding portions of the plurality of first-1 connection lines 221a may be portions of a plurality of circuit pads PDb coupled to the pixel driving circuit PD.

[0212] The protruding portions of the plurality of first-1 connection lines 221a and the plurality of circuit pads PDb are coupled and electrically connected to each other, and simultaneously fix the pixel driving circuit PD. For example, the plurality of first-1 connection lines 221a and the plurality of circuit pads PDb can be electrically connected by diffusion bonding. For example, the plurality of first-1 connection lines 221a and the plurality of circuit pads PDb can be connected by applying predetermined heat and pressure. However, this disclosure is not limited thereto.

[0213] Multiple circuit pads PDb can be electrically connected to the first-1 connection line 221a via a bonding pattern BP and transmit various signals. For example, multiple circuit pads PDb can be disposed inside the passivation film PDc and respectively coupled to the protruding portion of the first-1 connection line 221a. However, this disclosure is not limited thereto. The multiple circuit pads PDb can be made of a conductive material (e.g., a material containing titanium (Ti)). However, this disclosure is not limited thereto.

[0214] The passivation film PDc of the pixel driving circuit PD can be configured to surround the main body PDA and multiple circuit pads PDb. For example, the passivation film PDc may include a groove exposing multiple circuit pads. That is, the protruding portion of the first-1 connection line 221a can be disposed in the groove of the passivation film PDc, and the circuit pads PDb exposed through the groove can be coupled to the first-1 connection line 221a. However, this disclosure is not limited thereto.

[0215] Refer to together Figures 11 to 12B The bonding pattern BP can be disposed between multiple first-1 connection lines 221a and the pixel driving circuit PD. Specifically, the bonding pattern BP can be disposed in the groove of the passivation film PDc between multiple first-1 connection lines 221a and multiple circuit pads PDb of the pixel driving circuit PD. The bonding pattern BP can electrically connect the multiple first-1 connection lines 221a and the multiple circuit pads PDb of the pixel driving circuit PD.

[0216] For example, a bonding pattern BP can be formed by diffusion bonding between the first-1 connection line 221a and the circuit pad PDb. That is, a bonding pattern BP can be formed between the first-1 connection line 221a and the circuit pad PDb when the materials constituting the first-1 connection line 221a and the circuit pad PDb diffuse toward each other. However, this disclosure is not limited thereto.

[0217] For example, refer to Figure 12A The material constituting the initial first-1 connection line 221a' can diffuse from the protruding portion of the initial first-1 connection line 221a' adjacent to the initial circuit pad PDb' toward the initial circuit pad PDb'. Therefore, the thickness of the protruding portion of the initial first-1 connection line 221a' can be reduced. However, this disclosure is not limited thereto.

[0218] Similarly, the material constituting the initial circuit pad PDb' moves from the portion of the initial circuit pad PDb' adjacent to the initial first-1 connection line 221a' toward the initial first-1 connection line 221a', such that the thickness of the initial circuit pad PDb' can be reduced by the diffusion bonding process. However, this disclosure is not limited thereto.

[0219] In other words, referencing Figure 12A and Figure 12B The bonding pattern BP can be formed between the first-1 connection line 221a and the circuit pad PDb by reducing the initial thickness of the first-1 connection line 221a' and the circuit pad PDb' through a diffusion bonding process. Therefore, the bonding pattern BP can be disposed in the groove of the passivation film PDc between the first-1 connection line 221a and the circuit pad PDb, and simultaneously adjacent to both the first-1 connection line 221a and the circuit pad PDb. Thus, the bonding pattern BP can simultaneously fix and electrically connect the first-1 connection line 221a and the circuit pad PDb.

[0220] Therefore, after diffusion bonding, the first-1 connection line 221a and the circuit pad PDb can be spaced apart from each other based on the bonding pattern BP. However, this disclosure is not limited thereto.

[0221] The thickness of the bonding pattern BP can be determined based on the thickness of the initial first-1 connection line 221a' and the initial circuit pad PDb'. However, this disclosure is not limited thereto.

[0222] For example, the bonding pattern BP can be made of an intermetallic compound. For example, the bonding pattern BP can be made of an intermetallic compound consisting of the material constituting the plurality of first-1 connection lines 221a and the material constituting the plurality of circuit pads PDb of the pixel driving circuit PD. For example, if the first-1 connection lines 221a are made of aluminum (Al) and the circuit pads PDb are made of titanium (Ti), the bonding pattern BP can be made of titanium aluminide (TiAl3). However, this disclosure is not limited thereto.

[0223] In another embodiment of the display device 2000 according to this disclosure, a pixel driving circuit PD is disposed on the first-1 connection line 221a and bonded without a separate bonding layer, such that the pixel driving circuit PD and the first-1 connection line 221a can be electrically connected and the pixel driving circuit PD can be fixed. Specifically, the pixel driving circuit PD can be configured such that the circuit pad PDb is directed downwards, so that the pixel driving circuit PD can be disposed on the first-1 connection line 221a disposed below the pixel driving circuit PD. For example, the circuit pad PDb disposed on the bottom surface of the body PDA of the pixel driving circuit PD can be disposed inside the passivation film PDc, and the passivation film PDc can include a groove exposing the circuit pad PDb. Meanwhile, the first-1 connection line 221a can include a protrusion corresponding to the groove of the passivation film PDc. In other words, since the protruding portion of the first-1 connection line 221a is located in the groove of the passivation film PDc of the exposed circuit pad PDb, the pixel driving circuit PD can be electrically connected to the first-1 connection line 221a while being transferred to it. In this case, the circuit pad PDb and the first-1 connection line 221a are structurally coupled, and the circuit pad PDb and the first-1 connection line 221a are joined by diffusion bonding, which ensures the fixing force generated by the diffusion bonding.

[0224] In other words, in the display device 2000 according to another embodiment of the present disclosure, the pixel driving circuit PD can be effectively fixed to the substrate 110 without a separate bonding layer, and the bonding layer may not be required, which can reduce process time and cost. Furthermore, since the bonding layer is not required, defects caused by unwanted foreign matter adhering to the bonding layer can be suppressed. Therefore, since the process of removing foreign matter may also be omitted, process time and cost can be reduced more effectively.

[0225] Furthermore, in another embodiment of the display device 2000 according to this disclosure, the layered structure can be further simplified by omitting the bonding layer. Therefore, a thin display device can be realized, and various constituent elements can be stacked to minimize the problem of flatness degradation of the upper portion of the substrate 110, thereby ensuring the flatness of the display device 2000.

[0226] Furthermore, since the pixel driving circuit PD is disposed on the first-1 connection line 221a made of metal material, the first-1 connection line 221a can be used as an alignment key. Therefore, since the process of separately forming an alignment key made of metal material to align the position of the pixel driving circuit PD can be eliminated, process time and cost can be reduced.

[0227] Furthermore, in another embodiment of the display device 2000 according to this disclosure, the first-1 connection line 221a and the first-2 connection line 121b can be spaced apart from each other based on the pixel driving circuit PD and the protective layer 112 surrounding the pixel driving circuit PD. That is, since the first-2 connection line 121b is disposed on the protective layer 112, which is substantially configured to planarize the pixel driving circuit PD and the surrounding area, it is not necessary to provide a separate additional protective layer or insulating layer between the first-1 connection line 221a and the first-2 connection line 121b. Therefore, the process cost and time that may be caused by the arrangement of additional protective layers or insulating layers can be reduced. In addition, the layered structure can be minimized by omitting additional protective layers or insulating layers, making it possible to realize a thin display device and ensuring the flatness of the upper portion of the substrate 110.

[0228] Figure 13 This is a cross-sectional view of a display device according to yet another embodiment of the present disclosure. Figure 14A and Figure 14B This is an enlarged view illustrating the process of joining the pixel driving circuit and the first connecting line 1-1 of a display device according to another embodiment of the present disclosure. Figures 13 to 14B The display device 3000 in the middle is configured with Figures 1 to 10 The display device 1000 is basically the same as that in the above, except for the pixel driving circuit PD, the bonding pattern BP, and the first-1 connecting line 321a. Therefore, repeated descriptions of the same components will be omitted.

[0229] Reference Figure 13 The plurality of first-1 connection lines 321a may include grooves. The grooves of the plurality of first-1 connection lines 321a may be portions corresponding to the grooves of the passivation film PDc of the pixel driving circuit PD, and may be positions where the bonding pattern BP is set.

[0230] A bonding pattern BP can be disposed in the grooves of a plurality of first-1 connection lines 321a, such that the plurality of first-1 connection lines 321a and a plurality of circuit pads PDb can be coupled and electrically connected to each other by means of the bonding pattern BP, and simultaneously fix the pixel driving circuit PD. For example, the plurality of first-1 connection lines 321a and a plurality of circuit pads PDb can be electrically connected by diffusion bonding. For example, the plurality of first-1 connection lines 321a and a plurality of circuit pads PDb can be connected by applying predetermined heat and pressure. However, this disclosure is not limited thereto.

[0231] Multiple circuit pads PDb can be electrically connected to the first-1 connection line 321a via a bonding pattern BP and transmit various signals. For example, multiple circuit pads PDb can be disposed inside the passivation film PDc and coupled to the first-1 connection line 321a by means of the bonding pattern of the first-1 connection line 321a. However, this disclosure is not limited thereto. The multiple circuit pads PDb can be made of a conductive material (e.g., a material containing titanium (Ti)). However, this disclosure is not limited thereto.

[0232] The passivation film PDc of the pixel driving circuit PD can be configured to surround the main body PDA and multiple circuit pads PDb. For example, the passivation film PDc may include a groove exposing the multiple circuit pads PDb. The groove of the passivation film PDc can be configured to correspond to the groove of the first-1 connection line 321a. That is, like the groove of the first-1 connection line 321a, the groove of the passivation film PDc can be a location for setting the bonding pattern BP. In other words, the bonding pattern BP can be set in the groove of the passivation film PDc, such that the circuit pads exposed by the groove can be bonded to the first-1 connection line 321a.

[0233] Refer to together Figures 13 to 14B The bonding pattern BP can be disposed between the plurality of first-1 connection lines 321a and the pixel driving circuit PD. Specifically, the bonding pattern BP can be disposed in the grooves of the plurality of first-1 connection lines 321a and the grooves of the passivation film PDc between the plurality of first-1 connection lines 321a and the plurality of circuit pads PDb of the pixel driving circuit PD. The bonding pattern BP can electrically connect the plurality of first-1 connection lines 321a to the plurality of circuit pads PDb of the pixel driving circuit PD.

[0234] For example, a bonding pattern BP can be formed by diffusion bonding between the first-1 connection line 321a and the circuit pad PDb. That is, a bonding pattern BP can be formed between the first-1 connection line 321a and the circuit pad PDb when the materials constituting the first-1 connection line 321a and the materials constituting the circuit pad PDb diffuse toward each other. However, this disclosure is not limited thereto.

[0235] For example, refer to Figure 14A The initial circuit pad PDb' and the initial first-1 connection line 321a' can have a flat structure in which neither a protrusion nor a groove is provided. That is, the initial circuit pad PDb' can be disposed on the same plane as the passivation film PDc, and disposed parallel to and adjacent to the initial first-1 connection line 321a'. In this case, the material constituting the initial first-1 connection line 321a' can diffuse from the portion of the initial first-1 connection line 321a' adjacent to the initial circuit pad PDb' toward the initial circuit pad PDb'. Therefore, the thickness of the protrusion of the initial first-1 connection line 321a' can be reduced, and a groove can be formed. However, the present disclosure is not limited thereto.

[0236] Similarly, the material constituting the initial circuit pad PDb' moves from the portion of the initial circuit pad PDb' adjacent to the initial first-1 connection line 321a' toward the initial first-1 connection line 321a', such that the thickness of the initial circuit pad PDb' can be reduced by the diffusion bonding process, and the circuit pad PDb can be disposed inside the passivation film PDc. However, this disclosure is not limited thereto.

[0237] In other words, referencing Figure 14A and 14B The groove can be formed in the first-1 connection line 321a by reducing the thickness of the initial first-1 connection line 321a' through the diffusion bonding process. Similarly, the thickness of the circuit pad PDb' is reduced by the diffusion bonding process, and the circuit pad PDb is disposed inside the passivation film PDc, such that a groove exposing the circuit pad PDb can be formed from the angle of the passivation film PDc.

[0238] Therefore, the bonding pattern BP can be formed between the groove of the first-1 connection line 321a and the groove of the passivation film PDb. Thus, the bonding pattern BP can be disposed in the groove of the first-1 connection line 321a and the passivation film PDb, between the first-1 connection line 321a and the circuit pad PDb, and simultaneously adjacent to both the first-1 connection line 321a and the circuit pad PDb. Therefore, the bonding pattern BP can simultaneously fix and electrically connect the first-1 connection line 321a and the circuit pad PDb.

[0239] Therefore, after diffusion bonding, the first-1 connection line 321a and the circuit pad PDb can be spaced apart from each other based on the bonding pattern BP. However, this disclosure is not limited thereto.

[0240] The thickness of the bonding pattern BP can be determined based on the thickness of the initial first-1 connection line 321a' and the initial circuit pad PDb'. However, this disclosure is not limited thereto.

[0241] For example, the bonding pattern BP can be made of an intermetallic compound. For example, the bonding pattern BP can be made of an intermetallic compound of the material constituting the plurality of first-1 connection lines 321a and the material constituting the plurality of circuit pads PDb of the pixel driving circuit PD. For example, if the first-1 connection lines 321a are made of aluminum (Al) and the circuit pads PDb are made of titanium (Ti), the bonding pattern BP can be made of titanium aluminide (TiAl3). However, this disclosure is not limited thereto.

[0242] In another embodiment of the display device 3000 according to the present disclosure, a pixel driving circuit PD is disposed on the first-1 connection line 321a and bonded without a separate bonding layer, so that the pixel driving circuit PD and the first-1 connection line 321a can be electrically connected, and the pixel driving circuit PD can be fixed. Specifically, the pixel driving circuit PD can be configured such that the circuit pad PDb is directed downwards, so that the pixel driving circuit PD can be disposed on the first-1 connection line 321a disposed below the pixel driving circuit PD. For example, when the circuit pad PDb disposed on the bottom surface of the body PDA of the pixel driving circuit PD is disposed on the same plane as the passivation film PDc, i.e., parallel to the passivation film PDc, the circuit pad PDb is disposed on the first-1 connection line 321a, so that the pixel driving circuit PD can be electrically connected to the first-1 connection line 321a while being transferred to the first-1 connection line 321a. In this case, the circuit pad PDb and the first-1 connection line 321a can be bonded by diffusion bonding. Therefore, the first connecting line 321a and the passivation film PDc can have grooves formed corresponding to each other, and the first connecting line 321a and the passivation film PDc can be joined by means of the joining pattern BP formed between the grooves, so that the fixing force generated by diffusion joining can be ensured.

[0243] In other words, in the display device 3000 according to another embodiment of the present disclosure, the pixel driving circuit PD can be effectively fixed to the substrate 110 without a separate bonding layer, and the bonding layer may not be required, which can reduce process time and cost. Furthermore, since the bonding layer is not required, defects caused by unwanted foreign matter adhering to the bonding layer can be suppressed. Therefore, since the process of removing foreign matter may also be omitted, process time and cost can be reduced more effectively.

[0244] Furthermore, in another embodiment of the display device 3000 according to this disclosure, the layered structure can be further simplified by omitting the bonding layer. Therefore, a thin display device can be realized, and various constituent elements can be stacked to minimize the problem of flatness degradation of the upper portion of the substrate 110, thereby ensuring the flatness of the display device 3000.

[0245] Furthermore, since the pixel driving circuit PD is disposed on the first-1 connection line 321a made of metal material, the first-1 connection line 321a can be used as an alignment key. Therefore, since the process of separately forming an alignment key made of metal material to align the position of the pixel driving circuit PD can be eliminated, process time and cost can be reduced.

[0246] Furthermore, in another embodiment of the display device 3000 according to this disclosure, the first-1 connection line 321a and the first-2 connection line 121b can be spaced apart from each other based on the pixel driving circuit PD and the protective layer 112 surrounding the pixel driving circuit PD. That is, since the first-2 connection line 121b is disposed on the protective layer 112, which is essentially configured to planarize the pixel driving circuit PD and its surrounding area, it is not necessary to provide a separate additional protective layer or insulating layer between the first-1 connection line 321a and the first-2 connection line 121b. Therefore, the process cost and time that might be caused by the arrangement of additional protective or insulating layers can be reduced. Furthermore, by omitting additional protective or insulating layers, the layered structure can be minimized, enabling a thin display device and ensuring the flatness of the upper portion of the substrate 110.

[0247] Figures 15 to 18 This is a view of a display device that illustrates an embodiment of the present disclosure.

[0248] Reference Figures 15 to 18 The display devices 1000, 2000, and 3000 according to exemplary embodiments of this disclosure may be included in various devices or electronic devices. For example, refer to Figures 15 to 18 Various electronic devices may include wearable devices 1100, mobile devices 1200, laptop computers 1300, and monitors or TVs 1400, but exemplary embodiments of this disclosure are not limited thereto.

[0249] Each of the wearable device 1100, mobile device 1200, laptop computer 1300, and monitor or TV 1400 may include housing portions 1005, 1010, 1015, and 1020, and Figures 1 to 1 The display panel 100 and display devices 1000, 2000 and 3000 according to exemplary embodiments of the present disclosure described in section 4.

[0250] For example, the display device according to the exemplary embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbooks, workstations, navigation systems, vehicle display devices, theater display devices, televisions, wallpaper devices, signage devices, game consoles, laptops, monitors, camera devices, video cameras, home appliances, etc.

[0251] Exemplary implementations of this disclosure can also be described as follows:

[0252] According to one aspect of this disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area configured to surround the display area; a buffer layer disposed on the substrate; a plurality of first-1 connection lines disposed on the buffer layer in the display area; a pixel driving circuit disposed on the plurality of first-1 connection lines and including a body, a plurality of circuit pads disposed on a bottom surface of the body, and a passivation film disposed around the body and the plurality of circuit pads; a plurality of bonding patterns configured to connect the plurality of first-1 connection lines and the plurality of circuit pads; a dam disposed on the pixel driving circuit; and a plurality of micro-LEDs disposed on the dam and electrically connected to the pixel driving circuit.

[0253] Multiple first-1 connection lines may include grooves, and multiple circuit pads may protrude more than the passivation film and may be respectively disposed in the grooves of the multiple first-1 connection lines.

[0254] Multiple bonding patterns can be set in the grooves of multiple first-1 connecting lines between multiple first-1 connecting lines and multiple circuit pads.

[0255] The passivation film may include grooves configured to expose a plurality of circuit pads, and the plurality of first-1 connection lines may include protrusions disposed in the grooves of the passivation film.

[0256] Multiple bonding patterns can be set in the grooves of the passivation film between multiple first-1 connection lines and multiple circuit pads.

[0257] The plurality of first-1 connection lines may include grooves, the passivation film may include grooves configured to expose a plurality of circuit pads, and the grooves of the plurality of first-1 connection lines may be configured to correspond to the grooves of the passivation film.

[0258] Multiple bonding patterns can be set between multiple first-first connection lines and multiple circuit pads in the grooves of multiple first-first connection lines and the grooves of passivation film.

[0259] Multiple first-1 connection lines and multiple circuit pads can be electrically connected via diffusion bonding.

[0260] Multiple bonding patterns can be formed by diffusion bonding between multiple first-1 connection lines and multiple circuit pads.

[0261] Multiple bonding patterns can be made of intermetallic compounds of materials constituting multiple first-1 connection lines and materials constituting multiple circuit pads.

[0262] Multiple first-to-first connection lines can be made of aluminum (Al), multiple circuit pads can be made of titanium (Ti), and multiple bonding patterns can be made of titanium aluminide (TiAl3).

[0263] The display device may further include: a protective layer disposed around the pixel driving circuitry; and a plurality of first-second connecting lines disposed on the protective layer. The plurality of first-second connecting lines may be connected to a plurality of first-first connecting lines through contact holes in the protective layer.

[0264] The non-display area may include: a first non-display area configured to surround the display area; a curved area extending from the first non-display area; and a second non-display area extending from the curved area. The display device may also include a second connecting line disposed on a substrate, disposed in the display area, the first non-display area, the curved area, and the second non-display area, and electrically connected to a pixel driving circuit. The second connecting line may partially abut a buffer layer in the display area, the first non-display area, and the second non-display area, and may abut a substrate in the curved area.

[0265] Each of the multiple micro LEDs may include: an anode electrode; a first semiconductor layer disposed on the anode electrode; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a cathode electrode disposed on the second semiconductor layer.

[0266] The display device may further include: a first electrode disposed below a plurality of microLEDs and configured to electrically connect a pixel driving circuit and an anode electrode of each of the plurality of microLEDs; and a welding pattern disposed between the first electrode and the anode electrode. The first electrode and the anode electrode may be electrically connected via eutectic bonding using the welding pattern.

[0267] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area configured to surround the display area; A buffer layer disposed on the substrate; A plurality of first-1 connection lines are disposed on the buffer layer in the display area; A pixel driving circuit is disposed on the plurality of first-1 connection lines and includes a main body, a plurality of circuit pads disposed on the bottom surface of the main body, and a passivation film disposed around the main body and the plurality of circuit pads. Multiple bonding patterns are configured to connect the multiple first-1 connection lines and the multiple circuit pads; A dike is provided on the pixel driving circuit; as well as Multiple micro-LEDs are disposed on the embankment and electrically connected to the pixel driving circuit.

2. The display device according to claim 1, wherein, The plurality of first-1 connection lines include grooves, and the plurality of circuit pads protrude more than the passivation film and are respectively disposed in the grooves of the plurality of first-1 connection lines.

3. The display device according to claim 2, wherein, The plurality of bonding patterns are disposed in the grooves of the plurality of first-1 connecting lines between the plurality of first-1 connecting lines and the plurality of circuit pads.

4. The display device according to claim 1, wherein, The passivation film includes grooves configured to expose the plurality of circuit pads, and the plurality of first-1 connection lines include protrusions disposed in the grooves of the passivation film.

5. The display device according to claim 4, wherein, The plurality of bonding patterns are disposed in the grooves of the passivation film between the plurality of first-1 connecting lines and the plurality of circuit pads.

6. The display device according to claim 1, wherein, The plurality of first-1 connection lines include grooves, the passivation film includes grooves configured to expose the plurality of circuit pads, and the grooves of the plurality of first-1 connection lines are configured to correspond to the grooves of the passivation film.

7. The display device according to claim 6, wherein, The plurality of bonding patterns are disposed in the grooves of the plurality of first-1 connecting lines and the grooves of the passivation film between the plurality of first-1 connecting lines and the plurality of circuit pads.

8. The display device according to claim 1, wherein, The plurality of first-1 connection lines and the plurality of circuit pads are electrically connected by diffusion bonding.

9. The display device according to claim 1, wherein, The plurality of bonding patterns are formed by diffusion bonding between the plurality of first-1 connection lines and the plurality of circuit pads.

10. The display device according to claim 1, wherein, The plurality of bonding patterns are made of an intermetallic compound of the materials constituting the plurality of first-1 connecting lines and the materials constituting the plurality of circuit pads.

11. The display device according to claim 10, wherein, The plurality of first-1 connecting lines are made of aluminum (Al), the plurality of circuit pads are made of titanium (Ti), and the plurality of bonding patterns are made of titanium aluminide (TiAl3).

12. The display device according to claim 1, further comprising: Configured as a protective layer surrounding the pixel driving circuit; as well as Multiple first-second connecting lines are disposed on the protective layer. The plurality of first-2 connecting lines are connected to the plurality of first-1 connecting lines through the contact holes of the protective layer.

13. The display device according to claim 1, wherein, The non-display area includes: Set as a first non-display area surrounding the display area; The curved region extending from the first non-display area; and A second non-display area extending from the curved region The display device further includes a second connecting line, which is disposed on the substrate, in the display area, the first non-display area, the curved area, and the second non-display area, and is electrically connected to the pixel driving circuit. The second connecting line is partially adjacent to the buffer layer in the display area, the first non-display area, and the second non-display area, and is adjacent to the substrate in the curved area.

14. The display device according to claim 1, wherein, Each of the plurality of micro-LEDs includes: Anode electrode; A first semiconductor layer disposed on the anode electrode; An active layer disposed on the first semiconductor layer; A second semiconductor layer disposed on the active layer; and A cathode electrode disposed on the second semiconductor layer.

15. The display device according to claim 14, further comprising: A first electrode is disposed below the plurality of microLEDs and configured to electrically connect the pixel driving circuit and the anode electrode of each of the plurality of microLEDs; as well as A welding pattern disposed between the first electrode and the anode electrode. The first electrode and the anode electrode are electrically connected via eutectic bonding using the welding pattern.

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