Light-emitting display device

Abstract

Disclosed is a light-emitting display device configured such that oxidation of an edge portion of a display area due to moisture and oxygen is prevented by changing an edge structure of the display area, and shrinkage of a light-emitting layer of a light-emitting diode is prevented, this improves the characteristics of the light-emitting display device that are susceptible to moisture and oxygen. The light emitting display device includes: a substrate having a display area and a non-display area disposed at an edge of the display area and surrounding the display area, the display area including a central area and a peripheral area other than the central area, and the peripheral area and the non-display area of the display area being divided together into a corner area and a side area; a voltage line disposed in the non-display area on the substrate; a bank having light emitting openings provided in each pixel of the display area and bank openings provided on the voltage lines; and an electron injection layer disposed in the light emitting opening portion and the bank opening portion, in which the electron injection layer is disposed to have different thicknesses in a center region and a corner region of the display region.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0109164, filed on August 14, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a light-emitting display device configured such that oxidation of the edge portion of the display area due to moisture and oxygen is prevented by changing the edge structure of the display area, thereby improving the reliability of the light-emitting display device. Background Technology

[0003] In recent years, self-emissive display devices have been considered a highly competitive application, aiming to achieve miniaturization and vibrant color display without the need for a separate light source.

[0004] Self-emissive display devices include light-emitting diodes (LEDs) that are driven independently for each sub-pixel. Based on the material of the LED, LEDs can be classified into organic LEDs and inorganic LEDs.

[0005] Meanwhile, display devices with organic light-emitting diodes have the following problems: the internal organic layer is susceptible to moisture and other factors, which reduces reliability due to moisture penetration, or the light-emitting layer of the light-emitting diode shrinks due to UV irradiation. Summary of the Invention

[0006] Therefore, this disclosure relates to a light-emitting display device that substantially eliminates more than one problem caused by the limitations and disadvantages of the prior art.

[0007] The purpose of this disclosure is to provide a light-emitting display device configured to prevent oxidation of the edge portion of the display area due to moisture and oxygen by changing the edge structure of the display area, and to prevent shrinkage of the light-emitting layer of the light-emitting diode, thereby improving the characteristics of the light-emitting display device that are susceptible to moisture and oxygen.

[0008] The light-emitting display device according to this disclosure is configured such that the structure of the electron injection layer (EIL) is changed in the corner and side regions of the display panel, thereby preventing the corner and side regions from oxidizing due to moisture and oxygen and preventing the light-emitting diodes from shrinking.

[0009] The light-emitting display device according to this disclosure includes: a substrate having a display area and a non-display area disposed at the edge of the display area and surrounding the display area; the display area including a central area and a peripheral area other than the central area, and the peripheral area and the non-display area together being divided into a corner area and a side area; voltage lines disposed on the substrate in the non-display area; a dam having light-emitting openings disposed in each pixel of the display area and dam openings disposed on the voltage lines; and an electron injection layer disposed in the light-emitting openings and dam openings, wherein the electron injection layer is configured to have different thicknesses in the central area and the corner area of ​​the display area. Attached Figure Description

[0010] This disclosure includes accompanying drawings to provide a further understanding of the disclosure, and the drawings are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0011] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0012] Figure 2 This is a circuit diagram illustrating a pixel circuit in a display device according to an embodiment of the present disclosure;

[0013] Figure 3 It is a plan view of the display panel in the light-emitting display device according to the present disclosure;

[0014] Figure 4 It is along Figure 3 A sectional view taken by line I-I';

[0015] Figure 5A and Figure 5B They are shown respectively Figure 4 Sectional views of parts A and B; and

[0016] Figures 6A to 6C This is a comparative graph showing the UV transmittance, UV reflectance, and UV absorptance of ytterbium (Yb), silver (Ag), and magnesium (Mg), which can be used as materials for the electron injection layer (EIL) according to this disclosure. Detailed Implementation

[0017] In the following description, preferred embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. Throughout the specification, the same reference numerals denote substantially the same parts.

[0018] In the following description, detailed descriptions of known technologies and configurations included herein will be omitted where such descriptions might make the subject matter of this disclosure rather unclear. Furthermore, the names of components used in the following description are chosen for ease of preparation of the instruction manual and may differ from the names of components in the actual product.

[0019] In the accompanying drawings used to explain various embodiments of this disclosure, shapes, dimensions, scales, angles, and quantities are shown by way of example and therefore do not limit the disclosure. Throughout the specification, the same reference numerals denote the same parts.

[0020] Furthermore, in describing the specification, detailed descriptions of known technologies will be omitted where such descriptions may make the subject matter of this disclosure quite unclear.

[0021] The terms “comprising,” “including,” and / or “having” as used in this specification do not exclude the presence or addition of other elements unless used with the term “only.” The singular forms are also intended to include the plural forms unless the context clearly indicates otherwise.

[0022] In the explanation of the components included in the various embodiments of this disclosure, even if not explicitly described, the components are to be interpreted as including a range of error.

[0023] When describing positional relationships in various embodiments of this disclosure, for example, when using terms such as “above,” “over,” “below,” “near,” etc. to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless the terms “directly” or “closely” are used with them.

[0024] When describing the temporal relationships in various embodiments of this disclosure, for example, when using terms such as “after,” “following,” “next,” “before” to describe the temporal relationship between two actions, the actions may not occur sequentially unless the terms “immediately” or “directly” are used with them.

[0025] In describing various embodiments of this disclosure, for example, although terms such as “first” and “second” may be used to describe various components, these terms are only used to distinguish identical or similar components from one another. Therefore, in this specification, unless otherwise stated, a component modified by “first” may be the same as a component modified by “second” within the scope of this disclosure.

[0026] The corresponding features of the various embodiments of this disclosure can be combined and integrated with each other, either partially or completely, and various technical associations and methods of operation therebetween are possible. The various embodiments can be performed independently of each other or can be performed in conjunction with each other.

[0027] In the following description, an embodiment of the light-emitting display device of the present disclosure will be described with reference to the accompanying drawings.

[0028] Figure 1 This is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure.

[0029] Figure 2 This is a circuit diagram illustrating a pixel circuit in a display device according to an embodiment of the present disclosure.

[0030] like Figure 1 As shown, a display device 10 according to an embodiment of the present disclosure includes: a display panel 100, the display panel 100 including a plurality of pixels P; a controller 200; a gate driving circuit 300 configured to supply a gate signal to each of the plurality of pixels P; a data driving circuit 400 configured to supply a data signal to each of the plurality of pixels P; a power supply unit 500 configured to supply power for operation to each of the plurality of pixels P; and a level shifter 600 configured to adjust the potential of the gate signal applied to the gate driving circuit 300. Here, the controller 200, the gate driving circuit 300, and the data driving circuit 400 can be collectively referred to as a control unit.

[0031] The display panel 100 may include: a display area AA (see...) Figure 3 Pixel P is located in the display area AA; the gate driving circuit 300 and the data driving circuit 400 are disposed in the non-display area NA, and the non-display area is configured to surround the display area AA. The gate driving circuit 300 may also be disposed in the display area AA.

[0032] In the display panel 100, multiple gate lines (not shown) and multiple data lines DL intersect each other, and each of the multiple pixels P is connected to a corresponding gate line and a corresponding data line DL. Specifically, a pixel P receives a gate signal from the gate driving circuit 300 via the gate line, receives a data signal from the data driving circuit 400 via the data line DL, and receives a high-potential driving voltage EVDD and a low-potential driving voltage EVSS from the power supply unit 500 via the driving voltage line PL.

[0033] Here, the gate line supplies the scan signal SC and the light emission control signal EM, and the data line DL supplies the data voltage Vdata. Furthermore, according to various embodiments, the gate line may include multiple scan lines SCL configured to supply the scan signal SC and multiple light emission control lines EMLL configured to supply the light emission control signal EM. Additionally, each of the plurality of pixels P may also include a power supply line VL for receiving a reference voltage Vref and an initialization voltage Vini.

[0034] Each thin-film transistor (TFT) constituting pixel P can be implemented as an oxide TFT including an oxide semiconductor layer. Considering electron mobility, process variations, etc., oxide TFTs may be advantageous for large-area display panels 100. This disclosure is not limited thereto, and the semiconductor layer of the TFT can be made of amorphous silicon or polycrystalline silicon.

[0035] Furthermore, each pixel P includes a light-emitting diode (OLED) and pixel circuitry configured to control the operation of the OLED. Here, the OLED may include an anode, a cathode, and a light-emitting layer (EML) disposed between the anode and cathode.

[0036] like Figure 2 As shown, each pixel P may include a switching transistor ST, a driving transistor DT, a compensation circuit CC, a light-emitting diode OLED, and a storage capacitor Cst.

[0037] An OLED can operate by emitting light based on the driving current generated by the driving transistor DT.

[0038] The switching transistor ST can be switched so that, in response to the scan signal SCAN supplied through the gate line, the data signal supplied through the data line DL is stored as a data voltage in the storage capacitor Cst. The storage capacitor can hold the data voltage for one frame.

[0039] The driving transistor DT can operate such that, in response to the data voltage stored in the storage capacitor Cst, a constant driving current flows between the line supplying the high-potential driving voltage EVDD and the line supplying the low-potential driving voltage EVSS.

[0040] The compensation circuit CC is a circuit configured to compensate the threshold voltage of the driving transistor DT, and the compensation circuit CC may include a capacitor and one or more thin-film transistors. The configuration of the compensation circuit CC can vary greatly depending on the compensation method.

[0041] For example, Figure 2 The pixel P shown has a 2T (transistor) 1C (capacitor) structure including a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and a light-emitting diode OLED. However, if a compensation circuit CC is added, the pixel can have various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and 8T1C.

[0042] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, in which an image is displayed on the screen while real objects in the background are visible. The display panel 100 can be manufactured as a flexible display panel. A flexible display panel can be implemented as an organic light-emitting display panel using a plastic substrate.

[0043] Each pixel P can be divided into red, green, and blue sub-pixels to represent color. Each pixel P may also include a white sub-pixel. Each pixel P includes pixel circuitry.

[0044] A touch sensor may be provided on the display panel 100. Touch input can be sensed using a separate touch sensor or through a pixel P. The touch sensor may be implemented as an on-cell or additional touch sensor located on the display panel, or as an in-cell touch sensor embedded in the display panel 100.

[0045] The controller 200 processes externally input RGB image data into a format corresponding to the size and resolution of the display panel 100, and supplies it to the data driving circuit 400. The controller 200 uses externally input timing signals CS (such as dot clock signal CLK, data enable signal DE, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) to generate a gate control signal GCS and a data control signal DCS. The generated gate control signal GCS and data control signal DCS are supplied to the gate driving circuit 300 and the data driving circuit 400, respectively, to control the gate driving circuit 300 and the data driving circuit 400.

[0046] Depending on the device in which the controller is installed, the controller 200 can be integrated with various processors such as microprocessors, mobile processors, and application processors.

[0047] The host system can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system.

[0048] The controller 200 can control the operating timing of the display panel driving unit using a frame frequency obtained by multiplying the input frame frequency by i times (where i is a positive integer greater than 0) by i Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) method and 50 Hz in the Phase Inverting Line (PAL) method.

[0049] Controller 200 generates signals to drive pixel P at various refresh rates. That is, controller 200 generates driving-related signals that allow pixel P to be driven in a variable refresh rate (VRR) mode or to switch between a first refresh rate and a second refresh rate. For example, controller 200 can drive pixel P at various refresh rates by simply changing the speed of the clock signal, generating a synchronization signal to create horizontal or vertical blanking, or driving the gate drive circuit 300 in a masked manner.

[0050] Based on the timing signal CS received from the host system, the controller 200 generates a gate control signal GCS for controlling the operating timing of the gate drive circuit 300 and a data control signal DCS for controlling the operating timing of the data drive circuit 400. The controller 200 controls the operating timing of the display panel drive unit to synchronize the gate drive circuit 300 with the data drive circuit 400.

[0051] The data driving circuit 400 receives image data DATA and a data control signal DCS from the controller 200. In response to the data control signal DCS from the controller 200, the data driving circuit 400 converts the image data DATA into a gamma-compensated voltage to generate a data voltage Vdata, and supplies the data voltage Vdata to the data line DL of the display panel 100 synchronously with the scan signal SC. The data driving circuit 400 can be connected to the data line of the display panel 100 via a chip-on-glass (COG) or tape-on-board (TAB) process.

[0052] The gate drive circuit 300 operates according to the gate control signal GCS input from the level shifter 600 to generate a gate signal and sequentially supplies the gate signal to the gate line GL. The gate drive circuit 300 can be directly formed on the lower substrate of the display panel 100 using an in-panel gate driver (GIP) method. The gate drive circuit 300 can be formed in the display area AA of the display panel 100 where the image is displayed, or it can be formed in a non-display area NA outside the display area AA. The non-display area NA can include a border area, or it can be the same as the border area. In the GIP method, the level shifter 600 can be mounted on a printed circuit board (PCB) together with the controller 200.

[0053] The power supply unit 500 uses a DC-DC converter to generate the DC power required to drive the pixel array and display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter. The power supply unit 500 receives a DC input voltage from a host system (not shown) to generate DC voltages such as gate on-state voltages VGL and VEL, gate off-state voltages VGH and VEH, high-level drive voltage EVDD, and low-level drive voltage EVSS. The gate on-state voltages VGL and VEL, and the gate off-state voltages VGH and VEH, are supplied to the level shifter and gate drive circuit 300. The high-level drive voltage EVDD and the low-level drive voltage EVSS are jointly supplied to the pixel P.

[0054] The level shifter 600 raises the transistor-transistor-logic (TTL) level voltage of the gate control signal GCS input from the controller 200 to a gate high voltage VGH and gate low voltage VGL capable of driving the TFTs formed on the display panel 100, and supplies them to the gate drive circuit 300. The gate control signal GCS may include a start signal and a clock signal. The plurality of pixels P of the display panel 100 may include at least a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel may emit light of different colors. For example, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel.

[0055] Multiple pixels P can have the same size or different sizes. Considering the lifespan or color balance of the light-emitting diodes (OLEDs) included in each of the first, second, and third sub-pixels, the first, second, and third sub-pixels can be designed to have different sizes.

[0056] Figure 3 This is a plan view of the display panel in the light-emitting display device according to the present disclosure. Figure 4 It is along Figure 3 A sectional view taken from line I-I'.

[0057] like Figure 3 As shown, in the light-emitting display device according to the present disclosure, the display panel 100 includes a display area AA configured to display an image and a non-display area NA disposed at the edge of the display panel and surrounding the display area AA.

[0058] The display area AA can be divided into the central area AA(C) and the peripheral area. The peripheral area and non-display area NA of the display area AA can be divided into four corner areas C1 to C4 and four side areas S1 to S4.

[0059] In the display area AA, multiple pixels are arranged in a matrix, and light-emitting diodes (OLEDs) and driving circuits configured to drive the OLEDs are arranged at each pixel.

[0060] Each pixel may include a switching transistor ST, a driving transistor DT, a compensation circuit CC, a light-emitting diode OLED, and a storage capacitor Cst, such as Figure 2 As shown.

[0061] like Figure 4 As shown, the cross-sectional structure of the display panel according to the embodiments of this disclosure can be mainly divided into a substrate 101, a thin-film transistor array substrate 501, and a light-emitting diode (OLED). The thin-film transistor array substrate 501 may include thin-film transistors configured to drive the OLED, various signal lines, and power lines.

[0062] First, the configuration of the thin-film transistor array substrate 501 will be described.

[0063] A thin-film transistor (TFT) can be disposed on a substrate 101 in a display area AA. The substrate 101 is divided into a display area AA and a non-display area NA. The TFT includes a gate 102 disposed on the substrate 101, a gate insulating film 103 disposed on the entire surface of the substrate including the gate 102, a semiconductor layer 104 disposed on the gate insulating film 103 and overlapping the gate 102, and a source electrode 106a and a drain electrode 106b connected to both sides of the semiconductor layer 104.

[0064] A gate insulating film 103 is disposed between the gate 102 and the semiconductor layer 104, and a channel protection layer 105 is disposed above the channel of the semiconductor layer 104 to protect the channel of the semiconductor layer 104 when the source 106a and the drain 106b are connected to the semiconductor layer 104.

[0065] Depending on the circumstances, semiconductor layer 104 may include at least one of oxide semiconductor layer, polycrystalline silicon layer, and amorphous silicon layer, and may be formed having two or more layers containing the same or different materials.

[0066] The gate 102 may be made of a metallic material. For example, the gate 102 may have a single-layer or multi-layer structure comprising any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy of the above materials; however, this disclosure is not limited thereto.

[0067] Signal line 102a and first power supply voltage line 106c can be disposed on substrate 101 in non-display area NA. Signal line 102a can be a gate line (scan signal line) configured to provide a scan signal to a corresponding pixel, and first power supply voltage line 106c can be a power supply line configured to supply a common voltage to the cathode of the light-emitting diode OLED.

[0068] Signal line 102a can be disposed on substrate 101 and covered by gate insulating film 103, and first power supply voltage line 106c can be disposed on gate insulating film 103. Signal line 102a can be made of the same material as gate 102, and first power supply voltage line 106c can be made of the same material as source 106a and drain 106b.

[0069] The first planarization layer 107 and the second planarization layer 108 can be disposed in the display area AA and the non-display area NA to cover the thin film transistor, the signal line 102a and the first power supply voltage line 106c.

[0070] A first contact hole CT1 may be formed in the first planarization layer 107 to expose the source 106a of the thin film transistor, and a first connecting metal pattern 109 may be provided between the first planarization layer 107 and the second planarization layer 108 to be electrically connected to the source 106a via the first contact hole CT1.

[0071] Furthermore, a third contact hole CT3 may be formed in the first planarization layer 107 to expose the first power supply voltage line 106c in the non-display area NA. A second connecting metal pattern 109c may be disposed between the first planarization layer 107 and the second planarization layer 108 to be electrically connected to the first power supply voltage line 106c via the third contact hole CT3. The first connecting metal pattern 109 and the second connecting metal pattern 109c may be made of the same material and may be disposed on the same layer.

[0072] Next, the configuration of the light-emitting diode (OLED) will be described.

[0073] A second contact hole CT2 may be formed in the second planarization layer 108 to expose the first connection metal pattern 109. The anode 110 of the light-emitting diode OLED may be disposed on the second planarization layer 108 to be electrically connected to the first connection metal pattern 109 via the second contact hole CT2.

[0074] Furthermore, a fourth contact hole CT4 may be formed in the second planarization layer 108, exposing the second connection metal pattern 109c in the non-display area NA. A connection pattern 110a and an anode dummy pattern 110b may be provided on the second planarization layer 108 to be electrically connected to the second connection metal pattern 109c via the fourth contact hole CT4.

[0075] The connection pattern 110a, anode 110, and anode dummy pattern 110b can be made of the same material and formed using the same process. The connection pattern 110a can be configured for electrical connection to the first power supply voltage line 106c, and the anode dummy pattern 110b can be a pattern for inspecting the area surrounding the display area AA, or it can be configured for connection to other signals. In some cases, the second connection metal pattern 109c can be omitted, allowing the connection pattern 110a to be directly connected to the first power supply voltage line 106c.

[0076] The dam 120 can be disposed on a second planarization layer 108 on which the connecting pattern 110a, the anode 110 and the anode dummy pattern 110b are disposed.

[0077] The dam 120 may have a dam opening BO and a light-emitting opening EMP. The dam opening BO is configured to expose the connection pattern 110a disposed in the non-display area NA along the edge of the display area AA of the substrate 101. The light-emitting opening EMP is configured to expose the anode 110 of each pixel in the display area AA.

[0078] The first organic light-emitting layer 130 can be located in the light-emitting opening EMP and disposed on the anode 110, and the second organic light-emitting layer 130a can be located in the dam opening BO and disposed on the connecting pattern 110a. The stacking structure of the first organic light-emitting layer 130 located in the light-emitting opening EMP and disposed on the anode 110 and the second organic light-emitting layer 130a located in the dam opening BO and disposed on the connecting pattern 110a can be different. (Referring later...) Figure 5A and Figure 5B Describe the structure in more detail.

[0079] The cathode 201 can be disposed on the entire surface of the substrate on which the dam 120 and the first organic light-emitting layer 130 and the second organic light-emitting layer 130a are formed. In the display area AA, with the first organic light-emitting layer 130 between the cathode 201 and the anode 110, the cathode 201 overlaps with the anode 110, and the cathode 201 is electrically connected to the connection pattern 110a in the non-display area NA.

[0080] An encapsulation layer 301 is formed on the cathode 201, and the encapsulation layer 301 is configured to protect the light-emitting diode (OLED). As an example, the encapsulation layer 301 can be configured such that inorganic encapsulation layers 310 and 330 and organic encapsulation layer 320 are alternately disposed. Compared to the organic encapsulation layer 320, the inorganic encapsulation layers 310 and 330 can be formed adjacent to or extend to the edge of the substrate 101 to more effectively prevent moisture from penetrating from the sides.

[0081] Figure 5A and Figure 5B They are shown respectively Figure 4 Sectional views of parts A and B.

[0082] like Figure 5A As shown, the light-emitting diode (OLED) disposed in the display area includes a first organic light-emitting layer 130 located between an anode 110 and a cathode 201 opposite to each other. The first organic light-emitting layer 130 may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL stacked sequentially on the anode 110. The electron injection layer EIL may be relatively thin.

[0083] The second organic light-emitting layer 130a disposed on the connection pattern 110a in the embankment opening BO in the non-display area NA may include a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0084] However, as Figure 5B As shown, the second organic light-emitting layer 130a may consist only of the electron injection layer EIL to reduce the contact resistance between the connection pattern 110a and the cathode 201.

[0085] In reference Figure 4 In the described light-emitting display panel, when the dam opening BO and the light-emitting opening EMP are formed in the dam 120, moisture may be retained in the dam opening BO and the light-emitting opening EMP, and may permeate through the dam 120.

[0086] Furthermore, when the encapsulation layer 301 is formed after the first organic light-emitting layer 130 or the second organic light-emitting layer 130a is formed in the dam opening BO or the light-emitting opening EMP, the first organic light-emitting layer 130 or the second organic light-emitting layer 130a may degas due to the reaction of the p-type dopant in the hole injection layer HIL or the hole transport layer HTL under UV irradiation, which may cause the light-emitting diode OLED to shrink. Therefore, the characteristics of the light-emitting diode OLED may change.

[0087] However, since the electron injection layer EIL is provided in the dike opening BO and the light-emitting opening EMP, it can prevent the phenomenon that some moisture remains in the dike opening BO and the light-emitting opening EMP due to moisture from the outside or during cooling, and that this moisture permeates through the dike 120.

[0088] Furthermore, since the electron injection layer EIL is disposed in the dam opening BO and the light emission opening EMP, the light-emitting diode OLED can be prevented from shrinking due to exposure to external light (UV) or heat.

[0089] This is due to the following reasons.

[0090] The electron injection layer (EIL) is a component comprising inorganic substances or inorganic compounds and metals. For example, the EIL may contain at least one of lithium fluoride (LiF), ytterbium (Yb), silver (Ag), and magnesium (Mg), and may also include some components of the cathode 201. Simultaneously, the primary function of the EIL is to facilitate the injection of electrons from the cathode 201 into the first organic light-emitting layer 130 of the light-emitting diode (OLED). For this purpose, the EIL may contain a metal with low interfacial resistance and low work function compared to the first organic light-emitting layer 130.

[0091] Furthermore, the electron injection layer (EIL) can be formed without being too thick, so that the electrical connection resistance between the cathode 201 and the connection pattern 110a disposed below it will not increase.

[0092] For example, as shown in [Equation 1], if the electron injection layer EIL contains lithium fluoride (LiF) and moisture enters the dike opening BO or the light-emitting opening EMP, then lithium (Li) and fluorine (F) can be separated from each other, lithium (Li) and hydroxide can react with each other, and hydrogen fluoride (HF) can be released to the outside, thereby preventing the influence of moisture.

[0093] [Formula 1]

[0094] LiF + H₂O → LiOH + HF

[0095] Furthermore, if the electron injection layer EIL contains ytterbium (Yb), it can block UV irradiation of the first organic light-emitting layer 130 or the second organic light-emitting layer 130a, thereby preventing the light-emitting diode OLED from shrinking.

[0096] Figures 6A to 6C This is a comparative graph showing the UV transmittance, UV reflectance, and UV absorptance of ytterbium (Yb), silver (Ag), and magnesium (Mg), which can be used as materials for the electron injection layer (EIL) according to this disclosure.

[0097] In other words, Figure 6A This is a comparative graph showing the transmittance of ytterbium (Yb), silver (Ag), and magnesium (Mg). Figure 6B This is a comparative graph showing the reflectance of ytterbium (Yb), silver (Ag), and magnesium (Mg). Figure 6C This is a comparative graph showing the absorption rates of ytterbium (Yb), silver (Ag), and magnesium (Mg). Figures 6A to 6C In the figure, the thicknesses of ytterbium (Yb), silver (Ag), and magnesium (Mg) are all the same.

[0098] from Figure 6A It can be seen that magnesium (Mg) has the highest transmittance, followed by ytterbium (Yb) and silver (Ag).

[0099] from Figure 6B It can be seen that silver (Ag) has the highest reflectivity, followed by ytterbium (Yb) and magnesium (Mg).

[0100] In addition, from Figure 6C It can be seen that ytterbium (Yb) has the highest absorption rate, followed by silver (Ag) and magnesium (Mg).

[0101] As described above, since ytterbium (Yb) has the highest UV absorption rate, even if UV radiation is radiated to the first organic light-emitting layer 130 or the second organic light-emitting layer 130a when the encapsulation layer 301 is formed, if the electron injection layer EIL contains ytterbium (Yb), then when the encapsulation layer 301 is formed, UV radiation to the first organic light-emitting layer 130 or the second organic light-emitting layer 130a can be blocked.

[0102] At the same time, as referenced Figure 3 As described, the light-emitting display panel 100 according to this disclosure can be divided into a display area AA and a non-display area NA disposed at the edge of the light-emitting display device and surrounding the display area AA. The display area AA can be divided into a central area AA(C) and a peripheral area, and the peripheral area of ​​the display area AA and the non-display area NA can be divided into four corner areas C1 to C4 and four side areas S1 to S4.

[0103] Here, the four corner regions C1 to C4 are most likely to be wetted because the exposed portions of the four corner regions are the largest. In addition, the exposed portions of the four side regions S1 to S4 are smaller than those of the four corner regions C1 to C4. As a result, the four side regions are exposed to external light (UV) or heat rather than being wetted, and therefore the light-emitting diode OLED is likely to shrink.

[0104] Therefore, an electron injection layer EIL with a ytterbium (Yb) to lithium fluoride (LiF) ratio of 2:1 is disposed in the central region AA(C) of the display area AA.

[0105] An electron-injected layer (EIL) having a ytterbium (Yb) to lithium fluoride (LiF) ratio of 1:2 or 1:3 is disposed in each of the four corner regions C1 to C4. The thickness of the electron-injected layer EIL disposed in each of the four corner regions C1 to C4 is greater than the thickness of the electron-injected layer EIL disposed in the central region AA(C) of the display region AA. For example, the electron-injected layer EIL disposed in the central region AA(C) of the display region AA may have approximately [missing information - likely a thickness value]. The thickness, and the electron injection layer EIL disposed in each of the four corner regions C1 to C4 can have approximately to The thickness.

[0106] Furthermore, an electron injection layer (EIL) having a ytterbium (Yb) to lithium fluoride (LiF) ratio of 3:1 can be disposed in each of the four side regions S1 to S4. The thickness of the electron injection layer EIL disposed in each of the four side regions S1 to S4 is equal to the thickness of the electron injection layer EIL disposed in the central region AA(C) of the display region AA.

[0107] According to this disclosure, as described above, the material structure and thickness of the electron injection layer in the corner and side regions of the display panel can be changed, thereby preventing the corner and side regions from oxidizing due to moisture and oxygen and preventing the light-emitting diodes from shrinking.

[0108] The light-emitting display apparatus according to various embodiments of the present disclosure can be described as follows.

[0109] A light-emitting display device according to an embodiment of the present disclosure includes: a substrate having a display area and a non-display area disposed at the edge of the display area and surrounding the display area, the display area including a central area and a peripheral area other than the central area, and the peripheral area of ​​the display area and the non-display area together being divided into a corner area and a side area; voltage lines disposed on the substrate in the non-display area; a dam having light-emitting openings disposed in each pixel of the display area and dam openings disposed on the voltage lines; and an electron injection layer disposed in the light-emitting openings and dam openings, wherein the electron injection layer is configured to have different thicknesses in the central area and the corner area of ​​the display area.

[0110] According to embodiments of this disclosure, the electron injection layer can be configured to be thicker in the corner regions than in the central region of the display area.

[0111] According to embodiments of this disclosure, the electron injection layer can be configured to have the same thickness in the side region and the central region of the display area.

[0112] According to embodiments of this disclosure, the electron injection layer may contain ytterbium (Yb) and lithium fluoride (LiF), and the ratio of ytterbium (Yb) to lithium fluoride (LiF) in the electron injection layer disposed in the central region of the display area may be 2:1.

[0113] According to embodiments of this disclosure, the electron injection layer may contain ytterbium (Yb) and lithium fluoride (LiF), and the ratio of ytterbium (Yb) to lithium fluoride (LiF) in the electron injection layer disposed in the corner region may be 1:2 or 1:3.

[0114] According to embodiments of this disclosure, the electron injection layer may contain ytterbium (Yb) and lithium fluoride (LiF), and the ratio of ytterbium (Yb) to lithium fluoride (LiF) in the electron injection layer disposed in the side region may be 3:1.

[0115] A light-emitting display device according to another embodiment of the present disclosure includes: a substrate having a display area and a non-display area disposed at the edge of the display area and surrounding the display area, the display area including a central area and a peripheral area other than the central area, and the peripheral area and the non-display area together being divided into a corner area and a side area; voltage lines disposed on the substrate in the non-display area; thin-film transistors disposed in each pixel of the display area; an anode and a connection pattern, the anode being disposed on the thin-film transistor in each pixel and electrically connected to the thin-film transistor, and the connection pattern being disposed on the voltage line and electrically connected to the voltage line; a dam having a light-emitting opening configured to expose the anode and a dam opening configured to expose the connection pattern; an electron injection layer disposed in the light-emitting opening and the dam opening; and a cathode disposed on the anode and the connection pattern, and the electron injection layer being disposed between the cathode and the anode and the connection pattern, wherein the electron injection layer is configured to have different thicknesses in the central area and the corner area of ​​the display area.

[0116] According to embodiments of this disclosure, the hole injection layer, hole transport layer, light-emitting layer, and electron transport layer may be further disposed between the anode and the electron injection layer in the light-emitting opening, and are disposed sequentially starting from the anode.

[0117] According to embodiments of this disclosure, a first planarization layer and a second planarization layer may be further disposed between the voltage line and the thin-film transistor and the anode, and a first connection metal pattern configured to electrically connect the thin-film transistor and the anode and a second connection metal pattern configured to electrically connect the voltage line and the connection pattern may be further disposed between the first planarization layer and the second planarization layer.

[0118] According to embodiments of this disclosure, an encapsulation layer may be further provided on the cathode.

[0119] As is apparent from the above description, the light-emitting display device according to this disclosure has the following effects.

[0120] First, the material structure and thickness of the electron injection layer (EIL) can be changed in the corner and side areas of the display panel, thereby preventing the corner and side areas from oxidizing due to moisture and oxygen.

[0121] Secondly, the material structure and thickness of the electron injection layer (EIL) can be changed in the corner and side areas of the display panel, thereby preventing the light-emitting diodes from shrinking.

[0122] It will be apparent to those skilled in the art that the present disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications and changes can be made without departing from the technical concept of the present disclosure.

Claims

1. A light-emitting display device, comprising: A substrate having a display area and a non-display area disposed at the edge of the display area and surrounding the display area, the display area including a central area and a peripheral area other than the central area, and the peripheral area of ​​the display area and the non-display area together being divided into a corner area and a side area. Voltage lines, which are disposed on the substrate in the non-display area; The dam has light-emitting openings disposed in each pixel of the display area and dam openings disposed on the voltage line; as well as An electron injection layer is disposed in the light-emitting opening and the embankment opening. The electron injection layer is configured to have different thicknesses in the central region and the corner regions of the display area.

2. The light-emitting display device according to claim 1, wherein, The electron injection layer is configured to be thicker in the corner region than in the center region of the display area.

3. The light-emitting display device according to claim 2, wherein, The electron injection layer is configured to have the same thickness in the central region and the side regions of the display area.

4. The light-emitting display device according to claim 1, wherein, The electron injection layer comprises ytterbium (Yb) and lithium fluoride (LiF), and The electron injection layer disposed in the central region of the display area has a ytterbium (Yb) to lithium fluoride (LiF) ratio of 2:

1.

5. The light-emitting display device according to claim 1, wherein, The electron injection layer comprises ytterbium (Yb) and lithium fluoride (LiF), and The electron injection layer disposed in the corner region has a ytterbium (Yb) to lithium fluoride (LiF) ratio of 1:2 or 1:

3.

6. The light-emitting display device according to claim 1, wherein, The electron injection layer comprises ytterbium (Yb) and lithium fluoride (LiF), and The electron injection layer disposed in the side region has a ytterbium (Yb) to lithium fluoride (LiF) ratio of 3:

1.

7. A light-emitting display device, comprising: A substrate having a display area and a non-display area disposed at the edge of the display area and surrounding the display area, the display area including a central area and a peripheral area other than the central area, and the peripheral area of ​​the display area and the non-display area together being divided into a corner area and a side area. Voltage lines, which are disposed on the substrate in the non-display area; Thin-film transistors, wherein the thin-film transistors are disposed in each pixel of the display area; An anode and a connecting pattern, wherein the anode is disposed on and electrically connected to the thin-film transistor in each pixel, and the connecting pattern is disposed on and electrically connected to the voltage line; A dam having a light-emitting opening configured to expose the anode and a dam opening configured to expose the connection pattern; An electron injection layer is disposed in the light-emitting opening and the embankment opening; as well as A cathode is disposed on the anode and the connection pattern, and the electron injection layer is located between the cathode, the anode, and the connection pattern. The electron injection layer is configured to have different thicknesses in the central region and the corner regions of the display area.

8. The light-emitting display device according to claim 7, wherein, The electron injection layer is configured to be thicker in the corner region than in the center region of the display area.

9. The light-emitting display device according to claim 8, wherein, The electron injection layer is configured to have the same thickness in the central region and the side regions of the display area.

10. The light-emitting display device according to claim 7, wherein, The electron injection layer comprises ytterbium (Yb) and lithium fluoride (LiF), and The electron injection layer disposed in the central region of the display area has a ytterbium (Yb) to lithium fluoride (LiF) ratio of 2:

1.

11. The light-emitting display device according to claim 7, wherein, The electron injection layer comprises ytterbium (Yb) and lithium fluoride (LiF), and The electron injection layer disposed in the corner region has a ytterbium (Yb) to lithium fluoride (LiF) ratio of 1:2 or 1:

3.

12. The light-emitting display device according to claim 7, wherein, The electron injection layer comprises ytterbium (Yb) and lithium fluoride (LiF), and The electron injection layer disposed in the side region has a ytterbium (Yb) to lithium fluoride (LiF) ratio of 3:

1.

13. The light-emitting display device according to claim 7, further comprising: The light-emitting layer comprises a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer, wherein the hole injection layer, the hole transport layer, the light-emitting layer, and the electron transport layer are arranged sequentially from the anode in the light-emitting opening between the anode and the electron injection layer.

14. The light-emitting display device according to claim 7, further comprising: A first planarization layer and a second planarization layer are located between the voltage line and the thin-film transistor and the anode; A first connecting metal pattern is located between the first planarization layer and the second planarization layer and is configured to electrically connect the thin-film transistor and the anode; as well as A second connecting metal pattern is located between the first planarization layer and the second planarization layer, and is configured to electrically connect the voltage line and the connecting pattern.

15. The light-emitting display device according to claim 7, further comprising: An encapsulation layer is disposed on the cathode.

16. A display device, comprising: A substrate having a display area and a non-display area surrounding the display area, the display area including a central area and corner areas; A plurality of thin-film transistors, wherein the plurality of thin-film transistors includes a first thin-film transistor and a second thin-film transistor; A first light-emitting diode, wherein the first light-emitting diode is located in the central region, the first light-emitting diode is electrically connected to the first thin-film transistor, the first light-emitting diode includes a first anode, a first organic light-emitting layer on the first anode and a cathode on the first organic light-emitting layer, the first organic light-emitting layer including a first electron injection layer; as well as A second light-emitting diode (LED) is located in the corner region and is electrically connected to the second thin-film transistor. The second LED includes a second anode, a second organic light-emitting layer on the second anode, and a second cathode on the second organic light-emitting layer. The second organic light-emitting layer includes a second electron injection layer. The thickness of the first electron injection layer is different from the thickness of the second electron injection layer.

17. The display device according to claim 16, wherein, The thickness of the second electron injection layer is greater than the thickness of the first electron injection layer.

18. The display device according to claim 16, wherein, The plurality of thin-film transistors includes a third thin-film transistor, and the display device further includes: A third light-emitting diode, electrically connected to the third thin-film transistor and disposed in a side region of the display area, the side region being located between a pair of corner regions of the display area; the third thin-film transistor includes a third anode, a third organic light-emitting layer on the third anode, and a third cathode on the third organic light-emitting layer; the third organic light-emitting layer includes a third electron injection layer. The thickness of the first electron injection layer is the same as the thickness of the third electron injection layer.

19. The display device according to claim 18, wherein, The first electron-injected layer comprises yttrium and lithium fluoride, with a yttrium to lithium fluoride ratio of 2:1, and The second electron injection layer comprises yttrium and lithium fluoride, wherein the ratio of yttrium to lithium fluoride is 1:2 or 1:

3.

20. The display device according to claim 19, wherein, The third electron injection layer contains yttrium and lithium fluoride, with a yttrium to lithium fluoride ratio of 3:

1.

21. The display device according to claim 16, further comprising: Voltage lines, in the non-display area; as well as A third organic light-emitting layer overlaps with the voltage line in the non-display area. The third organic light-emitting layer has a third electron injection layer, but does not include a hole injection layer, a hole transport layer, a light-emitting layer, or an electron transport layer.

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